drivers/net/ixgbe/ixgbe_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/uaccess.h>
  37
  38 #include "ixgbe.h"
  39
  40
  41 #define IXGBE_ALL_RAR_ENTRIES 16
  42
  43 enum {NETDEV_STATS, IXGBE_STATS};
  44
  45 struct ixgbe_stats {
  46         char stat_string[ETH_GSTRING_LEN];
  47         int type;
  48         int sizeof_stat;
  49         int stat_offset;
  50 };
  51
  52 #define IXGBE_STAT(m)           IXGBE_STATS, \
  53                                 sizeof(((struct ixgbe_adapter *)0)->m), \
  54                                 offsetof(struct ixgbe_adapter, m)
  55 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
  56                                 sizeof(((struct net_device *)0)->m), \
  57                                 offsetof(struct net_device, m)
  58
  59 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
  60         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
  61         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
  62         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
  63         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
  64         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
  65         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
  66         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
  67         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
  68         {"lsc_int", IXGBE_STAT(lsc_int)},
  69         {"tx_busy", IXGBE_STAT(tx_busy)},
  70         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  71         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
  72         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
  73         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
  74         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
  75         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
  76         {"broadcast", IXGBE_STAT(stats.bprc)},
  77         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  78         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
  79         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
  80         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
  81         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
  82         {"hw_rsc_count", IXGBE_STAT(rsc_count)},
  83         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  84         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  85         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
  86         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
  87         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
  88         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
  89         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
  90         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
  91         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  92         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  93         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
  94         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
  95         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
  96         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
  97         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
  98         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
  99         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
 100         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
 101         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
 102         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
 103         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
 104         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
 105         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
 106         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
 107         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
 108 #ifdef IXGBE_FCOE
 109         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
 110         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
 111         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 112         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 113         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 114         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 115 #endif /* IXGBE_FCOE */
 116 };
 117
 118 #define IXGBE_QUEUE_STATS_LEN \
 119         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
 120         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
 121         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 122 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 123 #define IXGBE_PB_STATS_LEN ( \
 124                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
 125                  IXGBE_FLAG_DCB_ENABLED) ? \
 126                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 127                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 128                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 129                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 130                   / sizeof(u64) : 0)
 131 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 132                          IXGBE_PB_STATS_LEN + \
 133                          IXGBE_QUEUE_STATS_LEN)
 134
 135 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 136         "Register test  (offline)", "Eeprom test    (offline)",
 137         "Interrupt test (offline)", "Loopback test  (offline)",
 138         "Link test   (on/offline)"
 139 };
 140 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 141
 142 static int ixgbe_get_settings(struct net_device *netdev,
 143                               struct ethtool_cmd *ecmd)
 144 {
 145         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 146         struct ixgbe_hw *hw = &adapter->hw;
 147         u32 link_speed = 0;
 148         bool link_up;
 149
 150         ecmd->supported = SUPPORTED_10000baseT_Full;
 151         ecmd->autoneg = AUTONEG_ENABLE;
 152         ecmd->transceiver = XCVR_EXTERNAL;
 153         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 154             (hw->phy.multispeed_fiber)) {
 155                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
 156                                     SUPPORTED_Autoneg);
 157
 158                 ecmd->advertising = ADVERTISED_Autoneg;
 159                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 160                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 161                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 162                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 163                 /*
 164                  * It's possible that phy.autoneg_advertised may not be
 165                  * set yet.  If so display what the default would be -
 166                  * both 1G and 10G supported.
 167                  */
 168                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
 169                                            ADVERTISED_10000baseT_Full)))
 170                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
 171                                               ADVERTISED_1000baseT_Full);
 172
 173                 if (hw->phy.media_type == ixgbe_media_type_copper) {
 174                         ecmd->supported |= SUPPORTED_TP;
 175                         ecmd->advertising |= ADVERTISED_TP;
 176                         ecmd->port = PORT_TP;
 177                 } else {
 178                         ecmd->supported |= SUPPORTED_FIBRE;
 179                         ecmd->advertising |= ADVERTISED_FIBRE;
 180                         ecmd->port = PORT_FIBRE;
 181                 }
 182         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
 183                 /* Set as FIBRE until SERDES defined in kernel */
 184                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
 185                         ecmd->supported = (SUPPORTED_1000baseT_Full |
 186                                            SUPPORTED_FIBRE);
 187                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
 188                                              ADVERTISED_FIBRE);
 189                         ecmd->port = PORT_FIBRE;
 190                         ecmd->autoneg = AUTONEG_DISABLE;
 191                 } else {
 192                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 193                                             SUPPORTED_FIBRE);
 194                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
 195                                              ADVERTISED_1000baseT_Full |
 196                                              ADVERTISED_FIBRE);
 197                         ecmd->port = PORT_FIBRE;
 198                 }
 199         } else {
 200                 ecmd->supported |= SUPPORTED_FIBRE;
 201                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
 202                                      ADVERTISED_FIBRE);
 203                 ecmd->port = PORT_FIBRE;
 204                 ecmd->autoneg = AUTONEG_DISABLE;
 205         }
 206
 207         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 208         if (link_up) {
 209                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
 210                                SPEED_10000 : SPEED_1000;
 211                 ecmd->duplex = DUPLEX_FULL;
 212         } else {
 213                 ecmd->speed = -1;
 214                 ecmd->duplex = -1;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int ixgbe_set_settings(struct net_device *netdev,
 221                               struct ethtool_cmd *ecmd)
 222 {
 223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 224         struct ixgbe_hw *hw = &adapter->hw;
 225         u32 advertised, old;
 226         s32 err = 0;
 227
 228         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 229             (hw->phy.multispeed_fiber)) {
 230                 /* 10000/copper and 1000/copper must autoneg
 231                  * this function does not support any duplex forcing, but can
 232                  * limit the advertising of the adapter to only 10000 or 1000 */
 233                 if (ecmd->autoneg == AUTONEG_DISABLE)
 234                         return -EINVAL;
 235
 236                 old = hw->phy.autoneg_advertised;
 237                 advertised = 0;
 238                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 239                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 240
 241                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 242                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 243
 244                 if (old == advertised)
 245                         return err;
 246                 /* this sets the link speed and restarts auto-neg */
 247                 hw->mac.autotry_restart = true;
 248                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
 249                 if (err) {
 250                         DPRINTK(PROBE, INFO,
 251                                 "setup link failed with code %d\n", err);
 252                         hw->mac.ops.setup_link(hw, old, true, true);
 253                 }
 254         } else {
 255                 /* in this case we currently only support 10Gb/FULL */
 256                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 257                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 258                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 259                         return -EINVAL;
 260         }
 261
 262         return err;
 263 }
 264
 265 static void ixgbe_get_pauseparam(struct net_device *netdev,
 266                                  struct ethtool_pauseparam *pause)
 267 {
 268         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 269         struct ixgbe_hw *hw = &adapter->hw;
 270
 271         /*
 272          * Flow Control Autoneg isn't on if
 273          *  - we didn't ask for it OR
 274          *  - it failed, we know this by tx & rx being off
 275          */
 276         if (hw->fc.disable_fc_autoneg ||
 277             (hw->fc.current_mode == ixgbe_fc_none))
 278                 pause->autoneg = 0;
 279         else
 280                 pause->autoneg = 1;
 281
 282 #ifdef CONFIG_DCB
 283         if (hw->fc.current_mode == ixgbe_fc_pfc) {
 284                 pause->rx_pause = 0;
 285                 pause->tx_pause = 0;
 286         }
 287
 288 #endif
 289         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 290                 pause->rx_pause = 1;
 291         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 292                 pause->tx_pause = 1;
 293         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 294                 pause->rx_pause = 1;
 295                 pause->tx_pause = 1;
 296         }
 297 }
 298
 299 static int ixgbe_set_pauseparam(struct net_device *netdev,
 300                                 struct ethtool_pauseparam *pause)
 301 {
 302         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 303         struct ixgbe_hw *hw = &adapter->hw;
 304         struct ixgbe_fc_info fc;
 305
 306 #ifdef CONFIG_DCB
 307         if (adapter->dcb_cfg.pfc_mode_enable ||
 308                 ((hw->mac.type == ixgbe_mac_82598EB) &&
 309                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
 310                 return -EINVAL;
 311
 312 #endif
 313
 314         fc = hw->fc;
 315
 316         if (pause->autoneg != AUTONEG_ENABLE)
 317                 fc.disable_fc_autoneg = true;
 318         else
 319                 fc.disable_fc_autoneg = false;
 320
 321         if (pause->rx_pause && pause->tx_pause)
 322                 fc.requested_mode = ixgbe_fc_full;
 323         else if (pause->rx_pause && !pause->tx_pause)
 324                 fc.requested_mode = ixgbe_fc_rx_pause;
 325         else if (!pause->rx_pause && pause->tx_pause)
 326                 fc.requested_mode = ixgbe_fc_tx_pause;
 327         else if (!pause->rx_pause && !pause->tx_pause)
 328                 fc.requested_mode = ixgbe_fc_none;
 329         else
 330                 return -EINVAL;
 331
 332 #ifdef CONFIG_DCB
 333         adapter->last_lfc_mode = fc.requested_mode;
 334 #endif
 335
 336         /* if the thing changed then we'll update and use new autoneg */
 337         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 338                 hw->fc = fc;
 339                 if (netif_running(netdev))
 340                         ixgbe_reinit_locked(adapter);
 341                 else
 342                         ixgbe_reset(adapter);
 343         }
 344
 345         return 0;
 346 }
 347
 348 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
 349 {
 350         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 351         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
 352 }
 353
 354 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
 355 {
 356         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 357         if (data)
 358                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
 359         else
 360                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 361
 362         if (netif_running(netdev))
 363                 ixgbe_reinit_locked(adapter);
 364         else
 365                 ixgbe_reset(adapter);
 366
 367         return 0;
 368 }
 369
 370 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 371 {
 372         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 373 }
 374
 375 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 376 {
 377         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 378
 379         if (data) {
 380                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 381                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 382                         netdev->features |= NETIF_F_SCTP_CSUM;
 383         } else {
 384                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 385                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 386                         netdev->features &= ~NETIF_F_SCTP_CSUM;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
 393 {
 394         if (data) {
 395                 netdev->features |= NETIF_F_TSO;
 396                 netdev->features |= NETIF_F_TSO6;
 397         } else {
 398                 netif_tx_stop_all_queues(netdev);
 399                 netdev->features &= ~NETIF_F_TSO;
 400                 netdev->features &= ~NETIF_F_TSO6;
 401                 netif_tx_start_all_queues(netdev);
 402         }
 403         return 0;
 404 }
 405
 406 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 407 {
 408         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 409         return adapter->msg_enable;
 410 }
 411
 412 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 413 {
 414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 415         adapter->msg_enable = data;
 416 }
 417
 418 static int ixgbe_get_regs_len(struct net_device *netdev)
 419 {
 420 #define IXGBE_REGS_LEN  1128
 421         return IXGBE_REGS_LEN * sizeof(u32);
 422 }
 423
 424 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 425
 426 static void ixgbe_get_regs(struct net_device *netdev,
 427                            struct ethtool_regs *regs, void *p)
 428 {
 429         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 430         struct ixgbe_hw *hw = &adapter->hw;
 431         u32 *regs_buff = p;
 432         u8 i;
 433
 434         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 435
 436         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
 437
 438         /* General Registers */
 439         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 440         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 441         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 442         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 443         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 444         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 445         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 446         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 447
 448         /* NVM Register */
 449         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 450         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 451         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 452         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 453         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 454         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 455         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 456         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 457         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 458         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 459
 460         /* Interrupt */
 461         /* don't read EICR because it can clear interrupt causes, instead
 462          * read EICS which is a shadow but doesn't clear EICR */
 463         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 464         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 465         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 466         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 467         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 468         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 469         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 470         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 471         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 472         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 473         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 474         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 475
 476         /* Flow Control */
 477         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 478         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 479         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 480         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 481         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 482         for (i = 0; i < 8; i++)
 483                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 484         for (i = 0; i < 8; i++)
 485                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 486         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 487         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 488
 489         /* Receive DMA */
 490         for (i = 0; i < 64; i++)
 491                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 492         for (i = 0; i < 64; i++)
 493                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 494         for (i = 0; i < 64; i++)
 495                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 496         for (i = 0; i < 64; i++)
 497                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 498         for (i = 0; i < 64; i++)
 499                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 500         for (i = 0; i < 64; i++)
 501                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 502         for (i = 0; i < 16; i++)
 503                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 504         for (i = 0; i < 16; i++)
 505                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 506         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 507         for (i = 0; i < 8; i++)
 508                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 509         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 510         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 511
 512         /* Receive */
 513         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 514         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 515         for (i = 0; i < 16; i++)
 516                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 517         for (i = 0; i < 16; i++)
 518                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 519         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 520         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 521         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 522         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 523         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 524         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 525         for (i = 0; i < 8; i++)
 526                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 527         for (i = 0; i < 8; i++)
 528                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 529         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 530
 531         /* Transmit */
 532         for (i = 0; i < 32; i++)
 533                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 534         for (i = 0; i < 32; i++)
 535                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 536         for (i = 0; i < 32; i++)
 537                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 538         for (i = 0; i < 32; i++)
 539                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 540         for (i = 0; i < 32; i++)
 541                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 542         for (i = 0; i < 32; i++)
 543                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 544         for (i = 0; i < 32; i++)
 545                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 546         for (i = 0; i < 32; i++)
 547                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 548         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 549         for (i = 0; i < 16; i++)
 550                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 551         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 552         for (i = 0; i < 8; i++)
 553                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 554         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 555
 556         /* Wake Up */
 557         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 558         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 559         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 560         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 561         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 562         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 563         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 564         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 565         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 566
 567         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 568         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 569         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 570         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 571         for (i = 0; i < 8; i++)
 572                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 573         for (i = 0; i < 8; i++)
 574                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 575         for (i = 0; i < 8; i++)
 576                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 577         for (i = 0; i < 8; i++)
 578                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 579         for (i = 0; i < 8; i++)
 580                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 581         for (i = 0; i < 8; i++)
 582                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 583
 584         /* Statistics */
 585         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 586         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 587         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 588         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 589         for (i = 0; i < 8; i++)
 590                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 591         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 592         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 593         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 594         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 595         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 596         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 597         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 598         for (i = 0; i < 8; i++)
 599                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 600         for (i = 0; i < 8; i++)
 601                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 602         for (i = 0; i < 8; i++)
 603                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 604         for (i = 0; i < 8; i++)
 605                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 606         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 607         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 608         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 609         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 610         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 611         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 612         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 613         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 614         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 615         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 616         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 617         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 618         for (i = 0; i < 8; i++)
 619                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 620         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 621         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 622         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 623         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 624         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 625         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 626         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 627         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 628         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 629         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 630         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 631         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 632         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 633         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 634         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 635         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 636         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 637         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 638         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 639         for (i = 0; i < 16; i++)
 640                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 641         for (i = 0; i < 16; i++)
 642                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 643         for (i = 0; i < 16; i++)
 644                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 645         for (i = 0; i < 16; i++)
 646                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 647
 648         /* MAC */
 649         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 650         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 651         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 652         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 653         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 654         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 655         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 656         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 657         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 658         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 659         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 660         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 661         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 662         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 663         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 664         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 665         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 666         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 667         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 668         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 669         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 670         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 671         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 672         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 673         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 674         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 675         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 676         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 677         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 678         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 679         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 680         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 681         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 682
 683         /* Diagnostic */
 684         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 685         for (i = 0; i < 8; i++)
 686                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 687         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 688         for (i = 0; i < 4; i++)
 689                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 690         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 691         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 692         for (i = 0; i < 8; i++)
 693                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 694         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 695         for (i = 0; i < 4; i++)
 696                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 697         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 698         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 699         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 700         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 701         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 702         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 703         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 704         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 705         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 706         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 707         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 708         for (i = 0; i < 8; i++)
 709                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 710         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 711         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 712         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 713         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 714         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 715         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 716         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 717         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 718         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 719 }
 720
 721 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 722 {
 723         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 724         return adapter->hw.eeprom.word_size * 2;
 725 }
 726
 727 static int ixgbe_get_eeprom(struct net_device *netdev,
 728                             struct ethtool_eeprom *eeprom, u8 *bytes)
 729 {
 730         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 731         struct ixgbe_hw *hw = &adapter->hw;
 732         u16 *eeprom_buff;
 733         int first_word, last_word, eeprom_len;
 734         int ret_val = 0;
 735         u16 i;
 736
 737         if (eeprom->len == 0)
 738                 return -EINVAL;
 739
 740         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 741
 742         first_word = eeprom->offset >> 1;
 743         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 744         eeprom_len = last_word - first_word + 1;
 745
 746         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 747         if (!eeprom_buff)
 748                 return -ENOMEM;
 749
 750         for (i = 0; i < eeprom_len; i++) {
 751                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
 752                     &eeprom_buff[i])))
 753                         break;
 754         }
 755
 756         /* Device's eeprom is always little-endian, word addressable */
 757         for (i = 0; i < eeprom_len; i++)
 758                 le16_to_cpus(&eeprom_buff[i]);
 759
 760         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 761         kfree(eeprom_buff);
 762
 763         return ret_val;
 764 }
 765
 766 static void ixgbe_get_drvinfo(struct net_device *netdev,
 767                               struct ethtool_drvinfo *drvinfo)
 768 {
 769         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 770         char firmware_version[32];
 771
 772         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
 773         strncpy(drvinfo->version, ixgbe_driver_version, 32);
 774
 775         sprintf(firmware_version, "%d.%d-%d",
 776                 (adapter->eeprom_version & 0xF000) >> 12,
 777                 (adapter->eeprom_version & 0x0FF0) >> 4,
 778                 adapter->eeprom_version & 0x000F);
 779
 780         strncpy(drvinfo->fw_version, firmware_version, 32);
 781         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 782         drvinfo->n_stats = IXGBE_STATS_LEN;
 783         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 784         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 785 }
 786
 787 static void ixgbe_get_ringparam(struct net_device *netdev,
 788                                 struct ethtool_ringparam *ring)
 789 {
 790         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 791         struct ixgbe_ring *tx_ring = adapter->tx_ring;
 792         struct ixgbe_ring *rx_ring = adapter->rx_ring;
 793
 794         ring->rx_max_pending = IXGBE_MAX_RXD;
 795         ring->tx_max_pending = IXGBE_MAX_TXD;
 796         ring->rx_mini_max_pending = 0;
 797         ring->rx_jumbo_max_pending = 0;
 798         ring->rx_pending = rx_ring->count;
 799         ring->tx_pending = tx_ring->count;
 800         ring->rx_mini_pending = 0;
 801         ring->rx_jumbo_pending = 0;
 802 }
 803
 804 static int ixgbe_set_ringparam(struct net_device *netdev,
 805                                struct ethtool_ringparam *ring)
 806 {
 807         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 808         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
 809         int i, err = 0;
 810         u32 new_rx_count, new_tx_count;
 811         bool need_update = false;
 812
 813         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 814                 return -EINVAL;
 815
 816         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
 817         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
 818         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 819
 820         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
 821         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
 822         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 823
 824         if ((new_tx_count == adapter->tx_ring->count) &&
 825             (new_rx_count == adapter->rx_ring->count)) {
 826                 /* nothing to do */
 827                 return 0;
 828         }
 829
 830         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 831                 msleep(1);
 832
 833         if (!netif_running(adapter->netdev)) {
 834                 for (i = 0; i < adapter->num_tx_queues; i++)
 835                         adapter->tx_ring[i].count = new_tx_count;
 836                 for (i = 0; i < adapter->num_rx_queues; i++)
 837                         adapter->rx_ring[i].count = new_rx_count;
 838                 adapter->tx_ring_count = new_tx_count;
 839                 adapter->rx_ring_count = new_rx_count;
 840                 goto err_setup;
 841         }
 842
 843         temp_tx_ring = kcalloc(adapter->num_tx_queues,
 844                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 845         if (!temp_tx_ring) {
 846                 err = -ENOMEM;
 847                 goto err_setup;
 848         }
 849
 850         if (new_tx_count != adapter->tx_ring_count) {
 851                 memcpy(temp_tx_ring, adapter->tx_ring,
 852                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
 853                 for (i = 0; i < adapter->num_tx_queues; i++) {
 854                         temp_tx_ring[i].count = new_tx_count;
 855                         err = ixgbe_setup_tx_resources(adapter,
 856                                                        &temp_tx_ring[i]);
 857                         if (err) {
 858                                 while (i) {
 859                                         i--;
 860                                         ixgbe_free_tx_resources(adapter,
 861                                                                 &temp_tx_ring[i]);
 862                                 }
 863                                 goto err_setup;
 864                         }
 865                 }
 866                 need_update = true;
 867         }
 868
 869         temp_rx_ring = kcalloc(adapter->num_rx_queues,
 870                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 871         if ((!temp_rx_ring) && (need_update)) {
 872                 for (i = 0; i < adapter->num_tx_queues; i++)
 873                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
 874                 kfree(temp_tx_ring);
 875                 err = -ENOMEM;
 876                 goto err_setup;
 877         }
 878
 879         if (new_rx_count != adapter->rx_ring_count) {
 880                 memcpy(temp_rx_ring, adapter->rx_ring,
 881                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
 882                 for (i = 0; i < adapter->num_rx_queues; i++) {
 883                         temp_rx_ring[i].count = new_rx_count;
 884                         err = ixgbe_setup_rx_resources(adapter,
 885                                                        &temp_rx_ring[i]);
 886                         if (err) {
 887                                 while (i) {
 888                                         i--;
 889                                         ixgbe_free_rx_resources(adapter,
 890                                                               &temp_rx_ring[i]);
 891                                 }
 892                                 goto err_setup;
 893                         }
 894                 }
 895                 need_update = true;
 896         }
 897
 898         /* if rings need to be updated, here's the place to do it in one shot */
 899         if (need_update) {
 900                 ixgbe_down(adapter);
 901
 902                 /* tx */
 903                 if (new_tx_count != adapter->tx_ring_count) {
 904                         kfree(adapter->tx_ring);
 905                         adapter->tx_ring = temp_tx_ring;
 906                         temp_tx_ring = NULL;
 907                         adapter->tx_ring_count = new_tx_count;
 908                 }
 909
 910                 /* rx */
 911                 if (new_rx_count != adapter->rx_ring_count) {
 912                         kfree(adapter->rx_ring);
 913                         adapter->rx_ring = temp_rx_ring;
 914                         temp_rx_ring = NULL;
 915                         adapter->rx_ring_count = new_rx_count;
 916                 }
 917                 ixgbe_up(adapter);
 918         }
 919 err_setup:
 920         clear_bit(__IXGBE_RESETTING, &adapter->state);
 921         return err;
 922 }
 923
 924 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
 925 {
 926         switch (sset) {
 927         case ETH_SS_TEST:
 928                 return IXGBE_TEST_LEN;
 929         case ETH_SS_STATS:
 930                 return IXGBE_STATS_LEN;
 931         default:
 932                 return -EOPNOTSUPP;
 933         }
 934 }
 935
 936 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
 937                                     struct ethtool_stats *stats, u64 *data)
 938 {
 939         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 940         u64 *queue_stat;
 941         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
 942         int j, k;
 943         int i;
 944         char *p = NULL;
 945
 946         ixgbe_update_stats(adapter);
 947         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 948                 switch (ixgbe_gstrings_stats[i].type) {
 949                 case NETDEV_STATS:
 950                         p = (char *) netdev +
 951                                         ixgbe_gstrings_stats[i].stat_offset;
 952                         break;
 953                 case IXGBE_STATS:
 954                         p = (char *) adapter +
 955                                         ixgbe_gstrings_stats[i].stat_offset;
 956                         break;
 957                 }
 958
 959                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
 960                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
 961         }
 962         for (j = 0; j < adapter->num_tx_queues; j++) {
 963                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
 964                 for (k = 0; k < stat_count; k++)
 965                         data[i + k] = queue_stat[k];
 966                 i += k;
 967         }
 968         for (j = 0; j < adapter->num_rx_queues; j++) {
 969                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
 970                 for (k = 0; k < stat_count; k++)
 971                         data[i + k] = queue_stat[k];
 972                 i += k;
 973         }
 974         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 975                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
 976                         data[i++] = adapter->stats.pxontxc[j];
 977                         data[i++] = adapter->stats.pxofftxc[j];
 978                 }
 979                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
 980                         data[i++] = adapter->stats.pxonrxc[j];
 981                         data[i++] = adapter->stats.pxoffrxc[j];
 982                 }
 983         }
 984 }
 985
 986 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
 987                               u8 *data)
 988 {
 989         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 990         char *p = (char *)data;
 991         int i;
 992
 993         switch (stringset) {
 994         case ETH_SS_TEST:
 995                 memcpy(data, *ixgbe_gstrings_test,
 996                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
 997                 break;
 998         case ETH_SS_STATS:
 999                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1000                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1001                                ETH_GSTRING_LEN);
1002                         p += ETH_GSTRING_LEN;
1003                 }
1004                 for (i = 0; i < adapter->num_tx_queues; i++) {
1005                         sprintf(p, "tx_queue_%u_packets", i);
1006                         p += ETH_GSTRING_LEN;
1007                         sprintf(p, "tx_queue_%u_bytes", i);
1008                         p += ETH_GSTRING_LEN;
1009                 }
1010                 for (i = 0; i < adapter->num_rx_queues; i++) {
1011                         sprintf(p, "rx_queue_%u_packets", i);
1012                         p += ETH_GSTRING_LEN;
1013                         sprintf(p, "rx_queue_%u_bytes", i);
1014                         p += ETH_GSTRING_LEN;
1015                 }
1016                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1017                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1018                                 sprintf(p, "tx_pb_%u_pxon", i);
1019                                 p += ETH_GSTRING_LEN;
1020                                 sprintf(p, "tx_pb_%u_pxoff", i);
1021                                 p += ETH_GSTRING_LEN;
1022                         }
1023                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1024                                 sprintf(p, "rx_pb_%u_pxon", i);
1025                                 p += ETH_GSTRING_LEN;
1026                                 sprintf(p, "rx_pb_%u_pxoff", i);
1027                                 p += ETH_GSTRING_LEN;
1028                         }
1029                 }
1030                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1031                 break;
1032         }
1033 }
1034
1035 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1036 {
1037         struct ixgbe_hw *hw = &adapter->hw;
1038         bool link_up;
1039         u32 link_speed = 0;
1040         *data = 0;
1041
1042         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1043         if (link_up)
1044                 return *data;
1045         else
1046                 *data = 1;
1047         return *data;
1048 }
1049
1050 /* ethtool register test data */
1051 struct ixgbe_reg_test {
1052         u16 reg;
1053         u8  array_len;
1054         u8  test_type;
1055         u32 mask;
1056         u32 write;
1057 };
1058
1059 /* In the hardware, registers are laid out either singly, in arrays
1060  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1061  * most tests take place on arrays or single registers (handled
1062  * as a single-element array) and special-case the tables.
1063  * Table tests are always pattern tests.
1064  *
1065  * We also make provision for some required setup steps by specifying
1066  * registers to be written without any read-back testing.
1067  */
1068
1069 #define PATTERN_TEST    1
1070 #define SET_READ_TEST   2
1071 #define WRITE_NO_TEST   3
1072 #define TABLE32_TEST    4
1073 #define TABLE64_TEST_LO 5
1074 #define TABLE64_TEST_HI 6
1075
1076 /* default 82599 register test */
1077 static struct ixgbe_reg_test reg_test_82599[] = {
1078         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1079         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1080         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1082         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1083         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1085         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1086         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1087         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1088         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1089         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1090         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1091         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1092         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1093         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1094         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1095         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1096         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1097         { 0, 0, 0, 0 }
1098 };
1099
1100 /* default 82598 register test */
1101 static struct ixgbe_reg_test reg_test_82598[] = {
1102         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1103         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1104         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1105         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1106         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1107         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1108         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1109         /* Enable all four RX queues before testing. */
1110         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1111         /* RDH is read-only for 82598, only test RDT. */
1112         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1113         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1114         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1115         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1116         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1117         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1118         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1119         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1120         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1121         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1122         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1123         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1124         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1125         { 0, 0, 0, 0 }
1126 };
1127
1128 #define REG_PATTERN_TEST(R, M, W)                                             \
1129 {                                                                             \
1130         u32 pat, val, before;                                                 \
1131         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1132         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1133                 before = readl(adapter->hw.hw_addr + R);                      \
1134                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1135                 val = readl(adapter->hw.hw_addr + R);                         \
1136                 if (val != (_test[pat] & W & M)) {                            \
1137                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1138                                           "0x%08X expected 0x%08X\n",         \
1139                                 R, val, (_test[pat] & W & M));                \
1140                         *data = R;                                            \
1141                         writel(before, adapter->hw.hw_addr + R);              \
1142                         return 1;                                             \
1143                 }                                                             \
1144                 writel(before, adapter->hw.hw_addr + R);                      \
1145         }                                                                     \
1146 }
1147
1148 #define REG_SET_AND_CHECK(R, M, W)                                            \
1149 {                                                                             \
1150         u32 val, before;                                                      \
1151         before = readl(adapter->hw.hw_addr + R);                              \
1152         writel((W & M), (adapter->hw.hw_addr + R));                           \
1153         val = readl(adapter->hw.hw_addr + R);                                 \
1154         if ((W & M) != (val & M)) {                                           \
1155                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1156                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1157                 *data = R;                                                    \
1158                 writel(before, (adapter->hw.hw_addr + R));                    \
1159                 return 1;                                                     \
1160         }                                                                     \
1161         writel(before, (adapter->hw.hw_addr + R));                            \
1162 }
1163
1164 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1165 {
1166         struct ixgbe_reg_test *test;
1167         u32 value, before, after;
1168         u32 i, toggle;
1169
1170         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1171                 toggle = 0x7FFFF30F;
1172                 test = reg_test_82599;
1173         } else {
1174                 toggle = 0x7FFFF3FF;
1175                 test = reg_test_82598;
1176         }
1177
1178         /*
1179          * Because the status register is such a special case,
1180          * we handle it separately from the rest of the register
1181          * tests.  Some bits are read-only, some toggle, and some
1182          * are writeable on newer MACs.
1183          */
1184         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1185         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1186         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1187         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1188         if (value != after) {
1189                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1190                         "0x%08X expected: 0x%08X\n", after, value);
1191                 *data = 1;
1192                 return 1;
1193         }
1194         /* restore previous status */
1195         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1196
1197         /*
1198          * Perform the remainder of the register test, looping through
1199          * the test table until we either fail or reach the null entry.
1200          */
1201         while (test->reg) {
1202                 for (i = 0; i < test->array_len; i++) {
1203                         switch (test->test_type) {
1204                         case PATTERN_TEST:
1205                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1206                                                 test->mask,
1207                                                 test->write);
1208                                 break;
1209                         case SET_READ_TEST:
1210                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1211                                                 test->mask,
1212                                                 test->write);
1213                                 break;
1214                         case WRITE_NO_TEST:
1215                                 writel(test->write,
1216                                        (adapter->hw.hw_addr + test->reg)
1217                                        + (i * 0x40));
1218                                 break;
1219                         case TABLE32_TEST:
1220                                 REG_PATTERN_TEST(test->reg + (i * 4),
1221                                                 test->mask,
1222                                                 test->write);
1223                                 break;
1224                         case TABLE64_TEST_LO:
1225                                 REG_PATTERN_TEST(test->reg + (i * 8),
1226                                                 test->mask,
1227                                                 test->write);
1228                                 break;
1229                         case TABLE64_TEST_HI:
1230                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1231                                                 test->mask,
1232                                                 test->write);
1233                                 break;
1234                         }
1235                 }
1236                 test++;
1237         }
1238
1239         *data = 0;
1240         return 0;
1241 }
1242
1243 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1244 {
1245         struct ixgbe_hw *hw = &adapter->hw;
1246         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1247                 *data = 1;
1248         else
1249                 *data = 0;
1250         return *data;
1251 }
1252
1253 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1254 {
1255         struct net_device *netdev = (struct net_device *) data;
1256         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1257
1258         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1259
1260         return IRQ_HANDLED;
1261 }
1262
1263 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1264 {
1265         struct net_device *netdev = adapter->netdev;
1266         u32 mask, i = 0, shared_int = true;
1267         u32 irq = adapter->pdev->irq;
1268
1269         *data = 0;
1270
1271         /* Hook up test interrupt handler just for this test */
1272         if (adapter->msix_entries) {
1273                 /* NOTE: we don't test MSI-X interrupts here, yet */
1274                 return 0;
1275         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1276                 shared_int = false;
1277                 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1278                                 netdev)) {
1279                         *data = 1;
1280                         return -1;
1281                 }
1282         } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1283                                 netdev->name, netdev)) {
1284                 shared_int = false;
1285         } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1286                                netdev->name, netdev)) {
1287                 *data = 1;
1288                 return -1;
1289         }
1290         DPRINTK(HW, INFO, "testing %s interrupt\n",
1291                 (shared_int ? "shared" : "unshared"));
1292
1293         /* Disable all the interrupts */
1294         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1295         msleep(10);
1296
1297         /* Test each interrupt */
1298         for (; i < 10; i++) {
1299                 /* Interrupt to test */
1300                 mask = 1 << i;
1301
1302                 if (!shared_int) {
1303                         /*
1304                          * Disable the interrupts to be reported in
1305                          * the cause register and then force the same
1306                          * interrupt and see if one gets posted.  If
1307                          * an interrupt was posted to the bus, the
1308                          * test failed.
1309                          */
1310                         adapter->test_icr = 0;
1311                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1312                                         ~mask & 0x00007FFF);
1313                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1314                                         ~mask & 0x00007FFF);
1315                         msleep(10);
1316
1317                         if (adapter->test_icr & mask) {
1318                                 *data = 3;
1319                                 break;
1320                         }
1321                 }
1322
1323                 /*
1324                  * Enable the interrupt to be reported in the cause
1325                  * register and then force the same interrupt and see
1326                  * if one gets posted.  If an interrupt was not posted
1327                  * to the bus, the test failed.
1328                  */
1329                 adapter->test_icr = 0;
1330                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1331                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1332                 msleep(10);
1333
1334                 if (!(adapter->test_icr &mask)) {
1335                         *data = 4;
1336                         break;
1337                 }
1338
1339                 if (!shared_int) {
1340                         /*
1341                          * Disable the other interrupts to be reported in
1342                          * the cause register and then force the other
1343                          * interrupts and see if any get posted.  If
1344                          * an interrupt was posted to the bus, the
1345                          * test failed.
1346                          */
1347                         adapter->test_icr = 0;
1348                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1349                                         ~mask & 0x00007FFF);
1350                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1351                                         ~mask & 0x00007FFF);
1352                         msleep(10);
1353
1354                         if (adapter->test_icr) {
1355                                 *data = 5;
1356                                 break;
1357                         }
1358                 }
1359         }
1360
1361         /* Disable all the interrupts */
1362         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1363         msleep(10);
1364
1365         /* Unhook test interrupt handler */
1366         free_irq(irq, netdev);
1367
1368         return *data;
1369 }
1370
1371 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1372 {
1373         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1374         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1375         struct ixgbe_hw *hw = &adapter->hw;
1376         struct pci_dev *pdev = adapter->pdev;
1377         u32 reg_ctl;
1378         int i;
1379
1380         /* shut down the DMA engines now so they can be reinitialized later */
1381
1382         /* first Rx */
1383         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1384         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1385         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1386         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1387         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1388         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1389
1390         /* now Tx */
1391         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1392         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1393         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1394         if (hw->mac.type == ixgbe_mac_82599EB) {
1395                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1396                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1397                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1398         }
1399
1400         ixgbe_reset(adapter);
1401
1402         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1403                 for (i = 0; i < tx_ring->count; i++) {
1404                         struct ixgbe_tx_buffer *buf =
1405                                         &(tx_ring->tx_buffer_info[i]);
1406                         if (buf->dma)
1407                                 pci_unmap_single(pdev, buf->dma, buf->length,
1408                                                  PCI_DMA_TODEVICE);
1409                         if (buf->skb)
1410                                 dev_kfree_skb(buf->skb);
1411                 }
1412         }
1413
1414         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1415                 for (i = 0; i < rx_ring->count; i++) {
1416                         struct ixgbe_rx_buffer *buf =
1417                                         &(rx_ring->rx_buffer_info[i]);
1418                         if (buf->dma)
1419                                 pci_unmap_single(pdev, buf->dma,
1420                                                  IXGBE_RXBUFFER_2048,
1421                                                  PCI_DMA_FROMDEVICE);
1422                         if (buf->skb)
1423                                 dev_kfree_skb(buf->skb);
1424                 }
1425         }
1426
1427         if (tx_ring->desc) {
1428                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1429                                     tx_ring->dma);
1430                 tx_ring->desc = NULL;
1431         }
1432         if (rx_ring->desc) {
1433                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1434                                     rx_ring->dma);
1435                 rx_ring->desc = NULL;
1436         }
1437
1438         kfree(tx_ring->tx_buffer_info);
1439         tx_ring->tx_buffer_info = NULL;
1440         kfree(rx_ring->rx_buffer_info);
1441         rx_ring->rx_buffer_info = NULL;
1442
1443         return;
1444 }
1445
1446 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1447 {
1448         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1449         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1450         struct pci_dev *pdev = adapter->pdev;
1451         u32 rctl, reg_data;
1452         int i, ret_val;
1453
1454         /* Setup Tx descriptor ring and Tx buffers */
1455
1456         if (!tx_ring->count)
1457                 tx_ring->count = IXGBE_DEFAULT_TXD;
1458
1459         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1460                                           sizeof(struct ixgbe_tx_buffer),
1461                                           GFP_KERNEL);
1462         if (!(tx_ring->tx_buffer_info)) {
1463                 ret_val = 1;
1464                 goto err_nomem;
1465         }
1466
1467         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1468         tx_ring->size = ALIGN(tx_ring->size, 4096);
1469         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1470                                                    &tx_ring->dma))) {
1471                 ret_val = 2;
1472                 goto err_nomem;
1473         }
1474         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1475
1476         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1477                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1478         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1479                         ((u64) tx_ring->dma >> 32));
1480         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1481                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1482         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1483         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1484
1485         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1486         reg_data |= IXGBE_HLREG0_TXPADEN;
1487         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1488
1489         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1490                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1491                 reg_data |= IXGBE_DMATXCTL_TE;
1492                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1493         }
1494         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1495         reg_data |= IXGBE_TXDCTL_ENABLE;
1496         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1497
1498         for (i = 0; i < tx_ring->count; i++) {
1499                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1500                 struct sk_buff *skb;
1501                 unsigned int size = 1024;
1502
1503                 skb = alloc_skb(size, GFP_KERNEL);
1504                 if (!skb) {
1505                         ret_val = 3;
1506                         goto err_nomem;
1507                 }
1508                 skb_put(skb, size);
1509                 tx_ring->tx_buffer_info[i].skb = skb;
1510                 tx_ring->tx_buffer_info[i].length = skb->len;
1511                 tx_ring->tx_buffer_info[i].dma =
1512                         pci_map_single(pdev, skb->data, skb->len,
1513                                        PCI_DMA_TODEVICE);
1514                 desc->read.buffer_addr =
1515                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1516                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1517                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1518                                                        IXGBE_TXD_CMD_IFCS |
1519                                                        IXGBE_TXD_CMD_RS);
1520                 desc->read.olinfo_status = 0;
1521                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1522                         desc->read.olinfo_status |=
1523                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1524
1525         }
1526
1527         /* Setup Rx Descriptor ring and Rx buffers */
1528
1529         if (!rx_ring->count)
1530                 rx_ring->count = IXGBE_DEFAULT_RXD;
1531
1532         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1533                                           sizeof(struct ixgbe_rx_buffer),
1534                                           GFP_KERNEL);
1535         if (!(rx_ring->rx_buffer_info)) {
1536                 ret_val = 4;
1537                 goto err_nomem;
1538         }
1539
1540         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1541         rx_ring->size = ALIGN(rx_ring->size, 4096);
1542         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1543                                                    &rx_ring->dma))) {
1544                 ret_val = 5;
1545                 goto err_nomem;
1546         }
1547         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1548
1549         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1550         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1551         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1552                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1553         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1554                         ((u64) rx_ring->dma >> 32));
1555         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1557         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1558
1559         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1560         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1561         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1562
1563         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1564         reg_data &= ~IXGBE_HLREG0_LPBK;
1565         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1566
1567         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1568 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1569                                                   Threshold Size mask */
1570         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1571         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1572
1573         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1574 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1575         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1576         reg_data |= adapter->hw.mac.mc_filter_type;
1577         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1578
1579         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1580         reg_data |= IXGBE_RXDCTL_ENABLE;
1581         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1582         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1583                 int j = adapter->rx_ring[0].reg_idx;
1584                 u32 k;
1585                 for (k = 0; k < 10; k++) {
1586                         if (IXGBE_READ_REG(&adapter->hw,
1587                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1588                                 break;
1589                         else
1590                                 msleep(1);
1591                 }
1592         }
1593
1594         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1595         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1596
1597         for (i = 0; i < rx_ring->count; i++) {
1598                 union ixgbe_adv_rx_desc *rx_desc =
1599                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1600                 struct sk_buff *skb;
1601
1602                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1603                 if (!skb) {
1604                         ret_val = 6;
1605                         goto err_nomem;
1606                 }
1607                 skb_reserve(skb, NET_IP_ALIGN);
1608                 rx_ring->rx_buffer_info[i].skb = skb;
1609                 rx_ring->rx_buffer_info[i].dma =
1610                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1611                                        PCI_DMA_FROMDEVICE);
1612                 rx_desc->read.pkt_addr =
1613                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1614                 memset(skb->data, 0x00, skb->len);
1615         }
1616
1617         return 0;
1618
1619 err_nomem:
1620         ixgbe_free_desc_rings(adapter);
1621         return ret_val;
1622 }
1623
1624 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1625 {
1626         struct ixgbe_hw *hw = &adapter->hw;
1627         u32 reg_data;
1628
1629         /* right now we only support MAC loopback in the driver */
1630
1631         /* Setup MAC loopback */
1632         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1633         reg_data |= IXGBE_HLREG0_LPBK;
1634         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1635
1636         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1637         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1638         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1639         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1640
1641         /* Disable Atlas Tx lanes; re-enabled in reset path */
1642         if (hw->mac.type == ixgbe_mac_82598EB) {
1643                 u8 atlas;
1644
1645                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1646                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1647                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1648
1649                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1650                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1651                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1652
1653                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1654                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1655                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1656
1657                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1658                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1659                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1660         }
1661
1662         return 0;
1663 }
1664
1665 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1666 {
1667         u32 reg_data;
1668
1669         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1670         reg_data &= ~IXGBE_HLREG0_LPBK;
1671         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1672 }
1673
1674 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1675                                       unsigned int frame_size)
1676 {
1677         memset(skb->data, 0xFF, frame_size);
1678         frame_size &= ~1;
1679         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1680         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1681         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1682 }
1683
1684 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1685                                     unsigned int frame_size)
1686 {
1687         frame_size &= ~1;
1688         if (*(skb->data + 3) == 0xFF) {
1689                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1690                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1691                         return 0;
1692                 }
1693         }
1694         return 13;
1695 }
1696
1697 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1698 {
1699         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1700         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1701         struct pci_dev *pdev = adapter->pdev;
1702         int i, j, k, l, lc, good_cnt, ret_val = 0;
1703         unsigned long time;
1704
1705         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1706
1707         /*
1708          * Calculate the loop count based on the largest descriptor ring
1709          * The idea is to wrap the largest ring a number of times using 64
1710          * send/receive pairs during each loop
1711          */
1712
1713         if (rx_ring->count <= tx_ring->count)
1714                 lc = ((tx_ring->count / 64) * 2) + 1;
1715         else
1716                 lc = ((rx_ring->count / 64) * 2) + 1;
1717
1718         k = l = 0;
1719         for (j = 0; j <= lc; j++) {
1720                 for (i = 0; i < 64; i++) {
1721                         ixgbe_create_lbtest_frame(
1722                                         tx_ring->tx_buffer_info[k].skb,
1723                                         1024);
1724                         pci_dma_sync_single_for_device(pdev,
1725                                 tx_ring->tx_buffer_info[k].dma,
1726                                 tx_ring->tx_buffer_info[k].length,
1727                                 PCI_DMA_TODEVICE);
1728                         if (unlikely(++k == tx_ring->count))
1729                                 k = 0;
1730                 }
1731                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1732                 msleep(200);
1733                 /* set the start time for the receive */
1734                 time = jiffies;
1735                 good_cnt = 0;
1736                 do {
1737                         /* receive the sent packets */
1738                         pci_dma_sync_single_for_cpu(pdev,
1739                                         rx_ring->rx_buffer_info[l].dma,
1740                                         IXGBE_RXBUFFER_2048,
1741                                         PCI_DMA_FROMDEVICE);
1742                         ret_val = ixgbe_check_lbtest_frame(
1743                                         rx_ring->rx_buffer_info[l].skb, 1024);
1744                         if (!ret_val)
1745                                 good_cnt++;
1746                         if (++l == rx_ring->count)
1747                                 l = 0;
1748                         /*
1749                          * time + 20 msecs (200 msecs on 2.4) is more than
1750                          * enough time to complete the receives, if it's
1751                          * exceeded, break and error off
1752                          */
1753                 } while (good_cnt < 64 && jiffies < (time + 20));
1754                 if (good_cnt != 64) {
1755                         /* ret_val is the same as mis-compare */
1756                         ret_val = 13;
1757                         break;
1758                 }
1759                 if (jiffies >= (time + 20)) {
1760                         /* Error code for time out error */
1761                         ret_val = 14;
1762                         break;
1763                 }
1764         }
1765
1766         return ret_val;
1767 }
1768
1769 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1770 {
1771         *data = ixgbe_setup_desc_rings(adapter);
1772         if (*data)
1773                 goto out;
1774         *data = ixgbe_setup_loopback_test(adapter);
1775         if (*data)
1776                 goto err_loopback;
1777         *data = ixgbe_run_loopback_test(adapter);
1778         ixgbe_loopback_cleanup(adapter);
1779
1780 err_loopback:
1781         ixgbe_free_desc_rings(adapter);
1782 out:
1783         return *data;
1784 }
1785
1786 static void ixgbe_diag_test(struct net_device *netdev,
1787                             struct ethtool_test *eth_test, u64 *data)
1788 {
1789         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1790         bool if_running = netif_running(netdev);
1791
1792         set_bit(__IXGBE_TESTING, &adapter->state);
1793         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1794                 /* Offline tests */
1795
1796                 DPRINTK(HW, INFO, "offline testing starting\n");
1797
1798                 /* Link test performed before hardware reset so autoneg doesn't
1799                  * interfere with test result */
1800                 if (ixgbe_link_test(adapter, &data[4]))
1801                         eth_test->flags |= ETH_TEST_FL_FAILED;
1802
1803                 if (if_running)
1804                         /* indicate we're in test mode */
1805                         dev_close(netdev);
1806                 else
1807                         ixgbe_reset(adapter);
1808
1809                 DPRINTK(HW, INFO, "register testing starting\n");
1810                 if (ixgbe_reg_test(adapter, &data[0]))
1811                         eth_test->flags |= ETH_TEST_FL_FAILED;
1812
1813                 ixgbe_reset(adapter);
1814                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1815                 if (ixgbe_eeprom_test(adapter, &data[1]))
1816                         eth_test->flags |= ETH_TEST_FL_FAILED;
1817
1818                 ixgbe_reset(adapter);
1819                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1820                 if (ixgbe_intr_test(adapter, &data[2]))
1821                         eth_test->flags |= ETH_TEST_FL_FAILED;
1822
1823                 ixgbe_reset(adapter);
1824                 DPRINTK(HW, INFO, "loopback testing starting\n");
1825                 if (ixgbe_loopback_test(adapter, &data[3]))
1826                         eth_test->flags |= ETH_TEST_FL_FAILED;
1827
1828                 ixgbe_reset(adapter);
1829
1830                 clear_bit(__IXGBE_TESTING, &adapter->state);
1831                 if (if_running)
1832                         dev_open(netdev);
1833         } else {
1834                 DPRINTK(HW, INFO, "online testing starting\n");
1835                 /* Online tests */
1836                 if (ixgbe_link_test(adapter, &data[4]))
1837                         eth_test->flags |= ETH_TEST_FL_FAILED;
1838
1839                 /* Online tests aren't run; pass by default */
1840                 data[0] = 0;
1841                 data[1] = 0;
1842                 data[2] = 0;
1843                 data[3] = 0;
1844
1845                 clear_bit(__IXGBE_TESTING, &adapter->state);
1846         }
1847         msleep_interruptible(4 * 1000);
1848 }
1849
1850 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1851                                struct ethtool_wolinfo *wol)
1852 {
1853         struct ixgbe_hw *hw = &adapter->hw;
1854         int retval = 1;
1855
1856         switch(hw->device_id) {
1857         case IXGBE_DEV_ID_82599_KX4:
1858                 retval = 0;
1859                 break;
1860         default:
1861                 wol->supported = 0;
1862         }
1863
1864         return retval;
1865 }
1866
1867 static void ixgbe_get_wol(struct net_device *netdev,
1868                           struct ethtool_wolinfo *wol)
1869 {
1870         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1871
1872         wol->supported = WAKE_UCAST | WAKE_MCAST |
1873                          WAKE_BCAST | WAKE_MAGIC;
1874         wol->wolopts = 0;
1875
1876         if (ixgbe_wol_exclusion(adapter, wol) ||
1877             !device_can_wakeup(&adapter->pdev->dev))
1878                 return;
1879
1880         if (adapter->wol & IXGBE_WUFC_EX)
1881                 wol->wolopts |= WAKE_UCAST;
1882         if (adapter->wol & IXGBE_WUFC_MC)
1883                 wol->wolopts |= WAKE_MCAST;
1884         if (adapter->wol & IXGBE_WUFC_BC)
1885                 wol->wolopts |= WAKE_BCAST;
1886         if (adapter->wol & IXGBE_WUFC_MAG)
1887                 wol->wolopts |= WAKE_MAGIC;
1888
1889         return;
1890 }
1891
1892 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1893 {
1894         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1895
1896         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1897                 return -EOPNOTSUPP;
1898
1899         if (ixgbe_wol_exclusion(adapter, wol))
1900                 return wol->wolopts ? -EOPNOTSUPP : 0;
1901
1902         adapter->wol = 0;
1903
1904         if (wol->wolopts & WAKE_UCAST)
1905                 adapter->wol |= IXGBE_WUFC_EX;
1906         if (wol->wolopts & WAKE_MCAST)
1907                 adapter->wol |= IXGBE_WUFC_MC;
1908         if (wol->wolopts & WAKE_BCAST)
1909                 adapter->wol |= IXGBE_WUFC_BC;
1910         if (wol->wolopts & WAKE_MAGIC)
1911                 adapter->wol |= IXGBE_WUFC_MAG;
1912
1913         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1914
1915         return 0;
1916 }
1917
1918 static int ixgbe_nway_reset(struct net_device *netdev)
1919 {
1920         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1921
1922         if (netif_running(netdev))
1923                 ixgbe_reinit_locked(adapter);
1924
1925         return 0;
1926 }
1927
1928 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1929 {
1930         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1931         struct ixgbe_hw *hw = &adapter->hw;
1932         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1933         u32 i;
1934
1935         if (!data || data > 300)
1936                 data = 300;
1937
1938         for (i = 0; i < (data * 1000); i += 400) {
1939                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1940                 msleep_interruptible(200);
1941                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1942                 msleep_interruptible(200);
1943         }
1944
1945         /* Restore LED settings */
1946         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1947
1948         return 0;
1949 }
1950
1951 static int ixgbe_get_coalesce(struct net_device *netdev,
1952                               struct ethtool_coalesce *ec)
1953 {
1954         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1955
1956         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1957
1958         /* only valid if in constant ITR mode */
1959         switch (adapter->rx_itr_setting) {
1960         case 0:
1961                 /* throttling disabled */
1962                 ec->rx_coalesce_usecs = 0;
1963                 break;
1964         case 1:
1965                 /* dynamic ITR mode */
1966                 ec->rx_coalesce_usecs = 1;
1967                 break;
1968         default:
1969                 /* fixed interrupt rate mode */
1970                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
1971                 break;
1972         }
1973
1974         /* only valid if in constant ITR mode */
1975         switch (adapter->tx_itr_setting) {
1976         case 0:
1977                 /* throttling disabled */
1978                 ec->tx_coalesce_usecs = 0;
1979                 break;
1980         case 1:
1981                 /* dynamic ITR mode */
1982                 ec->tx_coalesce_usecs = 1;
1983                 break;
1984         default:
1985                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1986                 break;
1987         }
1988
1989         return 0;
1990 }
1991
1992 static int ixgbe_set_coalesce(struct net_device *netdev,
1993                               struct ethtool_coalesce *ec)
1994 {
1995         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1996         struct ixgbe_q_vector *q_vector;
1997         int i;
1998
1999         /*
2000          * don't accept tx specific changes if we've got mixed RxTx vectors
2001          * test and jump out here if needed before changing the rx numbers
2002          */
2003         if ((1000000/ec->tx_coalesce_usecs) != adapter->tx_eitr_param &&
2004             adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2005                 return -EINVAL;
2006
2007         if (ec->tx_max_coalesced_frames_irq)
2008                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
2009
2010         if (ec->rx_coalesce_usecs > 1) {
2011                 /* check the limits */
2012                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2013                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2014                         return -EINVAL;
2015
2016                 /* store the value in ints/second */
2017                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2018
2019                 /* static value of interrupt rate */
2020                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2021                 /* clear the lower bit as its used for dynamic state */
2022                 adapter->rx_itr_setting &= ~1;
2023         } else if (ec->rx_coalesce_usecs == 1) {
2024                 /* 1 means dynamic mode */
2025                 adapter->rx_eitr_param = 20000;
2026                 adapter->rx_itr_setting = 1;
2027         } else {
2028                 /*
2029                  * any other value means disable eitr, which is best
2030                  * served by setting the interrupt rate very high
2031                  */
2032                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2033                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2034                 else
2035                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2036                 adapter->rx_itr_setting = 0;
2037         }
2038
2039         if (ec->tx_coalesce_usecs > 1) {
2040                 /* check the limits */
2041                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2042                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2043                         return -EINVAL;
2044
2045                 /* store the value in ints/second */
2046                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2047
2048                 /* static value of interrupt rate */
2049                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2050
2051                 /* clear the lower bit as its used for dynamic state */
2052                 adapter->tx_itr_setting &= ~1;
2053         } else if (ec->tx_coalesce_usecs == 1) {
2054                 /* 1 means dynamic mode */
2055                 adapter->tx_eitr_param = 10000;
2056                 adapter->tx_itr_setting = 1;
2057         } else {
2058                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2059                 adapter->tx_itr_setting = 0;
2060         }
2061
2062         /* MSI/MSIx Interrupt Mode */
2063         if (adapter->flags &
2064             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2065                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2066                 for (i = 0; i < num_vectors; i++) {
2067                         q_vector = adapter->q_vector[i];
2068                         if (q_vector->txr_count && !q_vector->rxr_count)
2069                                 /* tx only */
2070                                 q_vector->eitr = adapter->tx_eitr_param;
2071                         else
2072                                 /* rx only or mixed */
2073                                 q_vector->eitr = adapter->rx_eitr_param;
2074                         ixgbe_write_eitr(q_vector);
2075                 }
2076         /* Legacy Interrupt Mode */
2077         } else {
2078                 q_vector = adapter->q_vector[0];
2079                 q_vector->eitr = adapter->rx_eitr_param;
2080                 ixgbe_write_eitr(q_vector);
2081         }
2082
2083         return 0;
2084 }
2085
2086 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2087 {
2088         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2089
2090         ethtool_op_set_flags(netdev, data);
2091
2092         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2093                 return 0;
2094
2095         /* if state changes we need to update adapter->flags and reset */
2096         if ((!!(data & ETH_FLAG_LRO)) !=
2097             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2098                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2099                 if (netif_running(netdev))
2100                         ixgbe_reinit_locked(adapter);
2101                 else
2102                         ixgbe_reset(adapter);
2103         }
2104         return 0;
2105
2106 }
2107
2108 static const struct ethtool_ops ixgbe_ethtool_ops = {
2109         .get_settings           = ixgbe_get_settings,
2110         .set_settings           = ixgbe_set_settings,
2111         .get_drvinfo            = ixgbe_get_drvinfo,
2112         .get_regs_len           = ixgbe_get_regs_len,
2113         .get_regs               = ixgbe_get_regs,
2114         .get_wol                = ixgbe_get_wol,
2115         .set_wol                = ixgbe_set_wol,
2116         .nway_reset             = ixgbe_nway_reset,
2117         .get_link               = ethtool_op_get_link,
2118         .get_eeprom_len         = ixgbe_get_eeprom_len,
2119         .get_eeprom             = ixgbe_get_eeprom,
2120         .get_ringparam          = ixgbe_get_ringparam,
2121         .set_ringparam          = ixgbe_set_ringparam,
2122         .get_pauseparam         = ixgbe_get_pauseparam,
2123         .set_pauseparam         = ixgbe_set_pauseparam,
2124         .get_rx_csum            = ixgbe_get_rx_csum,
2125         .set_rx_csum            = ixgbe_set_rx_csum,
2126         .get_tx_csum            = ixgbe_get_tx_csum,
2127         .set_tx_csum            = ixgbe_set_tx_csum,
2128         .get_sg                 = ethtool_op_get_sg,
2129         .set_sg                 = ethtool_op_set_sg,
2130         .get_msglevel           = ixgbe_get_msglevel,
2131         .set_msglevel           = ixgbe_set_msglevel,
2132         .get_tso                = ethtool_op_get_tso,
2133         .set_tso                = ixgbe_set_tso,
2134         .self_test              = ixgbe_diag_test,
2135         .get_strings            = ixgbe_get_strings,
2136         .phys_id                = ixgbe_phys_id,
2137         .get_sset_count         = ixgbe_get_sset_count,
2138         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2139         .get_coalesce           = ixgbe_get_coalesce,
2140         .set_coalesce           = ixgbe_set_coalesce,
2141         .get_flags              = ethtool_op_get_flags,
2142         .set_flags              = ixgbe_set_flags,
2143 };
2144
2145 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2146 {
2147         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2148 }