1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
147 struct ixgbe_hw *hw = &adapter->hw;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
170 /* take a breather then clean up driver data */
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
180 struct ixgbe_reg_info {
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
319 if (!netif_msg_hw(adapter))
322 /* Print netdevice Info */
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
367 /* Transmit Descriptor Formats
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
408 printk(KERN_CONT "\n");
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
419 /* Print RX Rings Summary */
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
430 if (!netif_msg_rx_status(adapter))
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
435 /* Advanced Receive Descriptor (Read) Format
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
444 * Advanced Receive Descriptor (Write-Back) Format
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
478 rx_buffer_info->skb);
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
510 printk(KERN_CONT "\n");
519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
605 struct ixgbe_tx_buffer
608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
610 dma_unmap_page(&adapter->pdev->dev,
612 tx_buffer_info->length,
615 dma_unmap_single(&adapter->pdev->dev,
617 tx_buffer_info->length,
619 tx_buffer_info->dma = 0;
621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
625 tx_buffer_info->time_stamp = 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
637 * Returns : true if in xon state (currently not paused)
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
640 struct ixgbe_ring *tx_ring)
642 u32 txoff = IXGBE_TFCS_TXOFF;
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter->dcb_cfg.pfc_mode_enable) {
647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
653 txoff = IXGBE_TFCS_TXOFF0;
655 case ixgbe_mac_82599EB:
657 txoff = IXGBE_TFCS_TXOFF;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
685 struct ixgbe_ring *tx_ring,
688 struct ixgbe_hw *hw = &adapter->hw;
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter->detect_tx_hung = false;
693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
695 ixgbe_tx_xon_state(adapter, tx_ring)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
699 e_err(drv, "Detected Tx Unit Hang\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
727 static void ixgbe_tx_timeout(struct net_device *netdev);
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
735 struct ixgbe_ring *tx_ring)
737 struct ixgbe_adapter *adapter = q_vector->adapter;
738 struct net_device *netdev = adapter->netdev;
739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
742 unsigned int total_bytes = 0, total_packets = 0;
744 i = tx_ring->next_to_clean;
745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
749 (count < tx_ring->work_limit)) {
750 bool cleaned = false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned; count++) {
754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
756 cleaned = (i == eop);
757 skb = tx_buffer_info->skb;
759 if (cleaned && skb) {
760 unsigned int segs, bytecount;
761 unsigned int hlen = skb_headlen(skb);
763 /* gso_segs is currently only valid for tcp */
764 segs = skb_shinfo(skb)->gso_segs ?: 1;
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount = ((segs - 1) * hlen) + skb->len;
779 total_packets += segs;
780 total_bytes += bytecount;
783 ixgbe_unmap_and_free_tx_resource(adapter,
786 tx_desc->wb.status = 0;
789 if (i == tx_ring->count)
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
797 tx_ring->next_to_clean = i;
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
809 ++tx_ring->restart_queue;
813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 tx_ring->stats.packets += total_packets;
829 tx_ring->stats.bytes += total_bytes;
830 return (count < tx_ring->work_limit);
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
835 struct ixgbe_ring *rx_ring)
839 int q = rx_ring->reg_idx;
841 if (rx_ring->cpu != cpu) {
842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *tx_ring)
867 int q = tx_ring->reg_idx;
868 struct ixgbe_hw *hw = &adapter->hw;
870 if (tx_ring->cpu != cpu) {
871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
900 for (i = 0; i < adapter->num_tx_queues; i++) {
901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
904 for (i = 0; i < adapter->num_rx_queues; i++) {
905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
910 static int __ixgbe_notify_dca(struct device *dev, void *data)
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
917 case DCA_PROVIDER_ADD:
918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
921 if (dca_add_requester(dev) == 0) {
922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
923 ixgbe_setup_dca(adapter);
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
939 #endif /* CONFIG_IXGBE_DCA */
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
962 napi_gro_receive(napi, skb);
964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
978 union ixgbe_adv_rx_desc *rx_desc,
981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
983 skb->ip_summed = CHECKSUM_NONE;
985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
992 adapter->hw_csum_rx_error++;
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1010 adapter->hw_csum_rx_error++;
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036 struct ixgbe_ring *rx_ring,
1039 struct net_device *netdev = adapter->netdev;
1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
1042 struct ixgbe_rx_buffer *bi;
1044 unsigned int bufsz = rx_ring->rx_buf_len;
1046 i = rx_ring->next_to_use;
1047 bi = &rx_ring->rx_buffer_info[i];
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1052 if (!bi->page_dma &&
1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1055 bi->page = netdev_alloc_page(netdev);
1057 adapter->alloc_rx_page_failed++;
1060 bi->page_offset = 0;
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1078 adapter->alloc_rx_buff_failed++;
1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1086 bi->dma = dma_map_single(&pdev->dev,
1088 rx_ring->rx_buf_len,
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1101 if (i == rx_ring->count)
1103 bi = &rx_ring->rx_buffer_info[i];
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1110 i = (rx_ring->count - 1);
1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
1136 * @count: pointer to number of packets coalesced in this context
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1145 unsigned int frag_list_size = 0;
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1155 skb_shinfo(skb)->frag_list = skb->next;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1163 struct ixgbe_rsc_cb {
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
1174 struct ixgbe_adapter *adapter = q_vector->adapter;
1175 struct net_device *netdev = adapter->netdev;
1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
1180 unsigned int i, rsc_count = 0;
1183 bool cleaned = false;
1184 int cleaned_count = 0;
1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1188 #endif /* IXGBE_FCOE */
1190 i = rx_ring->next_to_clean;
1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1195 while (staterr & IXGBE_RXD_STAT_DD) {
1197 if (*work_done >= work_to_do)
1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
1211 len = le16_to_cpu(rx_desc->wb.upper.length);
1215 skb = rx_buffer_info->skb;
1216 prefetch(skb->data);
1217 rx_buffer_info->skb = NULL;
1219 if (rx_buffer_info->dma) {
1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1233 dma_unmap_single(&pdev->dev,
1234 rx_buffer_info->dma,
1235 rx_ring->rx_buf_len,
1238 rx_buffer_info->dma = 0;
1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1255 get_page(rx_buffer_info->page);
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1263 if (i == rx_ring->count)
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1281 if (staterr & IXGBE_RXD_STAT_EOP) {
1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
1288 rx_ring->rx_buf_len,
1290 IXGBE_RSC_CB(skb)->dma = 0;
1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1311 rx_ring->non_eop_descs++;
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1334 #endif /* IXGBE_FCOE */
1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1338 rx_desc->wb.upper.status_error = 0;
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1346 /* use prefetched values */
1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1372 #endif /* IXGBE_FCOE */
1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403 q_vector = adapter->q_vector[v_idx];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx = find_first_bit(q_vector->rxr_idx,
1406 adapter->num_rx_queues);
1408 for (i = 0; i < q_vector->rxr_count; i++) {
1409 j = adapter->rx_ring[r_idx]->reg_idx;
1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
1411 r_idx = find_next_bit(q_vector->rxr_idx,
1412 adapter->num_rx_queues,
1415 r_idx = find_first_bit(q_vector->txr_idx,
1416 adapter->num_tx_queues);
1418 for (i = 0; i < q_vector->txr_count; i++) {
1419 j = adapter->tx_ring[r_idx]->reg_idx;
1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
1421 r_idx = find_next_bit(q_vector->txr_idx,
1422 adapter->num_tx_queues,
1426 if (q_vector->txr_count && !q_vector->rxr_count)
1428 q_vector->eitr = adapter->tx_eitr_param;
1429 else if (q_vector->rxr_count)
1431 q_vector->eitr = adapter->rx_eitr_param;
1433 ixgbe_write_eitr(q_vector);
1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1443 /* set up to autoclear timer, and the vectors */
1444 mask = IXGBE_EIMS_ENABLE_MASK;
1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1454 enum latency_range {
1458 latency_invalid = 255
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
1483 unsigned int retval = itr_setting;
1488 goto update_itr_done;
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
1523 * @q_vector: structure containing interrupt and ring information
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1531 struct ixgbe_adapter *adapter = q_vector->adapter;
1532 struct ixgbe_hw *hw = &adapter->hw;
1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
1562 u8 current_itr, ret_itr;
1564 struct ixgbe_ring *rx_ring, *tx_ring;
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
1568 tx_ring = adapter->tx_ring[r_idx];
1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576 q_vector->tx_itr - 1 : ret_itr);
1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
1583 rx_ring = adapter->rx_ring[r_idx];
1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591 q_vector->rx_itr - 1 : ret_itr);
1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1612 if (new_itr != q_vector->eitr) {
1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
1619 ixgbe_write_eitr(q_vector);
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1639 bool link_up = false;
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
1658 "persists, power off the system and replace the "
1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1667 struct ixgbe_hw *hw = &adapter->hw;
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1679 struct ixgbe_hw *hw = &adapter->hw;
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1690 /* Interrupt isn't for us... */
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1697 struct ixgbe_hw *hw = &adapter->hw;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704 IXGBE_WRITE_FLUSH(hw);
1705 schedule_work(&adapter->watchdog_task);
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 ixgbe_check_sfp_event(adapter, eicr);
1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
1749 adapter->tx_ring[i];
1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1776 /* skip the flush */
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1793 /* skip the flush */
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
1800 struct ixgbe_ring *tx_ring;
1803 if (!q_vector->txr_count)
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
1808 tx_ring = adapter->tx_ring[r_idx];
1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1815 /* EIAM disabled interrupts (on this vector) for us */
1816 napi_schedule(&q_vector->napi);
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1824 * @data: pointer to our q_vector struct for this interrupt vector
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
1830 struct ixgbe_ring *rx_ring;
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835 for (i = 0; i < q_vector->rxr_count; i++) {
1836 rx_ring = adapter->rx_ring[r_idx];
1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1843 if (!q_vector->rxr_count)
1846 /* disable interrupts on this vector only */
1847 /* EIAM disabled interrupts (on this vector) for us */
1848 napi_schedule(&q_vector->napi);
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
1866 ring = adapter->tx_ring[r_idx];
1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
1875 ring = adapter->rx_ring[r_idx];
1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1882 /* EIAM disabled interrupts (on this vector) for us */
1883 napi_schedule(&q_vector->napi);
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1893 * This function is optimized for cleaning one queue only on a single
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1898 struct ixgbe_q_vector *q_vector =
1899 container_of(napi, struct ixgbe_q_vector, napi);
1900 struct ixgbe_adapter *adapter = q_vector->adapter;
1901 struct ixgbe_ring *rx_ring = NULL;
1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906 rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909 ixgbe_update_rx_dca(adapter, rx_ring);
1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
1916 napi_complete(napi);
1917 if (adapter->rx_itr_setting & 1)
1918 ixgbe_set_itr_msix(q_vector);
1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1932 * This function will clean more than one rx queue associated with a
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
1940 struct ixgbe_ring *ring = NULL;
1941 int work_done = 0, i;
1943 bool tx_clean_complete = true;
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
1947 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
1963 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966 ixgbe_update_rx_dca(adapter, ring);
1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974 ring = adapter->rx_ring[r_idx];
1975 /* If all Rx work done, exit the polling mode */
1976 if (work_done < budget) {
1977 napi_complete(napi);
1978 if (adapter->rx_itr_setting & 1)
1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1994 * This function is optimized for cleaning one queue only on a single
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007 tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2016 /* If all Tx work done, exit the polling mode */
2017 if (work_done < budget) {
2018 napi_complete(napi);
2019 if (adapter->tx_itr_setting & 1)
2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
2138 for (vector = 0; vector < q_vectors; vector++) {
2139 handler = SET_HANDLER(adapter->q_vector[vector]);
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2153 err = request_irq(adapter->msix_entries[vector].vector,
2154 handler, 0, adapter->name[vector],
2155 adapter->q_vector[vector]);
2157 e_err(probe, "request_irq failed for MSIX interrupt "
2158 "Error: %d\n", err);
2159 goto free_queue_irqs;
2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168 goto free_queue_irqs;
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
2176 adapter->q_vector[i]);
2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2189 u32 new_itr = q_vector->eitr;
2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2219 if (new_itr != q_vector->eitr) {
2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
2226 ixgbe_write_eitr(q_vector);
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244 mask |= IXGBE_EIMS_ECC;
2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255 ixgbe_irq_enable_queues(adapter, ~0);
2256 IXGBE_WRITE_FLUSH(&adapter->hw);
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2265 * ixgbe_intr - legacy mode Interrupt Handler
2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
2291 return IRQ_NONE; /* Not our interrupt */
2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2300 ixgbe_check_fan_failure(adapter, eicr);
2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
2305 if (napi_schedule_prep(&(q_vector->napi))) {
2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
2310 /* would disable interrupts here but EIAM disabled it */
2311 __napi_schedule(&(q_vector->napi));
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2321 for (i = 0; i < q_vectors; i++) {
2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2339 struct net_device *netdev = adapter->netdev;
2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346 netdev->name, netdev);
2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349 netdev->name, netdev);
2353 e_err(probe, "request_irq failed, Error %d\n", err);
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2360 struct net_device *netdev = adapter->netdev;
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2365 q_vectors = adapter->num_msix_vectors;
2368 free_irq(adapter->msix_entries[i].vector, netdev);
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
2373 adapter->q_vector[i]);
2376 ixgbe_reset_q_vectors(adapter);
2378 free_irq(adapter->pdev->irq, netdev);
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2403 synchronize_irq(adapter->pdev->irq);
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2413 struct ixgbe_hw *hw = &adapter->hw;
2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
2428 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2429 * @adapter: board private structure
2431 * Configure the Tx unit of the MAC after a reset.
2433 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2436 struct ixgbe_hw *hw = &adapter->hw;
2437 u32 i, j, tdlen, txctrl;
2439 /* Setup the HW Tx Head and Tail descriptor pointers */
2440 for (i = 0; i < adapter->num_tx_queues; i++) {
2441 struct ixgbe_ring *ring = adapter->tx_ring[i];
2444 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2445 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2446 (tdba & DMA_BIT_MASK(32)));
2447 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2448 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2449 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2450 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2451 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2452 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2454 * Disable Tx Head Writeback RO bit, since this hoses
2455 * bookkeeping if things aren't delivered in order.
2457 switch (hw->mac.type) {
2458 case ixgbe_mac_82598EB:
2459 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2461 case ixgbe_mac_82599EB:
2463 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2466 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2467 switch (hw->mac.type) {
2468 case ixgbe_mac_82598EB:
2469 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2471 case ixgbe_mac_82599EB:
2473 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2478 if (hw->mac.type == ixgbe_mac_82599EB) {
2482 /* disable the arbiter while setting MTQC */
2483 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2484 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2485 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2487 /* set transmit pool layout */
2488 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2489 switch (adapter->flags & mask) {
2491 case (IXGBE_FLAG_SRIOV_ENABLED):
2492 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2493 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2496 case (IXGBE_FLAG_DCB_ENABLED):
2497 /* We enable 8 traffic classes, DCB only */
2498 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2499 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2503 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2507 /* re-eable the arbiter */
2508 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2509 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2513 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2515 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2516 struct ixgbe_ring *rx_ring)
2520 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2522 index = rx_ring->reg_idx;
2523 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2525 mask = (unsigned long) feature[RING_F_RSS].mask;
2526 index = index & mask;
2528 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2530 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2531 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2533 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2534 IXGBE_SRRCTL_BSIZEHDR_MASK;
2536 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2537 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2538 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2540 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2542 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2544 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2545 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2546 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2552 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2557 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2560 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2561 #ifdef CONFIG_IXGBE_DCB
2562 | IXGBE_FLAG_DCB_ENABLED
2564 | IXGBE_FLAG_SRIOV_ENABLED
2568 case (IXGBE_FLAG_RSS_ENABLED):
2569 mrqc = IXGBE_MRQC_RSSEN;
2571 case (IXGBE_FLAG_SRIOV_ENABLED):
2572 mrqc = IXGBE_MRQC_VMDQEN;
2574 #ifdef CONFIG_IXGBE_DCB
2575 case (IXGBE_FLAG_DCB_ENABLED):
2576 mrqc = IXGBE_MRQC_RT8TCEN;
2578 #endif /* CONFIG_IXGBE_DCB */
2587 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2588 * @adapter: address of board private structure
2589 * @index: index of ring to set
2591 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2593 struct ixgbe_ring *rx_ring;
2594 struct ixgbe_hw *hw = &adapter->hw;
2599 rx_ring = adapter->rx_ring[index];
2600 j = rx_ring->reg_idx;
2601 rx_buf_len = rx_ring->rx_buf_len;
2602 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2603 rscctrl |= IXGBE_RSCCTL_RSCEN;
2605 * we must limit the number of descriptors so that the
2606 * total size of max desc * buf_len is not greater
2609 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2610 #if (MAX_SKB_FRAGS > 16)
2611 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2612 #elif (MAX_SKB_FRAGS > 8)
2613 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2614 #elif (MAX_SKB_FRAGS > 4)
2615 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2617 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2620 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2621 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2622 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2623 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2625 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2627 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2631 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2632 * @adapter: board private structure
2634 * Configure the Rx unit of the MAC after a reset.
2636 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2639 struct ixgbe_hw *hw = &adapter->hw;
2640 struct ixgbe_ring *rx_ring;
2641 struct net_device *netdev = adapter->netdev;
2642 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2644 u32 rdlen, rxctrl, rxcsum;
2645 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2646 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2647 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2649 u32 reta = 0, mrqc = 0;
2653 /* Decide whether to use packet split mode or not */
2654 /* Do not use packet split if we're in SR-IOV Mode */
2655 if (!adapter->num_vfs)
2656 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2658 /* Set the RX buffer length according to the mode */
2659 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2660 rx_buf_len = IXGBE_RX_HDR_SIZE;
2661 if (hw->mac.type == ixgbe_mac_82599EB) {
2662 /* PSRTYPE must be initialized in 82599 */
2663 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2664 IXGBE_PSRTYPE_UDPHDR |
2665 IXGBE_PSRTYPE_IPV4HDR |
2666 IXGBE_PSRTYPE_IPV6HDR |
2667 IXGBE_PSRTYPE_L2HDR;
2669 IXGBE_PSRTYPE(adapter->num_vfs),
2673 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2674 (netdev->mtu <= ETH_DATA_LEN))
2675 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2677 rx_buf_len = ALIGN(max_frame, 1024);
2680 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2681 fctrl |= IXGBE_FCTRL_BAM;
2682 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2683 fctrl |= IXGBE_FCTRL_PMCF;
2684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2686 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2687 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2688 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2690 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2692 if (netdev->features & NETIF_F_FCOE_MTU)
2693 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2695 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2697 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2698 /* disable receives while setting up the descriptors */
2699 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2700 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2703 * Setup the HW Rx Head and Tail Descriptor Pointers and
2704 * the Base and Length of the Rx Descriptor Ring
2706 for (i = 0; i < adapter->num_rx_queues; i++) {
2707 rx_ring = adapter->rx_ring[i];
2708 rdba = rx_ring->dma;
2709 j = rx_ring->reg_idx;
2710 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2711 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2712 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2713 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2714 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2715 rx_ring->head = IXGBE_RDH(j);
2716 rx_ring->tail = IXGBE_RDT(j);
2717 rx_ring->rx_buf_len = rx_buf_len;
2719 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2720 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2722 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2725 if (netdev->features & NETIF_F_FCOE_MTU) {
2726 struct ixgbe_ring_feature *f;
2727 f = &adapter->ring_feature[RING_F_FCOE];
2728 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2729 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2730 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2731 rx_ring->rx_buf_len =
2732 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2736 #endif /* IXGBE_FCOE */
2737 ixgbe_configure_srrctl(adapter, rx_ring);
2740 if (hw->mac.type == ixgbe_mac_82598EB) {
2742 * For VMDq support of different descriptor types or
2743 * buffer sizes through the use of multiple SRRCTL
2744 * registers, RDRXCTL.MVMEN must be set to 1
2746 * also, the manual doesn't mention it clearly but DCA hints
2747 * will only use queue 0's tags unless this bit is set. Side
2748 * effects of setting this bit are only that SRRCTL must be
2749 * fully programmed [0..15]
2751 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2752 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2753 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2756 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2758 u32 reg_offset, vf_shift;
2759 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2760 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2761 | IXGBE_VT_CTL_REPLEN;
2762 vt_reg_bits |= (adapter->num_vfs <<
2763 IXGBE_VT_CTL_POOL_SHIFT);
2764 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2765 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2767 vf_shift = adapter->num_vfs % 32;
2768 reg_offset = adapter->num_vfs / 32;
2769 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2770 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2771 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2772 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2773 /* Enable only the PF's pool for Tx/Rx */
2774 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2775 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2776 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2777 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2780 /* Program MRQC for the distribution of queues */
2781 mrqc = ixgbe_setup_mrqc(adapter);
2783 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2784 /* Fill out redirection table */
2785 for (i = 0, j = 0; i < 128; i++, j++) {
2786 if (j == adapter->ring_feature[RING_F_RSS].indices)
2788 /* reta = 4-byte sliding window of
2789 * 0x00..(indices-1)(indices-1)00..etc. */
2790 reta = (reta << 8) | (j * 0x11);
2792 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2795 /* Fill out hash function seeds */
2796 for (i = 0; i < 10; i++)
2797 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2799 if (hw->mac.type == ixgbe_mac_82598EB)
2800 mrqc |= IXGBE_MRQC_RSSEN;
2801 /* Perform hash on these packet types */
2802 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2803 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2804 | IXGBE_MRQC_RSS_FIELD_IPV6
2805 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2807 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2809 if (adapter->num_vfs) {
2812 /* Map PF MAC address in RAR Entry 0 to first pool
2814 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2816 /* Set up VF register offsets for selected VT Mode, i.e.
2817 * 64 VFs for SR-IOV */
2818 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2819 reg |= IXGBE_GCR_EXT_SRIOV;
2820 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2823 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2825 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2826 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2827 /* Disable indicating checksum in descriptor, enables
2829 rxcsum |= IXGBE_RXCSUM_PCSD;
2831 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2832 /* Enable IPv4 payload checksum for UDP fragments
2833 * if PCSD is not set */
2834 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2837 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2839 if (hw->mac.type == ixgbe_mac_82599EB) {
2840 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2841 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2842 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2843 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2846 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2847 /* Enable 82599 HW-RSC */
2848 for (i = 0; i < adapter->num_rx_queues; i++)
2849 ixgbe_configure_rscctl(adapter, i);
2851 /* Disable RSC for ACK packets */
2852 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2853 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2857 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2860 struct ixgbe_hw *hw = &adapter->hw;
2861 int pool_ndx = adapter->num_vfs;
2863 /* add VID to filter table */
2864 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2867 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2869 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2870 struct ixgbe_hw *hw = &adapter->hw;
2871 int pool_ndx = adapter->num_vfs;
2873 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2874 ixgbe_irq_disable(adapter);
2876 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2878 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2879 ixgbe_irq_enable(adapter);
2881 /* remove VID from filter table */
2882 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2886 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2887 * @adapter: driver data
2889 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2891 struct ixgbe_hw *hw = &adapter->hw;
2892 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2895 switch (hw->mac.type) {
2896 case ixgbe_mac_82598EB:
2897 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2898 #ifdef CONFIG_IXGBE_DCB
2899 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2900 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2902 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2903 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2905 case ixgbe_mac_82599EB:
2906 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2907 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2908 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2909 #ifdef CONFIG_IXGBE_DCB
2910 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2913 for (i = 0; i < adapter->num_rx_queues; i++) {
2914 j = adapter->rx_ring[i]->reg_idx;
2915 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2916 vlnctrl &= ~IXGBE_RXDCTL_VME;
2917 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2926 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2927 * @adapter: driver data
2929 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2931 struct ixgbe_hw *hw = &adapter->hw;
2932 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2935 switch (hw->mac.type) {
2936 case ixgbe_mac_82598EB:
2937 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2938 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2939 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2941 case ixgbe_mac_82599EB:
2942 vlnctrl |= IXGBE_VLNCTRL_VFE;
2943 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2944 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2945 for (i = 0; i < adapter->num_rx_queues; i++) {
2946 j = adapter->rx_ring[i]->reg_idx;
2947 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2948 vlnctrl |= IXGBE_RXDCTL_VME;
2949 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2957 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2958 struct vlan_group *grp)
2960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2962 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2963 ixgbe_irq_disable(adapter);
2964 adapter->vlgrp = grp;
2967 * For a DCB driver, always enable VLAN tag stripping so we can
2968 * still receive traffic from a DCB-enabled host even if we're
2971 ixgbe_vlan_filter_enable(adapter);
2973 ixgbe_vlan_rx_add_vid(netdev, 0);
2975 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2976 ixgbe_irq_enable(adapter);
2979 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2981 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2983 if (adapter->vlgrp) {
2985 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2986 if (!vlan_group_get_device(adapter->vlgrp, vid))
2988 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2994 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2995 * @netdev: network interface device structure
2997 * Writes unicast address list to the RAR table.
2998 * Returns: -ENOMEM on failure/insufficient address space
2999 * 0 on no addresses written
3000 * X on writing X addresses to the RAR table
3002 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3004 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3005 struct ixgbe_hw *hw = &adapter->hw;
3006 unsigned int vfn = adapter->num_vfs;
3007 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3010 /* return ENOMEM indicating insufficient memory for addresses */
3011 if (netdev_uc_count(netdev) > rar_entries)
3014 if (!netdev_uc_empty(netdev) && rar_entries) {
3015 struct netdev_hw_addr *ha;
3016 /* return error if we do not support writing to RAR table */
3017 if (!hw->mac.ops.set_rar)
3020 netdev_for_each_uc_addr(ha, netdev) {
3023 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3028 /* write the addresses in reverse order to avoid write combining */
3029 for (; rar_entries > 0 ; rar_entries--)
3030 hw->mac.ops.clear_rar(hw, rar_entries);
3036 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3037 * @netdev: network interface device structure
3039 * The set_rx_method entry point is called whenever the unicast/multicast
3040 * address list or the network interface flags are updated. This routine is
3041 * responsible for configuring the hardware for proper unicast, multicast and
3044 void ixgbe_set_rx_mode(struct net_device *netdev)
3046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3047 struct ixgbe_hw *hw = &adapter->hw;
3048 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3051 /* Check for Promiscuous and All Multicast modes */
3053 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3055 /* clear the bits we are changing the status of */
3056 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3058 if (netdev->flags & IFF_PROMISC) {
3059 hw->addr_ctrl.user_set_promisc = true;
3060 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3061 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3062 /* don't hardware filter vlans in promisc mode */
3063 ixgbe_vlan_filter_disable(adapter);
3065 if (netdev->flags & IFF_ALLMULTI) {
3066 fctrl |= IXGBE_FCTRL_MPE;
3067 vmolr |= IXGBE_VMOLR_MPE;
3070 * Write addresses to the MTA, if the attempt fails
3071 * then we should just turn on promiscous mode so
3072 * that we can at least receive multicast traffic
3074 hw->mac.ops.update_mc_addr_list(hw, netdev);
3075 vmolr |= IXGBE_VMOLR_ROMPE;
3077 ixgbe_vlan_filter_enable(adapter);
3078 hw->addr_ctrl.user_set_promisc = false;
3080 * Write addresses to available RAR registers, if there is not
3081 * sufficient space to store all the addresses then enable
3082 * unicast promiscous mode
3084 count = ixgbe_write_uc_addr_list(netdev);
3086 fctrl |= IXGBE_FCTRL_UPE;
3087 vmolr |= IXGBE_VMOLR_ROPE;
3091 if (adapter->num_vfs) {
3092 ixgbe_restore_vf_multicasts(adapter);
3093 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3094 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3096 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3099 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3102 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3105 struct ixgbe_q_vector *q_vector;
3106 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3108 /* legacy and MSI only use one vector */
3109 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3112 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3113 struct napi_struct *napi;
3114 q_vector = adapter->q_vector[q_idx];
3115 napi = &q_vector->napi;
3116 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3117 if (!q_vector->rxr_count || !q_vector->txr_count) {
3118 if (q_vector->txr_count == 1)
3119 napi->poll = &ixgbe_clean_txonly;
3120 else if (q_vector->rxr_count == 1)
3121 napi->poll = &ixgbe_clean_rxonly;
3129 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3132 struct ixgbe_q_vector *q_vector;
3133 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3135 /* legacy and MSI only use one vector */
3136 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3139 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3140 q_vector = adapter->q_vector[q_idx];
3141 napi_disable(&q_vector->napi);
3145 #ifdef CONFIG_IXGBE_DCB
3147 * ixgbe_configure_dcb - Configure DCB hardware
3148 * @adapter: ixgbe adapter struct
3150 * This is called by the driver on open to configure the DCB hardware.
3151 * This is also called by the gennetlink interface when reconfiguring
3154 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3156 struct ixgbe_hw *hw = &adapter->hw;
3160 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3161 if (hw->mac.type == ixgbe_mac_82598EB)
3162 netif_set_gso_max_size(adapter->netdev, 65536);
3166 if (hw->mac.type == ixgbe_mac_82598EB)
3167 netif_set_gso_max_size(adapter->netdev, 32768);
3169 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3170 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3171 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3173 /* reconfigure the hardware */
3174 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3176 for (i = 0; i < adapter->num_tx_queues; i++) {
3177 j = adapter->tx_ring[i]->reg_idx;
3178 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3179 /* PThresh workaround for Tx hang with DFP enabled. */
3181 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3183 /* Enable VLAN tag insert/strip */
3184 ixgbe_vlan_filter_enable(adapter);
3186 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3190 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3192 struct net_device *netdev = adapter->netdev;
3193 struct ixgbe_hw *hw = &adapter->hw;
3196 ixgbe_set_rx_mode(netdev);
3198 ixgbe_restore_vlan(adapter);
3199 #ifdef CONFIG_IXGBE_DCB
3200 ixgbe_configure_dcb(adapter);
3204 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3205 ixgbe_configure_fcoe(adapter);
3207 #endif /* IXGBE_FCOE */
3208 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3209 for (i = 0; i < adapter->num_tx_queues; i++)
3210 adapter->tx_ring[i]->atr_sample_rate =
3211 adapter->atr_sample_rate;
3212 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3213 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3214 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3217 ixgbe_configure_tx(adapter);
3218 ixgbe_configure_rx(adapter);
3219 for (i = 0; i < adapter->num_rx_queues; i++)
3220 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3221 (adapter->rx_ring[i]->count - 1));
3224 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3226 switch (hw->phy.type) {
3227 case ixgbe_phy_sfp_avago:
3228 case ixgbe_phy_sfp_ftl:
3229 case ixgbe_phy_sfp_intel:
3230 case ixgbe_phy_sfp_unknown:
3231 case ixgbe_phy_sfp_passive_tyco:
3232 case ixgbe_phy_sfp_passive_unknown:
3233 case ixgbe_phy_sfp_active_unknown:
3234 case ixgbe_phy_sfp_ftl_active:
3242 * ixgbe_sfp_link_config - set up SFP+ link
3243 * @adapter: pointer to private adapter struct
3245 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3247 struct ixgbe_hw *hw = &adapter->hw;
3249 if (hw->phy.multispeed_fiber) {
3251 * In multispeed fiber setups, the device may not have
3252 * had a physical connection when the driver loaded.
3253 * If that's the case, the initial link configuration
3254 * couldn't get the MAC into 10G or 1G mode, so we'll
3255 * never have a link status change interrupt fire.
3256 * We need to try and force an autonegotiation
3257 * session, then bring up link.
3259 hw->mac.ops.setup_sfp(hw);
3260 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3261 schedule_work(&adapter->multispeed_fiber_task);
3264 * Direct Attach Cu and non-multispeed fiber modules
3265 * still need to be configured properly prior to
3268 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3269 schedule_work(&adapter->sfp_config_module_task);
3274 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3275 * @hw: pointer to private hardware struct
3277 * Returns 0 on success, negative on failure
3279 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3282 bool negotiation, link_up = false;
3283 u32 ret = IXGBE_ERR_LINK_SETUP;
3285 if (hw->mac.ops.check_link)
3286 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3291 if (hw->mac.ops.get_link_capabilities)
3292 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3296 if (hw->mac.ops.setup_link)
3297 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3302 #define IXGBE_MAX_RX_DESC_POLL 10
3303 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3306 int j = adapter->rx_ring[rxr]->reg_idx;
3309 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3310 if (IXGBE_READ_REG(&adapter->hw,
3311 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3316 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3317 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3318 "the polling period\n", rxr);
3320 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3321 (adapter->rx_ring[rxr]->count - 1));
3324 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3326 struct net_device *netdev = adapter->netdev;
3327 struct ixgbe_hw *hw = &adapter->hw;
3329 int num_rx_rings = adapter->num_rx_queues;
3331 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3332 u32 txdctl, rxdctl, mhadd;
3337 ixgbe_get_hw_control(adapter);
3339 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3340 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3341 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3342 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3343 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3348 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3349 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3350 gpie |= IXGBE_GPIE_VTMODE_64;
3352 /* XXX: to interrupt immediately for EICS writes, enable this */
3353 /* gpie |= IXGBE_GPIE_EIMEN; */
3354 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3357 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3359 * use EIAM to auto-mask when MSI-X interrupt is asserted
3360 * this saves a register write for every interrupt
3362 switch (hw->mac.type) {
3363 case ixgbe_mac_82598EB:
3364 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3367 case ixgbe_mac_82599EB:
3368 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3369 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3373 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3374 * specifically only auto mask tx and rx interrupts */
3375 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3378 /* Enable Thermal over heat sensor interrupt */
3379 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3380 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3381 gpie |= IXGBE_SDP0_GPIEN;
3382 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3385 /* Enable fan failure interrupt if media type is copper */
3386 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3387 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3388 gpie |= IXGBE_SDP1_GPIEN;
3389 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3392 if (hw->mac.type == ixgbe_mac_82599EB) {
3393 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3394 gpie |= IXGBE_SDP1_GPIEN;
3395 gpie |= IXGBE_SDP2_GPIEN;
3396 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3400 /* adjust max frame to be able to do baby jumbo for FCoE */
3401 if ((netdev->features & NETIF_F_FCOE_MTU) &&
3402 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3403 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3405 #endif /* IXGBE_FCOE */
3406 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3407 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3408 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3409 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3411 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3414 if (hw->mac.type == ixgbe_mac_82599EB) {
3415 /* DMATXCTL.EN must be set after all Tx queue config is done */
3416 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3417 dmatxctl |= IXGBE_DMATXCTL_TE;
3418 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3420 for (i = 0; i < adapter->num_tx_queues; i++) {
3421 j = adapter->tx_ring[i]->reg_idx;
3422 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3423 if (adapter->rx_itr_setting == 0) {
3424 /* cannot set wthresh when itr==0 */
3425 txdctl &= ~0x007F0000;
3427 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3428 txdctl |= (8 << 16);
3430 txdctl |= IXGBE_TXDCTL_ENABLE;
3431 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3432 if (hw->mac.type == ixgbe_mac_82599EB) {
3434 /* poll for Tx Enable ready */
3437 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3438 } while (--wait_loop &&
3439 !(txdctl & IXGBE_TXDCTL_ENABLE));
3441 e_err(drv, "Could not enable Tx Queue %d\n", j);
3445 for (i = 0; i < num_rx_rings; i++) {
3446 j = adapter->rx_ring[i]->reg_idx;
3447 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3448 /* enable PTHRESH=32 descriptors (half the internal cache)
3449 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3450 * this also removes a pesky rx_no_buffer_count increment */
3452 rxdctl |= IXGBE_RXDCTL_ENABLE;
3453 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3454 if (hw->mac.type == ixgbe_mac_82599EB)
3455 ixgbe_rx_desc_queue_enable(adapter, i);
3457 /* enable all receives */
3458 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3459 if (hw->mac.type == ixgbe_mac_82598EB)
3460 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3462 rxdctl |= IXGBE_RXCTRL_RXEN;
3463 hw->mac.ops.enable_rx_dma(hw, rxdctl);
3465 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3466 ixgbe_configure_msix(adapter);
3468 ixgbe_configure_msi_and_legacy(adapter);
3470 /* enable the optics */
3471 if (hw->phy.multispeed_fiber)
3472 hw->mac.ops.enable_tx_laser(hw);
3474 clear_bit(__IXGBE_DOWN, &adapter->state);
3475 ixgbe_napi_enable_all(adapter);
3477 /* clear any pending interrupts, may auto mask */
3478 IXGBE_READ_REG(hw, IXGBE_EICR);
3480 ixgbe_irq_enable(adapter);
3483 * If this adapter has a fan, check to see if we had a failure
3484 * before we enabled the interrupt.
3486 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3487 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3488 if (esdp & IXGBE_ESDP_SDP1)
3489 e_crit(drv, "Fan has stopped, replace the adapter\n");
3493 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3494 * arrived before interrupts were enabled but after probe. Such
3495 * devices wouldn't have their type identified yet. We need to
3496 * kick off the SFP+ module setup first, then try to bring up link.
3497 * If we're not hot-pluggable SFP+, we just need to configure link
3500 if (hw->phy.type == ixgbe_phy_unknown) {
3501 err = hw->phy.ops.identify(hw);
3502 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3504 * Take the device down and schedule the sfp tasklet
3505 * which will unregister_netdev and log it.
3507 ixgbe_down(adapter);
3508 schedule_work(&adapter->sfp_config_module_task);
3513 if (ixgbe_is_sfp(hw)) {
3514 ixgbe_sfp_link_config(adapter);
3516 err = ixgbe_non_sfp_link_config(hw);
3518 e_err(probe, "link_config FAILED %d\n", err);
3521 for (i = 0; i < adapter->num_tx_queues; i++)
3522 set_bit(__IXGBE_FDIR_INIT_DONE,
3523 &(adapter->tx_ring[i]->reinit_state));
3525 /* enable transmits */
3526 netif_tx_start_all_queues(netdev);
3528 /* bring the link up in the watchdog, this could race with our first
3529 * link up interrupt but shouldn't be a problem */
3530 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3531 adapter->link_check_timeout = jiffies;
3532 mod_timer(&adapter->watchdog_timer, jiffies);
3534 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3535 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3536 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3537 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3542 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3544 WARN_ON(in_interrupt());
3545 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3547 ixgbe_down(adapter);
3549 * If SR-IOV enabled then wait a bit before bringing the adapter
3550 * back up to give the VFs time to respond to the reset. The
3551 * two second wait is based upon the watchdog timer cycle in
3554 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3557 clear_bit(__IXGBE_RESETTING, &adapter->state);
3560 int ixgbe_up(struct ixgbe_adapter *adapter)
3562 /* hardware has been reset, we need to reload some things */
3563 ixgbe_configure(adapter);
3565 return ixgbe_up_complete(adapter);
3568 void ixgbe_reset(struct ixgbe_adapter *adapter)
3570 struct ixgbe_hw *hw = &adapter->hw;
3573 err = hw->mac.ops.init_hw(hw);
3576 case IXGBE_ERR_SFP_NOT_PRESENT:
3578 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3579 e_dev_err("master disable timed out\n");
3581 case IXGBE_ERR_EEPROM_VERSION:
3582 /* We are running on a pre-production device, log a warning */
3583 e_dev_warn("This device is a pre-production adapter/LOM. "
3584 "Please be aware there may be issuesassociated with "
3585 "your hardware. If you are experiencing problems "
3586 "please contact your Intel or hardware "
3587 "representative who provided you with this "
3591 e_dev_err("Hardware Error: %d\n", err);
3594 /* reprogram the RAR[0] in case user changed it. */
3595 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3600 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3601 * @adapter: board private structure
3602 * @rx_ring: ring to free buffers from
3604 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3605 struct ixgbe_ring *rx_ring)
3607 struct pci_dev *pdev = adapter->pdev;
3611 /* Free all the Rx ring sk_buffs */
3613 for (i = 0; i < rx_ring->count; i++) {
3614 struct ixgbe_rx_buffer *rx_buffer_info;
3616 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3617 if (rx_buffer_info->dma) {
3618 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3619 rx_ring->rx_buf_len,
3621 rx_buffer_info->dma = 0;
3623 if (rx_buffer_info->skb) {
3624 struct sk_buff *skb = rx_buffer_info->skb;
3625 rx_buffer_info->skb = NULL;
3627 struct sk_buff *this = skb;
3628 if (IXGBE_RSC_CB(this)->delay_unmap) {
3629 dma_unmap_single(&pdev->dev,
3630 IXGBE_RSC_CB(this)->dma,
3631 rx_ring->rx_buf_len,
3633 IXGBE_RSC_CB(this)->dma = 0;
3634 IXGBE_RSC_CB(skb)->delay_unmap = false;
3637 dev_kfree_skb(this);
3640 if (!rx_buffer_info->page)
3642 if (rx_buffer_info->page_dma) {
3643 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3644 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3645 rx_buffer_info->page_dma = 0;
3647 put_page(rx_buffer_info->page);
3648 rx_buffer_info->page = NULL;
3649 rx_buffer_info->page_offset = 0;
3652 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3653 memset(rx_ring->rx_buffer_info, 0, size);
3655 /* Zero out the descriptor ring */
3656 memset(rx_ring->desc, 0, rx_ring->size);
3658 rx_ring->next_to_clean = 0;
3659 rx_ring->next_to_use = 0;
3662 writel(0, adapter->hw.hw_addr + rx_ring->head);
3664 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3668 * ixgbe_clean_tx_ring - Free Tx Buffers
3669 * @adapter: board private structure
3670 * @tx_ring: ring to be cleaned
3672 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3673 struct ixgbe_ring *tx_ring)
3675 struct ixgbe_tx_buffer *tx_buffer_info;
3679 /* Free all the Tx ring sk_buffs */
3681 for (i = 0; i < tx_ring->count; i++) {
3682 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3683 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3686 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3687 memset(tx_ring->tx_buffer_info, 0, size);
3689 /* Zero out the descriptor ring */
3690 memset(tx_ring->desc, 0, tx_ring->size);
3692 tx_ring->next_to_use = 0;
3693 tx_ring->next_to_clean = 0;
3696 writel(0, adapter->hw.hw_addr + tx_ring->head);
3698 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3702 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3703 * @adapter: board private structure
3705 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3709 for (i = 0; i < adapter->num_rx_queues; i++)
3710 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3714 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3715 * @adapter: board private structure
3717 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3721 for (i = 0; i < adapter->num_tx_queues; i++)
3722 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3725 void ixgbe_down(struct ixgbe_adapter *adapter)
3727 struct net_device *netdev = adapter->netdev;
3728 struct ixgbe_hw *hw = &adapter->hw;
3733 /* signal that we are down to the interrupt handler */
3734 set_bit(__IXGBE_DOWN, &adapter->state);
3736 /* disable receive for all VFs and wait one second */
3737 if (adapter->num_vfs) {
3738 /* ping all the active vfs to let them know we are going down */
3739 ixgbe_ping_all_vfs(adapter);
3741 /* Disable all VFTE/VFRE TX/RX */
3742 ixgbe_disable_tx_rx(adapter);
3744 /* Mark all the VFs as inactive */
3745 for (i = 0 ; i < adapter->num_vfs; i++)
3746 adapter->vfinfo[i].clear_to_send = 0;
3749 /* disable receives */
3750 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3751 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3753 IXGBE_WRITE_FLUSH(hw);
3756 netif_tx_stop_all_queues(netdev);
3758 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3759 del_timer_sync(&adapter->sfp_timer);
3760 del_timer_sync(&adapter->watchdog_timer);
3761 cancel_work_sync(&adapter->watchdog_task);
3763 netif_carrier_off(netdev);
3764 netif_tx_disable(netdev);
3766 ixgbe_irq_disable(adapter);
3768 ixgbe_napi_disable_all(adapter);
3770 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3771 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3772 cancel_work_sync(&adapter->fdir_reinit_task);
3774 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3775 cancel_work_sync(&adapter->check_overtemp_task);
3777 /* disable transmits in the hardware now that interrupts are off */
3778 for (i = 0; i < adapter->num_tx_queues; i++) {
3779 j = adapter->tx_ring[i]->reg_idx;
3780 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3781 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3782 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3784 /* Disable the Tx DMA engine on 82599 */
3785 if (hw->mac.type == ixgbe_mac_82599EB)
3786 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3787 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3788 ~IXGBE_DMATXCTL_TE));
3790 /* power down the optics */
3791 if (hw->phy.multispeed_fiber)
3792 hw->mac.ops.disable_tx_laser(hw);
3794 /* clear n-tuple filters that are cached */
3795 ethtool_ntuple_flush(netdev);
3797 if (!pci_channel_offline(adapter->pdev))
3798 ixgbe_reset(adapter);
3799 ixgbe_clean_all_tx_rings(adapter);
3800 ixgbe_clean_all_rx_rings(adapter);
3802 #ifdef CONFIG_IXGBE_DCA
3803 /* since we reset the hardware DCA settings were cleared */
3804 ixgbe_setup_dca(adapter);
3809 * ixgbe_poll - NAPI Rx polling callback
3810 * @napi: structure for representing this polling device
3811 * @budget: how many packets driver is allowed to clean
3813 * This function is used for legacy and MSI, NAPI mode
3815 static int ixgbe_poll(struct napi_struct *napi, int budget)
3817 struct ixgbe_q_vector *q_vector =
3818 container_of(napi, struct ixgbe_q_vector, napi);
3819 struct ixgbe_adapter *adapter = q_vector->adapter;
3820 int tx_clean_complete, work_done = 0;
3822 #ifdef CONFIG_IXGBE_DCA
3823 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3824 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3825 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3829 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3830 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3832 if (!tx_clean_complete)
3835 /* If budget not fully consumed, exit the polling mode */
3836 if (work_done < budget) {
3837 napi_complete(napi);
3838 if (adapter->rx_itr_setting & 1)
3839 ixgbe_set_itr(adapter);
3840 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3841 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3847 * ixgbe_tx_timeout - Respond to a Tx Hang
3848 * @netdev: network interface device structure
3850 static void ixgbe_tx_timeout(struct net_device *netdev)
3852 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3854 /* Do the reset outside of interrupt context */
3855 schedule_work(&adapter->reset_task);
3858 static void ixgbe_reset_task(struct work_struct *work)
3860 struct ixgbe_adapter *adapter;
3861 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3863 /* If we're already down or resetting, just bail */
3864 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3865 test_bit(__IXGBE_RESETTING, &adapter->state))
3868 adapter->tx_timeout_count++;
3870 ixgbe_dump(adapter);
3871 netdev_err(adapter->netdev, "Reset adapter\n");
3872 ixgbe_reinit_locked(adapter);
3875 #ifdef CONFIG_IXGBE_DCB
3876 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3879 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3881 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3885 adapter->num_rx_queues = f->indices;
3886 adapter->num_tx_queues = f->indices;
3894 * ixgbe_set_rss_queues: Allocate queues for RSS
3895 * @adapter: board private structure to initialize
3897 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3898 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3901 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3904 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3906 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3908 adapter->num_rx_queues = f->indices;
3909 adapter->num_tx_queues = f->indices;
3919 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3920 * @adapter: board private structure to initialize
3922 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3923 * to the original CPU that initiated the Tx session. This runs in addition
3924 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3925 * Rx load across CPUs using RSS.
3928 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3931 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3933 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3936 /* Flow Director must have RSS enabled */
3937 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3938 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3939 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3940 adapter->num_tx_queues = f_fdir->indices;
3941 adapter->num_rx_queues = f_fdir->indices;
3944 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3945 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3952 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3953 * @adapter: board private structure to initialize
3955 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3956 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3957 * rx queues out of the max number of rx queues, instead, it is used as the
3958 * index of the first rx queue used by FCoE.
3961 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3964 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3966 f->indices = min((int)num_online_cpus(), f->indices);
3967 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3968 adapter->num_rx_queues = 1;
3969 adapter->num_tx_queues = 1;
3970 #ifdef CONFIG_IXGBE_DCB
3971 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3972 e_info(probe, "FCoE enabled with DCB\n");
3973 ixgbe_set_dcb_queues(adapter);
3976 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3977 e_info(probe, "FCoE enabled with RSS\n");
3978 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3979 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3980 ixgbe_set_fdir_queues(adapter);
3982 ixgbe_set_rss_queues(adapter);
3984 /* adding FCoE rx rings to the end */
3985 f->mask = adapter->num_rx_queues;
3986 adapter->num_rx_queues += f->indices;
3987 adapter->num_tx_queues += f->indices;
3995 #endif /* IXGBE_FCOE */
3997 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3998 * @adapter: board private structure to initialize
4000 * IOV doesn't actually use anything, so just NAK the
4001 * request for now and let the other queue routines
4002 * figure out what to do.
4004 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4010 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4011 * @adapter: board private structure to initialize
4013 * This is the top level queue allocation routine. The order here is very
4014 * important, starting with the "most" number of features turned on at once,
4015 * and ending with the smallest set of features. This way large combinations
4016 * can be allocated if they're turned on, and smaller combinations are the
4017 * fallthrough conditions.
4020 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4022 /* Start with base case */
4023 adapter->num_rx_queues = 1;
4024 adapter->num_tx_queues = 1;
4025 adapter->num_rx_pools = adapter->num_rx_queues;
4026 adapter->num_rx_queues_per_pool = 1;
4028 if (ixgbe_set_sriov_queues(adapter))
4032 if (ixgbe_set_fcoe_queues(adapter))
4035 #endif /* IXGBE_FCOE */
4036 #ifdef CONFIG_IXGBE_DCB
4037 if (ixgbe_set_dcb_queues(adapter))
4041 if (ixgbe_set_fdir_queues(adapter))
4044 if (ixgbe_set_rss_queues(adapter))
4047 /* fallback to base case */
4048 adapter->num_rx_queues = 1;
4049 adapter->num_tx_queues = 1;
4052 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4053 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4056 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4059 int err, vector_threshold;
4061 /* We'll want at least 3 (vector_threshold):
4064 * 3) Other (Link Status Change, etc.)
4065 * 4) TCP Timer (optional)
4067 vector_threshold = MIN_MSIX_COUNT;
4069 /* The more we get, the more we will assign to Tx/Rx Cleanup
4070 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4071 * Right now, we simply care about how many we'll get; we'll
4072 * set them up later while requesting irq's.
4074 while (vectors >= vector_threshold) {
4075 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4077 if (!err) /* Success in acquiring all requested vectors. */
4080 vectors = 0; /* Nasty failure, quit now */
4081 else /* err == number of vectors we should try again with */
4085 if (vectors < vector_threshold) {
4086 /* Can't allocate enough MSI-X interrupts? Oh well.
4087 * This just means we'll go with either a single MSI
4088 * vector or fall back to legacy interrupts.
4090 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4091 "Unable to allocate MSI-X interrupts\n");
4092 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4093 kfree(adapter->msix_entries);
4094 adapter->msix_entries = NULL;
4096 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4098 * Adjust for only the vectors we'll use, which is minimum
4099 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4100 * vectors we were allocated.
4102 adapter->num_msix_vectors = min(vectors,
4103 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4108 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4109 * @adapter: board private structure to initialize
4111 * Cache the descriptor ring offsets for RSS to the assigned rings.
4114 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4119 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4120 for (i = 0; i < adapter->num_rx_queues; i++)
4121 adapter->rx_ring[i]->reg_idx = i;
4122 for (i = 0; i < adapter->num_tx_queues; i++)
4123 adapter->tx_ring[i]->reg_idx = i;
4132 #ifdef CONFIG_IXGBE_DCB
4134 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4135 * @adapter: board private structure to initialize
4137 * Cache the descriptor ring offsets for DCB to the assigned rings.
4140 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4144 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4146 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4147 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4148 /* the number of queues is assumed to be symmetric */
4149 for (i = 0; i < dcb_i; i++) {
4150 adapter->rx_ring[i]->reg_idx = i << 3;
4151 adapter->tx_ring[i]->reg_idx = i << 2;
4154 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4157 * Tx TC0 starts at: descriptor queue 0
4158 * Tx TC1 starts at: descriptor queue 32
4159 * Tx TC2 starts at: descriptor queue 64
4160 * Tx TC3 starts at: descriptor queue 80
4161 * Tx TC4 starts at: descriptor queue 96
4162 * Tx TC5 starts at: descriptor queue 104
4163 * Tx TC6 starts at: descriptor queue 112
4164 * Tx TC7 starts at: descriptor queue 120
4166 * Rx TC0-TC7 are offset by 16 queues each
4168 for (i = 0; i < 3; i++) {
4169 adapter->tx_ring[i]->reg_idx = i << 5;
4170 adapter->rx_ring[i]->reg_idx = i << 4;
4172 for ( ; i < 5; i++) {
4173 adapter->tx_ring[i]->reg_idx =
4175 adapter->rx_ring[i]->reg_idx = i << 4;
4177 for ( ; i < dcb_i; i++) {
4178 adapter->tx_ring[i]->reg_idx =
4180 adapter->rx_ring[i]->reg_idx = i << 4;
4184 } else if (dcb_i == 4) {
4186 * Tx TC0 starts at: descriptor queue 0
4187 * Tx TC1 starts at: descriptor queue 64
4188 * Tx TC2 starts at: descriptor queue 96
4189 * Tx TC3 starts at: descriptor queue 112
4191 * Rx TC0-TC3 are offset by 32 queues each
4193 adapter->tx_ring[0]->reg_idx = 0;
4194 adapter->tx_ring[1]->reg_idx = 64;
4195 adapter->tx_ring[2]->reg_idx = 96;
4196 adapter->tx_ring[3]->reg_idx = 112;
4197 for (i = 0 ; i < dcb_i; i++)
4198 adapter->rx_ring[i]->reg_idx = i << 5;
4216 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4217 * @adapter: board private structure to initialize
4219 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4222 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4227 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4228 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4229 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4230 for (i = 0; i < adapter->num_rx_queues; i++)
4231 adapter->rx_ring[i]->reg_idx = i;
4232 for (i = 0; i < adapter->num_tx_queues; i++)
4233 adapter->tx_ring[i]->reg_idx = i;
4242 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4243 * @adapter: board private structure to initialize
4245 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4248 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4250 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4252 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4254 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4255 #ifdef CONFIG_IXGBE_DCB
4256 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4257 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4259 ixgbe_cache_ring_dcb(adapter);
4260 /* find out queues in TC for FCoE */
4261 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4262 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4264 * In 82599, the number of Tx queues for each traffic
4265 * class for both 8-TC and 4-TC modes are:
4266 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4267 * 8 TCs: 32 32 16 16 8 8 8 8
4268 * 4 TCs: 64 64 32 32
4269 * We have max 8 queues for FCoE, where 8 the is
4270 * FCoE redirection table size. If TC for FCoE is
4271 * less than or equal to TC3, we have enough queues
4272 * to add max of 8 queues for FCoE, so we start FCoE
4273 * tx descriptor from the next one, i.e., reg_idx + 1.
4274 * If TC for FCoE is above TC3, implying 8 TC mode,
4275 * and we need 8 for FCoE, we have to take all queues
4276 * in that traffic class for FCoE.
4278 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4281 #endif /* CONFIG_IXGBE_DCB */
4282 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4283 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4284 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4285 ixgbe_cache_ring_fdir(adapter);
4287 ixgbe_cache_ring_rss(adapter);
4289 fcoe_rx_i = f->mask;
4290 fcoe_tx_i = f->mask;
4292 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4293 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4294 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4301 #endif /* IXGBE_FCOE */
4303 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4304 * @adapter: board private structure to initialize
4306 * SR-IOV doesn't use any descriptor rings but changes the default if
4307 * no other mapping is used.
4310 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4312 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4313 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4314 if (adapter->num_vfs)
4321 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4322 * @adapter: board private structure to initialize
4324 * Once we know the feature-set enabled for the device, we'll cache
4325 * the register offset the descriptor ring is assigned to.
4327 * Note, the order the various feature calls is important. It must start with
4328 * the "most" features enabled at the same time, then trickle down to the
4329 * least amount of features turned on at once.
4331 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4333 /* start with default case */
4334 adapter->rx_ring[0]->reg_idx = 0;
4335 adapter->tx_ring[0]->reg_idx = 0;
4337 if (ixgbe_cache_ring_sriov(adapter))
4341 if (ixgbe_cache_ring_fcoe(adapter))
4344 #endif /* IXGBE_FCOE */
4345 #ifdef CONFIG_IXGBE_DCB
4346 if (ixgbe_cache_ring_dcb(adapter))
4350 if (ixgbe_cache_ring_fdir(adapter))
4353 if (ixgbe_cache_ring_rss(adapter))
4358 * ixgbe_alloc_queues - Allocate memory for all rings
4359 * @adapter: board private structure to initialize
4361 * We allocate one ring per queue at run-time since we don't know the
4362 * number of queues at compile-time. The polling_netdev array is
4363 * intended for Multiqueue, but should work fine with a single queue.
4365 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4368 int orig_node = adapter->node;
4370 for (i = 0; i < adapter->num_tx_queues; i++) {
4371 struct ixgbe_ring *ring = adapter->tx_ring[i];
4372 if (orig_node == -1) {
4373 int cur_node = next_online_node(adapter->node);
4374 if (cur_node == MAX_NUMNODES)
4375 cur_node = first_online_node;
4376 adapter->node = cur_node;
4378 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4381 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4383 goto err_tx_ring_allocation;
4384 ring->count = adapter->tx_ring_count;
4385 ring->queue_index = i;
4386 ring->numa_node = adapter->node;
4388 adapter->tx_ring[i] = ring;
4391 /* Restore the adapter's original node */
4392 adapter->node = orig_node;
4394 for (i = 0; i < adapter->num_rx_queues; i++) {
4395 struct ixgbe_ring *ring = adapter->rx_ring[i];
4396 if (orig_node == -1) {
4397 int cur_node = next_online_node(adapter->node);
4398 if (cur_node == MAX_NUMNODES)
4399 cur_node = first_online_node;
4400 adapter->node = cur_node;
4402 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4405 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4407 goto err_rx_ring_allocation;
4408 ring->count = adapter->rx_ring_count;
4409 ring->queue_index = i;
4410 ring->numa_node = adapter->node;
4412 adapter->rx_ring[i] = ring;
4415 /* Restore the adapter's original node */
4416 adapter->node = orig_node;
4418 ixgbe_cache_ring_register(adapter);
4422 err_rx_ring_allocation:
4423 for (i = 0; i < adapter->num_tx_queues; i++)
4424 kfree(adapter->tx_ring[i]);
4425 err_tx_ring_allocation:
4430 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4431 * @adapter: board private structure to initialize
4433 * Attempt to configure the interrupts using the best available
4434 * capabilities of the hardware and the kernel.
4436 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4438 struct ixgbe_hw *hw = &adapter->hw;
4440 int vector, v_budget;
4443 * It's easy to be greedy for MSI-X vectors, but it really
4444 * doesn't do us much good if we have a lot more vectors
4445 * than CPU's. So let's be conservative and only ask for
4446 * (roughly) the same number of vectors as there are CPU's.
4448 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4449 (int)num_online_cpus()) + NON_Q_VECTORS;
4452 * At the same time, hardware can only support a maximum of
4453 * hw.mac->max_msix_vectors vectors. With features
4454 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4455 * descriptor queues supported by our device. Thus, we cap it off in
4456 * those rare cases where the cpu count also exceeds our vector limit.
4458 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4460 /* A failure in MSI-X entry allocation isn't fatal, but it does
4461 * mean we disable MSI-X capabilities of the adapter. */
4462 adapter->msix_entries = kcalloc(v_budget,
4463 sizeof(struct msix_entry), GFP_KERNEL);
4464 if (adapter->msix_entries) {
4465 for (vector = 0; vector < v_budget; vector++)
4466 adapter->msix_entries[vector].entry = vector;
4468 ixgbe_acquire_msix_vectors(adapter, v_budget);
4470 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4474 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4475 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4476 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4477 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4478 adapter->atr_sample_rate = 0;
4479 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4480 ixgbe_disable_sriov(adapter);
4482 ixgbe_set_num_queues(adapter);
4484 err = pci_enable_msi(adapter->pdev);
4486 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4488 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4489 "Unable to allocate MSI interrupt, "
4490 "falling back to legacy. Error: %d\n", err);
4500 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4501 * @adapter: board private structure to initialize
4503 * We allocate one q_vector per queue interrupt. If allocation fails we
4506 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4508 int q_idx, num_q_vectors;
4509 struct ixgbe_q_vector *q_vector;
4511 int (*poll)(struct napi_struct *, int);
4513 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4514 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4515 napi_vectors = adapter->num_rx_queues;
4516 poll = &ixgbe_clean_rxtx_many;
4523 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4524 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4525 GFP_KERNEL, adapter->node);
4527 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4531 q_vector->adapter = adapter;
4532 if (q_vector->txr_count && !q_vector->rxr_count)
4533 q_vector->eitr = adapter->tx_eitr_param;
4535 q_vector->eitr = adapter->rx_eitr_param;
4536 q_vector->v_idx = q_idx;
4537 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4538 adapter->q_vector[q_idx] = q_vector;
4546 q_vector = adapter->q_vector[q_idx];
4547 netif_napi_del(&q_vector->napi);
4549 adapter->q_vector[q_idx] = NULL;
4555 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4556 * @adapter: board private structure to initialize
4558 * This function frees the memory allocated to the q_vectors. In addition if
4559 * NAPI is enabled it will delete any references to the NAPI struct prior
4560 * to freeing the q_vector.
4562 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4564 int q_idx, num_q_vectors;
4566 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4567 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4571 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4572 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4573 adapter->q_vector[q_idx] = NULL;
4574 netif_napi_del(&q_vector->napi);
4579 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4581 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4582 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4583 pci_disable_msix(adapter->pdev);
4584 kfree(adapter->msix_entries);
4585 adapter->msix_entries = NULL;
4586 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4587 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4588 pci_disable_msi(adapter->pdev);
4593 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4594 * @adapter: board private structure to initialize
4596 * We determine which interrupt scheme to use based on...
4597 * - Kernel support (MSI, MSI-X)
4598 * - which can be user-defined (via MODULE_PARAM)
4599 * - Hardware queue count (num_*_queues)
4600 * - defined by miscellaneous hardware support/features (RSS, etc.)
4602 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4606 /* Number of supported queues */
4607 ixgbe_set_num_queues(adapter);
4609 err = ixgbe_set_interrupt_capability(adapter);
4611 e_dev_err("Unable to setup interrupt capabilities\n");
4612 goto err_set_interrupt;
4615 err = ixgbe_alloc_q_vectors(adapter);
4617 e_dev_err("Unable to allocate memory for queue vectors\n");
4618 goto err_alloc_q_vectors;
4621 err = ixgbe_alloc_queues(adapter);
4623 e_dev_err("Unable to allocate memory for queues\n");
4624 goto err_alloc_queues;
4627 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4628 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4629 adapter->num_rx_queues, adapter->num_tx_queues);
4631 set_bit(__IXGBE_DOWN, &adapter->state);
4636 ixgbe_free_q_vectors(adapter);
4637 err_alloc_q_vectors:
4638 ixgbe_reset_interrupt_capability(adapter);
4644 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4645 * @adapter: board private structure to clear interrupt scheme on
4647 * We go through and clear interrupt specific resources and reset the structure
4648 * to pre-load conditions
4650 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4654 for (i = 0; i < adapter->num_tx_queues; i++) {
4655 kfree(adapter->tx_ring[i]);
4656 adapter->tx_ring[i] = NULL;
4658 for (i = 0; i < adapter->num_rx_queues; i++) {
4659 kfree(adapter->rx_ring[i]);
4660 adapter->rx_ring[i] = NULL;
4663 ixgbe_free_q_vectors(adapter);
4664 ixgbe_reset_interrupt_capability(adapter);
4668 * ixgbe_sfp_timer - worker thread to find a missing module
4669 * @data: pointer to our adapter struct
4671 static void ixgbe_sfp_timer(unsigned long data)
4673 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4676 * Do the sfp_timer outside of interrupt context due to the
4677 * delays that sfp+ detection requires
4679 schedule_work(&adapter->sfp_task);
4683 * ixgbe_sfp_task - worker thread to find a missing module
4684 * @work: pointer to work_struct containing our data
4686 static void ixgbe_sfp_task(struct work_struct *work)
4688 struct ixgbe_adapter *adapter = container_of(work,
4689 struct ixgbe_adapter,
4691 struct ixgbe_hw *hw = &adapter->hw;
4693 if ((hw->phy.type == ixgbe_phy_nl) &&
4694 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4695 s32 ret = hw->phy.ops.identify_sfp(hw);
4696 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4698 ret = hw->phy.ops.reset(hw);
4699 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4700 e_dev_err("failed to initialize because an unsupported "
4701 "SFP+ module type was detected.\n");
4702 e_dev_err("Reload the driver after installing a "
4703 "supported module.\n");
4704 unregister_netdev(adapter->netdev);
4706 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4708 /* don't need this routine any more */
4709 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4713 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4714 mod_timer(&adapter->sfp_timer,
4715 round_jiffies(jiffies + (2 * HZ)));
4719 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4720 * @adapter: board private structure to initialize
4722 * ixgbe_sw_init initializes the Adapter private data structure.
4723 * Fields are initialized based on PCI device information and
4724 * OS network device settings (MTU size).
4726 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4728 struct ixgbe_hw *hw = &adapter->hw;
4729 struct pci_dev *pdev = adapter->pdev;
4730 struct net_device *dev = adapter->netdev;
4732 #ifdef CONFIG_IXGBE_DCB
4734 struct tc_configuration *tc;
4737 /* PCI config space info */
4739 hw->vendor_id = pdev->vendor;
4740 hw->device_id = pdev->device;
4741 hw->revision_id = pdev->revision;
4742 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4743 hw->subsystem_device_id = pdev->subsystem_device;
4745 /* Set capability flags */
4746 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4747 adapter->ring_feature[RING_F_RSS].indices = rss;
4748 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4749 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4750 if (hw->mac.type == ixgbe_mac_82598EB) {
4751 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4752 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4753 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4754 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4755 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4756 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4757 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4758 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4759 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4760 if (dev->features & NETIF_F_NTUPLE) {
4761 /* Flow Director perfect filter enabled */
4762 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4763 adapter->atr_sample_rate = 0;
4764 spin_lock_init(&adapter->fdir_perfect_lock);
4766 /* Flow Director hash filters enabled */
4767 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4768 adapter->atr_sample_rate = 20;
4770 adapter->ring_feature[RING_F_FDIR].indices =
4771 IXGBE_MAX_FDIR_INDICES;
4772 adapter->fdir_pballoc = 0;
4774 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4775 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4776 adapter->ring_feature[RING_F_FCOE].indices = 0;
4777 #ifdef CONFIG_IXGBE_DCB
4778 /* Default traffic class to use for FCoE */
4779 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4780 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4782 #endif /* IXGBE_FCOE */
4785 #ifdef CONFIG_IXGBE_DCB
4786 /* Configure DCB traffic classes */
4787 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4788 tc = &adapter->dcb_cfg.tc_config[j];
4789 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4790 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4791 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4792 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4793 tc->dcb_pfc = pfc_disabled;
4795 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4796 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4797 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4798 adapter->dcb_cfg.pfc_mode_enable = false;
4799 adapter->dcb_cfg.round_robin_enable = false;
4800 adapter->dcb_set_bitmap = 0x00;
4801 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4802 adapter->ring_feature[RING_F_DCB].indices);
4806 /* default flow control settings */
4807 hw->fc.requested_mode = ixgbe_fc_full;
4808 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4810 adapter->last_lfc_mode = hw->fc.current_mode;
4812 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4813 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4814 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4815 hw->fc.send_xon = true;
4816 hw->fc.disable_fc_autoneg = false;
4818 /* enable itr by default in dynamic mode */
4819 adapter->rx_itr_setting = 1;
4820 adapter->rx_eitr_param = 20000;
4821 adapter->tx_itr_setting = 1;
4822 adapter->tx_eitr_param = 10000;
4824 /* set defaults for eitr in MegaBytes */
4825 adapter->eitr_low = 10;
4826 adapter->eitr_high = 20;
4828 /* set default ring sizes */
4829 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4830 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4832 /* initialize eeprom parameters */
4833 if (ixgbe_init_eeprom_params_generic(hw)) {
4834 e_dev_err("EEPROM initialization failed\n");
4838 /* enable rx csum by default */
4839 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4841 /* get assigned NUMA node */
4842 adapter->node = dev_to_node(&pdev->dev);
4844 set_bit(__IXGBE_DOWN, &adapter->state);
4850 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4851 * @adapter: board private structure
4852 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4854 * Return 0 on success, negative on failure
4856 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4857 struct ixgbe_ring *tx_ring)
4859 struct pci_dev *pdev = adapter->pdev;
4862 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4863 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4864 if (!tx_ring->tx_buffer_info)
4865 tx_ring->tx_buffer_info = vmalloc(size);
4866 if (!tx_ring->tx_buffer_info)
4868 memset(tx_ring->tx_buffer_info, 0, size);
4870 /* round up to nearest 4K */
4871 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4872 tx_ring->size = ALIGN(tx_ring->size, 4096);
4874 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4875 &tx_ring->dma, GFP_KERNEL);
4879 tx_ring->next_to_use = 0;
4880 tx_ring->next_to_clean = 0;
4881 tx_ring->work_limit = tx_ring->count;
4885 vfree(tx_ring->tx_buffer_info);
4886 tx_ring->tx_buffer_info = NULL;
4887 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4892 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4893 * @adapter: board private structure
4895 * If this function returns with an error, then it's possible one or
4896 * more of the rings is populated (while the rest are not). It is the
4897 * callers duty to clean those orphaned rings.
4899 * Return 0 on success, negative on failure
4901 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4905 for (i = 0; i < adapter->num_tx_queues; i++) {
4906 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4909 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4917 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4918 * @adapter: board private structure
4919 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4921 * Returns 0 on success, negative on failure
4923 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4924 struct ixgbe_ring *rx_ring)
4926 struct pci_dev *pdev = adapter->pdev;
4929 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4930 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4931 if (!rx_ring->rx_buffer_info)
4932 rx_ring->rx_buffer_info = vmalloc(size);
4933 if (!rx_ring->rx_buffer_info) {
4934 e_err(probe, "vmalloc allocation failed for the Rx "
4935 "descriptor ring\n");
4938 memset(rx_ring->rx_buffer_info, 0, size);
4940 /* Round up to nearest 4K */
4941 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4942 rx_ring->size = ALIGN(rx_ring->size, 4096);
4944 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4945 &rx_ring->dma, GFP_KERNEL);
4947 if (!rx_ring->desc) {
4948 e_err(probe, "Memory allocation failed for the Rx "
4949 "descriptor ring\n");
4950 vfree(rx_ring->rx_buffer_info);
4954 rx_ring->next_to_clean = 0;
4955 rx_ring->next_to_use = 0;
4964 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4965 * @adapter: board private structure
4967 * If this function returns with an error, then it's possible one or
4968 * more of the rings is populated (while the rest are not). It is the
4969 * callers duty to clean those orphaned rings.
4971 * Return 0 on success, negative on failure
4974 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4978 for (i = 0; i < adapter->num_rx_queues; i++) {
4979 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4982 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4990 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4991 * @adapter: board private structure
4992 * @tx_ring: Tx descriptor ring for a specific queue
4994 * Free all transmit software resources
4996 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4997 struct ixgbe_ring *tx_ring)
4999 struct pci_dev *pdev = adapter->pdev;
5001 ixgbe_clean_tx_ring(adapter, tx_ring);
5003 vfree(tx_ring->tx_buffer_info);
5004 tx_ring->tx_buffer_info = NULL;
5006 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5009 tx_ring->desc = NULL;
5013 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5014 * @adapter: board private structure
5016 * Free all transmit software resources
5018 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5022 for (i = 0; i < adapter->num_tx_queues; i++)
5023 if (adapter->tx_ring[i]->desc)
5024 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5028 * ixgbe_free_rx_resources - Free Rx Resources
5029 * @adapter: board private structure
5030 * @rx_ring: ring to clean the resources from
5032 * Free all receive software resources
5034 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5035 struct ixgbe_ring *rx_ring)
5037 struct pci_dev *pdev = adapter->pdev;
5039 ixgbe_clean_rx_ring(adapter, rx_ring);
5041 vfree(rx_ring->rx_buffer_info);
5042 rx_ring->rx_buffer_info = NULL;
5044 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5047 rx_ring->desc = NULL;
5051 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5052 * @adapter: board private structure
5054 * Free all receive software resources
5056 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5060 for (i = 0; i < adapter->num_rx_queues; i++)
5061 if (adapter->rx_ring[i]->desc)
5062 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5066 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5067 * @netdev: network interface device structure
5068 * @new_mtu: new value for maximum frame size
5070 * Returns 0 on success, negative on failure
5072 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5074 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5075 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5077 /* MTU < 68 is an error and causes problems on some kernels */
5078 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5081 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5082 /* must set new MTU before calling down or up */
5083 netdev->mtu = new_mtu;
5085 if (netif_running(netdev))
5086 ixgbe_reinit_locked(adapter);
5092 * ixgbe_open - Called when a network interface is made active
5093 * @netdev: network interface device structure
5095 * Returns 0 on success, negative value on failure
5097 * The open entry point is called when a network interface is made
5098 * active by the system (IFF_UP). At this point all resources needed
5099 * for transmit and receive operations are allocated, the interrupt
5100 * handler is registered with the OS, the watchdog timer is started,
5101 * and the stack is notified that the interface is ready.
5103 static int ixgbe_open(struct net_device *netdev)
5105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5108 /* disallow open during test */
5109 if (test_bit(__IXGBE_TESTING, &adapter->state))
5112 netif_carrier_off(netdev);
5114 /* allocate transmit descriptors */
5115 err = ixgbe_setup_all_tx_resources(adapter);
5119 /* allocate receive descriptors */
5120 err = ixgbe_setup_all_rx_resources(adapter);
5124 ixgbe_configure(adapter);
5126 err = ixgbe_request_irq(adapter);
5130 err = ixgbe_up_complete(adapter);
5134 netif_tx_start_all_queues(netdev);
5139 ixgbe_release_hw_control(adapter);
5140 ixgbe_free_irq(adapter);
5143 ixgbe_free_all_rx_resources(adapter);
5145 ixgbe_free_all_tx_resources(adapter);
5146 ixgbe_reset(adapter);
5152 * ixgbe_close - Disables a network interface
5153 * @netdev: network interface device structure
5155 * Returns 0, this is not allowed to fail
5157 * The close entry point is called when an interface is de-activated
5158 * by the OS. The hardware is still under the drivers control, but
5159 * needs to be disabled. A global MAC reset is issued to stop the
5160 * hardware, and all transmit and receive resources are freed.
5162 static int ixgbe_close(struct net_device *netdev)
5164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5166 ixgbe_down(adapter);
5167 ixgbe_free_irq(adapter);
5169 ixgbe_free_all_tx_resources(adapter);
5170 ixgbe_free_all_rx_resources(adapter);
5172 ixgbe_release_hw_control(adapter);
5178 static int ixgbe_resume(struct pci_dev *pdev)
5180 struct net_device *netdev = pci_get_drvdata(pdev);
5181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5184 pci_set_power_state(pdev, PCI_D0);
5185 pci_restore_state(pdev);
5187 * pci_restore_state clears dev->state_saved so call
5188 * pci_save_state to restore it.
5190 pci_save_state(pdev);
5192 err = pci_enable_device_mem(pdev);
5194 e_dev_err("Cannot enable PCI device from suspend\n");
5197 pci_set_master(pdev);
5199 pci_wake_from_d3(pdev, false);
5201 err = ixgbe_init_interrupt_scheme(adapter);
5203 e_dev_err("Cannot initialize interrupts for device\n");
5207 ixgbe_reset(adapter);
5209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5211 if (netif_running(netdev)) {
5212 err = ixgbe_open(adapter->netdev);
5217 netif_device_attach(netdev);
5221 #endif /* CONFIG_PM */
5223 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5225 struct net_device *netdev = pci_get_drvdata(pdev);
5226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5227 struct ixgbe_hw *hw = &adapter->hw;
5229 u32 wufc = adapter->wol;
5234 netif_device_detach(netdev);
5236 if (netif_running(netdev)) {
5237 ixgbe_down(adapter);
5238 ixgbe_free_irq(adapter);
5239 ixgbe_free_all_tx_resources(adapter);
5240 ixgbe_free_all_rx_resources(adapter);
5244 retval = pci_save_state(pdev);
5250 ixgbe_set_rx_mode(netdev);
5252 /* turn on all-multi mode if wake on multicast is enabled */
5253 if (wufc & IXGBE_WUFC_MC) {
5254 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5255 fctrl |= IXGBE_FCTRL_MPE;
5256 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5259 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5260 ctrl |= IXGBE_CTRL_GIO_DIS;
5261 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5263 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5265 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5266 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5269 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5270 pci_wake_from_d3(pdev, true);
5272 pci_wake_from_d3(pdev, false);
5274 *enable_wake = !!wufc;
5276 ixgbe_clear_interrupt_scheme(adapter);
5278 ixgbe_release_hw_control(adapter);
5280 pci_disable_device(pdev);
5286 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5291 retval = __ixgbe_shutdown(pdev, &wake);
5296 pci_prepare_to_sleep(pdev);
5298 pci_wake_from_d3(pdev, false);
5299 pci_set_power_state(pdev, PCI_D3hot);
5304 #endif /* CONFIG_PM */
5306 static void ixgbe_shutdown(struct pci_dev *pdev)
5310 __ixgbe_shutdown(pdev, &wake);
5312 if (system_state == SYSTEM_POWER_OFF) {
5313 pci_wake_from_d3(pdev, wake);
5314 pci_set_power_state(pdev, PCI_D3hot);
5319 * ixgbe_update_stats - Update the board statistics counters.
5320 * @adapter: board private structure
5322 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5324 struct net_device *netdev = adapter->netdev;
5325 struct ixgbe_hw *hw = &adapter->hw;
5327 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5328 u64 non_eop_descs = 0, restart_queue = 0;
5330 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5331 test_bit(__IXGBE_RESETTING, &adapter->state))
5334 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5337 for (i = 0; i < 16; i++)
5338 adapter->hw_rx_no_dma_resources +=
5339 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5340 for (i = 0; i < adapter->num_rx_queues; i++) {
5341 rsc_count += adapter->rx_ring[i]->rsc_count;
5342 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5344 adapter->rsc_total_count = rsc_count;
5345 adapter->rsc_total_flush = rsc_flush;
5348 /* gather some stats to the adapter struct that are per queue */
5349 for (i = 0; i < adapter->num_tx_queues; i++)
5350 restart_queue += adapter->tx_ring[i]->restart_queue;
5351 adapter->restart_queue = restart_queue;
5353 for (i = 0; i < adapter->num_rx_queues; i++)
5354 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5355 adapter->non_eop_descs = non_eop_descs;
5357 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5358 for (i = 0; i < 8; i++) {
5359 /* for packet buffers not used, the register should read 0 */
5360 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5362 adapter->stats.mpc[i] += mpc;
5363 total_mpc += adapter->stats.mpc[i];
5364 if (hw->mac.type == ixgbe_mac_82598EB)
5365 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5366 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5367 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5368 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5369 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5370 if (hw->mac.type == ixgbe_mac_82599EB) {
5371 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5372 IXGBE_PXONRXCNT(i));
5373 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5374 IXGBE_PXOFFRXCNT(i));
5375 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5377 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5379 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5382 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5384 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5387 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5388 /* work around hardware counting issue */
5389 adapter->stats.gprc -= missed_rx;
5391 /* 82598 hardware only has a 32 bit counter in the high register */
5392 if (hw->mac.type == ixgbe_mac_82599EB) {
5394 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5395 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5396 adapter->stats.gorc += (tmp << 32);
5397 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5398 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5399 adapter->stats.gotc += (tmp << 32);
5400 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5401 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5402 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5403 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5404 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5405 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5407 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5408 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5409 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5410 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5411 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5412 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5413 #endif /* IXGBE_FCOE */
5415 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5416 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5417 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5418 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5419 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5421 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5422 adapter->stats.bprc += bprc;
5423 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5424 if (hw->mac.type == ixgbe_mac_82598EB)
5425 adapter->stats.mprc -= bprc;
5426 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5427 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5428 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5429 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5430 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5431 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5432 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5433 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5434 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5435 adapter->stats.lxontxc += lxon;
5436 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5437 adapter->stats.lxofftxc += lxoff;
5438 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5439 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5440 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5442 * 82598 errata - tx of flow control packets is included in tx counters
5444 xon_off_tot = lxon + lxoff;
5445 adapter->stats.gptc -= xon_off_tot;
5446 adapter->stats.mptc -= xon_off_tot;
5447 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5448 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5449 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5450 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5451 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5452 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5453 adapter->stats.ptc64 -= xon_off_tot;
5454 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5455 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5456 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5457 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5458 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5459 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5461 /* Fill out the OS statistics structure */
5462 netdev->stats.multicast = adapter->stats.mprc;
5465 netdev->stats.rx_errors = adapter->stats.crcerrs +
5466 adapter->stats.rlec;
5467 netdev->stats.rx_dropped = 0;
5468 netdev->stats.rx_length_errors = adapter->stats.rlec;
5469 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5470 netdev->stats.rx_missed_errors = total_mpc;
5474 * ixgbe_watchdog - Timer Call-back
5475 * @data: pointer to adapter cast into an unsigned long
5477 static void ixgbe_watchdog(unsigned long data)
5479 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5480 struct ixgbe_hw *hw = &adapter->hw;
5485 * Do the watchdog outside of interrupt context due to the lovely
5486 * delays that some of the newer hardware requires
5489 if (test_bit(__IXGBE_DOWN, &adapter->state))
5490 goto watchdog_short_circuit;
5492 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5494 * for legacy and MSI interrupts don't set any bits
5495 * that are enabled for EIAM, because this operation
5496 * would set *both* EIMS and EICS for any bit in EIAM
5498 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5499 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5500 goto watchdog_reschedule;
5503 /* get one bit for every active tx/rx interrupt vector */
5504 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5505 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5506 if (qv->rxr_count || qv->txr_count)
5507 eics |= ((u64)1 << i);
5510 /* Cause software interrupt to ensure rx rings are cleaned */
5511 ixgbe_irq_rearm_queues(adapter, eics);
5513 watchdog_reschedule:
5514 /* Reset the timer */
5515 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5517 watchdog_short_circuit:
5518 schedule_work(&adapter->watchdog_task);
5522 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5523 * @work: pointer to work_struct containing our data
5525 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5527 struct ixgbe_adapter *adapter = container_of(work,
5528 struct ixgbe_adapter,
5529 multispeed_fiber_task);
5530 struct ixgbe_hw *hw = &adapter->hw;
5534 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5535 autoneg = hw->phy.autoneg_advertised;
5536 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5537 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5538 hw->mac.autotry_restart = false;
5539 if (hw->mac.ops.setup_link)
5540 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5541 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5542 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5546 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5547 * @work: pointer to work_struct containing our data
5549 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5551 struct ixgbe_adapter *adapter = container_of(work,
5552 struct ixgbe_adapter,
5553 sfp_config_module_task);
5554 struct ixgbe_hw *hw = &adapter->hw;
5557 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5559 /* Time for electrical oscillations to settle down */
5561 err = hw->phy.ops.identify_sfp(hw);
5563 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5564 e_dev_err("failed to initialize because an unsupported SFP+ "
5565 "module type was detected.\n");
5566 e_dev_err("Reload the driver after installing a supported "
5568 unregister_netdev(adapter->netdev);
5571 hw->mac.ops.setup_sfp(hw);
5573 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5574 /* This will also work for DA Twinax connections */
5575 schedule_work(&adapter->multispeed_fiber_task);
5576 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5580 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5581 * @work: pointer to work_struct containing our data
5583 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5585 struct ixgbe_adapter *adapter = container_of(work,
5586 struct ixgbe_adapter,
5588 struct ixgbe_hw *hw = &adapter->hw;
5591 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5592 for (i = 0; i < adapter->num_tx_queues; i++)
5593 set_bit(__IXGBE_FDIR_INIT_DONE,
5594 &(adapter->tx_ring[i]->reinit_state));
5596 e_err(probe, "failed to finish FDIR re-initialization, "
5597 "ignored adding FDIR ATR filters\n");
5599 /* Done FDIR Re-initialization, enable transmits */
5600 netif_tx_start_all_queues(adapter->netdev);
5603 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5606 * ixgbe_watchdog_task - worker thread to bring link up
5607 * @work: pointer to work_struct containing our data
5609 static void ixgbe_watchdog_task(struct work_struct *work)
5611 struct ixgbe_adapter *adapter = container_of(work,
5612 struct ixgbe_adapter,
5614 struct net_device *netdev = adapter->netdev;
5615 struct ixgbe_hw *hw = &adapter->hw;
5619 struct ixgbe_ring *tx_ring;
5620 int some_tx_pending = 0;
5622 mutex_lock(&ixgbe_watchdog_lock);
5624 link_up = adapter->link_up;
5625 link_speed = adapter->link_speed;
5627 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5628 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5631 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5632 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5633 hw->mac.ops.fc_enable(hw, i);
5635 hw->mac.ops.fc_enable(hw, 0);
5638 hw->mac.ops.fc_enable(hw, 0);
5643 time_after(jiffies, (adapter->link_check_timeout +
5644 IXGBE_TRY_LINK_TIMEOUT))) {
5645 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5646 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5648 adapter->link_up = link_up;
5649 adapter->link_speed = link_speed;
5653 if (!netif_carrier_ok(netdev)) {
5654 bool flow_rx, flow_tx;
5656 if (hw->mac.type == ixgbe_mac_82599EB) {
5657 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5658 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5659 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5660 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5662 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5663 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5664 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5665 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5668 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5669 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5671 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5672 "1 Gbps" : "unknown speed")),
5673 ((flow_rx && flow_tx) ? "RX/TX" :
5675 (flow_tx ? "TX" : "None"))));
5677 netif_carrier_on(netdev);
5679 /* Force detection of hung controller */
5680 adapter->detect_tx_hung = true;
5683 adapter->link_up = false;
5684 adapter->link_speed = 0;
5685 if (netif_carrier_ok(netdev)) {
5686 e_info(drv, "NIC Link is Down\n");
5687 netif_carrier_off(netdev);
5691 if (!netif_carrier_ok(netdev)) {
5692 for (i = 0; i < adapter->num_tx_queues; i++) {
5693 tx_ring = adapter->tx_ring[i];
5694 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5695 some_tx_pending = 1;
5700 if (some_tx_pending) {
5701 /* We've lost link, so the controller stops DMA,
5702 * but we've got queued Tx work that's never going
5703 * to get done, so reset controller to flush Tx.
5704 * (Do the reset outside of interrupt context).
5706 schedule_work(&adapter->reset_task);
5710 ixgbe_update_stats(adapter);
5711 mutex_unlock(&ixgbe_watchdog_lock);
5714 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5715 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5716 u32 tx_flags, u8 *hdr_len)
5718 struct ixgbe_adv_tx_context_desc *context_desc;
5721 struct ixgbe_tx_buffer *tx_buffer_info;
5722 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5723 u32 mss_l4len_idx, l4len;
5725 if (skb_is_gso(skb)) {
5726 if (skb_header_cloned(skb)) {
5727 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5731 l4len = tcp_hdrlen(skb);
5734 if (skb->protocol == htons(ETH_P_IP)) {
5735 struct iphdr *iph = ip_hdr(skb);
5738 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5742 } else if (skb_is_gso_v6(skb)) {
5743 ipv6_hdr(skb)->payload_len = 0;
5744 tcp_hdr(skb)->check =
5745 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5746 &ipv6_hdr(skb)->daddr,
5750 i = tx_ring->next_to_use;
5752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5753 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5755 /* VLAN MACLEN IPLEN */
5756 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5758 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5759 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5760 IXGBE_ADVTXD_MACLEN_SHIFT);
5761 *hdr_len += skb_network_offset(skb);
5763 (skb_transport_header(skb) - skb_network_header(skb));
5765 (skb_transport_header(skb) - skb_network_header(skb));
5766 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5767 context_desc->seqnum_seed = 0;
5769 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5770 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5771 IXGBE_ADVTXD_DTYP_CTXT);
5773 if (skb->protocol == htons(ETH_P_IP))
5774 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5775 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5776 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5780 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5781 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5782 /* use index 1 for TSO */
5783 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5784 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5786 tx_buffer_info->time_stamp = jiffies;
5787 tx_buffer_info->next_to_watch = i;
5790 if (i == tx_ring->count)
5792 tx_ring->next_to_use = i;
5799 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5800 struct ixgbe_ring *tx_ring,
5801 struct sk_buff *skb, u32 tx_flags)
5803 struct ixgbe_adv_tx_context_desc *context_desc;
5805 struct ixgbe_tx_buffer *tx_buffer_info;
5806 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5808 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5809 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5810 i = tx_ring->next_to_use;
5811 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5812 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5814 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5816 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5817 vlan_macip_lens |= (skb_network_offset(skb) <<
5818 IXGBE_ADVTXD_MACLEN_SHIFT);
5819 if (skb->ip_summed == CHECKSUM_PARTIAL)
5820 vlan_macip_lens |= (skb_transport_header(skb) -
5821 skb_network_header(skb));
5823 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5824 context_desc->seqnum_seed = 0;
5826 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5827 IXGBE_ADVTXD_DTYP_CTXT);
5829 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5832 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5833 const struct vlan_ethhdr *vhdr =
5834 (const struct vlan_ethhdr *)skb->data;
5836 protocol = vhdr->h_vlan_encapsulated_proto;
5838 protocol = skb->protocol;
5842 case cpu_to_be16(ETH_P_IP):
5843 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5844 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5846 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5847 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5849 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5851 case cpu_to_be16(ETH_P_IPV6):
5852 /* XXX what about other V6 headers?? */
5853 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5855 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5856 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5858 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5861 if (unlikely(net_ratelimit())) {
5862 e_warn(probe, "partial checksum "
5870 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5871 /* use index zero for tx checksum offload */
5872 context_desc->mss_l4len_idx = 0;
5874 tx_buffer_info->time_stamp = jiffies;
5875 tx_buffer_info->next_to_watch = i;
5878 if (i == tx_ring->count)
5880 tx_ring->next_to_use = i;
5888 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5889 struct ixgbe_ring *tx_ring,
5890 struct sk_buff *skb, u32 tx_flags,
5893 struct pci_dev *pdev = adapter->pdev;
5894 struct ixgbe_tx_buffer *tx_buffer_info;
5896 unsigned int total = skb->len;
5897 unsigned int offset = 0, size, count = 0, i;
5898 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5901 i = tx_ring->next_to_use;
5903 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5904 /* excluding fcoe_crc_eof for FCoE */
5905 total -= sizeof(struct fcoe_crc_eof);
5907 len = min(skb_headlen(skb), total);
5909 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5910 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5912 tx_buffer_info->length = size;
5913 tx_buffer_info->mapped_as_page = false;
5914 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5916 size, DMA_TO_DEVICE);
5917 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5919 tx_buffer_info->time_stamp = jiffies;
5920 tx_buffer_info->next_to_watch = i;
5929 if (i == tx_ring->count)
5934 for (f = 0; f < nr_frags; f++) {
5935 struct skb_frag_struct *frag;
5937 frag = &skb_shinfo(skb)->frags[f];
5938 len = min((unsigned int)frag->size, total);
5939 offset = frag->page_offset;
5943 if (i == tx_ring->count)
5946 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5947 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5949 tx_buffer_info->length = size;
5950 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5954 tx_buffer_info->mapped_as_page = true;
5955 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5957 tx_buffer_info->time_stamp = jiffies;
5958 tx_buffer_info->next_to_watch = i;
5969 tx_ring->tx_buffer_info[i].skb = skb;
5970 tx_ring->tx_buffer_info[first].next_to_watch = i;
5975 e_dev_err("TX DMA map failed\n");
5977 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5978 tx_buffer_info->dma = 0;
5979 tx_buffer_info->time_stamp = 0;
5980 tx_buffer_info->next_to_watch = 0;
5984 /* clear timestamp and dma mappings for remaining portion of packet */
5987 i += tx_ring->count;
5989 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5990 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5996 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5997 struct ixgbe_ring *tx_ring,
5998 int tx_flags, int count, u32 paylen, u8 hdr_len)
6000 union ixgbe_adv_tx_desc *tx_desc = NULL;
6001 struct ixgbe_tx_buffer *tx_buffer_info;
6002 u32 olinfo_status = 0, cmd_type_len = 0;
6004 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6006 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6008 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6010 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6011 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6013 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6014 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6016 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6017 IXGBE_ADVTXD_POPTS_SHIFT;
6019 /* use index 1 context for tso */
6020 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6021 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6022 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6023 IXGBE_ADVTXD_POPTS_SHIFT;
6025 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6026 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6027 IXGBE_ADVTXD_POPTS_SHIFT;
6029 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6030 olinfo_status |= IXGBE_ADVTXD_CC;
6031 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6032 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6033 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6036 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6038 i = tx_ring->next_to_use;
6040 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6041 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6042 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6043 tx_desc->read.cmd_type_len =
6044 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6045 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6047 if (i == tx_ring->count)
6051 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6054 * Force memory writes to complete before letting h/w
6055 * know there are new descriptors to fetch. (Only
6056 * applicable for weak-ordered memory model archs,
6061 tx_ring->next_to_use = i;
6062 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6065 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6066 int queue, u32 tx_flags)
6068 struct ixgbe_atr_input atr_input;
6070 struct iphdr *iph = ip_hdr(skb);
6071 struct ethhdr *eth = (struct ethhdr *)skb->data;
6072 u16 vlan_id, src_port, dst_port, flex_bytes;
6073 u32 src_ipv4_addr, dst_ipv4_addr;
6076 /* Right now, we support IPv4 only */
6077 if (skb->protocol != htons(ETH_P_IP))
6079 /* check if we're UDP or TCP */
6080 if (iph->protocol == IPPROTO_TCP) {
6082 src_port = th->source;
6083 dst_port = th->dest;
6084 l4type |= IXGBE_ATR_L4TYPE_TCP;
6085 /* l4type IPv4 type is 0, no need to assign */
6087 /* Unsupported L4 header, just bail here */
6091 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6093 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6094 IXGBE_TX_FLAGS_VLAN_SHIFT;
6095 src_ipv4_addr = iph->saddr;
6096 dst_ipv4_addr = iph->daddr;
6097 flex_bytes = eth->h_proto;
6099 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6100 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6101 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6102 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6103 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6104 /* src and dst are inverted, think how the receiver sees them */
6105 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6106 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6108 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6109 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6112 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6113 struct ixgbe_ring *tx_ring, int size)
6115 netif_stop_subqueue(netdev, tx_ring->queue_index);
6116 /* Herbert's original patch had:
6117 * smp_mb__after_netif_stop_queue();
6118 * but since that doesn't exist yet, just open code it. */
6121 /* We need to check again in a case another CPU has just
6122 * made room available. */
6123 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6126 /* A reprieve! - use start_queue because it doesn't call schedule */
6127 netif_start_subqueue(netdev, tx_ring->queue_index);
6128 ++tx_ring->restart_queue;
6132 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6133 struct ixgbe_ring *tx_ring, int size)
6135 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6137 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6140 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6142 struct ixgbe_adapter *adapter = netdev_priv(dev);
6143 int txq = smp_processor_id();
6146 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6147 (skb->protocol == htons(ETH_P_FIP))) {
6148 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6149 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6150 txq += adapter->ring_feature[RING_F_FCOE].mask;
6152 #ifdef CONFIG_IXGBE_DCB
6153 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6154 txq = adapter->fcoe.up;
6161 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6162 while (unlikely(txq >= dev->real_num_tx_queues))
6163 txq -= dev->real_num_tx_queues;
6167 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6168 if (skb->priority == TC_PRIO_CONTROL)
6169 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6171 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6176 return skb_tx_hash(dev, skb);
6179 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6180 struct net_device *netdev)
6182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6183 struct ixgbe_ring *tx_ring;
6184 struct netdev_queue *txq;
6186 unsigned int tx_flags = 0;
6192 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6193 tx_flags |= vlan_tx_tag_get(skb);
6194 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6195 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6196 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6198 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6199 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6200 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6201 skb->priority != TC_PRIO_CONTROL) {
6202 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6203 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6204 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6207 tx_ring = adapter->tx_ring[skb->queue_mapping];
6210 /* for FCoE with DCB, we force the priority to what
6211 * was specified by the switch */
6212 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6213 (skb->protocol == htons(ETH_P_FCOE) ||
6214 skb->protocol == htons(ETH_P_FIP))) {
6215 #ifdef CONFIG_IXGBE_DCB
6216 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6217 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6218 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6219 tx_flags |= ((adapter->fcoe.up << 13)
6220 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6223 /* flag for FCoE offloads */
6224 if (skb->protocol == htons(ETH_P_FCOE))
6225 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6229 /* four things can cause us to need a context descriptor */
6230 if (skb_is_gso(skb) ||
6231 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6232 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6233 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6236 count += TXD_USE_COUNT(skb_headlen(skb));
6237 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6238 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6240 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6242 return NETDEV_TX_BUSY;
6245 first = tx_ring->next_to_use;
6246 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6248 /* setup tx offload for FCoE */
6249 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6251 dev_kfree_skb_any(skb);
6252 return NETDEV_TX_OK;
6255 tx_flags |= IXGBE_TX_FLAGS_FSO;
6256 #endif /* IXGBE_FCOE */
6258 if (skb->protocol == htons(ETH_P_IP))
6259 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6260 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6262 dev_kfree_skb_any(skb);
6263 return NETDEV_TX_OK;
6267 tx_flags |= IXGBE_TX_FLAGS_TSO;
6268 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6269 (skb->ip_summed == CHECKSUM_PARTIAL))
6270 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6273 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6275 /* add the ATR filter if ATR is on */
6276 if (tx_ring->atr_sample_rate) {
6277 ++tx_ring->atr_count;
6278 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6279 test_bit(__IXGBE_FDIR_INIT_DONE,
6280 &tx_ring->reinit_state)) {
6281 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6283 tx_ring->atr_count = 0;
6286 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6287 txq->tx_bytes += skb->len;
6289 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6291 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6294 dev_kfree_skb_any(skb);
6295 tx_ring->tx_buffer_info[first].time_stamp = 0;
6296 tx_ring->next_to_use = first;
6299 return NETDEV_TX_OK;
6303 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6304 * @netdev: network interface device structure
6305 * @p: pointer to an address structure
6307 * Returns 0 on success, negative on failure
6309 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6312 struct ixgbe_hw *hw = &adapter->hw;
6313 struct sockaddr *addr = p;
6315 if (!is_valid_ether_addr(addr->sa_data))
6316 return -EADDRNOTAVAIL;
6318 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6319 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6321 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6328 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6330 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6331 struct ixgbe_hw *hw = &adapter->hw;
6335 if (prtad != hw->phy.mdio.prtad)
6337 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6343 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6344 u16 addr, u16 value)
6346 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6347 struct ixgbe_hw *hw = &adapter->hw;
6349 if (prtad != hw->phy.mdio.prtad)
6351 return hw->phy.ops.write_reg(hw, addr, devad, value);
6354 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6356 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6358 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6362 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6364 * @netdev: network interface device structure
6366 * Returns non-zero on failure
6368 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6371 struct ixgbe_adapter *adapter = netdev_priv(dev);
6372 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6374 if (is_valid_ether_addr(mac->san_addr)) {
6376 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6383 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6385 * @netdev: network interface device structure
6387 * Returns non-zero on failure
6389 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6392 struct ixgbe_adapter *adapter = netdev_priv(dev);
6393 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6395 if (is_valid_ether_addr(mac->san_addr)) {
6397 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6403 #ifdef CONFIG_NET_POLL_CONTROLLER
6405 * Polling 'interrupt' - used by things like netconsole to send skbs
6406 * without having to re-enable interrupts. It's not called while
6407 * the interrupt routine is executing.
6409 static void ixgbe_netpoll(struct net_device *netdev)
6411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6414 /* if interface is down do nothing */
6415 if (test_bit(__IXGBE_DOWN, &adapter->state))
6418 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6419 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6420 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6421 for (i = 0; i < num_q_vectors; i++) {
6422 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6423 ixgbe_msix_clean_many(0, q_vector);
6426 ixgbe_intr(adapter->pdev->irq, netdev);
6428 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6432 static const struct net_device_ops ixgbe_netdev_ops = {
6433 .ndo_open = ixgbe_open,
6434 .ndo_stop = ixgbe_close,
6435 .ndo_start_xmit = ixgbe_xmit_frame,
6436 .ndo_select_queue = ixgbe_select_queue,
6437 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6438 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6439 .ndo_validate_addr = eth_validate_addr,
6440 .ndo_set_mac_address = ixgbe_set_mac,
6441 .ndo_change_mtu = ixgbe_change_mtu,
6442 .ndo_tx_timeout = ixgbe_tx_timeout,
6443 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6444 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6445 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6446 .ndo_do_ioctl = ixgbe_ioctl,
6447 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6448 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6449 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6450 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6451 #ifdef CONFIG_NET_POLL_CONTROLLER
6452 .ndo_poll_controller = ixgbe_netpoll,
6455 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6456 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6457 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6458 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6459 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6460 #endif /* IXGBE_FCOE */
6463 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6464 const struct ixgbe_info *ii)
6466 #ifdef CONFIG_PCI_IOV
6467 struct ixgbe_hw *hw = &adapter->hw;
6470 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6473 /* The 82599 supports up to 64 VFs per physical function
6474 * but this implementation limits allocation to 63 so that
6475 * basic networking resources are still available to the
6478 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6479 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6480 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6482 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6485 /* If call to enable VFs succeeded then allocate memory
6486 * for per VF control structures.
6489 kcalloc(adapter->num_vfs,
6490 sizeof(struct vf_data_storage), GFP_KERNEL);
6491 if (adapter->vfinfo) {
6492 /* Now that we're sure SR-IOV is enabled
6493 * and memory allocated set up the mailbox parameters
6495 ixgbe_init_mbx_params_pf(hw);
6496 memcpy(&hw->mbx.ops, ii->mbx_ops,
6497 sizeof(hw->mbx.ops));
6499 /* Disable RSC when in SR-IOV mode */
6500 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6501 IXGBE_FLAG2_RSC_ENABLED);
6506 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6507 "SRIOV disabled\n");
6508 pci_disable_sriov(adapter->pdev);
6511 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6512 adapter->num_vfs = 0;
6513 #endif /* CONFIG_PCI_IOV */
6517 * ixgbe_probe - Device Initialization Routine
6518 * @pdev: PCI device information struct
6519 * @ent: entry in ixgbe_pci_tbl
6521 * Returns 0 on success, negative on failure
6523 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6524 * The OS initialization, configuring of the adapter private structure,
6525 * and a hardware reset occur.
6527 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6528 const struct pci_device_id *ent)
6530 struct net_device *netdev;
6531 struct ixgbe_adapter *adapter = NULL;
6532 struct ixgbe_hw *hw;
6533 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6534 static int cards_found;
6535 int i, err, pci_using_dac;
6536 unsigned int indices = num_possible_cpus();
6542 /* Catch broken hardware that put the wrong VF device ID in
6543 * the PCIe SR-IOV capability.
6545 if (pdev->is_virtfn) {
6546 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6547 pci_name(pdev), pdev->vendor, pdev->device);
6551 err = pci_enable_device_mem(pdev);
6555 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6556 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6559 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6561 err = dma_set_coherent_mask(&pdev->dev,
6565 "No usable DMA configuration, aborting\n");
6572 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6573 IORESOURCE_MEM), ixgbe_driver_name);
6576 "pci_request_selected_regions failed 0x%x\n", err);
6580 pci_enable_pcie_error_reporting(pdev);
6582 pci_set_master(pdev);
6583 pci_save_state(pdev);
6585 if (ii->mac == ixgbe_mac_82598EB)
6586 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6588 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6590 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6592 indices += min_t(unsigned int, num_possible_cpus(),
6593 IXGBE_MAX_FCOE_INDICES);
6595 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6598 goto err_alloc_etherdev;
6601 SET_NETDEV_DEV(netdev, &pdev->dev);
6603 pci_set_drvdata(pdev, netdev);
6604 adapter = netdev_priv(netdev);
6606 adapter->netdev = netdev;
6607 adapter->pdev = pdev;
6610 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6612 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6613 pci_resource_len(pdev, 0));
6619 for (i = 1; i <= 5; i++) {
6620 if (pci_resource_len(pdev, i) == 0)
6624 netdev->netdev_ops = &ixgbe_netdev_ops;
6625 ixgbe_set_ethtool_ops(netdev);
6626 netdev->watchdog_timeo = 5 * HZ;
6627 strcpy(netdev->name, pci_name(pdev));
6629 adapter->bd_number = cards_found;
6632 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6633 hw->mac.type = ii->mac;
6636 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6637 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6638 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6639 if (!(eec & (1 << 8)))
6640 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6643 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6644 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6645 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6646 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6647 hw->phy.mdio.mmds = 0;
6648 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6649 hw->phy.mdio.dev = netdev;
6650 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6651 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6653 /* set up this timer and work struct before calling get_invariants
6654 * which might start the timer
6656 init_timer(&adapter->sfp_timer);
6657 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6658 adapter->sfp_timer.data = (unsigned long) adapter;
6660 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6662 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6663 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6665 /* a new SFP+ module arrival, called from GPI SDP2 context */
6666 INIT_WORK(&adapter->sfp_config_module_task,
6667 ixgbe_sfp_config_module_task);
6669 ii->get_invariants(hw);
6671 /* setup the private structure */
6672 err = ixgbe_sw_init(adapter);
6676 /* Make it possible the adapter to be woken up via WOL */
6677 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6681 * If there is a fan on this device and it has failed log the
6684 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6685 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6686 if (esdp & IXGBE_ESDP_SDP1)
6687 e_crit(probe, "Fan has stopped, replace the adapter\n");
6690 /* reset_hw fills in the perm_addr as well */
6691 hw->phy.reset_if_overtemp = true;
6692 err = hw->mac.ops.reset_hw(hw);
6693 hw->phy.reset_if_overtemp = false;
6694 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6695 hw->mac.type == ixgbe_mac_82598EB) {
6697 * Start a kernel thread to watch for a module to arrive.
6698 * Only do this for 82598, since 82599 will generate
6699 * interrupts on module arrival.
6701 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6702 mod_timer(&adapter->sfp_timer,
6703 round_jiffies(jiffies + (2 * HZ)));
6705 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6706 e_dev_err("failed to initialize because an unsupported SFP+ "
6707 "module type was detected.\n");
6708 e_dev_err("Reload the driver after installing a supported "
6712 e_dev_err("HW Init failed: %d\n", err);
6716 ixgbe_probe_vf(adapter, ii);
6718 netdev->features = NETIF_F_SG |
6720 NETIF_F_HW_VLAN_TX |
6721 NETIF_F_HW_VLAN_RX |
6722 NETIF_F_HW_VLAN_FILTER;
6724 netdev->features |= NETIF_F_IPV6_CSUM;
6725 netdev->features |= NETIF_F_TSO;
6726 netdev->features |= NETIF_F_TSO6;
6727 netdev->features |= NETIF_F_GRO;
6729 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6730 netdev->features |= NETIF_F_SCTP_CSUM;
6732 netdev->vlan_features |= NETIF_F_TSO;
6733 netdev->vlan_features |= NETIF_F_TSO6;
6734 netdev->vlan_features |= NETIF_F_IP_CSUM;
6735 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6736 netdev->vlan_features |= NETIF_F_SG;
6738 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6739 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6740 IXGBE_FLAG_DCB_ENABLED);
6741 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6742 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6744 #ifdef CONFIG_IXGBE_DCB
6745 netdev->dcbnl_ops = &dcbnl_ops;
6749 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6750 if (hw->mac.ops.get_device_caps) {
6751 hw->mac.ops.get_device_caps(hw, &device_caps);
6752 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6753 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6756 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6757 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6758 netdev->vlan_features |= NETIF_F_FSO;
6759 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6761 #endif /* IXGBE_FCOE */
6763 netdev->features |= NETIF_F_HIGHDMA;
6765 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6766 netdev->features |= NETIF_F_LRO;
6768 /* make sure the EEPROM is good */
6769 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6770 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6775 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6776 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6778 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6779 e_dev_err("invalid MAC address\n");
6784 /* power down the optics */
6785 if (hw->phy.multispeed_fiber)
6786 hw->mac.ops.disable_tx_laser(hw);
6788 init_timer(&adapter->watchdog_timer);
6789 adapter->watchdog_timer.function = &ixgbe_watchdog;
6790 adapter->watchdog_timer.data = (unsigned long)adapter;
6792 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6793 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6795 err = ixgbe_init_interrupt_scheme(adapter);
6799 switch (pdev->device) {
6800 case IXGBE_DEV_ID_82599_KX4:
6801 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6802 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6808 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6810 /* pick up the PCI bus settings for reporting later */
6811 hw->mac.ops.get_bus_info(hw);
6813 /* print bus type/speed/width info */
6814 e_dev_info("(PCI Express:%s:%s) %pM\n",
6815 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6816 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6817 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6818 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6819 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6822 ixgbe_read_pba_num_generic(hw, &part_num);
6823 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6824 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6825 "PBA No: %06x-%03x\n",
6826 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6827 (part_num >> 8), (part_num & 0xff));
6829 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6830 hw->mac.type, hw->phy.type,
6831 (part_num >> 8), (part_num & 0xff));
6833 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6834 e_dev_warn("PCI-Express bandwidth available for this card is "
6835 "not sufficient for optimal performance.\n");
6836 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6840 /* save off EEPROM version number */
6841 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6843 /* reset the hardware with the new settings */
6844 err = hw->mac.ops.start_hw(hw);
6846 if (err == IXGBE_ERR_EEPROM_VERSION) {
6847 /* We are running on a pre-production device, log a warning */
6848 e_dev_warn("This device is a pre-production adapter/LOM. "
6849 "Please be aware there may be issues associated "
6850 "with your hardware. If you are experiencing "
6851 "problems please contact your Intel or hardware "
6852 "representative who provided you with this "
6855 strcpy(netdev->name, "eth%d");
6856 err = register_netdev(netdev);
6860 /* carrier off reporting is important to ethtool even BEFORE open */
6861 netif_carrier_off(netdev);
6863 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6864 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6865 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6867 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6868 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6869 #ifdef CONFIG_IXGBE_DCA
6870 if (dca_add_requester(&pdev->dev) == 0) {
6871 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6872 ixgbe_setup_dca(adapter);
6875 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6876 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6877 for (i = 0; i < adapter->num_vfs; i++)
6878 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6881 /* add san mac addr to netdev */
6882 ixgbe_add_sanmac_netdev(netdev);
6884 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6889 ixgbe_release_hw_control(adapter);
6890 ixgbe_clear_interrupt_scheme(adapter);
6893 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6894 ixgbe_disable_sriov(adapter);
6895 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6896 del_timer_sync(&adapter->sfp_timer);
6897 cancel_work_sync(&adapter->sfp_task);
6898 cancel_work_sync(&adapter->multispeed_fiber_task);
6899 cancel_work_sync(&adapter->sfp_config_module_task);
6900 iounmap(hw->hw_addr);
6902 free_netdev(netdev);
6904 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6908 pci_disable_device(pdev);
6913 * ixgbe_remove - Device Removal Routine
6914 * @pdev: PCI device information struct
6916 * ixgbe_remove is called by the PCI subsystem to alert the driver
6917 * that it should release a PCI device. The could be caused by a
6918 * Hot-Plug event, or because the driver is going to be removed from
6921 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6923 struct net_device *netdev = pci_get_drvdata(pdev);
6924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926 set_bit(__IXGBE_DOWN, &adapter->state);
6927 /* clear the module not found bit to make sure the worker won't
6930 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6931 del_timer_sync(&adapter->watchdog_timer);
6933 del_timer_sync(&adapter->sfp_timer);
6934 cancel_work_sync(&adapter->watchdog_task);
6935 cancel_work_sync(&adapter->sfp_task);
6936 cancel_work_sync(&adapter->multispeed_fiber_task);
6937 cancel_work_sync(&adapter->sfp_config_module_task);
6938 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6939 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6940 cancel_work_sync(&adapter->fdir_reinit_task);
6941 flush_scheduled_work();
6943 #ifdef CONFIG_IXGBE_DCA
6944 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6945 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6946 dca_remove_requester(&pdev->dev);
6947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6952 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6953 ixgbe_cleanup_fcoe(adapter);
6955 #endif /* IXGBE_FCOE */
6957 /* remove the added san mac */
6958 ixgbe_del_sanmac_netdev(netdev);
6960 if (netdev->reg_state == NETREG_REGISTERED)
6961 unregister_netdev(netdev);
6963 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6964 ixgbe_disable_sriov(adapter);
6966 ixgbe_clear_interrupt_scheme(adapter);
6968 ixgbe_release_hw_control(adapter);
6970 iounmap(adapter->hw.hw_addr);
6971 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6974 e_dev_info("complete\n");
6976 free_netdev(netdev);
6978 pci_disable_pcie_error_reporting(pdev);
6980 pci_disable_device(pdev);
6984 * ixgbe_io_error_detected - called when PCI error is detected
6985 * @pdev: Pointer to PCI device
6986 * @state: The current pci connection state
6988 * This function is called after a PCI bus error affecting
6989 * this device has been detected.
6991 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6992 pci_channel_state_t state)
6994 struct net_device *netdev = pci_get_drvdata(pdev);
6995 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6997 netif_device_detach(netdev);
6999 if (state == pci_channel_io_perm_failure)
7000 return PCI_ERS_RESULT_DISCONNECT;
7002 if (netif_running(netdev))
7003 ixgbe_down(adapter);
7004 pci_disable_device(pdev);
7006 /* Request a slot reset. */
7007 return PCI_ERS_RESULT_NEED_RESET;
7011 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7012 * @pdev: Pointer to PCI device
7014 * Restart the card from scratch, as if from a cold-boot.
7016 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7018 struct net_device *netdev = pci_get_drvdata(pdev);
7019 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7020 pci_ers_result_t result;
7023 if (pci_enable_device_mem(pdev)) {
7024 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7025 result = PCI_ERS_RESULT_DISCONNECT;
7027 pci_set_master(pdev);
7028 pci_restore_state(pdev);
7029 pci_save_state(pdev);
7031 pci_wake_from_d3(pdev, false);
7033 ixgbe_reset(adapter);
7034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7035 result = PCI_ERS_RESULT_RECOVERED;
7038 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7040 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7041 "failed 0x%0x\n", err);
7042 /* non-fatal, continue */
7049 * ixgbe_io_resume - called when traffic can start flowing again.
7050 * @pdev: Pointer to PCI device
7052 * This callback is called when the error recovery driver tells us that
7053 * its OK to resume normal operation.
7055 static void ixgbe_io_resume(struct pci_dev *pdev)
7057 struct net_device *netdev = pci_get_drvdata(pdev);
7058 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7060 if (netif_running(netdev)) {
7061 if (ixgbe_up(adapter)) {
7062 e_info(probe, "ixgbe_up failed after reset\n");
7067 netif_device_attach(netdev);
7070 static struct pci_error_handlers ixgbe_err_handler = {
7071 .error_detected = ixgbe_io_error_detected,
7072 .slot_reset = ixgbe_io_slot_reset,
7073 .resume = ixgbe_io_resume,
7076 static struct pci_driver ixgbe_driver = {
7077 .name = ixgbe_driver_name,
7078 .id_table = ixgbe_pci_tbl,
7079 .probe = ixgbe_probe,
7080 .remove = __devexit_p(ixgbe_remove),
7082 .suspend = ixgbe_suspend,
7083 .resume = ixgbe_resume,
7085 .shutdown = ixgbe_shutdown,
7086 .err_handler = &ixgbe_err_handler
7090 * ixgbe_init_module - Driver Registration Routine
7092 * ixgbe_init_module is the first routine called when the driver is
7093 * loaded. All it does is register with the PCI subsystem.
7095 static int __init ixgbe_init_module(void)
7098 pr_info("%s - version %s\n", ixgbe_driver_string,
7099 ixgbe_driver_version);
7100 pr_info("%s\n", ixgbe_copyright);
7102 #ifdef CONFIG_IXGBE_DCA
7103 dca_register_notify(&dca_notifier);
7106 ret = pci_register_driver(&ixgbe_driver);
7110 module_init(ixgbe_init_module);
7113 * ixgbe_exit_module - Driver Exit Cleanup Routine
7115 * ixgbe_exit_module is called just before the driver is removed
7118 static void __exit ixgbe_exit_module(void)
7120 #ifdef CONFIG_IXGBE_DCA
7121 dca_unregister_notify(&dca_notifier);
7123 pci_unregister_driver(&ixgbe_driver);
7126 #ifdef CONFIG_IXGBE_DCA
7127 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7132 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7133 __ixgbe_notify_dca);
7135 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7138 #endif /* CONFIG_IXGBE_DCA */
7141 * ixgbe_get_hw_dev return device
7142 * used by hardware layer to print debugging information
7144 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7146 struct ixgbe_adapter *adapter = hw->back;
7147 return adapter->netdev;
7150 module_exit(ixgbe_exit_module);