drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.16-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  92          board_82599 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  94          board_82599 },
  95
  96         /* required last entry */
  97         {0, }
  98 };
  99 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 100
 101 #ifdef CONFIG_IXGBE_DCA
 102 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 103                             void *p);
 104 static struct notifier_block dca_notifier = {
 105         .notifier_call = ixgbe_notify_dca,
 106         .next          = NULL,
 107         .priority      = 0
 108 };
 109 #endif
 110
 111 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 112 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 113 MODULE_LICENSE("GPL");
 114 MODULE_VERSION(DRV_VERSION);
 115
 116 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 117
 118 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 119 {
 120         u32 ctrl_ext;
 121
 122         /* Let firmware take over control of h/w */
 123         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 124         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 125                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 126 }
 127
 128 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 129 {
 130         u32 ctrl_ext;
 131
 132         /* Let firmware know the driver has taken over */
 133         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 134         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 135                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 136 }
 137
 138 /*
 139  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 140  * @adapter: pointer to adapter struct
 141  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 142  * @queue: queue to map the corresponding interrupt to
 143  * @msix_vector: the vector to map to the corresponding queue
 144  *
 145  */
 146 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 147                            u8 queue, u8 msix_vector)
 148 {
 149         u32 ivar, index;
 150         struct ixgbe_hw *hw = &adapter->hw;
 151         switch (hw->mac.type) {
 152         case ixgbe_mac_82598EB:
 153                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 154                 if (direction == -1)
 155                         direction = 0;
 156                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 157                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 158                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 159                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 160                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 161                 break;
 162         case ixgbe_mac_82599EB:
 163                 if (direction == -1) {
 164                         /* other causes */
 165                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 166                         index = ((queue & 1) * 8);
 167                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 168                         ivar &= ~(0xFF << index);
 169                         ivar |= (msix_vector << index);
 170                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 171                         break;
 172                 } else {
 173                         /* tx or rx causes */
 174                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 175                         index = ((16 * (queue & 1)) + (8 * direction));
 176                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 177                         ivar &= ~(0xFF << index);
 178                         ivar |= (msix_vector << index);
 179                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 180                         break;
 181                 }
 182         default:
 183                 break;
 184         }
 185 }
 186
 187 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 188                                              struct ixgbe_tx_buffer
 189                                              *tx_buffer_info)
 190 {
 191         tx_buffer_info->dma = 0;
 192         if (tx_buffer_info->skb) {
 193                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 194                               DMA_TO_DEVICE);
 195                 dev_kfree_skb_any(tx_buffer_info->skb);
 196                 tx_buffer_info->skb = NULL;
 197         }
 198         tx_buffer_info->time_stamp = 0;
 199         /* tx_buffer_info must be completely set up in the transmit path */
 200 }
 201
 202 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 203                                        struct ixgbe_ring *tx_ring,
 204                                        unsigned int eop)
 205 {
 206         struct ixgbe_hw *hw = &adapter->hw;
 207
 208         /* Detect a transmit hang in hardware, this serializes the
 209          * check with the clearing of time_stamp and movement of eop */
 210         adapter->detect_tx_hung = false;
 211         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 212             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 213             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 214                 /* detected Tx unit hang */
 215                 union ixgbe_adv_tx_desc *tx_desc;
 216                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 217                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 218                         "  Tx Queue             <%d>\n"
 219                         "  TDH, TDT             <%x>, <%x>\n"
 220                         "  next_to_use          <%x>\n"
 221                         "  next_to_clean        <%x>\n"
 222                         "tx_buffer_info[next_to_clean]\n"
 223                         "  time_stamp           <%lx>\n"
 224                         "  jiffies              <%lx>\n",
 225                         tx_ring->queue_index,
 226                         IXGBE_READ_REG(hw, tx_ring->head),
 227                         IXGBE_READ_REG(hw, tx_ring->tail),
 228                         tx_ring->next_to_use, eop,
 229                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 230                 return true;
 231         }
 232
 233         return false;
 234 }
 235
 236 #define IXGBE_MAX_TXD_PWR       14
 237 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 238
 239 /* Tx Descriptors needed, worst case */
 240 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 241                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 242 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 243         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 244
 245 static void ixgbe_tx_timeout(struct net_device *netdev);
 246
 247 /**
 248  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 249  * @adapter: board private structure
 250  * @tx_ring: tx ring to clean
 251  *
 252  * returns true if transmit work is done
 253  **/
 254 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 255                                struct ixgbe_ring *tx_ring)
 256 {
 257         struct net_device *netdev = adapter->netdev;
 258         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 259         struct ixgbe_tx_buffer *tx_buffer_info;
 260         unsigned int i, eop, count = 0;
 261         unsigned int total_bytes = 0, total_packets = 0;
 262
 263         i = tx_ring->next_to_clean;
 264         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 265         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 266
 267         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 268                (count < tx_ring->work_limit)) {
 269                 bool cleaned = false;
 270                 for ( ; !cleaned; count++) {
 271                         struct sk_buff *skb;
 272                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 273                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 274                         cleaned = (i == eop);
 275                         skb = tx_buffer_info->skb;
 276
 277                         if (cleaned && skb) {
 278                                 unsigned int segs, bytecount;
 279
 280                                 /* gso_segs is currently only valid for tcp */
 281                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 282                                 /* multiply data chunks by size of headers */
 283                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 284                                             skb->len;
 285                                 total_packets += segs;
 286                                 total_bytes += bytecount;
 287                         }
 288
 289                         ixgbe_unmap_and_free_tx_resource(adapter,
 290                                                          tx_buffer_info);
 291
 292                         tx_desc->wb.status = 0;
 293
 294                         i++;
 295                         if (i == tx_ring->count)
 296                                 i = 0;
 297                 }
 298
 299                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 300                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 301         }
 302
 303         tx_ring->next_to_clean = i;
 304
 305 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 306         if (unlikely(count && netif_carrier_ok(netdev) &&
 307                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 308                 /* Make sure that anybody stopping the queue after this
 309                  * sees the new next_to_clean.
 310                  */
 311                 smp_mb();
 312                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 313                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 314                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 315                         ++adapter->restart_queue;
 316                 }
 317         }
 318
 319         if (adapter->detect_tx_hung) {
 320                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 321                         /* schedule immediate reset if we believe we hung */
 322                         DPRINTK(PROBE, INFO,
 323                                 "tx hang %d detected, resetting adapter\n",
 324                                 adapter->tx_timeout_count + 1);
 325                         ixgbe_tx_timeout(adapter->netdev);
 326                 }
 327         }
 328
 329         /* re-arm the interrupt */
 330         if (count >= tx_ring->work_limit) {
 331                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 332                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
 333                                         tx_ring->v_idx);
 334                 else if (tx_ring->v_idx & 0xFFFFFFFF)
 335                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
 336                                         tx_ring->v_idx);
 337                 else
 338                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
 339                                         (tx_ring->v_idx >> 32));
 340         }
 341
 342
 343         tx_ring->total_bytes += total_bytes;
 344         tx_ring->total_packets += total_packets;
 345         tx_ring->stats.packets += total_packets;
 346         tx_ring->stats.bytes += total_bytes;
 347         adapter->net_stats.tx_bytes += total_bytes;
 348         adapter->net_stats.tx_packets += total_packets;
 349         return (count < tx_ring->work_limit);
 350 }
 351
 352 #ifdef CONFIG_IXGBE_DCA
 353 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 354                                 struct ixgbe_ring *rx_ring)
 355 {
 356         u32 rxctrl;
 357         int cpu = get_cpu();
 358         int q = rx_ring - adapter->rx_ring;
 359
 360         if (rx_ring->cpu != cpu) {
 361                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 362                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 363                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 364                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 365                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 366                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 367                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 368                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 369                 }
 370                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 371                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 372                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 373                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 374                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 375                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 376                 rx_ring->cpu = cpu;
 377         }
 378         put_cpu();
 379 }
 380
 381 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 382                                 struct ixgbe_ring *tx_ring)
 383 {
 384         u32 txctrl;
 385         int cpu = get_cpu();
 386         int q = tx_ring - adapter->tx_ring;
 387
 388         if (tx_ring->cpu != cpu) {
 389                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 390                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 391                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 392                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 393                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 394                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 395                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 396                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 397                 }
 398                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 399                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 400                 tx_ring->cpu = cpu;
 401         }
 402         put_cpu();
 403 }
 404
 405 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 406 {
 407         int i;
 408
 409         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 410                 return;
 411
 412         for (i = 0; i < adapter->num_tx_queues; i++) {
 413                 adapter->tx_ring[i].cpu = -1;
 414                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 415         }
 416         for (i = 0; i < adapter->num_rx_queues; i++) {
 417                 adapter->rx_ring[i].cpu = -1;
 418                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 419         }
 420 }
 421
 422 static int __ixgbe_notify_dca(struct device *dev, void *data)
 423 {
 424         struct net_device *netdev = dev_get_drvdata(dev);
 425         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 426         unsigned long event = *(unsigned long *)data;
 427
 428         switch (event) {
 429         case DCA_PROVIDER_ADD:
 430                 /* if we're already enabled, don't do it again */
 431                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 432                         break;
 433                 /* Always use CB2 mode, difference is masked
 434                  * in the CB driver. */
 435                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 436                 if (dca_add_requester(dev) == 0) {
 437                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 438                         ixgbe_setup_dca(adapter);
 439                         break;
 440                 }
 441                 /* Fall Through since DCA is disabled. */
 442         case DCA_PROVIDER_REMOVE:
 443                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 444                         dca_remove_requester(dev);
 445                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 446                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 447                 }
 448                 break;
 449         }
 450
 451         return 0;
 452 }
 453
 454 #endif /* CONFIG_IXGBE_DCA */
 455 /**
 456  * ixgbe_receive_skb - Send a completed packet up the stack
 457  * @adapter: board private structure
 458  * @skb: packet to send up
 459  * @status: hardware indication of status of receive
 460  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 461  * @rx_desc: rx descriptor
 462  **/
 463 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 464                               struct sk_buff *skb, u8 status,
 465                               struct ixgbe_ring *ring,
 466                               union ixgbe_adv_rx_desc *rx_desc)
 467 {
 468         struct ixgbe_adapter *adapter = q_vector->adapter;
 469         struct napi_struct *napi = &q_vector->napi;
 470         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 471         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 472
 473         skb_record_rx_queue(skb, ring->queue_index);
 474         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 475                 if (adapter->vlgrp && is_vlan && (tag != 0))
 476                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 477                 else
 478                         napi_gro_receive(napi, skb);
 479         } else {
 480                 if (adapter->vlgrp && is_vlan && (tag != 0))
 481                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 482                 else
 483                         netif_rx(skb);
 484         }
 485 }
 486
 487 /**
 488  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 489  * @adapter: address of board private structure
 490  * @status_err: hardware indication of status of receive
 491  * @skb: skb currently being received and modified
 492  **/
 493 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 494                                      u32 status_err, struct sk_buff *skb)
 495 {
 496         skb->ip_summed = CHECKSUM_NONE;
 497
 498         /* Rx csum disabled */
 499         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 500                 return;
 501
 502         /* if IP and error */
 503         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 504             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 505                 adapter->hw_csum_rx_error++;
 506                 return;
 507         }
 508
 509         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 510                 return;
 511
 512         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 513                 adapter->hw_csum_rx_error++;
 514                 return;
 515         }
 516
 517         /* It must be a TCP or UDP packet with a valid checksum */
 518         skb->ip_summed = CHECKSUM_UNNECESSARY;
 519         adapter->hw_csum_rx_good++;
 520 }
 521
 522 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 523                                          struct ixgbe_ring *rx_ring, u32 val)
 524 {
 525         /*
 526          * Force memory writes to complete before letting h/w
 527          * know there are new descriptors to fetch.  (Only
 528          * applicable for weak-ordered memory model archs,
 529          * such as IA-64).
 530          */
 531         wmb();
 532         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 533 }
 534
 535 /**
 536  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 537  * @adapter: address of board private structure
 538  **/
 539 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 540                                    struct ixgbe_ring *rx_ring,
 541                                    int cleaned_count)
 542 {
 543         struct pci_dev *pdev = adapter->pdev;
 544         union ixgbe_adv_rx_desc *rx_desc;
 545         struct ixgbe_rx_buffer *bi;
 546         unsigned int i;
 547         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 548
 549         i = rx_ring->next_to_use;
 550         bi = &rx_ring->rx_buffer_info[i];
 551
 552         while (cleaned_count--) {
 553                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 554
 555                 if (!bi->page_dma &&
 556                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 557                         if (!bi->page) {
 558                                 bi->page = alloc_page(GFP_ATOMIC);
 559                                 if (!bi->page) {
 560                                         adapter->alloc_rx_page_failed++;
 561                                         goto no_buffers;
 562                                 }
 563                                 bi->page_offset = 0;
 564                         } else {
 565                                 /* use a half page if we're re-using */
 566                                 bi->page_offset ^= (PAGE_SIZE / 2);
 567                         }
 568
 569                         bi->page_dma = pci_map_page(pdev, bi->page,
 570                                                     bi->page_offset,
 571                                                     (PAGE_SIZE / 2),
 572                                                     PCI_DMA_FROMDEVICE);
 573                 }
 574
 575                 if (!bi->skb) {
 576                         struct sk_buff *skb;
 577                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 578
 579                         if (!skb) {
 580                                 adapter->alloc_rx_buff_failed++;
 581                                 goto no_buffers;
 582                         }
 583
 584                         /*
 585                          * Make buffer alignment 2 beyond a 16 byte boundary
 586                          * this will result in a 16 byte aligned IP header after
 587                          * the 14 byte MAC header is removed
 588                          */
 589                         skb_reserve(skb, NET_IP_ALIGN);
 590
 591                         bi->skb = skb;
 592                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 593                                                  PCI_DMA_FROMDEVICE);
 594                 }
 595                 /* Refresh the desc even if buffer_addrs didn't change because
 596                  * each write-back erases this info. */
 597                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 598                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 599                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 600                 } else {
 601                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 602                 }
 603
 604                 i++;
 605                 if (i == rx_ring->count)
 606                         i = 0;
 607                 bi = &rx_ring->rx_buffer_info[i];
 608         }
 609
 610 no_buffers:
 611         if (rx_ring->next_to_use != i) {
 612                 rx_ring->next_to_use = i;
 613                 if (i-- == 0)
 614                         i = (rx_ring->count - 1);
 615
 616                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 617         }
 618 }
 619
 620 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 621 {
 622         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 623 }
 624
 625 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 626 {
 627         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 628 }
 629
 630 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 631 {
 632         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 633                 IXGBE_RXDADV_RSCCNT_MASK) >>
 634                 IXGBE_RXDADV_RSCCNT_SHIFT;
 635 }
 636
 637 /**
 638  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 639  * @skb: pointer to the last skb in the rsc queue
 640  *
 641  * This function changes a queue full of hw rsc buffers into a completed
 642  * packet.  It uses the ->prev pointers to find the first packet and then
 643  * turns it into the frag list owner.
 644  **/
 645 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 646 {
 647         unsigned int frag_list_size = 0;
 648
 649         while (skb->prev) {
 650                 struct sk_buff *prev = skb->prev;
 651                 frag_list_size += skb->len;
 652                 skb->prev = NULL;
 653                 skb = prev;
 654         }
 655
 656         skb_shinfo(skb)->frag_list = skb->next;
 657         skb->next = NULL;
 658         skb->len += frag_list_size;
 659         skb->data_len += frag_list_size;
 660         skb->truesize += frag_list_size;
 661         return skb;
 662 }
 663
 664 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 665                                struct ixgbe_ring *rx_ring,
 666                                int *work_done, int work_to_do)
 667 {
 668         struct ixgbe_adapter *adapter = q_vector->adapter;
 669         struct pci_dev *pdev = adapter->pdev;
 670         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 671         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 672         struct sk_buff *skb;
 673         unsigned int i, rsc_count = 0;
 674         u32 len, staterr;
 675         u16 hdr_info;
 676         bool cleaned = false;
 677         int cleaned_count = 0;
 678         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 679
 680         i = rx_ring->next_to_clean;
 681         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 682         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 683         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 684
 685         while (staterr & IXGBE_RXD_STAT_DD) {
 686                 u32 upper_len = 0;
 687                 if (*work_done >= work_to_do)
 688                         break;
 689                 (*work_done)++;
 690
 691                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 692                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 693                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 694                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 695                         if (hdr_info & IXGBE_RXDADV_SPH)
 696                                 adapter->rx_hdr_split++;
 697                         if (len > IXGBE_RX_HDR_SIZE)
 698                                 len = IXGBE_RX_HDR_SIZE;
 699                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 700                 } else {
 701                         len = le16_to_cpu(rx_desc->wb.upper.length);
 702                 }
 703
 704                 cleaned = true;
 705                 skb = rx_buffer_info->skb;
 706                 prefetch(skb->data - NET_IP_ALIGN);
 707                 rx_buffer_info->skb = NULL;
 708
 709                 if (len && !skb_shinfo(skb)->nr_frags) {
 710                         pci_unmap_single(pdev, rx_buffer_info->dma,
 711                                          rx_ring->rx_buf_len,
 712                                          PCI_DMA_FROMDEVICE);
 713                         skb_put(skb, len);
 714                 }
 715
 716                 if (upper_len) {
 717                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 718                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 719                         rx_buffer_info->page_dma = 0;
 720                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 721                                            rx_buffer_info->page,
 722                                            rx_buffer_info->page_offset,
 723                                            upper_len);
 724
 725                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 726                             (page_count(rx_buffer_info->page) != 1))
 727                                 rx_buffer_info->page = NULL;
 728                         else
 729                                 get_page(rx_buffer_info->page);
 730
 731                         skb->len += upper_len;
 732                         skb->data_len += upper_len;
 733                         skb->truesize += upper_len;
 734                 }
 735
 736                 i++;
 737                 if (i == rx_ring->count)
 738                         i = 0;
 739
 740                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 741                 prefetch(next_rxd);
 742                 cleaned_count++;
 743
 744                 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
 745                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 746
 747                 if (rsc_count) {
 748                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 749                                      IXGBE_RXDADV_NEXTP_SHIFT;
 750                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 751                         rx_ring->rsc_count += (rsc_count - 1);
 752                 } else {
 753                         next_buffer = &rx_ring->rx_buffer_info[i];
 754                 }
 755
 756                 if (staterr & IXGBE_RXD_STAT_EOP) {
 757                         if (skb->prev)
 758                                 skb = ixgbe_transform_rsc_queue(skb);
 759                         rx_ring->stats.packets++;
 760                         rx_ring->stats.bytes += skb->len;
 761                 } else {
 762                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 763                                 rx_buffer_info->skb = next_buffer->skb;
 764                                 rx_buffer_info->dma = next_buffer->dma;
 765                                 next_buffer->skb = skb;
 766                                 next_buffer->dma = 0;
 767                         } else {
 768                                 skb->next = next_buffer->skb;
 769                                 skb->next->prev = skb;
 770                         }
 771                         adapter->non_eop_descs++;
 772                         goto next_desc;
 773                 }
 774
 775                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 776                         dev_kfree_skb_irq(skb);
 777                         goto next_desc;
 778                 }
 779
 780                 ixgbe_rx_checksum(adapter, staterr, skb);
 781
 782                 /* probably a little skewed due to removing CRC */
 783                 total_rx_bytes += skb->len;
 784                 total_rx_packets++;
 785
 786                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 787 #ifdef IXGBE_FCOE
 788                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 789                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 790                         if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
 791                                 goto next_desc;
 792 #endif /* IXGBE_FCOE */
 793                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 794
 795 next_desc:
 796                 rx_desc->wb.upper.status_error = 0;
 797
 798                 /* return some buffers to hardware, one at a time is too slow */
 799                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 800                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 801                         cleaned_count = 0;
 802                 }
 803
 804                 /* use prefetched values */
 805                 rx_desc = next_rxd;
 806                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 807
 808                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 809         }
 810
 811         rx_ring->next_to_clean = i;
 812         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 813
 814         if (cleaned_count)
 815                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 816
 817         rx_ring->total_packets += total_rx_packets;
 818         rx_ring->total_bytes += total_rx_bytes;
 819         adapter->net_stats.rx_bytes += total_rx_bytes;
 820         adapter->net_stats.rx_packets += total_rx_packets;
 821
 822         return cleaned;
 823 }
 824
 825 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 826 /**
 827  * ixgbe_configure_msix - Configure MSI-X hardware
 828  * @adapter: board private structure
 829  *
 830  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 831  * interrupts.
 832  **/
 833 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 834 {
 835         struct ixgbe_q_vector *q_vector;
 836         int i, j, q_vectors, v_idx, r_idx;
 837         u32 mask;
 838
 839         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 840
 841         /*
 842          * Populate the IVAR table and set the ITR values to the
 843          * corresponding register.
 844          */
 845         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 846                 q_vector = adapter->q_vector[v_idx];
 847                 /* XXX for_each_bit(...) */
 848                 r_idx = find_first_bit(q_vector->rxr_idx,
 849                                        adapter->num_rx_queues);
 850
 851                 for (i = 0; i < q_vector->rxr_count; i++) {
 852                         j = adapter->rx_ring[r_idx].reg_idx;
 853                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 854                         r_idx = find_next_bit(q_vector->rxr_idx,
 855                                               adapter->num_rx_queues,
 856                                               r_idx + 1);
 857                 }
 858                 r_idx = find_first_bit(q_vector->txr_idx,
 859                                        adapter->num_tx_queues);
 860
 861                 for (i = 0; i < q_vector->txr_count; i++) {
 862                         j = adapter->tx_ring[r_idx].reg_idx;
 863                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 864                         r_idx = find_next_bit(q_vector->txr_idx,
 865                                               adapter->num_tx_queues,
 866                                               r_idx + 1);
 867                 }
 868
 869                 /* if this is a tx only vector halve the interrupt rate */
 870                 if (q_vector->txr_count && !q_vector->rxr_count)
 871                         q_vector->eitr = (adapter->eitr_param >> 1);
 872                 else if (q_vector->rxr_count)
 873                         /* rx only */
 874                         q_vector->eitr = adapter->eitr_param;
 875
 876                 /*
 877                  * since this is initial set up don't need to call
 878                  * ixgbe_write_eitr helper
 879                  */
 880                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 881                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 882         }
 883
 884         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 885                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 886                                v_idx);
 887         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 888                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 889         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 890
 891         /* set up to autoclear timer, and the vectors */
 892         mask = IXGBE_EIMS_ENABLE_MASK;
 893         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 894         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 895 }
 896
 897 enum latency_range {
 898         lowest_latency = 0,
 899         low_latency = 1,
 900         bulk_latency = 2,
 901         latency_invalid = 255
 902 };
 903
 904 /**
 905  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 906  * @adapter: pointer to adapter
 907  * @eitr: eitr setting (ints per sec) to give last timeslice
 908  * @itr_setting: current throttle rate in ints/second
 909  * @packets: the number of packets during this measurement interval
 910  * @bytes: the number of bytes during this measurement interval
 911  *
 912  *      Stores a new ITR value based on packets and byte
 913  *      counts during the last interrupt.  The advantage of per interrupt
 914  *      computation is faster updates and more accurate ITR for the current
 915  *      traffic pattern.  Constants in this function were computed
 916  *      based on theoretical maximum wire speed and thresholds were set based
 917  *      on testing data as well as attempting to minimize response time
 918  *      while increasing bulk throughput.
 919  *      this functionality is controlled by the InterruptThrottleRate module
 920  *      parameter (see ixgbe_param.c)
 921  **/
 922 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 923                            u32 eitr, u8 itr_setting,
 924                            int packets, int bytes)
 925 {
 926         unsigned int retval = itr_setting;
 927         u32 timepassed_us;
 928         u64 bytes_perint;
 929
 930         if (packets == 0)
 931                 goto update_itr_done;
 932
 933
 934         /* simple throttlerate management
 935          *    0-20MB/s lowest (100000 ints/s)
 936          *   20-100MB/s low   (20000 ints/s)
 937          *  100-1249MB/s bulk (8000 ints/s)
 938          */
 939         /* what was last interrupt timeslice? */
 940         timepassed_us = 1000000/eitr;
 941         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 942
 943         switch (itr_setting) {
 944         case lowest_latency:
 945                 if (bytes_perint > adapter->eitr_low)
 946                         retval = low_latency;
 947                 break;
 948         case low_latency:
 949                 if (bytes_perint > adapter->eitr_high)
 950                         retval = bulk_latency;
 951                 else if (bytes_perint <= adapter->eitr_low)
 952                         retval = lowest_latency;
 953                 break;
 954         case bulk_latency:
 955                 if (bytes_perint <= adapter->eitr_high)
 956                         retval = low_latency;
 957                 break;
 958         }
 959
 960 update_itr_done:
 961         return retval;
 962 }
 963
 964 /**
 965  * ixgbe_write_eitr - write EITR register in hardware specific way
 966  * @adapter: pointer to adapter struct
 967  * @v_idx: vector index into q_vector array
 968  * @itr_reg: new value to be written in *register* format, not ints/s
 969  *
 970  * This function is made to be called by ethtool and by the driver
 971  * when it needs to update EITR registers at runtime.  Hardware
 972  * specific quirks/differences are taken care of here.
 973  */
 974 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
 975 {
 976         struct ixgbe_hw *hw = &adapter->hw;
 977         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 978                 /* must write high and low 16 bits to reset counter */
 979                 itr_reg |= (itr_reg << 16);
 980         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 981                 /*
 982                  * set the WDIS bit to not clear the timer bits and cause an
 983                  * immediate assertion of the interrupt
 984                  */
 985                 itr_reg |= IXGBE_EITR_CNT_WDIS;
 986         }
 987         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 988 }
 989
 990 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 991 {
 992         struct ixgbe_adapter *adapter = q_vector->adapter;
 993         u32 new_itr;
 994         u8 current_itr, ret_itr;
 995         int i, r_idx, v_idx = q_vector->v_idx;
 996         struct ixgbe_ring *rx_ring, *tx_ring;
 997
 998         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 999         for (i = 0; i < q_vector->txr_count; i++) {
1000                 tx_ring = &(adapter->tx_ring[r_idx]);
1001                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1002                                            q_vector->tx_itr,
1003                                            tx_ring->total_packets,
1004                                            tx_ring->total_bytes);
1005                 /* if the result for this queue would decrease interrupt
1006                  * rate for this vector then use that result */
1007                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1008                                     q_vector->tx_itr - 1 : ret_itr);
1009                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1010                                       r_idx + 1);
1011         }
1012
1013         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1014         for (i = 0; i < q_vector->rxr_count; i++) {
1015                 rx_ring = &(adapter->rx_ring[r_idx]);
1016                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1017                                            q_vector->rx_itr,
1018                                            rx_ring->total_packets,
1019                                            rx_ring->total_bytes);
1020                 /* if the result for this queue would decrease interrupt
1021                  * rate for this vector then use that result */
1022                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1023                                     q_vector->rx_itr - 1 : ret_itr);
1024                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1025                                       r_idx + 1);
1026         }
1027
1028         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1029
1030         switch (current_itr) {
1031         /* counts and packets in update_itr are dependent on these numbers */
1032         case lowest_latency:
1033                 new_itr = 100000;
1034                 break;
1035         case low_latency:
1036                 new_itr = 20000; /* aka hwitr = ~200 */
1037                 break;
1038         case bulk_latency:
1039         default:
1040                 new_itr = 8000;
1041                 break;
1042         }
1043
1044         if (new_itr != q_vector->eitr) {
1045                 u32 itr_reg;
1046
1047                 /* save the algorithm value here, not the smoothed one */
1048                 q_vector->eitr = new_itr;
1049                 /* do an exponential smoothing */
1050                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1051                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1052                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1053         }
1054
1055         return;
1056 }
1057
1058 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1059 {
1060         struct ixgbe_hw *hw = &adapter->hw;
1061
1062         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1063             (eicr & IXGBE_EICR_GPI_SDP1)) {
1064                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1065                 /* write to clear the interrupt */
1066                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1067         }
1068 }
1069
1070 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1071 {
1072         struct ixgbe_hw *hw = &adapter->hw;
1073
1074         if (eicr & IXGBE_EICR_GPI_SDP1) {
1075                 /* Clear the interrupt */
1076                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1077                 schedule_work(&adapter->multispeed_fiber_task);
1078         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1079                 /* Clear the interrupt */
1080                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1081                 schedule_work(&adapter->sfp_config_module_task);
1082         } else {
1083                 /* Interrupt isn't for us... */
1084                 return;
1085         }
1086 }
1087
1088 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1089 {
1090         struct ixgbe_hw *hw = &adapter->hw;
1091
1092         adapter->lsc_int++;
1093         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1094         adapter->link_check_timeout = jiffies;
1095         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1096                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1097                 schedule_work(&adapter->watchdog_task);
1098         }
1099 }
1100
1101 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1102 {
1103         struct net_device *netdev = data;
1104         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1105         struct ixgbe_hw *hw = &adapter->hw;
1106         u32 eicr;
1107
1108         /*
1109          * Workaround for Silicon errata.  Use clear-by-write instead
1110          * of clear-by-read.  Reading with EICS will return the
1111          * interrupt causes without clearing, which later be done
1112          * with the write to EICR.
1113          */
1114         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1115         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1116
1117         if (eicr & IXGBE_EICR_LSC)
1118                 ixgbe_check_lsc(adapter);
1119
1120         if (hw->mac.type == ixgbe_mac_82598EB)
1121                 ixgbe_check_fan_failure(adapter, eicr);
1122
1123         if (hw->mac.type == ixgbe_mac_82599EB)
1124                 ixgbe_check_sfp_event(adapter, eicr);
1125         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1126                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1127
1128         return IRQ_HANDLED;
1129 }
1130
1131 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1132 {
1133         struct ixgbe_q_vector *q_vector = data;
1134         struct ixgbe_adapter  *adapter = q_vector->adapter;
1135         struct ixgbe_ring     *tx_ring;
1136         int i, r_idx;
1137
1138         if (!q_vector->txr_count)
1139                 return IRQ_HANDLED;
1140
1141         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1142         for (i = 0; i < q_vector->txr_count; i++) {
1143                 tx_ring = &(adapter->tx_ring[r_idx]);
1144 #ifdef CONFIG_IXGBE_DCA
1145                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1146                         ixgbe_update_tx_dca(adapter, tx_ring);
1147 #endif
1148                 tx_ring->total_bytes = 0;
1149                 tx_ring->total_packets = 0;
1150                 ixgbe_clean_tx_irq(adapter, tx_ring);
1151                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1152                                       r_idx + 1);
1153         }
1154
1155         return IRQ_HANDLED;
1156 }
1157
1158 /**
1159  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1160  * @irq: unused
1161  * @data: pointer to our q_vector struct for this interrupt vector
1162  **/
1163 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1164 {
1165         struct ixgbe_q_vector *q_vector = data;
1166         struct ixgbe_adapter  *adapter = q_vector->adapter;
1167         struct ixgbe_ring  *rx_ring;
1168         int r_idx;
1169         int i;
1170
1171         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1172         for (i = 0;  i < q_vector->rxr_count; i++) {
1173                 rx_ring = &(adapter->rx_ring[r_idx]);
1174                 rx_ring->total_bytes = 0;
1175                 rx_ring->total_packets = 0;
1176                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1177                                       r_idx + 1);
1178         }
1179
1180         if (!q_vector->rxr_count)
1181                 return IRQ_HANDLED;
1182
1183         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1184         rx_ring = &(adapter->rx_ring[r_idx]);
1185         /* disable interrupts on this vector only */
1186         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1187                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1188         else if (rx_ring->v_idx & 0xFFFFFFFF)
1189                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1190         else
1191                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1192                                 (rx_ring->v_idx >> 32));
1193         napi_schedule(&q_vector->napi);
1194
1195         return IRQ_HANDLED;
1196 }
1197
1198 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1199 {
1200         ixgbe_msix_clean_rx(irq, data);
1201         ixgbe_msix_clean_tx(irq, data);
1202
1203         return IRQ_HANDLED;
1204 }
1205
1206 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1207                                            u64 qmask)
1208 {
1209         u32 mask;
1210
1211         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1212                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1214         } else {
1215                 mask = (qmask & 0xFFFFFFFF);
1216                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1217                 mask = (qmask >> 32);
1218                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1219         }
1220         /* skip the flush */
1221 }
1222
1223 /**
1224  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1225  * @napi: napi struct with our devices info in it
1226  * @budget: amount of work driver is allowed to do this pass, in packets
1227  *
1228  * This function is optimized for cleaning one queue only on a single
1229  * q_vector!!!
1230  **/
1231 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1232 {
1233         struct ixgbe_q_vector *q_vector =
1234                                container_of(napi, struct ixgbe_q_vector, napi);
1235         struct ixgbe_adapter *adapter = q_vector->adapter;
1236         struct ixgbe_ring *rx_ring = NULL;
1237         int work_done = 0;
1238         long r_idx;
1239
1240         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1241         rx_ring = &(adapter->rx_ring[r_idx]);
1242 #ifdef CONFIG_IXGBE_DCA
1243         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1244                 ixgbe_update_rx_dca(adapter, rx_ring);
1245 #endif
1246
1247         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1248
1249         /* If all Rx work done, exit the polling mode */
1250         if (work_done < budget) {
1251                 napi_complete(napi);
1252                 if (adapter->itr_setting & 1)
1253                         ixgbe_set_itr_msix(q_vector);
1254                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1255                         ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1256         }
1257
1258         return work_done;
1259 }
1260
1261 /**
1262  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1263  * @napi: napi struct with our devices info in it
1264  * @budget: amount of work driver is allowed to do this pass, in packets
1265  *
1266  * This function will clean more than one rx queue associated with a
1267  * q_vector.
1268  **/
1269 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1270 {
1271         struct ixgbe_q_vector *q_vector =
1272                                container_of(napi, struct ixgbe_q_vector, napi);
1273         struct ixgbe_adapter *adapter = q_vector->adapter;
1274         struct ixgbe_ring *rx_ring = NULL;
1275         int work_done = 0, i;
1276         long r_idx;
1277         u64 enable_mask = 0;
1278
1279         /* attempt to distribute budget to each queue fairly, but don't allow
1280          * the budget to go below 1 because we'll exit polling */
1281         budget /= (q_vector->rxr_count ?: 1);
1282         budget = max(budget, 1);
1283         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1284         for (i = 0; i < q_vector->rxr_count; i++) {
1285                 rx_ring = &(adapter->rx_ring[r_idx]);
1286 #ifdef CONFIG_IXGBE_DCA
1287                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288                         ixgbe_update_rx_dca(adapter, rx_ring);
1289 #endif
1290                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1291                 enable_mask |= rx_ring->v_idx;
1292                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1293                                       r_idx + 1);
1294         }
1295
1296         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1297         rx_ring = &(adapter->rx_ring[r_idx]);
1298         /* If all Rx work done, exit the polling mode */
1299         if (work_done < budget) {
1300                 napi_complete(napi);
1301                 if (adapter->itr_setting & 1)
1302                         ixgbe_set_itr_msix(q_vector);
1303                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1304                         ixgbe_irq_enable_queues(adapter, enable_mask);
1305                 return 0;
1306         }
1307
1308         return work_done;
1309 }
1310 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1311                                      int r_idx)
1312 {
1313         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1314
1315         set_bit(r_idx, q_vector->rxr_idx);
1316         q_vector->rxr_count++;
1317         a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
1318 }
1319
1320 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1321                                      int t_idx)
1322 {
1323         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1324
1325         set_bit(t_idx, q_vector->txr_idx);
1326         q_vector->txr_count++;
1327         a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
1328 }
1329
1330 /**
1331  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1332  * @adapter: board private structure to initialize
1333  * @vectors: allotted vector count for descriptor rings
1334  *
1335  * This function maps descriptor rings to the queue-specific vectors
1336  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1337  * one vector per ring/queue, but on a constrained vector budget, we
1338  * group the rings as "efficiently" as possible.  You would add new
1339  * mapping configurations in here.
1340  **/
1341 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1342                                       int vectors)
1343 {
1344         int v_start = 0;
1345         int rxr_idx = 0, txr_idx = 0;
1346         int rxr_remaining = adapter->num_rx_queues;
1347         int txr_remaining = adapter->num_tx_queues;
1348         int i, j;
1349         int rqpv, tqpv;
1350         int err = 0;
1351
1352         /* No mapping required if MSI-X is disabled. */
1353         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1354                 goto out;
1355
1356         /*
1357          * The ideal configuration...
1358          * We have enough vectors to map one per queue.
1359          */
1360         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1361                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1362                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1363
1364                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1365                         map_vector_to_txq(adapter, v_start, txr_idx);
1366
1367                 goto out;
1368         }
1369
1370         /*
1371          * If we don't have enough vectors for a 1-to-1
1372          * mapping, we'll have to group them so there are
1373          * multiple queues per vector.
1374          */
1375         /* Re-adjusting *qpv takes care of the remainder. */
1376         for (i = v_start; i < vectors; i++) {
1377                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1378                 for (j = 0; j < rqpv; j++) {
1379                         map_vector_to_rxq(adapter, i, rxr_idx);
1380                         rxr_idx++;
1381                         rxr_remaining--;
1382                 }
1383         }
1384         for (i = v_start; i < vectors; i++) {
1385                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1386                 for (j = 0; j < tqpv; j++) {
1387                         map_vector_to_txq(adapter, i, txr_idx);
1388                         txr_idx++;
1389                         txr_remaining--;
1390                 }
1391         }
1392
1393 out:
1394         return err;
1395 }
1396
1397 /**
1398  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1399  * @adapter: board private structure
1400  *
1401  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1402  * interrupts from the kernel.
1403  **/
1404 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1405 {
1406         struct net_device *netdev = adapter->netdev;
1407         irqreturn_t (*handler)(int, void *);
1408         int i, vector, q_vectors, err;
1409         int ri=0, ti=0;
1410
1411         /* Decrement for Other and TCP Timer vectors */
1412         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1413
1414         /* Map the Tx/Rx rings to the vectors we were allotted. */
1415         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1416         if (err)
1417                 goto out;
1418
1419 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1420                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1421                          &ixgbe_msix_clean_many)
1422         for (vector = 0; vector < q_vectors; vector++) {
1423                 handler = SET_HANDLER(adapter->q_vector[vector]);
1424
1425                 if(handler == &ixgbe_msix_clean_rx) {
1426                         sprintf(adapter->name[vector], "%s-%s-%d",
1427                                 netdev->name, "rx", ri++);
1428                 }
1429                 else if(handler == &ixgbe_msix_clean_tx) {
1430                         sprintf(adapter->name[vector], "%s-%s-%d",
1431                                 netdev->name, "tx", ti++);
1432                 }
1433                 else
1434                         sprintf(adapter->name[vector], "%s-%s-%d",
1435                                 netdev->name, "TxRx", vector);
1436
1437                 err = request_irq(adapter->msix_entries[vector].vector,
1438                                   handler, 0, adapter->name[vector],
1439                                   adapter->q_vector[vector]);
1440                 if (err) {
1441                         DPRINTK(PROBE, ERR,
1442                                 "request_irq failed for MSIX interrupt "
1443                                 "Error: %d\n", err);
1444                         goto free_queue_irqs;
1445                 }
1446         }
1447
1448         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1449         err = request_irq(adapter->msix_entries[vector].vector,
1450                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1451         if (err) {
1452                 DPRINTK(PROBE, ERR,
1453                         "request_irq for msix_lsc failed: %d\n", err);
1454                 goto free_queue_irqs;
1455         }
1456
1457         return 0;
1458
1459 free_queue_irqs:
1460         for (i = vector - 1; i >= 0; i--)
1461                 free_irq(adapter->msix_entries[--vector].vector,
1462                          adapter->q_vector[i]);
1463         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1464         pci_disable_msix(adapter->pdev);
1465         kfree(adapter->msix_entries);
1466         adapter->msix_entries = NULL;
1467 out:
1468         return err;
1469 }
1470
1471 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1472 {
1473         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1474         u8 current_itr;
1475         u32 new_itr = q_vector->eitr;
1476         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1477         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1478
1479         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1480                                             q_vector->tx_itr,
1481                                             tx_ring->total_packets,
1482                                             tx_ring->total_bytes);
1483         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1484                                             q_vector->rx_itr,
1485                                             rx_ring->total_packets,
1486                                             rx_ring->total_bytes);
1487
1488         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1489
1490         switch (current_itr) {
1491         /* counts and packets in update_itr are dependent on these numbers */
1492         case lowest_latency:
1493                 new_itr = 100000;
1494                 break;
1495         case low_latency:
1496                 new_itr = 20000; /* aka hwitr = ~200 */
1497                 break;
1498         case bulk_latency:
1499                 new_itr = 8000;
1500                 break;
1501         default:
1502                 break;
1503         }
1504
1505         if (new_itr != q_vector->eitr) {
1506                 u32 itr_reg;
1507
1508                 /* save the algorithm value here, not the smoothed one */
1509                 q_vector->eitr = new_itr;
1510                 /* do an exponential smoothing */
1511                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1512                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1513                 ixgbe_write_eitr(adapter, 0, itr_reg);
1514         }
1515
1516         return;
1517 }
1518
1519 /**
1520  * ixgbe_irq_enable - Enable default interrupt generation settings
1521  * @adapter: board private structure
1522  **/
1523 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1524 {
1525         u32 mask;
1526
1527         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1528         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1529                 mask |= IXGBE_EIMS_GPI_SDP1;
1530         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1531                 mask |= IXGBE_EIMS_ECC;
1532                 mask |= IXGBE_EIMS_GPI_SDP1;
1533                 mask |= IXGBE_EIMS_GPI_SDP2;
1534         }
1535
1536         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1537         ixgbe_irq_enable_queues(adapter, ~0);
1538         IXGBE_WRITE_FLUSH(&adapter->hw);
1539 }
1540
1541 /**
1542  * ixgbe_intr - legacy mode Interrupt Handler
1543  * @irq: interrupt number
1544  * @data: pointer to a network interface device structure
1545  **/
1546 static irqreturn_t ixgbe_intr(int irq, void *data)
1547 {
1548         struct net_device *netdev = data;
1549         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1550         struct ixgbe_hw *hw = &adapter->hw;
1551         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1552         u32 eicr;
1553
1554         /*
1555          * Workaround for silicon errata.  Mask the interrupts
1556          * before the read of EICR.
1557          */
1558         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1559
1560         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1561          * therefore no explict interrupt disable is necessary */
1562         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1563         if (!eicr) {
1564                 /* shared interrupt alert!
1565                  * make sure interrupts are enabled because the read will
1566                  * have disabled interrupts due to EIAM */
1567                 ixgbe_irq_enable(adapter);
1568                 return IRQ_NONE;        /* Not our interrupt */
1569         }
1570
1571         if (eicr & IXGBE_EICR_LSC)
1572                 ixgbe_check_lsc(adapter);
1573
1574         if (hw->mac.type == ixgbe_mac_82599EB)
1575                 ixgbe_check_sfp_event(adapter, eicr);
1576
1577         ixgbe_check_fan_failure(adapter, eicr);
1578
1579         if (napi_schedule_prep(&(q_vector->napi))) {
1580                 adapter->tx_ring[0].total_packets = 0;
1581                 adapter->tx_ring[0].total_bytes = 0;
1582                 adapter->rx_ring[0].total_packets = 0;
1583                 adapter->rx_ring[0].total_bytes = 0;
1584                 /* would disable interrupts here but EIAM disabled it */
1585                 __napi_schedule(&(q_vector->napi));
1586         }
1587
1588         return IRQ_HANDLED;
1589 }
1590
1591 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1592 {
1593         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1594
1595         for (i = 0; i < q_vectors; i++) {
1596                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1597                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1598                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1599                 q_vector->rxr_count = 0;
1600                 q_vector->txr_count = 0;
1601         }
1602 }
1603
1604 /**
1605  * ixgbe_request_irq - initialize interrupts
1606  * @adapter: board private structure
1607  *
1608  * Attempts to configure interrupts using the best available
1609  * capabilities of the hardware and kernel.
1610  **/
1611 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1612 {
1613         struct net_device *netdev = adapter->netdev;
1614         int err;
1615
1616         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1617                 err = ixgbe_request_msix_irqs(adapter);
1618         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1619                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1620                                   netdev->name, netdev);
1621         } else {
1622                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1623                                   netdev->name, netdev);
1624         }
1625
1626         if (err)
1627                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1628
1629         return err;
1630 }
1631
1632 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1633 {
1634         struct net_device *netdev = adapter->netdev;
1635
1636         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1637                 int i, q_vectors;
1638
1639                 q_vectors = adapter->num_msix_vectors;
1640
1641                 i = q_vectors - 1;
1642                 free_irq(adapter->msix_entries[i].vector, netdev);
1643
1644                 i--;
1645                 for (; i >= 0; i--) {
1646                         free_irq(adapter->msix_entries[i].vector,
1647                                  adapter->q_vector[i]);
1648                 }
1649
1650                 ixgbe_reset_q_vectors(adapter);
1651         } else {
1652                 free_irq(adapter->pdev->irq, netdev);
1653         }
1654 }
1655
1656 /**
1657  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1658  * @adapter: board private structure
1659  **/
1660 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1661 {
1662         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1663                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1664         } else {
1665                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1666                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1667                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1668         }
1669         IXGBE_WRITE_FLUSH(&adapter->hw);
1670         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1671                 int i;
1672                 for (i = 0; i < adapter->num_msix_vectors; i++)
1673                         synchronize_irq(adapter->msix_entries[i].vector);
1674         } else {
1675                 synchronize_irq(adapter->pdev->irq);
1676         }
1677 }
1678
1679 /**
1680  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1681  *
1682  **/
1683 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1684 {
1685         struct ixgbe_hw *hw = &adapter->hw;
1686
1687         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1688                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1689
1690         ixgbe_set_ivar(adapter, 0, 0, 0);
1691         ixgbe_set_ivar(adapter, 1, 0, 0);
1692
1693         map_vector_to_rxq(adapter, 0, 0);
1694         map_vector_to_txq(adapter, 0, 0);
1695
1696         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1697 }
1698
1699 /**
1700  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1701  * @adapter: board private structure
1702  *
1703  * Configure the Tx unit of the MAC after a reset.
1704  **/
1705 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1706 {
1707         u64 tdba;
1708         struct ixgbe_hw *hw = &adapter->hw;
1709         u32 i, j, tdlen, txctrl;
1710
1711         /* Setup the HW Tx Head and Tail descriptor pointers */
1712         for (i = 0; i < adapter->num_tx_queues; i++) {
1713                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1714                 j = ring->reg_idx;
1715                 tdba = ring->dma;
1716                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1717                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1718                                 (tdba & DMA_BIT_MASK(32)));
1719                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1720                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1721                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1722                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1723                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1724                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1725                 /* Disable Tx Head Writeback RO bit, since this hoses
1726                  * bookkeeping if things aren't delivered in order.
1727                  */
1728                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1729                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1730                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1731         }
1732         if (hw->mac.type == ixgbe_mac_82599EB) {
1733                 /* We enable 8 traffic classes, DCB only */
1734                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1735                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1736                                         IXGBE_MTQC_8TC_8TQ));
1737         }
1738 }
1739
1740 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1741
1742 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1743 {
1744         struct ixgbe_ring *rx_ring;
1745         u32 srrctl;
1746         int queue0 = 0;
1747         unsigned long mask;
1748
1749         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1750                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1751                         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1752                         if (dcb_i == 8)
1753                                 queue0 = index >> 4;
1754                         else if (dcb_i == 4)
1755                                 queue0 = index >> 5;
1756                         else
1757                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1758                                         "configuration\n");
1759 #ifdef IXGBE_FCOE
1760                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1761                                 struct ixgbe_ring_feature *f;
1762
1763                                 rx_ring = &adapter->rx_ring[queue0];
1764                                 f = &adapter->ring_feature[RING_F_FCOE];
1765                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1766                                         queue0 = f->mask + index -
1767                                                  rx_ring->reg_idx - 1;
1768                         }
1769 #endif /* IXGBE_FCOE */
1770                 } else {
1771                         queue0 = index;
1772                 }
1773         } else {
1774                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1775                 queue0 = index & mask;
1776                 index = index & mask;
1777         }
1778
1779         rx_ring = &adapter->rx_ring[queue0];
1780
1781         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1782
1783         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1784         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1785
1786         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1787                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1788
1789         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1790 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1791                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1792 #else
1793                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1794 #endif
1795                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1796         } else {
1797                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1798                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1799                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1800         }
1801
1802         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1803 }
1804
1805 /**
1806  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1807  * @adapter: board private structure
1808  *
1809  * Configure the Rx unit of the MAC after a reset.
1810  **/
1811 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1812 {
1813         u64 rdba;
1814         struct ixgbe_hw *hw = &adapter->hw;
1815         struct net_device *netdev = adapter->netdev;
1816         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1817         int i, j;
1818         u32 rdlen, rxctrl, rxcsum;
1819         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1820                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1821                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1822         u32 fctrl, hlreg0;
1823         u32 reta = 0, mrqc = 0;
1824         u32 rdrxctl;
1825         u32 rscctrl;
1826         int rx_buf_len;
1827
1828         /* Decide whether to use packet split mode or not */
1829         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1830
1831 #ifdef IXGBE_FCOE
1832         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1833                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1834 #endif /* IXGBE_FCOE */
1835
1836         /* Set the RX buffer length according to the mode */
1837         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1838                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1839                 if (hw->mac.type == ixgbe_mac_82599EB) {
1840                         /* PSRTYPE must be initialized in 82599 */
1841                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1842                                       IXGBE_PSRTYPE_UDPHDR |
1843                                       IXGBE_PSRTYPE_IPV4HDR |
1844                                       IXGBE_PSRTYPE_IPV6HDR |
1845                                       IXGBE_PSRTYPE_L2HDR;
1846                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1847                 }
1848         } else {
1849                 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1850                     (netdev->mtu <= ETH_DATA_LEN))
1851                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1852                 else
1853                         rx_buf_len = ALIGN(max_frame, 1024);
1854         }
1855
1856         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1857         fctrl |= IXGBE_FCTRL_BAM;
1858         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1859         fctrl |= IXGBE_FCTRL_PMCF;
1860         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1861
1862         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1863         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1864                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1865         else
1866                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1867         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1868
1869         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1870         /* disable receives while setting up the descriptors */
1871         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1872         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1873
1874         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1875          * the Base and Length of the Rx Descriptor Ring */
1876         for (i = 0; i < adapter->num_rx_queues; i++) {
1877                 rdba = adapter->rx_ring[i].dma;
1878                 j = adapter->rx_ring[i].reg_idx;
1879                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1880                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1881                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1882                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1883                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1884                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1885                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1886                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1887
1888                 ixgbe_configure_srrctl(adapter, j);
1889         }
1890
1891         if (hw->mac.type == ixgbe_mac_82598EB) {
1892                 /*
1893                  * For VMDq support of different descriptor types or
1894                  * buffer sizes through the use of multiple SRRCTL
1895                  * registers, RDRXCTL.MVMEN must be set to 1
1896                  *
1897                  * also, the manual doesn't mention it clearly but DCA hints
1898                  * will only use queue 0's tags unless this bit is set.  Side
1899                  * effects of setting this bit are only that SRRCTL must be
1900                  * fully programmed [0..15]
1901                  */
1902                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1903                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1904                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1905         }
1906
1907         /* Program MRQC for the distribution of queues */
1908         if (hw->mac.type == ixgbe_mac_82599EB) {
1909                 int mask = adapter->flags & (
1910                                 IXGBE_FLAG_RSS_ENABLED
1911                                 | IXGBE_FLAG_DCB_ENABLED
1912                                 );
1913
1914                 switch (mask) {
1915                 case (IXGBE_FLAG_RSS_ENABLED):
1916                         mrqc = IXGBE_MRQC_RSSEN;
1917                         break;
1918                 case (IXGBE_FLAG_DCB_ENABLED):
1919                         mrqc = IXGBE_MRQC_RT8TCEN;
1920                         break;
1921                 default:
1922                         break;
1923                 }
1924         }
1925         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1926                 /* Fill out redirection table */
1927                 for (i = 0, j = 0; i < 128; i++, j++) {
1928                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1929                                 j = 0;
1930                         /* reta = 4-byte sliding window of
1931                          * 0x00..(indices-1)(indices-1)00..etc. */
1932                         reta = (reta << 8) | (j * 0x11);
1933                         if ((i & 3) == 3)
1934                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1935                 }
1936
1937                 /* Fill out hash function seeds */
1938                 for (i = 0; i < 10; i++)
1939                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1940
1941                 if (hw->mac.type == ixgbe_mac_82598EB)
1942                         mrqc |= IXGBE_MRQC_RSSEN;
1943                     /* Perform hash on these packet types */
1944                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1945                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1946                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1947                       | IXGBE_MRQC_RSS_FIELD_IPV6
1948                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1949                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1950         }
1951         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1952
1953         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1954
1955         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1956             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1957                 /* Disable indicating checksum in descriptor, enables
1958                  * RSS hash */
1959                 rxcsum |= IXGBE_RXCSUM_PCSD;
1960         }
1961         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1962                 /* Enable IPv4 payload checksum for UDP fragments
1963                  * if PCSD is not set */
1964                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1965         }
1966
1967         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1968
1969         if (hw->mac.type == ixgbe_mac_82599EB) {
1970                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1971                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1972                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
1973                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1974         }
1975
1976         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1977                 /* Enable 82599 HW-RSC */
1978                 for (i = 0; i < adapter->num_rx_queues; i++) {
1979                         j = adapter->rx_ring[i].reg_idx;
1980                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1981                         rscctrl |= IXGBE_RSCCTL_RSCEN;
1982                         /*
1983                          *  if packet split is enabled we can only support up
1984                          *  to max frags + 1 descriptors.
1985                          */
1986                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1987 #if (MAX_SKB_FRAGS < 3)
1988                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1989 #elif (MAX_SKB_FRAGS < 7)
1990                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1991 #elif (MAX_SKB_FRAGS < 15)
1992                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1993 #else
1994                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1995 #endif
1996                         else
1997                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1998                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1999                 }
2000                 /* Disable RSC for ACK packets */
2001                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2002                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2003         }
2004 }
2005
2006 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2007 {
2008         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2009         struct ixgbe_hw *hw = &adapter->hw;
2010
2011         /* add VID to filter table */
2012         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2013 }
2014
2015 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2016 {
2017         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2018         struct ixgbe_hw *hw = &adapter->hw;
2019
2020         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2021                 ixgbe_irq_disable(adapter);
2022
2023         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2024
2025         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2026                 ixgbe_irq_enable(adapter);
2027
2028         /* remove VID from filter table */
2029         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2030 }
2031
2032 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2033                                    struct vlan_group *grp)
2034 {
2035         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2036         u32 ctrl;
2037         int i, j;
2038
2039         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2040                 ixgbe_irq_disable(adapter);
2041         adapter->vlgrp = grp;
2042
2043         /*
2044          * For a DCB driver, always enable VLAN tag stripping so we can
2045          * still receive traffic from a DCB-enabled host even if we're
2046          * not in DCB mode.
2047          */
2048         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2049         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2050                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2051                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2052                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2053         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2054                 ctrl |= IXGBE_VLNCTRL_VFE;
2055                 /* enable VLAN tag insert/strip */
2056                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2057                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2058                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2059                 for (i = 0; i < adapter->num_rx_queues; i++) {
2060                         j = adapter->rx_ring[i].reg_idx;
2061                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2062                         ctrl |= IXGBE_RXDCTL_VME;
2063                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2064                 }
2065         }
2066         ixgbe_vlan_rx_add_vid(netdev, 0);
2067
2068         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2069                 ixgbe_irq_enable(adapter);
2070 }
2071
2072 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2073 {
2074         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2075
2076         if (adapter->vlgrp) {
2077                 u16 vid;
2078                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2079                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2080                                 continue;
2081                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2082                 }
2083         }
2084 }
2085
2086 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2087 {
2088         struct dev_mc_list *mc_ptr;
2089         u8 *addr = *mc_addr_ptr;
2090         *vmdq = 0;
2091
2092         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2093         if (mc_ptr->next)
2094                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2095         else
2096                 *mc_addr_ptr = NULL;
2097
2098         return addr;
2099 }
2100
2101 /**
2102  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2103  * @netdev: network interface device structure
2104  *
2105  * The set_rx_method entry point is called whenever the unicast/multicast
2106  * address list or the network interface flags are updated.  This routine is
2107  * responsible for configuring the hardware for proper unicast, multicast and
2108  * promiscuous mode.
2109  **/
2110 static void ixgbe_set_rx_mode(struct net_device *netdev)
2111 {
2112         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2113         struct ixgbe_hw *hw = &adapter->hw;
2114         u32 fctrl, vlnctrl;
2115         u8 *addr_list = NULL;
2116         int addr_count = 0;
2117
2118         /* Check for Promiscuous and All Multicast modes */
2119
2120         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2121         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122
2123         if (netdev->flags & IFF_PROMISC) {
2124                 hw->addr_ctrl.user_set_promisc = 1;
2125                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2126                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2127         } else {
2128                 if (netdev->flags & IFF_ALLMULTI) {
2129                         fctrl |= IXGBE_FCTRL_MPE;
2130                         fctrl &= ~IXGBE_FCTRL_UPE;
2131                 } else {
2132                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2133                 }
2134                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2135                 hw->addr_ctrl.user_set_promisc = 0;
2136         }
2137
2138         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2139         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2140
2141         /* reprogram secondary unicast list */
2142         addr_count = netdev->uc_count;
2143         if (addr_count)
2144                 addr_list = netdev->uc_list->dmi_addr;
2145         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2146                                           ixgbe_addr_list_itr);
2147
2148         /* reprogram multicast list */
2149         addr_count = netdev->mc_count;
2150         if (addr_count)
2151                 addr_list = netdev->mc_list->dmi_addr;
2152         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2153                                         ixgbe_addr_list_itr);
2154 }
2155
2156 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2157 {
2158         int q_idx;
2159         struct ixgbe_q_vector *q_vector;
2160         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2161
2162         /* legacy and MSI only use one vector */
2163         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2164                 q_vectors = 1;
2165
2166         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2167                 struct napi_struct *napi;
2168                 q_vector = adapter->q_vector[q_idx];
2169                 if (!q_vector->rxr_count)
2170                         continue;
2171                 napi = &q_vector->napi;
2172                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2173                     (q_vector->rxr_count > 1))
2174                         napi->poll = &ixgbe_clean_rxonly_many;
2175
2176                 napi_enable(napi);
2177         }
2178 }
2179
2180 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2181 {
2182         int q_idx;
2183         struct ixgbe_q_vector *q_vector;
2184         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2185
2186         /* legacy and MSI only use one vector */
2187         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2188                 q_vectors = 1;
2189
2190         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2191                 q_vector = adapter->q_vector[q_idx];
2192                 if (!q_vector->rxr_count)
2193                         continue;
2194                 napi_disable(&q_vector->napi);
2195         }
2196 }
2197
2198 #ifdef CONFIG_IXGBE_DCB
2199 /*
2200  * ixgbe_configure_dcb - Configure DCB hardware
2201  * @adapter: ixgbe adapter struct
2202  *
2203  * This is called by the driver on open to configure the DCB hardware.
2204  * This is also called by the gennetlink interface when reconfiguring
2205  * the DCB state.
2206  */
2207 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2208 {
2209         struct ixgbe_hw *hw = &adapter->hw;
2210         u32 txdctl, vlnctrl;
2211         int i, j;
2212
2213         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2214         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2215         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2216
2217         /* reconfigure the hardware */
2218         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2219
2220         for (i = 0; i < adapter->num_tx_queues; i++) {
2221                 j = adapter->tx_ring[i].reg_idx;
2222                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2223                 /* PThresh workaround for Tx hang with DFP enabled. */
2224                 txdctl |= 32;
2225                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2226         }
2227         /* Enable VLAN tag insert/strip */
2228         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2229         if (hw->mac.type == ixgbe_mac_82598EB) {
2230                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2231                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2232                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2233         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2234                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2235                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2236                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2237                 for (i = 0; i < adapter->num_rx_queues; i++) {
2238                         j = adapter->rx_ring[i].reg_idx;
2239                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2240                         vlnctrl |= IXGBE_RXDCTL_VME;
2241                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2242                 }
2243         }
2244         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2245 }
2246
2247 #endif
2248 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2249 {
2250         struct net_device *netdev = adapter->netdev;
2251         int i;
2252
2253         ixgbe_set_rx_mode(netdev);
2254
2255         ixgbe_restore_vlan(adapter);
2256 #ifdef CONFIG_IXGBE_DCB
2257         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2258                 netif_set_gso_max_size(netdev, 32768);
2259                 ixgbe_configure_dcb(adapter);
2260         } else {
2261                 netif_set_gso_max_size(netdev, 65536);
2262         }
2263 #else
2264         netif_set_gso_max_size(netdev, 65536);
2265 #endif
2266
2267 #ifdef IXGBE_FCOE
2268         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2269                 ixgbe_configure_fcoe(adapter);
2270
2271 #endif /* IXGBE_FCOE */
2272         ixgbe_configure_tx(adapter);
2273         ixgbe_configure_rx(adapter);
2274         for (i = 0; i < adapter->num_rx_queues; i++)
2275                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2276                                        (adapter->rx_ring[i].count - 1));
2277 }
2278
2279 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2280 {
2281         switch (hw->phy.type) {
2282         case ixgbe_phy_sfp_avago:
2283         case ixgbe_phy_sfp_ftl:
2284         case ixgbe_phy_sfp_intel:
2285         case ixgbe_phy_sfp_unknown:
2286         case ixgbe_phy_tw_tyco:
2287         case ixgbe_phy_tw_unknown:
2288                 return true;
2289         default:
2290                 return false;
2291         }
2292 }
2293
2294 /**
2295  * ixgbe_sfp_link_config - set up SFP+ link
2296  * @adapter: pointer to private adapter struct
2297  **/
2298 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2299 {
2300         struct ixgbe_hw *hw = &adapter->hw;
2301
2302                 if (hw->phy.multispeed_fiber) {
2303                         /*
2304                          * In multispeed fiber setups, the device may not have
2305                          * had a physical connection when the driver loaded.
2306                          * If that's the case, the initial link configuration
2307                          * couldn't get the MAC into 10G or 1G mode, so we'll
2308                          * never have a link status change interrupt fire.
2309                          * We need to try and force an autonegotiation
2310                          * session, then bring up link.
2311                          */
2312                         hw->mac.ops.setup_sfp(hw);
2313                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2314                                 schedule_work(&adapter->multispeed_fiber_task);
2315                 } else {
2316                         /*
2317                          * Direct Attach Cu and non-multispeed fiber modules
2318                          * still need to be configured properly prior to
2319                          * attempting link.
2320                          */
2321                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2322                                 schedule_work(&adapter->sfp_config_module_task);
2323                 }
2324 }
2325
2326 /**
2327  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2328  * @hw: pointer to private hardware struct
2329  *
2330  * Returns 0 on success, negative on failure
2331  **/
2332 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2333 {
2334         u32 autoneg;
2335         bool link_up = false;
2336         u32 ret = IXGBE_ERR_LINK_SETUP;
2337
2338         if (hw->mac.ops.check_link)
2339                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2340
2341         if (ret)
2342                 goto link_cfg_out;
2343
2344         if (hw->mac.ops.get_link_capabilities)
2345                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2346                                                         &hw->mac.autoneg);
2347         if (ret)
2348                 goto link_cfg_out;
2349
2350         if (hw->mac.ops.setup_link_speed)
2351                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2352 link_cfg_out:
2353         return ret;
2354 }
2355
2356 #define IXGBE_MAX_RX_DESC_POLL 10
2357 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2358                                               int rxr)
2359 {
2360         int j = adapter->rx_ring[rxr].reg_idx;
2361         int k;
2362
2363         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2364                 if (IXGBE_READ_REG(&adapter->hw,
2365                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2366                         break;
2367                 else
2368                         msleep(1);
2369         }
2370         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2371                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2372                         "not set within the polling period\n", rxr);
2373         }
2374         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2375                               (adapter->rx_ring[rxr].count - 1));
2376 }
2377
2378 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2379 {
2380         struct net_device *netdev = adapter->netdev;
2381         struct ixgbe_hw *hw = &adapter->hw;
2382         int i, j = 0;
2383         int num_rx_rings = adapter->num_rx_queues;
2384         int err;
2385         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2386         u32 txdctl, rxdctl, mhadd;
2387         u32 dmatxctl;
2388         u32 gpie;
2389
2390         ixgbe_get_hw_control(adapter);
2391
2392         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2393             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2394                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2395                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2396                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2397                 } else {
2398                         /* MSI only */
2399                         gpie = 0;
2400                 }
2401                 /* XXX: to interrupt immediately for EICS writes, enable this */
2402                 /* gpie |= IXGBE_GPIE_EIMEN; */
2403                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2404         }
2405
2406         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2407                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2408                  * specifically only auto mask tx and rx interrupts */
2409                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2410         }
2411
2412         /* Enable fan failure interrupt if media type is copper */
2413         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2414                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2415                 gpie |= IXGBE_SDP1_GPIEN;
2416                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2417         }
2418
2419         if (hw->mac.type == ixgbe_mac_82599EB) {
2420                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2421                 gpie |= IXGBE_SDP1_GPIEN;
2422                 gpie |= IXGBE_SDP2_GPIEN;
2423                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2424         }
2425
2426         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2427         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2428                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2429                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2430
2431                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2432         }
2433
2434         for (i = 0; i < adapter->num_tx_queues; i++) {
2435                 j = adapter->tx_ring[i].reg_idx;
2436                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2437                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2438                 txdctl |= (8 << 16);
2439                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2440         }
2441
2442         if (hw->mac.type == ixgbe_mac_82599EB) {
2443                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2444                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2445                 dmatxctl |= IXGBE_DMATXCTL_TE;
2446                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2447         }
2448         for (i = 0; i < adapter->num_tx_queues; i++) {
2449                 j = adapter->tx_ring[i].reg_idx;
2450                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2451                 txdctl |= IXGBE_TXDCTL_ENABLE;
2452                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2453         }
2454
2455         for (i = 0; i < num_rx_rings; i++) {
2456                 j = adapter->rx_ring[i].reg_idx;
2457                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2458                 /* enable PTHRESH=32 descriptors (half the internal cache)
2459                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2460                  * this also removes a pesky rx_no_buffer_count increment */
2461                 rxdctl |= 0x0020;
2462                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2463                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2464                 if (hw->mac.type == ixgbe_mac_82599EB)
2465                         ixgbe_rx_desc_queue_enable(adapter, i);
2466         }
2467         /* enable all receives */
2468         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2469         if (hw->mac.type == ixgbe_mac_82598EB)
2470                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2471         else
2472                 rxdctl |= IXGBE_RXCTRL_RXEN;
2473         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2474
2475         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2476                 ixgbe_configure_msix(adapter);
2477         else
2478                 ixgbe_configure_msi_and_legacy(adapter);
2479
2480         clear_bit(__IXGBE_DOWN, &adapter->state);
2481         ixgbe_napi_enable_all(adapter);
2482
2483         /* clear any pending interrupts, may auto mask */
2484         IXGBE_READ_REG(hw, IXGBE_EICR);
2485
2486         ixgbe_irq_enable(adapter);
2487
2488         /*
2489          * If this adapter has a fan, check to see if we had a failure
2490          * before we enabled the interrupt.
2491          */
2492         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2493                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2494                 if (esdp & IXGBE_ESDP_SDP1)
2495                         DPRINTK(DRV, CRIT,
2496                                 "Fan has stopped, replace the adapter\n");
2497         }
2498
2499         /*
2500          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2501          * arrived before interrupts were enabled.  We need to kick off
2502          * the SFP+ module setup first, then try to bring up link.
2503          * If we're not hot-pluggable SFP+, we just need to configure link
2504          * and bring it up.
2505          */
2506         err = hw->phy.ops.identify(hw);
2507         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2508                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2509                 ixgbe_down(adapter);
2510                 return err;
2511         }
2512
2513         if (ixgbe_is_sfp(hw)) {
2514                 ixgbe_sfp_link_config(adapter);
2515         } else {
2516                 err = ixgbe_non_sfp_link_config(hw);
2517                 if (err)
2518                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2519         }
2520
2521         /* enable transmits */
2522         netif_tx_start_all_queues(netdev);
2523
2524         /* bring the link up in the watchdog, this could race with our first
2525          * link up interrupt but shouldn't be a problem */
2526         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2527         adapter->link_check_timeout = jiffies;
2528         mod_timer(&adapter->watchdog_timer, jiffies);
2529         return 0;
2530 }
2531
2532 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2533 {
2534         WARN_ON(in_interrupt());
2535         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2536                 msleep(1);
2537         ixgbe_down(adapter);
2538         ixgbe_up(adapter);
2539         clear_bit(__IXGBE_RESETTING, &adapter->state);
2540 }
2541
2542 int ixgbe_up(struct ixgbe_adapter *adapter)
2543 {
2544         /* hardware has been reset, we need to reload some things */
2545         ixgbe_configure(adapter);
2546
2547         return ixgbe_up_complete(adapter);
2548 }
2549
2550 void ixgbe_reset(struct ixgbe_adapter *adapter)
2551 {
2552         struct ixgbe_hw *hw = &adapter->hw;
2553         if (hw->mac.ops.init_hw(hw))
2554                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2555
2556         /* reprogram the RAR[0] in case user changed it. */
2557         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2558
2559 }
2560
2561 /**
2562  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2563  * @adapter: board private structure
2564  * @rx_ring: ring to free buffers from
2565  **/
2566 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2567                                 struct ixgbe_ring *rx_ring)
2568 {
2569         struct pci_dev *pdev = adapter->pdev;
2570         unsigned long size;
2571         unsigned int i;
2572
2573         /* Free all the Rx ring sk_buffs */
2574
2575         for (i = 0; i < rx_ring->count; i++) {
2576                 struct ixgbe_rx_buffer *rx_buffer_info;
2577
2578                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2579                 if (rx_buffer_info->dma) {
2580                         pci_unmap_single(pdev, rx_buffer_info->dma,
2581                                          rx_ring->rx_buf_len,
2582                                          PCI_DMA_FROMDEVICE);
2583                         rx_buffer_info->dma = 0;
2584                 }
2585                 if (rx_buffer_info->skb) {
2586                         struct sk_buff *skb = rx_buffer_info->skb;
2587                         rx_buffer_info->skb = NULL;
2588                         do {
2589                                 struct sk_buff *this = skb;
2590                                 skb = skb->prev;
2591                                 dev_kfree_skb(this);
2592                         } while (skb);
2593                 }
2594                 if (!rx_buffer_info->page)
2595                         continue;
2596                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2597                                PCI_DMA_FROMDEVICE);
2598                 rx_buffer_info->page_dma = 0;
2599                 put_page(rx_buffer_info->page);
2600                 rx_buffer_info->page = NULL;
2601                 rx_buffer_info->page_offset = 0;
2602         }
2603
2604         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2605         memset(rx_ring->rx_buffer_info, 0, size);
2606
2607         /* Zero out the descriptor ring */
2608         memset(rx_ring->desc, 0, rx_ring->size);
2609
2610         rx_ring->next_to_clean = 0;
2611         rx_ring->next_to_use = 0;
2612
2613         if (rx_ring->head)
2614                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2615         if (rx_ring->tail)
2616                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2617 }
2618
2619 /**
2620  * ixgbe_clean_tx_ring - Free Tx Buffers
2621  * @adapter: board private structure
2622  * @tx_ring: ring to be cleaned
2623  **/
2624 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2625                                 struct ixgbe_ring *tx_ring)
2626 {
2627         struct ixgbe_tx_buffer *tx_buffer_info;
2628         unsigned long size;
2629         unsigned int i;
2630
2631         /* Free all the Tx ring sk_buffs */
2632
2633         for (i = 0; i < tx_ring->count; i++) {
2634                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2635                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2636         }
2637
2638         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2639         memset(tx_ring->tx_buffer_info, 0, size);
2640
2641         /* Zero out the descriptor ring */
2642         memset(tx_ring->desc, 0, tx_ring->size);
2643
2644         tx_ring->next_to_use = 0;
2645         tx_ring->next_to_clean = 0;
2646
2647         if (tx_ring->head)
2648                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2649         if (tx_ring->tail)
2650                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2651 }
2652
2653 /**
2654  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2655  * @adapter: board private structure
2656  **/
2657 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2658 {
2659         int i;
2660
2661         for (i = 0; i < adapter->num_rx_queues; i++)
2662                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2663 }
2664
2665 /**
2666  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2667  * @adapter: board private structure
2668  **/
2669 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2670 {
2671         int i;
2672
2673         for (i = 0; i < adapter->num_tx_queues; i++)
2674                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2675 }
2676
2677 void ixgbe_down(struct ixgbe_adapter *adapter)
2678 {
2679         struct net_device *netdev = adapter->netdev;
2680         struct ixgbe_hw *hw = &adapter->hw;
2681         u32 rxctrl;
2682         u32 txdctl;
2683         int i, j;
2684
2685         /* signal that we are down to the interrupt handler */
2686         set_bit(__IXGBE_DOWN, &adapter->state);
2687
2688         /* disable receives */
2689         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2690         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2691
2692         netif_tx_disable(netdev);
2693
2694         IXGBE_WRITE_FLUSH(hw);
2695         msleep(10);
2696
2697         netif_tx_stop_all_queues(netdev);
2698
2699         ixgbe_irq_disable(adapter);
2700
2701         ixgbe_napi_disable_all(adapter);
2702
2703         del_timer_sync(&adapter->watchdog_timer);
2704         cancel_work_sync(&adapter->watchdog_task);
2705
2706         /* disable transmits in the hardware now that interrupts are off */
2707         for (i = 0; i < adapter->num_tx_queues; i++) {
2708                 j = adapter->tx_ring[i].reg_idx;
2709                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2710                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2711                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2712         }
2713         /* Disable the Tx DMA engine on 82599 */
2714         if (hw->mac.type == ixgbe_mac_82599EB)
2715                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2716                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2717                                  ~IXGBE_DMATXCTL_TE));
2718
2719         netif_carrier_off(netdev);
2720
2721 #ifdef CONFIG_IXGBE_DCA
2722         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2723                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2724                 dca_remove_requester(&adapter->pdev->dev);
2725         }
2726
2727 #endif
2728         if (!pci_channel_offline(adapter->pdev))
2729                 ixgbe_reset(adapter);
2730         ixgbe_clean_all_tx_rings(adapter);
2731         ixgbe_clean_all_rx_rings(adapter);
2732
2733 #ifdef CONFIG_IXGBE_DCA
2734         /* since we reset the hardware DCA settings were cleared */
2735         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2736                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2737                 /* always use CB2 mode, difference is masked
2738                  * in the CB driver */
2739                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2740                 ixgbe_setup_dca(adapter);
2741         }
2742 #endif
2743 }
2744
2745 /**
2746  * ixgbe_poll - NAPI Rx polling callback
2747  * @napi: structure for representing this polling device
2748  * @budget: how many packets driver is allowed to clean
2749  *
2750  * This function is used for legacy and MSI, NAPI mode
2751  **/
2752 static int ixgbe_poll(struct napi_struct *napi, int budget)
2753 {
2754         struct ixgbe_q_vector *q_vector =
2755                                 container_of(napi, struct ixgbe_q_vector, napi);
2756         struct ixgbe_adapter *adapter = q_vector->adapter;
2757         int tx_clean_complete, work_done = 0;
2758
2759 #ifdef CONFIG_IXGBE_DCA
2760         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2761                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2762                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2763         }
2764 #endif
2765
2766         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2767         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2768
2769         if (!tx_clean_complete)
2770                 work_done = budget;
2771
2772         /* If budget not fully consumed, exit the polling mode */
2773         if (work_done < budget) {
2774                 napi_complete(napi);
2775                 if (adapter->itr_setting & 1)
2776                         ixgbe_set_itr(adapter);
2777                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2778                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2779         }
2780         return work_done;
2781 }
2782
2783 /**
2784  * ixgbe_tx_timeout - Respond to a Tx Hang
2785  * @netdev: network interface device structure
2786  **/
2787 static void ixgbe_tx_timeout(struct net_device *netdev)
2788 {
2789         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2790
2791         /* Do the reset outside of interrupt context */
2792         schedule_work(&adapter->reset_task);
2793 }
2794
2795 static void ixgbe_reset_task(struct work_struct *work)
2796 {
2797         struct ixgbe_adapter *adapter;
2798         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2799
2800         /* If we're already down or resetting, just bail */
2801         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2802             test_bit(__IXGBE_RESETTING, &adapter->state))
2803                 return;
2804
2805         adapter->tx_timeout_count++;
2806
2807         ixgbe_reinit_locked(adapter);
2808 }
2809
2810 #ifdef CONFIG_IXGBE_DCB
2811 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2812 {
2813         bool ret = false;
2814
2815         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2816                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2817                 adapter->num_rx_queues =
2818                                       adapter->ring_feature[RING_F_DCB].indices;
2819                 adapter->num_tx_queues =
2820                                       adapter->ring_feature[RING_F_DCB].indices;
2821                 ret = true;
2822         } else {
2823                 ret = false;
2824         }
2825
2826         return ret;
2827 }
2828 #endif
2829
2830 /**
2831  * ixgbe_set_rss_queues: Allocate queues for RSS
2832  * @adapter: board private structure to initialize
2833  *
2834  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2835  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2836  *
2837  **/
2838 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2839 {
2840         bool ret = false;
2841
2842         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2843                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2844                 adapter->num_rx_queues =
2845                                       adapter->ring_feature[RING_F_RSS].indices;
2846                 adapter->num_tx_queues =
2847                                       adapter->ring_feature[RING_F_RSS].indices;
2848                 ret = true;
2849         } else {
2850                 ret = false;
2851         }
2852
2853         return ret;
2854 }
2855
2856 #ifdef IXGBE_FCOE
2857 /**
2858  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2859  * @adapter: board private structure to initialize
2860  *
2861  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2862  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2863  * rx queues out of the max number of rx queues, instead, it is used as the
2864  * index of the first rx queue used by FCoE.
2865  *
2866  **/
2867 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2868 {
2869         bool ret = false;
2870         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2871
2872         f->indices = min((int)num_online_cpus(), f->indices);
2873         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2874 #ifdef CONFIG_IXGBE_DCB
2875                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2876                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2877                         ixgbe_set_dcb_queues(adapter);
2878                 }
2879 #endif
2880                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2881                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2882                         ixgbe_set_rss_queues(adapter);
2883                 }
2884                 /* adding FCoE rx rings to the end */
2885                 f->mask = adapter->num_rx_queues;
2886                 adapter->num_rx_queues += f->indices;
2887                 if (adapter->num_tx_queues == 0)
2888                         adapter->num_tx_queues = f->indices;
2889
2890                 ret = true;
2891         }
2892
2893         return ret;
2894 }
2895
2896 #endif /* IXGBE_FCOE */
2897 /*
2898  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2899  * @adapter: board private structure to initialize
2900  *
2901  * This is the top level queue allocation routine.  The order here is very
2902  * important, starting with the "most" number of features turned on at once,
2903  * and ending with the smallest set of features.  This way large combinations
2904  * can be allocated if they're turned on, and smaller combinations are the
2905  * fallthrough conditions.
2906  *
2907  **/
2908 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2909 {
2910 #ifdef IXGBE_FCOE
2911         if (ixgbe_set_fcoe_queues(adapter))
2912                 goto done;
2913
2914 #endif /* IXGBE_FCOE */
2915 #ifdef CONFIG_IXGBE_DCB
2916         if (ixgbe_set_dcb_queues(adapter))
2917                 goto done;
2918
2919 #endif
2920         if (ixgbe_set_rss_queues(adapter))
2921                 goto done;
2922
2923         /* fallback to base case */
2924         adapter->num_rx_queues = 1;
2925         adapter->num_tx_queues = 1;
2926
2927 done:
2928         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2929         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2930 }
2931
2932 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2933                                        int vectors)
2934 {
2935         int err, vector_threshold;
2936
2937         /* We'll want at least 3 (vector_threshold):
2938          * 1) TxQ[0] Cleanup
2939          * 2) RxQ[0] Cleanup
2940          * 3) Other (Link Status Change, etc.)
2941          * 4) TCP Timer (optional)
2942          */
2943         vector_threshold = MIN_MSIX_COUNT;
2944
2945         /* The more we get, the more we will assign to Tx/Rx Cleanup
2946          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2947          * Right now, we simply care about how many we'll get; we'll
2948          * set them up later while requesting irq's.
2949          */
2950         while (vectors >= vector_threshold) {
2951                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2952                                       vectors);
2953                 if (!err) /* Success in acquiring all requested vectors. */
2954                         break;
2955                 else if (err < 0)
2956                         vectors = 0; /* Nasty failure, quit now */
2957                 else /* err == number of vectors we should try again with */
2958                         vectors = err;
2959         }
2960
2961         if (vectors < vector_threshold) {
2962                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2963                  * This just means we'll go with either a single MSI
2964                  * vector or fall back to legacy interrupts.
2965                  */
2966                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2967                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2968                 kfree(adapter->msix_entries);
2969                 adapter->msix_entries = NULL;
2970         } else {
2971                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2972                 /*
2973                  * Adjust for only the vectors we'll use, which is minimum
2974                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2975                  * vectors we were allocated.
2976                  */
2977                 adapter->num_msix_vectors = min(vectors,
2978                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2979         }
2980 }
2981
2982 /**
2983  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2984  * @adapter: board private structure to initialize
2985  *
2986  * Cache the descriptor ring offsets for RSS to the assigned rings.
2987  *
2988  **/
2989 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2990 {
2991         int i;
2992         bool ret = false;
2993
2994         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2995                 for (i = 0; i < adapter->num_rx_queues; i++)
2996                         adapter->rx_ring[i].reg_idx = i;
2997                 for (i = 0; i < adapter->num_tx_queues; i++)
2998                         adapter->tx_ring[i].reg_idx = i;
2999                 ret = true;
3000         } else {
3001                 ret = false;
3002         }
3003
3004         return ret;
3005 }
3006
3007 #ifdef CONFIG_IXGBE_DCB
3008 /**
3009  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3010  * @adapter: board private structure to initialize
3011  *
3012  * Cache the descriptor ring offsets for DCB to the assigned rings.
3013  *
3014  **/
3015 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3016 {
3017         int i;
3018         bool ret = false;
3019         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3020
3021         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3022                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3023                         /* the number of queues is assumed to be symmetric */
3024                         for (i = 0; i < dcb_i; i++) {
3025                                 adapter->rx_ring[i].reg_idx = i << 3;
3026                                 adapter->tx_ring[i].reg_idx = i << 2;
3027                         }
3028                         ret = true;
3029                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3030                         if (dcb_i == 8) {
3031                                 /*
3032                                  * Tx TC0 starts at: descriptor queue 0
3033                                  * Tx TC1 starts at: descriptor queue 32
3034                                  * Tx TC2 starts at: descriptor queue 64
3035                                  * Tx TC3 starts at: descriptor queue 80
3036                                  * Tx TC4 starts at: descriptor queue 96
3037                                  * Tx TC5 starts at: descriptor queue 104
3038                                  * Tx TC6 starts at: descriptor queue 112
3039                                  * Tx TC7 starts at: descriptor queue 120
3040                                  *
3041                                  * Rx TC0-TC7 are offset by 16 queues each
3042                                  */
3043                                 for (i = 0; i < 3; i++) {
3044                                         adapter->tx_ring[i].reg_idx = i << 5;
3045                                         adapter->rx_ring[i].reg_idx = i << 4;
3046                                 }
3047                                 for ( ; i < 5; i++) {
3048                                         adapter->tx_ring[i].reg_idx =
3049                                                                  ((i + 2) << 4);
3050                                         adapter->rx_ring[i].reg_idx = i << 4;
3051                                 }
3052                                 for ( ; i < dcb_i; i++) {
3053                                         adapter->tx_ring[i].reg_idx =
3054                                                                  ((i + 8) << 3);
3055                                         adapter->rx_ring[i].reg_idx = i << 4;
3056                                 }
3057
3058                                 ret = true;
3059                         } else if (dcb_i == 4) {
3060                                 /*
3061                                  * Tx TC0 starts at: descriptor queue 0
3062                                  * Tx TC1 starts at: descriptor queue 64
3063                                  * Tx TC2 starts at: descriptor queue 96
3064                                  * Tx TC3 starts at: descriptor queue 112
3065                                  *
3066                                  * Rx TC0-TC3 are offset by 32 queues each
3067                                  */
3068                                 adapter->tx_ring[0].reg_idx = 0;
3069                                 adapter->tx_ring[1].reg_idx = 64;
3070                                 adapter->tx_ring[2].reg_idx = 96;
3071                                 adapter->tx_ring[3].reg_idx = 112;
3072                                 for (i = 0 ; i < dcb_i; i++)
3073                                         adapter->rx_ring[i].reg_idx = i << 5;
3074
3075                                 ret = true;
3076                         } else {
3077                                 ret = false;
3078                         }
3079                 } else {
3080                         ret = false;
3081                 }
3082         } else {
3083                 ret = false;
3084         }
3085
3086         return ret;
3087 }
3088 #endif
3089
3090 #ifdef IXGBE_FCOE
3091 /**
3092  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3093  * @adapter: board private structure to initialize
3094  *
3095  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3096  *
3097  */
3098 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3099 {
3100         int i, fcoe_i = 0;
3101         bool ret = false;
3102         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3103
3104         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3105 #ifdef CONFIG_IXGBE_DCB
3106                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3107                         ixgbe_cache_ring_dcb(adapter);
3108                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3109                 }
3110 #endif /* CONFIG_IXGBE_DCB */
3111                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3112                         ixgbe_cache_ring_rss(adapter);
3113                         fcoe_i = f->mask;
3114                 }
3115                 for (i = 0; i < f->indices; i++, fcoe_i++)
3116                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3117                 ret = true;
3118         }
3119         return ret;
3120 }
3121
3122 #endif /* IXGBE_FCOE */
3123 /**
3124  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3125  * @adapter: board private structure to initialize
3126  *
3127  * Once we know the feature-set enabled for the device, we'll cache
3128  * the register offset the descriptor ring is assigned to.
3129  *
3130  * Note, the order the various feature calls is important.  It must start with
3131  * the "most" features enabled at the same time, then trickle down to the
3132  * least amount of features turned on at once.
3133  **/
3134 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3135 {
3136         /* start with default case */
3137         adapter->rx_ring[0].reg_idx = 0;
3138         adapter->tx_ring[0].reg_idx = 0;
3139
3140 #ifdef IXGBE_FCOE
3141         if (ixgbe_cache_ring_fcoe(adapter))
3142                 return;
3143
3144 #endif /* IXGBE_FCOE */
3145 #ifdef CONFIG_IXGBE_DCB
3146         if (ixgbe_cache_ring_dcb(adapter))
3147                 return;
3148
3149 #endif
3150         if (ixgbe_cache_ring_rss(adapter))
3151                 return;
3152 }
3153
3154 /**
3155  * ixgbe_alloc_queues - Allocate memory for all rings
3156  * @adapter: board private structure to initialize
3157  *
3158  * We allocate one ring per queue at run-time since we don't know the
3159  * number of queues at compile-time.  The polling_netdev array is
3160  * intended for Multiqueue, but should work fine with a single queue.
3161  **/
3162 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3163 {
3164         int i;
3165
3166         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3167                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3168         if (!adapter->tx_ring)
3169                 goto err_tx_ring_allocation;
3170
3171         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3172                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3173         if (!adapter->rx_ring)
3174                 goto err_rx_ring_allocation;
3175
3176         for (i = 0; i < adapter->num_tx_queues; i++) {
3177                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3178                 adapter->tx_ring[i].queue_index = i;
3179         }
3180
3181         for (i = 0; i < adapter->num_rx_queues; i++) {
3182                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3183                 adapter->rx_ring[i].queue_index = i;
3184         }
3185
3186         ixgbe_cache_ring_register(adapter);
3187
3188         return 0;
3189
3190 err_rx_ring_allocation:
3191         kfree(adapter->tx_ring);
3192 err_tx_ring_allocation:
3193         return -ENOMEM;
3194 }
3195
3196 /**
3197  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3198  * @adapter: board private structure to initialize
3199  *
3200  * Attempt to configure the interrupts using the best available
3201  * capabilities of the hardware and the kernel.
3202  **/
3203 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3204 {
3205         struct ixgbe_hw *hw = &adapter->hw;
3206         int err = 0;
3207         int vector, v_budget;
3208
3209         /*
3210          * It's easy to be greedy for MSI-X vectors, but it really
3211          * doesn't do us much good if we have a lot more vectors
3212          * than CPU's.  So let's be conservative and only ask for
3213          * (roughly) twice the number of vectors as there are CPU's.
3214          */
3215         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3216                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3217
3218         /*
3219          * At the same time, hardware can only support a maximum of
3220          * hw.mac->max_msix_vectors vectors.  With features
3221          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3222          * descriptor queues supported by our device.  Thus, we cap it off in
3223          * those rare cases where the cpu count also exceeds our vector limit.
3224          */
3225         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3226
3227         /* A failure in MSI-X entry allocation isn't fatal, but it does
3228          * mean we disable MSI-X capabilities of the adapter. */
3229         adapter->msix_entries = kcalloc(v_budget,
3230                                         sizeof(struct msix_entry), GFP_KERNEL);
3231         if (adapter->msix_entries) {
3232                 for (vector = 0; vector < v_budget; vector++)
3233                         adapter->msix_entries[vector].entry = vector;
3234
3235                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3236
3237                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3238                         goto out;
3239         }
3240
3241         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3242         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3243         ixgbe_set_num_queues(adapter);
3244
3245         err = pci_enable_msi(adapter->pdev);
3246         if (!err) {
3247                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3248         } else {
3249                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3250                         "falling back to legacy.  Error: %d\n", err);
3251                 /* reset err */
3252                 err = 0;
3253         }
3254
3255 out:
3256         return err;
3257 }
3258
3259 /**
3260  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3261  * @adapter: board private structure to initialize
3262  *
3263  * We allocate one q_vector per queue interrupt.  If allocation fails we
3264  * return -ENOMEM.
3265  **/
3266 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3267 {
3268         int q_idx, num_q_vectors;
3269         struct ixgbe_q_vector *q_vector;
3270         int napi_vectors;
3271         int (*poll)(struct napi_struct *, int);
3272
3273         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3274                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3275                 napi_vectors = adapter->num_rx_queues;
3276                 poll = &ixgbe_clean_rxonly;
3277         } else {
3278                 num_q_vectors = 1;
3279                 napi_vectors = 1;
3280                 poll = &ixgbe_poll;
3281         }
3282
3283         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3284                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3285                 if (!q_vector)
3286                         goto err_out;
3287                 q_vector->adapter = adapter;
3288                 q_vector->v_idx = q_idx;
3289                 q_vector->eitr = adapter->eitr_param;
3290                 if (q_idx < napi_vectors)
3291                         netif_napi_add(adapter->netdev, &q_vector->napi,
3292                                        (*poll), 64);
3293                 adapter->q_vector[q_idx] = q_vector;
3294         }
3295
3296         return 0;
3297
3298 err_out:
3299         while (q_idx) {
3300                 q_idx--;
3301                 q_vector = adapter->q_vector[q_idx];
3302                 netif_napi_del(&q_vector->napi);
3303                 kfree(q_vector);
3304                 adapter->q_vector[q_idx] = NULL;
3305         }
3306         return -ENOMEM;
3307 }
3308
3309 /**
3310  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3311  * @adapter: board private structure to initialize
3312  *
3313  * This function frees the memory allocated to the q_vectors.  In addition if
3314  * NAPI is enabled it will delete any references to the NAPI struct prior
3315  * to freeing the q_vector.
3316  **/
3317 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3318 {
3319         int q_idx, num_q_vectors;
3320         int napi_vectors;
3321
3322         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3323                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3324                 napi_vectors = adapter->num_rx_queues;
3325         } else {
3326                 num_q_vectors = 1;
3327                 napi_vectors = 1;
3328         }
3329
3330         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3331                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3332
3333                 adapter->q_vector[q_idx] = NULL;
3334                 if (q_idx < napi_vectors)
3335                         netif_napi_del(&q_vector->napi);
3336                 kfree(q_vector);
3337         }
3338 }
3339
3340 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3341 {
3342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3343                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3344                 pci_disable_msix(adapter->pdev);
3345                 kfree(adapter->msix_entries);
3346                 adapter->msix_entries = NULL;
3347         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3348                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3349                 pci_disable_msi(adapter->pdev);
3350         }
3351         return;
3352 }
3353
3354 /**
3355  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3356  * @adapter: board private structure to initialize
3357  *
3358  * We determine which interrupt scheme to use based on...
3359  * - Kernel support (MSI, MSI-X)
3360  *   - which can be user-defined (via MODULE_PARAM)
3361  * - Hardware queue count (num_*_queues)
3362  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3363  **/
3364 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3365 {
3366         int err;
3367
3368         /* Number of supported queues */
3369         ixgbe_set_num_queues(adapter);
3370
3371         err = ixgbe_set_interrupt_capability(adapter);
3372         if (err) {
3373                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3374                 goto err_set_interrupt;
3375         }
3376
3377         err = ixgbe_alloc_q_vectors(adapter);
3378         if (err) {
3379                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3380                         "vectors\n");
3381                 goto err_alloc_q_vectors;
3382         }
3383
3384         err = ixgbe_alloc_queues(adapter);
3385         if (err) {
3386                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3387                 goto err_alloc_queues;
3388         }
3389
3390         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3391                 "Tx Queue count = %u\n",
3392                 (adapter->num_rx_queues > 1) ? "Enabled" :
3393                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3394
3395         set_bit(__IXGBE_DOWN, &adapter->state);
3396
3397         return 0;
3398
3399 err_alloc_queues:
3400         ixgbe_free_q_vectors(adapter);
3401 err_alloc_q_vectors:
3402         ixgbe_reset_interrupt_capability(adapter);
3403 err_set_interrupt:
3404         return err;
3405 }
3406
3407 /**
3408  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3409  * @adapter: board private structure to clear interrupt scheme on
3410  *
3411  * We go through and clear interrupt specific resources and reset the structure
3412  * to pre-load conditions
3413  **/
3414 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3415 {
3416         kfree(adapter->tx_ring);
3417         kfree(adapter->rx_ring);
3418         adapter->tx_ring = NULL;
3419         adapter->rx_ring = NULL;
3420
3421         ixgbe_free_q_vectors(adapter);
3422         ixgbe_reset_interrupt_capability(adapter);
3423 }
3424
3425 /**
3426  * ixgbe_sfp_timer - worker thread to find a missing module
3427  * @data: pointer to our adapter struct
3428  **/
3429 static void ixgbe_sfp_timer(unsigned long data)
3430 {
3431         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3432
3433         /*
3434          * Do the sfp_timer outside of interrupt context due to the
3435          * delays that sfp+ detection requires
3436          */
3437         schedule_work(&adapter->sfp_task);
3438 }
3439
3440 /**
3441  * ixgbe_sfp_task - worker thread to find a missing module
3442  * @work: pointer to work_struct containing our data
3443  **/
3444 static void ixgbe_sfp_task(struct work_struct *work)
3445 {
3446         struct ixgbe_adapter *adapter = container_of(work,
3447                                                      struct ixgbe_adapter,
3448                                                      sfp_task);
3449         struct ixgbe_hw *hw = &adapter->hw;
3450
3451         if ((hw->phy.type == ixgbe_phy_nl) &&
3452             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3453                 s32 ret = hw->phy.ops.identify_sfp(hw);
3454                 if (ret)
3455                         goto reschedule;
3456                 ret = hw->phy.ops.reset(hw);
3457                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3458                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3459                                 "unsupported SFP+ module type was detected.\n"
3460                                 "Reload the driver after installing a "
3461                                 "supported module.\n");
3462                         unregister_netdev(adapter->netdev);
3463                 } else {
3464                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3465                                 hw->phy.sfp_type);
3466                 }
3467                 /* don't need this routine any more */
3468                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3469         }
3470         return;
3471 reschedule:
3472         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3473                 mod_timer(&adapter->sfp_timer,
3474                           round_jiffies(jiffies + (2 * HZ)));
3475 }
3476
3477 /**
3478  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3479  * @adapter: board private structure to initialize
3480  *
3481  * ixgbe_sw_init initializes the Adapter private data structure.
3482  * Fields are initialized based on PCI device information and
3483  * OS network device settings (MTU size).
3484  **/
3485 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3486 {
3487         struct ixgbe_hw *hw = &adapter->hw;
3488         struct pci_dev *pdev = adapter->pdev;
3489         unsigned int rss;
3490 #ifdef CONFIG_IXGBE_DCB
3491         int j;
3492         struct tc_configuration *tc;
3493 #endif
3494
3495         /* PCI config space info */
3496
3497         hw->vendor_id = pdev->vendor;
3498         hw->device_id = pdev->device;
3499         hw->revision_id = pdev->revision;
3500         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3501         hw->subsystem_device_id = pdev->subsystem_device;
3502
3503         /* Set capability flags */
3504         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3505         adapter->ring_feature[RING_F_RSS].indices = rss;
3506         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3507         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3508         if (hw->mac.type == ixgbe_mac_82598EB) {
3509                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3510                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3511                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3512         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3513                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3514                 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3515                 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3516 #ifdef IXGBE_FCOE
3517                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3518                 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3519 #endif /* IXGBE_FCOE */
3520         }
3521
3522 #ifdef CONFIG_IXGBE_DCB
3523         /* Configure DCB traffic classes */
3524         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3525                 tc = &adapter->dcb_cfg.tc_config[j];
3526                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3527                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3528                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3529                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3530                 tc->dcb_pfc = pfc_disabled;
3531         }
3532         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3533         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3534         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3535         adapter->dcb_cfg.round_robin_enable = false;
3536         adapter->dcb_set_bitmap = 0x00;
3537         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3538                            adapter->ring_feature[RING_F_DCB].indices);
3539
3540 #endif
3541
3542         /* default flow control settings */
3543         hw->fc.requested_mode = ixgbe_fc_full;
3544         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3545         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3546         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3547         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3548         hw->fc.send_xon = true;
3549         hw->fc.disable_fc_autoneg = false;
3550
3551         /* enable itr by default in dynamic mode */
3552         adapter->itr_setting = 1;
3553         adapter->eitr_param = 20000;
3554
3555         /* set defaults for eitr in MegaBytes */
3556         adapter->eitr_low = 10;
3557         adapter->eitr_high = 20;
3558
3559         /* set default ring sizes */
3560         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3561         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3562
3563         /* initialize eeprom parameters */
3564         if (ixgbe_init_eeprom_params_generic(hw)) {
3565                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3566                 return -EIO;
3567         }
3568
3569         /* enable rx csum by default */
3570         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3571
3572         set_bit(__IXGBE_DOWN, &adapter->state);
3573
3574         return 0;
3575 }
3576
3577 /**
3578  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3579  * @adapter: board private structure
3580  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3581  *
3582  * Return 0 on success, negative on failure
3583  **/
3584 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3585                              struct ixgbe_ring *tx_ring)
3586 {
3587         struct pci_dev *pdev = adapter->pdev;
3588         int size;
3589
3590         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3591         tx_ring->tx_buffer_info = vmalloc(size);
3592         if (!tx_ring->tx_buffer_info)
3593                 goto err;
3594         memset(tx_ring->tx_buffer_info, 0, size);
3595
3596         /* round up to nearest 4K */
3597         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3598         tx_ring->size = ALIGN(tx_ring->size, 4096);
3599
3600         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3601                                              &tx_ring->dma);
3602         if (!tx_ring->desc)
3603                 goto err;
3604
3605         tx_ring->next_to_use = 0;
3606         tx_ring->next_to_clean = 0;
3607         tx_ring->work_limit = tx_ring->count;
3608         return 0;
3609
3610 err:
3611         vfree(tx_ring->tx_buffer_info);
3612         tx_ring->tx_buffer_info = NULL;
3613         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3614                             "descriptor ring\n");
3615         return -ENOMEM;
3616 }
3617
3618 /**
3619  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3620  * @adapter: board private structure
3621  *
3622  * If this function returns with an error, then it's possible one or
3623  * more of the rings is populated (while the rest are not).  It is the
3624  * callers duty to clean those orphaned rings.
3625  *
3626  * Return 0 on success, negative on failure
3627  **/
3628 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3629 {
3630         int i, err = 0;
3631
3632         for (i = 0; i < adapter->num_tx_queues; i++) {
3633                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3634                 if (!err)
3635                         continue;
3636                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3637                 break;
3638         }
3639
3640         return err;
3641 }
3642
3643 /**
3644  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3645  * @adapter: board private structure
3646  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3647  *
3648  * Returns 0 on success, negative on failure
3649  **/
3650 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3651                              struct ixgbe_ring *rx_ring)
3652 {
3653         struct pci_dev *pdev = adapter->pdev;
3654         int size;
3655
3656         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3657         rx_ring->rx_buffer_info = vmalloc(size);
3658         if (!rx_ring->rx_buffer_info) {
3659                 DPRINTK(PROBE, ERR,
3660                         "vmalloc allocation failed for the rx desc ring\n");
3661                 goto alloc_failed;
3662         }
3663         memset(rx_ring->rx_buffer_info, 0, size);
3664
3665         /* Round up to nearest 4K */
3666         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3667         rx_ring->size = ALIGN(rx_ring->size, 4096);
3668
3669         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3670
3671         if (!rx_ring->desc) {
3672                 DPRINTK(PROBE, ERR,
3673                         "Memory allocation failed for the rx desc ring\n");
3674                 vfree(rx_ring->rx_buffer_info);
3675                 goto alloc_failed;
3676         }
3677
3678         rx_ring->next_to_clean = 0;
3679         rx_ring->next_to_use = 0;
3680
3681         return 0;
3682
3683 alloc_failed:
3684         return -ENOMEM;
3685 }
3686
3687 /**
3688  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3689  * @adapter: board private structure
3690  *
3691  * If this function returns with an error, then it's possible one or
3692  * more of the rings is populated (while the rest are not).  It is the
3693  * callers duty to clean those orphaned rings.
3694  *
3695  * Return 0 on success, negative on failure
3696  **/
3697
3698 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3699 {
3700         int i, err = 0;
3701
3702         for (i = 0; i < adapter->num_rx_queues; i++) {
3703                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3704                 if (!err)
3705                         continue;
3706                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3707                 break;
3708         }
3709
3710         return err;
3711 }
3712
3713 /**
3714  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3715  * @adapter: board private structure
3716  * @tx_ring: Tx descriptor ring for a specific queue
3717  *
3718  * Free all transmit software resources
3719  **/
3720 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3721                              struct ixgbe_ring *tx_ring)
3722 {
3723         struct pci_dev *pdev = adapter->pdev;
3724
3725         ixgbe_clean_tx_ring(adapter, tx_ring);
3726
3727         vfree(tx_ring->tx_buffer_info);
3728         tx_ring->tx_buffer_info = NULL;
3729
3730         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3731
3732         tx_ring->desc = NULL;
3733 }
3734
3735 /**
3736  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3737  * @adapter: board private structure
3738  *
3739  * Free all transmit software resources
3740  **/
3741 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3742 {
3743         int i;
3744
3745         for (i = 0; i < adapter->num_tx_queues; i++)
3746                 if (adapter->tx_ring[i].desc)
3747                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3748 }
3749
3750 /**
3751  * ixgbe_free_rx_resources - Free Rx Resources
3752  * @adapter: board private structure
3753  * @rx_ring: ring to clean the resources from
3754  *
3755  * Free all receive software resources
3756  **/
3757 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3758                              struct ixgbe_ring *rx_ring)
3759 {
3760         struct pci_dev *pdev = adapter->pdev;
3761
3762         ixgbe_clean_rx_ring(adapter, rx_ring);
3763
3764         vfree(rx_ring->rx_buffer_info);
3765         rx_ring->rx_buffer_info = NULL;
3766
3767         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3768
3769         rx_ring->desc = NULL;
3770 }
3771
3772 /**
3773  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3774  * @adapter: board private structure
3775  *
3776  * Free all receive software resources
3777  **/
3778 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3779 {
3780         int i;
3781
3782         for (i = 0; i < adapter->num_rx_queues; i++)
3783                 if (adapter->rx_ring[i].desc)
3784                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3785 }
3786
3787 /**
3788  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3789  * @netdev: network interface device structure
3790  * @new_mtu: new value for maximum frame size
3791  *
3792  * Returns 0 on success, negative on failure
3793  **/
3794 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3795 {
3796         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3797         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3798
3799         /* MTU < 68 is an error and causes problems on some kernels */
3800         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3801                 return -EINVAL;
3802
3803         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3804                 netdev->mtu, new_mtu);
3805         /* must set new MTU before calling down or up */
3806         netdev->mtu = new_mtu;
3807
3808         if (netif_running(netdev))
3809                 ixgbe_reinit_locked(adapter);
3810
3811         return 0;
3812 }
3813
3814 /**
3815  * ixgbe_open - Called when a network interface is made active
3816  * @netdev: network interface device structure
3817  *
3818  * Returns 0 on success, negative value on failure
3819  *
3820  * The open entry point is called when a network interface is made
3821  * active by the system (IFF_UP).  At this point all resources needed
3822  * for transmit and receive operations are allocated, the interrupt
3823  * handler is registered with the OS, the watchdog timer is started,
3824  * and the stack is notified that the interface is ready.
3825  **/
3826 static int ixgbe_open(struct net_device *netdev)
3827 {
3828         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3829         int err;
3830
3831         /* disallow open during test */
3832         if (test_bit(__IXGBE_TESTING, &adapter->state))
3833                 return -EBUSY;
3834
3835         netif_carrier_off(netdev);
3836
3837         /* allocate transmit descriptors */
3838         err = ixgbe_setup_all_tx_resources(adapter);
3839         if (err)
3840                 goto err_setup_tx;
3841
3842         /* allocate receive descriptors */
3843         err = ixgbe_setup_all_rx_resources(adapter);
3844         if (err)
3845                 goto err_setup_rx;
3846
3847         ixgbe_configure(adapter);
3848
3849         err = ixgbe_request_irq(adapter);
3850         if (err)
3851                 goto err_req_irq;
3852
3853         err = ixgbe_up_complete(adapter);
3854         if (err)
3855                 goto err_up;
3856
3857         netif_tx_start_all_queues(netdev);
3858
3859         return 0;
3860
3861 err_up:
3862         ixgbe_release_hw_control(adapter);
3863         ixgbe_free_irq(adapter);
3864 err_req_irq:
3865 err_setup_rx:
3866         ixgbe_free_all_rx_resources(adapter);
3867 err_setup_tx:
3868         ixgbe_free_all_tx_resources(adapter);
3869         ixgbe_reset(adapter);
3870
3871         return err;
3872 }
3873
3874 /**
3875  * ixgbe_close - Disables a network interface
3876  * @netdev: network interface device structure
3877  *
3878  * Returns 0, this is not allowed to fail
3879  *
3880  * The close entry point is called when an interface is de-activated
3881  * by the OS.  The hardware is still under the drivers control, but
3882  * needs to be disabled.  A global MAC reset is issued to stop the
3883  * hardware, and all transmit and receive resources are freed.
3884  **/
3885 static int ixgbe_close(struct net_device *netdev)
3886 {
3887         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3888
3889         ixgbe_down(adapter);
3890         ixgbe_free_irq(adapter);
3891
3892         ixgbe_free_all_tx_resources(adapter);
3893         ixgbe_free_all_rx_resources(adapter);
3894
3895         ixgbe_release_hw_control(adapter);
3896
3897         return 0;
3898 }
3899
3900 #ifdef CONFIG_PM
3901 static int ixgbe_resume(struct pci_dev *pdev)
3902 {
3903         struct net_device *netdev = pci_get_drvdata(pdev);
3904         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3905         u32 err;
3906
3907         pci_set_power_state(pdev, PCI_D0);
3908         pci_restore_state(pdev);
3909
3910         err = pci_enable_device_mem(pdev);
3911         if (err) {
3912                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3913                                 "suspend\n");
3914                 return err;
3915         }
3916         pci_set_master(pdev);
3917
3918         pci_wake_from_d3(pdev, false);
3919
3920         err = ixgbe_init_interrupt_scheme(adapter);
3921         if (err) {
3922                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3923                                 "device\n");
3924                 return err;
3925         }
3926
3927         ixgbe_reset(adapter);
3928
3929         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3930
3931         if (netif_running(netdev)) {
3932                 err = ixgbe_open(adapter->netdev);
3933                 if (err)
3934                         return err;
3935         }
3936
3937         netif_device_attach(netdev);
3938
3939         return 0;
3940 }
3941 #endif /* CONFIG_PM */
3942
3943 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3944 {
3945         struct net_device *netdev = pci_get_drvdata(pdev);
3946         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3947         struct ixgbe_hw *hw = &adapter->hw;
3948         u32 ctrl, fctrl;
3949         u32 wufc = adapter->wol;
3950 #ifdef CONFIG_PM
3951         int retval = 0;
3952 #endif
3953
3954         netif_device_detach(netdev);
3955
3956         if (netif_running(netdev)) {
3957                 ixgbe_down(adapter);
3958                 ixgbe_free_irq(adapter);
3959                 ixgbe_free_all_tx_resources(adapter);
3960                 ixgbe_free_all_rx_resources(adapter);
3961         }
3962         ixgbe_clear_interrupt_scheme(adapter);
3963
3964 #ifdef CONFIG_PM
3965         retval = pci_save_state(pdev);
3966         if (retval)
3967                 return retval;
3968
3969 #endif
3970         if (wufc) {
3971                 ixgbe_set_rx_mode(netdev);
3972
3973                 /* turn on all-multi mode if wake on multicast is enabled */
3974                 if (wufc & IXGBE_WUFC_MC) {
3975                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3976                         fctrl |= IXGBE_FCTRL_MPE;
3977                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3978                 }
3979
3980                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3981                 ctrl |= IXGBE_CTRL_GIO_DIS;
3982                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3983
3984                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3985         } else {
3986                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3987                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3988         }
3989
3990         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3991                 pci_wake_from_d3(pdev, true);
3992         else
3993                 pci_wake_from_d3(pdev, false);
3994
3995         *enable_wake = !!wufc;
3996
3997         ixgbe_release_hw_control(adapter);
3998
3999         pci_disable_device(pdev);
4000
4001         return 0;
4002 }
4003
4004 #ifdef CONFIG_PM
4005 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4006 {
4007         int retval;
4008         bool wake;
4009
4010         retval = __ixgbe_shutdown(pdev, &wake);
4011         if (retval)
4012                 return retval;
4013
4014         if (wake) {
4015                 pci_prepare_to_sleep(pdev);
4016         } else {
4017                 pci_wake_from_d3(pdev, false);
4018                 pci_set_power_state(pdev, PCI_D3hot);
4019         }
4020
4021         return 0;
4022 }
4023 #endif /* CONFIG_PM */
4024
4025 static void ixgbe_shutdown(struct pci_dev *pdev)
4026 {
4027         bool wake;
4028
4029         __ixgbe_shutdown(pdev, &wake);
4030
4031         if (system_state == SYSTEM_POWER_OFF) {
4032                 pci_wake_from_d3(pdev, wake);
4033                 pci_set_power_state(pdev, PCI_D3hot);
4034         }
4035 }
4036
4037 /**
4038  * ixgbe_update_stats - Update the board statistics counters.
4039  * @adapter: board private structure
4040  **/
4041 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4042 {
4043         struct ixgbe_hw *hw = &adapter->hw;
4044         u64 total_mpc = 0;
4045         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4046
4047         if (hw->mac.type == ixgbe_mac_82599EB) {
4048                 u64 rsc_count = 0;
4049                 for (i = 0; i < 16; i++)
4050                         adapter->hw_rx_no_dma_resources +=
4051                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4052                 for (i = 0; i < adapter->num_rx_queues; i++)
4053                         rsc_count += adapter->rx_ring[i].rsc_count;
4054                 adapter->rsc_count = rsc_count;
4055         }
4056
4057         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4058         for (i = 0; i < 8; i++) {
4059                 /* for packet buffers not used, the register should read 0 */
4060                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4061                 missed_rx += mpc;
4062                 adapter->stats.mpc[i] += mpc;
4063                 total_mpc += adapter->stats.mpc[i];
4064                 if (hw->mac.type == ixgbe_mac_82598EB)
4065                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4066                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4067                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4068                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4069                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4070                 if (hw->mac.type == ixgbe_mac_82599EB) {
4071                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4072                                                             IXGBE_PXONRXCNT(i));
4073                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4074                                                            IXGBE_PXOFFRXCNT(i));
4075                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4076                 } else {
4077                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4078                                                               IXGBE_PXONRXC(i));
4079                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4080                                                              IXGBE_PXOFFRXC(i));
4081                 }
4082                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4083                                                             IXGBE_PXONTXC(i));
4084                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4085                                                              IXGBE_PXOFFTXC(i));
4086         }
4087         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4088         /* work around hardware counting issue */
4089         adapter->stats.gprc -= missed_rx;
4090
4091         /* 82598 hardware only has a 32 bit counter in the high register */
4092         if (hw->mac.type == ixgbe_mac_82599EB) {
4093                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4094                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4095                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4096                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4097                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4098                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4099                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4100                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4101 #ifdef IXGBE_FCOE
4102                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4103                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4104                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4105                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4106                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4107                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4108 #endif /* IXGBE_FCOE */
4109         } else {
4110                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4111                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4112                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4113                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4114                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4115         }
4116         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4117         adapter->stats.bprc += bprc;
4118         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4119         if (hw->mac.type == ixgbe_mac_82598EB)
4120                 adapter->stats.mprc -= bprc;
4121         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4122         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4123         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4124         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4125         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4126         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4127         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4128         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4129         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4130         adapter->stats.lxontxc += lxon;
4131         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4132         adapter->stats.lxofftxc += lxoff;
4133         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4134         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4135         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4136         /*
4137          * 82598 errata - tx of flow control packets is included in tx counters
4138          */
4139         xon_off_tot = lxon + lxoff;
4140         adapter->stats.gptc -= xon_off_tot;
4141         adapter->stats.mptc -= xon_off_tot;
4142         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4143         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4144         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4145         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4146         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4147         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4148         adapter->stats.ptc64 -= xon_off_tot;
4149         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4150         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4151         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4152         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4153         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4154         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4155
4156         /* Fill out the OS statistics structure */
4157         adapter->net_stats.multicast = adapter->stats.mprc;
4158
4159         /* Rx Errors */
4160         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4161                                        adapter->stats.rlec;
4162         adapter->net_stats.rx_dropped = 0;
4163         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4164         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4165         adapter->net_stats.rx_missed_errors = total_mpc;
4166 }
4167
4168 /**
4169  * ixgbe_watchdog - Timer Call-back
4170  * @data: pointer to adapter cast into an unsigned long
4171  **/
4172 static void ixgbe_watchdog(unsigned long data)
4173 {
4174         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4175         struct ixgbe_hw *hw = &adapter->hw;
4176
4177         /* Do the watchdog outside of interrupt context due to the lovely
4178          * delays that some of the newer hardware requires */
4179         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
4180                 u64 eics = 0;
4181                 int i;
4182
4183                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4184                         eics |= ((u64)1 << i);
4185
4186                 /* Cause software interrupt to ensure rx rings are cleaned */
4187                 switch (hw->mac.type) {
4188                 case ixgbe_mac_82598EB:
4189                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4190                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4191                         } else {
4192                                 /*
4193                                  * for legacy and MSI interrupts don't set any
4194                                  * bits that are enabled for EIAM, because this
4195                                  * operation would set *both* EIMS and EICS for
4196                                  * any bit in EIAM
4197                                  */
4198                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4199                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4200                         }
4201                         break;
4202                 case ixgbe_mac_82599EB:
4203                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4204                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4205                                                 (u32)(eics & 0xFFFFFFFF));
4206                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4207                                                 (u32)(eics >> 32));
4208                         } else {
4209                                 /*
4210                                  * for legacy and MSI interrupts don't set any
4211                                  * bits that are enabled for EIAM, because this
4212                                  * operation would set *both* EIMS and EICS for
4213                                  * any bit in EIAM
4214                                  */
4215                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4216                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4217                         }
4218                         break;
4219                 default:
4220                         break;
4221                 }
4222                 /* Reset the timer */
4223                 mod_timer(&adapter->watchdog_timer,
4224                           round_jiffies(jiffies + 2 * HZ));
4225         }
4226
4227         schedule_work(&adapter->watchdog_task);
4228 }
4229
4230 /**
4231  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4232  * @work: pointer to work_struct containing our data
4233  **/
4234 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4235 {
4236         struct ixgbe_adapter *adapter = container_of(work,
4237                                                      struct ixgbe_adapter,
4238                                                      multispeed_fiber_task);
4239         struct ixgbe_hw *hw = &adapter->hw;
4240         u32 autoneg;
4241
4242         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4243         if (hw->mac.ops.get_link_capabilities)
4244                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4245                                                   &hw->mac.autoneg);
4246         if (hw->mac.ops.setup_link_speed)
4247                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4248         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4249         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4250 }
4251
4252 /**
4253  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4254  * @work: pointer to work_struct containing our data
4255  **/
4256 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4257 {
4258         struct ixgbe_adapter *adapter = container_of(work,
4259                                                      struct ixgbe_adapter,
4260                                                      sfp_config_module_task);
4261         struct ixgbe_hw *hw = &adapter->hw;
4262         u32 err;
4263
4264         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4265         err = hw->phy.ops.identify_sfp(hw);
4266         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4267                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4268                 ixgbe_down(adapter);
4269                 return;
4270         }
4271         hw->mac.ops.setup_sfp(hw);
4272
4273         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4274                 /* This will also work for DA Twinax connections */
4275                 schedule_work(&adapter->multispeed_fiber_task);
4276         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4277 }
4278
4279 /**
4280  * ixgbe_watchdog_task - worker thread to bring link up
4281  * @work: pointer to work_struct containing our data
4282  **/
4283 static void ixgbe_watchdog_task(struct work_struct *work)
4284 {
4285         struct ixgbe_adapter *adapter = container_of(work,
4286                                                      struct ixgbe_adapter,
4287                                                      watchdog_task);
4288         struct net_device *netdev = adapter->netdev;
4289         struct ixgbe_hw *hw = &adapter->hw;
4290         u32 link_speed = adapter->link_speed;
4291         bool link_up = adapter->link_up;
4292         int i;
4293         struct ixgbe_ring *tx_ring;
4294         int some_tx_pending = 0;
4295
4296         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4297
4298         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4299                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4300                 if (link_up ||
4301                     time_after(jiffies, (adapter->link_check_timeout +
4302                                          IXGBE_TRY_LINK_TIMEOUT))) {
4303                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4304                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4305                 }
4306                 adapter->link_up = link_up;
4307                 adapter->link_speed = link_speed;
4308         }
4309
4310         if (link_up) {
4311                 if (!netif_carrier_ok(netdev)) {
4312                         bool flow_rx, flow_tx;
4313
4314                         if (hw->mac.type == ixgbe_mac_82599EB) {
4315                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4316                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4317                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4318                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4319                         } else {
4320                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4321                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4322                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4323                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4324                         }
4325
4326                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4327                                "Flow Control: %s\n",
4328                                netdev->name,
4329                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4330                                 "10 Gbps" :
4331                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4332                                  "1 Gbps" : "unknown speed")),
4333                                ((flow_rx && flow_tx) ? "RX/TX" :
4334                                 (flow_rx ? "RX" :
4335                                 (flow_tx ? "TX" : "None"))));
4336
4337                         netif_carrier_on(netdev);
4338                 } else {
4339                         /* Force detection of hung controller */
4340                         adapter->detect_tx_hung = true;
4341                 }
4342         } else {
4343                 adapter->link_up = false;
4344                 adapter->link_speed = 0;
4345                 if (netif_carrier_ok(netdev)) {
4346                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4347                                netdev->name);
4348                         netif_carrier_off(netdev);
4349                 }
4350         }
4351
4352         if (!netif_carrier_ok(netdev)) {
4353                 for (i = 0; i < adapter->num_tx_queues; i++) {
4354                         tx_ring = &adapter->tx_ring[i];
4355                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4356                                 some_tx_pending = 1;
4357                                 break;
4358                         }
4359                 }
4360
4361                 if (some_tx_pending) {
4362                         /* We've lost link, so the controller stops DMA,
4363                          * but we've got queued Tx work that's never going
4364                          * to get done, so reset controller to flush Tx.
4365                          * (Do the reset outside of interrupt context).
4366                          */
4367                          schedule_work(&adapter->reset_task);
4368                 }
4369         }
4370
4371         ixgbe_update_stats(adapter);
4372         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4373 }
4374
4375 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4376                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4377                      u32 tx_flags, u8 *hdr_len)
4378 {
4379         struct ixgbe_adv_tx_context_desc *context_desc;
4380         unsigned int i;
4381         int err;
4382         struct ixgbe_tx_buffer *tx_buffer_info;
4383         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4384         u32 mss_l4len_idx, l4len;
4385
4386         if (skb_is_gso(skb)) {
4387                 if (skb_header_cloned(skb)) {
4388                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4389                         if (err)
4390                                 return err;
4391                 }
4392                 l4len = tcp_hdrlen(skb);
4393                 *hdr_len += l4len;
4394
4395                 if (skb->protocol == htons(ETH_P_IP)) {
4396                         struct iphdr *iph = ip_hdr(skb);
4397                         iph->tot_len = 0;
4398                         iph->check = 0;
4399                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4400                                                                  iph->daddr, 0,
4401                                                                  IPPROTO_TCP,
4402                                                                  0);
4403                         adapter->hw_tso_ctxt++;
4404                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4405                         ipv6_hdr(skb)->payload_len = 0;
4406                         tcp_hdr(skb)->check =
4407                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4408                                              &ipv6_hdr(skb)->daddr,
4409                                              0, IPPROTO_TCP, 0);
4410                         adapter->hw_tso6_ctxt++;
4411                 }
4412
4413                 i = tx_ring->next_to_use;
4414
4415                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4416                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4417
4418                 /* VLAN MACLEN IPLEN */
4419                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4420                         vlan_macip_lens |=
4421                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4422                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4423                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4424                 *hdr_len += skb_network_offset(skb);
4425                 vlan_macip_lens |=
4426                     (skb_transport_header(skb) - skb_network_header(skb));
4427                 *hdr_len +=
4428                     (skb_transport_header(skb) - skb_network_header(skb));
4429                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4430                 context_desc->seqnum_seed = 0;
4431
4432                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4433                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4434                                    IXGBE_ADVTXD_DTYP_CTXT);
4435
4436                 if (skb->protocol == htons(ETH_P_IP))
4437                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4438                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4439                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4440
4441                 /* MSS L4LEN IDX */
4442                 mss_l4len_idx =
4443                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4444                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4445                 /* use index 1 for TSO */
4446                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4447                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4448
4449                 tx_buffer_info->time_stamp = jiffies;
4450                 tx_buffer_info->next_to_watch = i;
4451
4452                 i++;
4453                 if (i == tx_ring->count)
4454                         i = 0;
4455                 tx_ring->next_to_use = i;
4456
4457                 return true;
4458         }
4459         return false;
4460 }
4461
4462 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4463                           struct ixgbe_ring *tx_ring,
4464                           struct sk_buff *skb, u32 tx_flags)
4465 {
4466         struct ixgbe_adv_tx_context_desc *context_desc;
4467         unsigned int i;
4468         struct ixgbe_tx_buffer *tx_buffer_info;
4469         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4470
4471         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4472             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4473                 i = tx_ring->next_to_use;
4474                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4475                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4476
4477                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4478                         vlan_macip_lens |=
4479                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4480                 vlan_macip_lens |= (skb_network_offset(skb) <<
4481                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4482                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4483                         vlan_macip_lens |= (skb_transport_header(skb) -
4484                                             skb_network_header(skb));
4485
4486                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4487                 context_desc->seqnum_seed = 0;
4488
4489                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4490                                     IXGBE_ADVTXD_DTYP_CTXT);
4491
4492                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4493                         switch (skb->protocol) {
4494                         case cpu_to_be16(ETH_P_IP):
4495                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4496                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4497                                         type_tucmd_mlhl |=
4498                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4499                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4500                                         type_tucmd_mlhl |=
4501                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4502                                 break;
4503                         case cpu_to_be16(ETH_P_IPV6):
4504                                 /* XXX what about other V6 headers?? */
4505                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4506                                         type_tucmd_mlhl |=
4507                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4508                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4509                                         type_tucmd_mlhl |=
4510                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4511                                 break;
4512                         default:
4513                                 if (unlikely(net_ratelimit())) {
4514                                         DPRINTK(PROBE, WARNING,
4515                                          "partial checksum but proto=%x!\n",
4516                                          skb->protocol);
4517                                 }
4518                                 break;
4519                         }
4520                 }
4521
4522                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4523                 /* use index zero for tx checksum offload */
4524                 context_desc->mss_l4len_idx = 0;
4525
4526                 tx_buffer_info->time_stamp = jiffies;
4527                 tx_buffer_info->next_to_watch = i;
4528
4529                 adapter->hw_csum_tx_good++;
4530                 i++;
4531                 if (i == tx_ring->count)
4532                         i = 0;
4533                 tx_ring->next_to_use = i;
4534
4535                 return true;
4536         }
4537
4538         return false;
4539 }
4540
4541 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4542                         struct ixgbe_ring *tx_ring,
4543                         struct sk_buff *skb, u32 tx_flags,
4544                         unsigned int first)
4545 {
4546         struct ixgbe_tx_buffer *tx_buffer_info;
4547         unsigned int len;
4548         unsigned int total = skb->len;
4549         unsigned int offset = 0, size, count = 0, i;
4550         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4551         unsigned int f;
4552         dma_addr_t *map;
4553
4554         i = tx_ring->next_to_use;
4555
4556         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4557                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4558                 return 0;
4559         }
4560
4561         map = skb_shinfo(skb)->dma_maps;
4562
4563         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4564                 /* excluding fcoe_crc_eof for FCoE */
4565                 total -= sizeof(struct fcoe_crc_eof);
4566
4567         len = min(skb_headlen(skb), total);
4568         while (len) {
4569                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4570                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4571
4572                 tx_buffer_info->length = size;
4573                 tx_buffer_info->dma = map[0] + offset;
4574                 tx_buffer_info->time_stamp = jiffies;
4575                 tx_buffer_info->next_to_watch = i;
4576
4577                 len -= size;
4578                 total -= size;
4579                 offset += size;
4580                 count++;
4581
4582                 if (len) {
4583                         i++;
4584                         if (i == tx_ring->count)
4585                                 i = 0;
4586                 }
4587         }
4588
4589         for (f = 0; f < nr_frags; f++) {
4590                 struct skb_frag_struct *frag;
4591
4592                 frag = &skb_shinfo(skb)->frags[f];
4593                 len = min((unsigned int)frag->size, total);
4594                 offset = 0;
4595
4596                 while (len) {
4597                         i++;
4598                         if (i == tx_ring->count)
4599                                 i = 0;
4600
4601                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4602                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4603
4604                         tx_buffer_info->length = size;
4605                         tx_buffer_info->dma = map[f + 1] + offset;
4606                         tx_buffer_info->time_stamp = jiffies;
4607                         tx_buffer_info->next_to_watch = i;
4608
4609                         len -= size;
4610                         total -= size;
4611                         offset += size;
4612                         count++;
4613                 }
4614                 if (total == 0)
4615                         break;
4616         }
4617
4618         tx_ring->tx_buffer_info[i].skb = skb;
4619         tx_ring->tx_buffer_info[first].next_to_watch = i;
4620
4621         return count;
4622 }
4623
4624 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4625                            struct ixgbe_ring *tx_ring,
4626                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4627 {
4628         union ixgbe_adv_tx_desc *tx_desc = NULL;
4629         struct ixgbe_tx_buffer *tx_buffer_info;
4630         u32 olinfo_status = 0, cmd_type_len = 0;
4631         unsigned int i;
4632         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4633
4634         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4635
4636         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4637
4638         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4639                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4640
4641         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4642                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4643
4644                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4645                                  IXGBE_ADVTXD_POPTS_SHIFT;
4646
4647                 /* use index 1 context for tso */
4648                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4649                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4650                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4651                                          IXGBE_ADVTXD_POPTS_SHIFT;
4652
4653         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4654                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4655                                  IXGBE_ADVTXD_POPTS_SHIFT;
4656
4657         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4658                 olinfo_status |= IXGBE_ADVTXD_CC;
4659                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4660                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4661                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4662         }
4663
4664         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4665
4666         i = tx_ring->next_to_use;
4667         while (count--) {
4668                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4669                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4670                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4671                 tx_desc->read.cmd_type_len =
4672                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4673                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4674                 i++;
4675                 if (i == tx_ring->count)
4676                         i = 0;
4677         }
4678
4679         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4680
4681         /*
4682          * Force memory writes to complete before letting h/w
4683          * know there are new descriptors to fetch.  (Only
4684          * applicable for weak-ordered memory model archs,
4685          * such as IA-64).
4686          */
4687         wmb();
4688
4689         tx_ring->next_to_use = i;
4690         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4691 }
4692
4693 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4694                                  struct ixgbe_ring *tx_ring, int size)
4695 {
4696         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4697
4698         netif_stop_subqueue(netdev, tx_ring->queue_index);
4699         /* Herbert's original patch had:
4700          *  smp_mb__after_netif_stop_queue();
4701          * but since that doesn't exist yet, just open code it. */
4702         smp_mb();
4703
4704         /* We need to check again in a case another CPU has just
4705          * made room available. */
4706         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4707                 return -EBUSY;
4708
4709         /* A reprieve! - use start_queue because it doesn't call schedule */
4710         netif_start_subqueue(netdev, tx_ring->queue_index);
4711         ++adapter->restart_queue;
4712         return 0;
4713 }
4714
4715 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4716                               struct ixgbe_ring *tx_ring, int size)
4717 {
4718         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4719                 return 0;
4720         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4721 }
4722
4723 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4724 {
4725         struct ixgbe_adapter *adapter = netdev_priv(dev);
4726
4727         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4728                 return 0;  /* All traffic should default to class 0 */
4729
4730         return skb_tx_hash(dev, skb);
4731 }
4732
4733 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4734 {
4735         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4736         struct ixgbe_ring *tx_ring;
4737         unsigned int first;
4738         unsigned int tx_flags = 0;
4739         u8 hdr_len = 0;
4740         int r_idx = 0, tso;
4741         int count = 0;
4742         unsigned int f;
4743
4744         r_idx = skb->queue_mapping;
4745         tx_ring = &adapter->tx_ring[r_idx];
4746
4747         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4748                 tx_flags |= vlan_tx_tag_get(skb);
4749                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4750                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4751                         tx_flags |= (skb->queue_mapping << 13);
4752                 }
4753                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4754                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4755         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4756                 tx_flags |= (skb->queue_mapping << 13);
4757                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4758                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4759         }
4760
4761         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4762             (skb->protocol == htons(ETH_P_FCOE)))
4763                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4764
4765         /* four things can cause us to need a context descriptor */
4766         if (skb_is_gso(skb) ||
4767             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4768             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4769             (tx_flags & IXGBE_TX_FLAGS_FCOE))
4770                 count++;
4771
4772         count += TXD_USE_COUNT(skb_headlen(skb));
4773         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4774                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4775
4776         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4777                 adapter->tx_busy++;
4778                 return NETDEV_TX_BUSY;
4779         }
4780
4781         first = tx_ring->next_to_use;
4782         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4783 #ifdef IXGBE_FCOE
4784                 /* setup tx offload for FCoE */
4785                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4786                 if (tso < 0) {
4787                         dev_kfree_skb_any(skb);
4788                         return NETDEV_TX_OK;
4789                 }
4790                 if (tso)
4791                         tx_flags |= IXGBE_TX_FLAGS_FSO;
4792 #endif /* IXGBE_FCOE */
4793         } else {
4794                 if (skb->protocol == htons(ETH_P_IP))
4795                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
4796                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4797                 if (tso < 0) {
4798                         dev_kfree_skb_any(skb);
4799                         return NETDEV_TX_OK;
4800                 }
4801
4802                 if (tso)
4803                         tx_flags |= IXGBE_TX_FLAGS_TSO;
4804                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4805                          (skb->ip_summed == CHECKSUM_PARTIAL))
4806                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
4807         }
4808
4809         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
4810         if (count) {
4811                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4812                                hdr_len);
4813                 netdev->trans_start = jiffies;
4814                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4815
4816         } else {
4817                 dev_kfree_skb_any(skb);
4818                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4819                 tx_ring->next_to_use = first;
4820         }
4821
4822         return NETDEV_TX_OK;
4823 }
4824
4825 /**
4826  * ixgbe_get_stats - Get System Network Statistics
4827  * @netdev: network interface device structure
4828  *
4829  * Returns the address of the device statistics structure.
4830  * The statistics are actually updated from the timer callback.
4831  **/
4832 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4833 {
4834         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4835
4836         /* only return the current stats */
4837         return &adapter->net_stats;
4838 }
4839
4840 /**
4841  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4842  * @netdev: network interface device structure
4843  * @p: pointer to an address structure
4844  *
4845  * Returns 0 on success, negative on failure
4846  **/
4847 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4848 {
4849         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4850         struct ixgbe_hw *hw = &adapter->hw;
4851         struct sockaddr *addr = p;
4852
4853         if (!is_valid_ether_addr(addr->sa_data))
4854                 return -EADDRNOTAVAIL;
4855
4856         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4857         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4858
4859         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4860
4861         return 0;
4862 }
4863
4864 static int
4865 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4866 {
4867         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4868         struct ixgbe_hw *hw = &adapter->hw;
4869         u16 value;
4870         int rc;
4871
4872         if (prtad != hw->phy.mdio.prtad)
4873                 return -EINVAL;
4874         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4875         if (!rc)
4876                 rc = value;
4877         return rc;
4878 }
4879
4880 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4881                             u16 addr, u16 value)
4882 {
4883         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4884         struct ixgbe_hw *hw = &adapter->hw;
4885
4886         if (prtad != hw->phy.mdio.prtad)
4887                 return -EINVAL;
4888         return hw->phy.ops.write_reg(hw, addr, devad, value);
4889 }
4890
4891 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4892 {
4893         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4894
4895         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4896 }
4897
4898 /**
4899  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4900  * netdev->dev_addr_list
4901  * @netdev: network interface device structure
4902  *
4903  * Returns non-zero on failure
4904  **/
4905 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4906 {
4907         int err = 0;
4908         struct ixgbe_adapter *adapter = netdev_priv(dev);
4909         struct ixgbe_mac_info *mac = &adapter->hw.mac;
4910
4911         if (is_valid_ether_addr(mac->san_addr)) {
4912                 rtnl_lock();
4913                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4914                 rtnl_unlock();
4915         }
4916         return err;
4917 }
4918
4919 /**
4920  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4921  * netdev->dev_addr_list
4922  * @netdev: network interface device structure
4923  *
4924  * Returns non-zero on failure
4925  **/
4926 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4927 {
4928         int err = 0;
4929         struct ixgbe_adapter *adapter = netdev_priv(dev);
4930         struct ixgbe_mac_info *mac = &adapter->hw.mac;
4931
4932         if (is_valid_ether_addr(mac->san_addr)) {
4933                 rtnl_lock();
4934                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4935                 rtnl_unlock();
4936         }
4937         return err;
4938 }
4939
4940 #ifdef CONFIG_NET_POLL_CONTROLLER
4941 /*
4942  * Polling 'interrupt' - used by things like netconsole to send skbs
4943  * without having to re-enable interrupts. It's not called while
4944  * the interrupt routine is executing.
4945  */
4946 static void ixgbe_netpoll(struct net_device *netdev)
4947 {
4948         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4949
4950         disable_irq(adapter->pdev->irq);
4951         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4952         ixgbe_intr(adapter->pdev->irq, netdev);
4953         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4954         enable_irq(adapter->pdev->irq);
4955 }
4956 #endif
4957
4958 static const struct net_device_ops ixgbe_netdev_ops = {
4959         .ndo_open               = ixgbe_open,
4960         .ndo_stop               = ixgbe_close,
4961         .ndo_start_xmit         = ixgbe_xmit_frame,
4962         .ndo_select_queue       = ixgbe_select_queue,
4963         .ndo_get_stats          = ixgbe_get_stats,
4964         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
4965         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4966         .ndo_validate_addr      = eth_validate_addr,
4967         .ndo_set_mac_address    = ixgbe_set_mac,
4968         .ndo_change_mtu         = ixgbe_change_mtu,
4969         .ndo_tx_timeout         = ixgbe_tx_timeout,
4970         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4971         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4972         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4973         .ndo_do_ioctl           = ixgbe_ioctl,
4974 #ifdef CONFIG_NET_POLL_CONTROLLER
4975         .ndo_poll_controller    = ixgbe_netpoll,
4976 #endif
4977 #ifdef IXGBE_FCOE
4978         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
4979         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
4980 #endif /* IXGBE_FCOE */
4981 };
4982
4983 /**
4984  * ixgbe_probe - Device Initialization Routine
4985  * @pdev: PCI device information struct
4986  * @ent: entry in ixgbe_pci_tbl
4987  *
4988  * Returns 0 on success, negative on failure
4989  *
4990  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4991  * The OS initialization, configuring of the adapter private structure,
4992  * and a hardware reset occur.
4993  **/
4994 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4995                                  const struct pci_device_id *ent)
4996 {
4997         struct net_device *netdev;
4998         struct ixgbe_adapter *adapter = NULL;
4999         struct ixgbe_hw *hw;
5000         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5001         static int cards_found;
5002         int i, err, pci_using_dac;
5003 #ifdef IXGBE_FCOE
5004         u16 device_caps;
5005 #endif
5006         u32 part_num, eec;
5007
5008         err = pci_enable_device_mem(pdev);
5009         if (err)
5010                 return err;
5011
5012         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5013             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5014                 pci_using_dac = 1;
5015         } else {
5016                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5017                 if (err) {
5018                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5019                         if (err) {
5020                                 dev_err(&pdev->dev, "No usable DMA "
5021                                         "configuration, aborting\n");
5022                                 goto err_dma;
5023                         }
5024                 }
5025                 pci_using_dac = 0;
5026         }
5027
5028         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5029                                            IORESOURCE_MEM), ixgbe_driver_name);
5030         if (err) {
5031                 dev_err(&pdev->dev,
5032                         "pci_request_selected_regions failed 0x%x\n", err);
5033                 goto err_pci_reg;
5034         }
5035
5036         err = pci_enable_pcie_error_reporting(pdev);
5037         if (err) {
5038                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5039                                     "0x%x\n", err);
5040                 /* non-fatal, continue */
5041         }
5042
5043         pci_set_master(pdev);
5044         pci_save_state(pdev);
5045
5046         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5047         if (!netdev) {
5048                 err = -ENOMEM;
5049                 goto err_alloc_etherdev;
5050         }
5051
5052         SET_NETDEV_DEV(netdev, &pdev->dev);
5053
5054         pci_set_drvdata(pdev, netdev);
5055         adapter = netdev_priv(netdev);
5056
5057         adapter->netdev = netdev;
5058         adapter->pdev = pdev;
5059         hw = &adapter->hw;
5060         hw->back = adapter;
5061         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5062
5063         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5064                               pci_resource_len(pdev, 0));
5065         if (!hw->hw_addr) {
5066                 err = -EIO;
5067                 goto err_ioremap;
5068         }
5069
5070         for (i = 1; i <= 5; i++) {
5071                 if (pci_resource_len(pdev, i) == 0)
5072                         continue;
5073         }
5074
5075         netdev->netdev_ops = &ixgbe_netdev_ops;
5076         ixgbe_set_ethtool_ops(netdev);
5077         netdev->watchdog_timeo = 5 * HZ;
5078         strcpy(netdev->name, pci_name(pdev));
5079
5080         adapter->bd_number = cards_found;
5081
5082         /* Setup hw api */
5083         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5084         hw->mac.type  = ii->mac;
5085
5086         /* EEPROM */
5087         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5088         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5089         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5090         if (!(eec & (1 << 8)))
5091                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5092
5093         /* PHY */
5094         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5095         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5096         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5097         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5098         hw->phy.mdio.mmds = 0;
5099         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5100         hw->phy.mdio.dev = netdev;
5101         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5102         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5103
5104         /* set up this timer and work struct before calling get_invariants
5105          * which might start the timer
5106          */
5107         init_timer(&adapter->sfp_timer);
5108         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5109         adapter->sfp_timer.data = (unsigned long) adapter;
5110
5111         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5112
5113         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5114         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5115
5116         /* a new SFP+ module arrival, called from GPI SDP2 context */
5117         INIT_WORK(&adapter->sfp_config_module_task,
5118                   ixgbe_sfp_config_module_task);
5119
5120         err = ii->get_invariants(hw);
5121         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5122                 /* start a kernel thread to watch for a module to arrive */
5123                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5124                 mod_timer(&adapter->sfp_timer,
5125                           round_jiffies(jiffies + (2 * HZ)));
5126                 err = 0;
5127         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5128                 DPRINTK(PROBE, ERR, "failed to load because an "
5129                         "unsupported SFP+ module type was detected.\n");
5130                 goto err_hw_init;
5131         } else if (err) {
5132                 goto err_hw_init;
5133         }
5134
5135         /* setup the private structure */
5136         err = ixgbe_sw_init(adapter);
5137         if (err)
5138                 goto err_sw_init;
5139
5140         /*
5141          * If there is a fan on this device and it has failed log the
5142          * failure.
5143          */
5144         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5145                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5146                 if (esdp & IXGBE_ESDP_SDP1)
5147                         DPRINTK(PROBE, CRIT,
5148                                 "Fan has stopped, replace the adapter\n");
5149         }
5150
5151         /* reset_hw fills in the perm_addr as well */
5152         err = hw->mac.ops.reset_hw(hw);
5153         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5154                 dev_err(&adapter->pdev->dev, "failed to load because an "
5155                         "unsupported SFP+ module type was detected.\n");
5156                 goto err_sw_init;
5157         } else if (err) {
5158                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5159                 goto err_sw_init;
5160         }
5161
5162         netdev->features = NETIF_F_SG |
5163                            NETIF_F_IP_CSUM |
5164                            NETIF_F_HW_VLAN_TX |
5165                            NETIF_F_HW_VLAN_RX |
5166                            NETIF_F_HW_VLAN_FILTER;
5167
5168         netdev->features |= NETIF_F_IPV6_CSUM;
5169         netdev->features |= NETIF_F_TSO;
5170         netdev->features |= NETIF_F_TSO6;
5171         netdev->features |= NETIF_F_GRO;
5172
5173         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5174                 netdev->features |= NETIF_F_SCTP_CSUM;
5175
5176         netdev->vlan_features |= NETIF_F_TSO;
5177         netdev->vlan_features |= NETIF_F_TSO6;
5178         netdev->vlan_features |= NETIF_F_IP_CSUM;
5179         netdev->vlan_features |= NETIF_F_SG;
5180
5181         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5182                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5183
5184 #ifdef CONFIG_IXGBE_DCB
5185         netdev->dcbnl_ops = &dcbnl_ops;
5186 #endif
5187
5188 #ifdef IXGBE_FCOE
5189         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5190                 if (hw->mac.ops.get_device_caps) {
5191                         hw->mac.ops.get_device_caps(hw, &device_caps);
5192                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5193                                 netdev->features |= NETIF_F_FCOE_CRC;
5194                                 netdev->features |= NETIF_F_FSO;
5195                                 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5196                         } else {
5197                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5198                         }
5199                 }
5200         }
5201 #endif /* IXGBE_FCOE */
5202         if (pci_using_dac)
5203                 netdev->features |= NETIF_F_HIGHDMA;
5204
5205         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5206                 netdev->features |= NETIF_F_LRO;
5207
5208         /* make sure the EEPROM is good */
5209         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5210                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5211                 err = -EIO;
5212                 goto err_eeprom;
5213         }
5214
5215         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5216         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5217
5218         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5219                 dev_err(&pdev->dev, "invalid MAC address\n");
5220                 err = -EIO;
5221                 goto err_eeprom;
5222         }
5223
5224         init_timer(&adapter->watchdog_timer);
5225         adapter->watchdog_timer.function = &ixgbe_watchdog;
5226         adapter->watchdog_timer.data = (unsigned long)adapter;
5227
5228         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5229         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5230
5231         err = ixgbe_init_interrupt_scheme(adapter);
5232         if (err)
5233                 goto err_sw_init;
5234
5235         switch (pdev->device) {
5236         case IXGBE_DEV_ID_82599_KX4:
5237                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5238                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5239                 break;
5240         default:
5241                 adapter->wol = 0;
5242                 break;
5243         }
5244         device_init_wakeup(&adapter->pdev->dev, true);
5245         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5246
5247         /* pick up the PCI bus settings for reporting later */
5248         hw->mac.ops.get_bus_info(hw);
5249
5250         /* print bus type/speed/width info */
5251         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5252                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5253                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5254                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5255                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5256                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5257                  "Unknown"),
5258                 netdev->dev_addr);
5259         ixgbe_read_pba_num_generic(hw, &part_num);
5260         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5261                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5262                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5263                          (part_num >> 8), (part_num & 0xff));
5264         else
5265                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5266                          hw->mac.type, hw->phy.type,
5267                          (part_num >> 8), (part_num & 0xff));
5268
5269         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5270                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5271                          "this card is not sufficient for optimal "
5272                          "performance.\n");
5273                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5274                          "PCI-Express slot is required.\n");
5275         }
5276
5277         /* save off EEPROM version number */
5278         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5279
5280         /* reset the hardware with the new settings */
5281         hw->mac.ops.start_hw(hw);
5282
5283         strcpy(netdev->name, "eth%d");
5284         err = register_netdev(netdev);
5285         if (err)
5286                 goto err_register;
5287
5288         /* carrier off reporting is important to ethtool even BEFORE open */
5289         netif_carrier_off(netdev);
5290
5291 #ifdef CONFIG_IXGBE_DCA
5292         if (dca_add_requester(&pdev->dev) == 0) {
5293                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5294                 /* always use CB2 mode, difference is masked
5295                  * in the CB driver */
5296                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5297                 ixgbe_setup_dca(adapter);
5298         }
5299 #endif
5300         /* add san mac addr to netdev */
5301         ixgbe_add_sanmac_netdev(netdev);
5302
5303         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5304         cards_found++;
5305         return 0;
5306
5307 err_register:
5308         ixgbe_release_hw_control(adapter);
5309 err_hw_init:
5310         ixgbe_clear_interrupt_scheme(adapter);
5311 err_sw_init:
5312 err_eeprom:
5313         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5314         del_timer_sync(&adapter->sfp_timer);
5315         cancel_work_sync(&adapter->sfp_task);
5316         cancel_work_sync(&adapter->multispeed_fiber_task);
5317         cancel_work_sync(&adapter->sfp_config_module_task);
5318         iounmap(hw->hw_addr);
5319 err_ioremap:
5320         free_netdev(netdev);
5321 err_alloc_etherdev:
5322         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5323                                      IORESOURCE_MEM));
5324 err_pci_reg:
5325 err_dma:
5326         pci_disable_device(pdev);
5327         return err;
5328 }
5329
5330 /**
5331  * ixgbe_remove - Device Removal Routine
5332  * @pdev: PCI device information struct
5333  *
5334  * ixgbe_remove is called by the PCI subsystem to alert the driver
5335  * that it should release a PCI device.  The could be caused by a
5336  * Hot-Plug event, or because the driver is going to be removed from
5337  * memory.
5338  **/
5339 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5340 {
5341         struct net_device *netdev = pci_get_drvdata(pdev);
5342         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5343         int err;
5344
5345         set_bit(__IXGBE_DOWN, &adapter->state);
5346         /* clear the module not found bit to make sure the worker won't
5347          * reschedule
5348          */
5349         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5350         del_timer_sync(&adapter->watchdog_timer);
5351
5352         del_timer_sync(&adapter->sfp_timer);
5353         cancel_work_sync(&adapter->watchdog_task);
5354         cancel_work_sync(&adapter->sfp_task);
5355         cancel_work_sync(&adapter->multispeed_fiber_task);
5356         cancel_work_sync(&adapter->sfp_config_module_task);
5357         flush_scheduled_work();
5358
5359 #ifdef CONFIG_IXGBE_DCA
5360         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5361                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5362                 dca_remove_requester(&pdev->dev);
5363                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5364         }
5365
5366 #endif
5367 #ifdef IXGBE_FCOE
5368         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5369                 ixgbe_cleanup_fcoe(adapter);
5370
5371 #endif /* IXGBE_FCOE */
5372
5373         /* remove the added san mac */
5374         ixgbe_del_sanmac_netdev(netdev);
5375
5376         if (netdev->reg_state == NETREG_REGISTERED)
5377                 unregister_netdev(netdev);
5378
5379         ixgbe_clear_interrupt_scheme(adapter);
5380
5381         ixgbe_release_hw_control(adapter);
5382
5383         iounmap(adapter->hw.hw_addr);
5384         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5385                                      IORESOURCE_MEM));
5386
5387         DPRINTK(PROBE, INFO, "complete\n");
5388
5389         free_netdev(netdev);
5390
5391         err = pci_disable_pcie_error_reporting(pdev);
5392         if (err)
5393                 dev_err(&pdev->dev,
5394                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5395
5396         pci_disable_device(pdev);
5397 }
5398
5399 /**
5400  * ixgbe_io_error_detected - called when PCI error is detected
5401  * @pdev: Pointer to PCI device
5402  * @state: The current pci connection state
5403  *
5404  * This function is called after a PCI bus error affecting
5405  * this device has been detected.
5406  */
5407 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5408                                                 pci_channel_state_t state)
5409 {
5410         struct net_device *netdev = pci_get_drvdata(pdev);
5411         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5412
5413         netif_device_detach(netdev);
5414
5415         if (state == pci_channel_io_perm_failure)
5416                 return PCI_ERS_RESULT_DISCONNECT;
5417
5418         if (netif_running(netdev))
5419                 ixgbe_down(adapter);
5420         pci_disable_device(pdev);
5421
5422         /* Request a slot reset. */
5423         return PCI_ERS_RESULT_NEED_RESET;
5424 }
5425
5426 /**
5427  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5428  * @pdev: Pointer to PCI device
5429  *
5430  * Restart the card from scratch, as if from a cold-boot.
5431  */
5432 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5433 {
5434         struct net_device *netdev = pci_get_drvdata(pdev);
5435         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5436         pci_ers_result_t result;
5437         int err;
5438
5439         if (pci_enable_device_mem(pdev)) {
5440                 DPRINTK(PROBE, ERR,
5441                         "Cannot re-enable PCI device after reset.\n");
5442                 result = PCI_ERS_RESULT_DISCONNECT;
5443         } else {
5444                 pci_set_master(pdev);
5445                 pci_restore_state(pdev);
5446
5447                 pci_wake_from_d3(pdev, false);
5448
5449                 ixgbe_reset(adapter);
5450                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5451                 result = PCI_ERS_RESULT_RECOVERED;
5452         }
5453
5454         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5455         if (err) {
5456                 dev_err(&pdev->dev,
5457                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5458                 /* non-fatal, continue */
5459         }
5460
5461         return result;
5462 }
5463
5464 /**
5465  * ixgbe_io_resume - called when traffic can start flowing again.
5466  * @pdev: Pointer to PCI device
5467  *
5468  * This callback is called when the error recovery driver tells us that
5469  * its OK to resume normal operation.
5470  */
5471 static void ixgbe_io_resume(struct pci_dev *pdev)
5472 {
5473         struct net_device *netdev = pci_get_drvdata(pdev);
5474         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5475
5476         if (netif_running(netdev)) {
5477                 if (ixgbe_up(adapter)) {
5478                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5479                         return;
5480                 }
5481         }
5482
5483         netif_device_attach(netdev);
5484 }
5485
5486 static struct pci_error_handlers ixgbe_err_handler = {
5487         .error_detected = ixgbe_io_error_detected,
5488         .slot_reset = ixgbe_io_slot_reset,
5489         .resume = ixgbe_io_resume,
5490 };
5491
5492 static struct pci_driver ixgbe_driver = {
5493         .name     = ixgbe_driver_name,
5494         .id_table = ixgbe_pci_tbl,
5495         .probe    = ixgbe_probe,
5496         .remove   = __devexit_p(ixgbe_remove),
5497 #ifdef CONFIG_PM
5498         .suspend  = ixgbe_suspend,
5499         .resume   = ixgbe_resume,
5500 #endif
5501         .shutdown = ixgbe_shutdown,
5502         .err_handler = &ixgbe_err_handler
5503 };
5504
5505 /**
5506  * ixgbe_init_module - Driver Registration Routine
5507  *
5508  * ixgbe_init_module is the first routine called when the driver is
5509  * loaded. All it does is register with the PCI subsystem.
5510  **/
5511 static int __init ixgbe_init_module(void)
5512 {
5513         int ret;
5514         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5515                ixgbe_driver_string, ixgbe_driver_version);
5516
5517         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5518
5519 #ifdef CONFIG_IXGBE_DCA
5520         dca_register_notify(&dca_notifier);
5521 #endif
5522
5523         ret = pci_register_driver(&ixgbe_driver);
5524         return ret;
5525 }
5526
5527 module_init(ixgbe_init_module);
5528
5529 /**
5530  * ixgbe_exit_module - Driver Exit Cleanup Routine
5531  *
5532  * ixgbe_exit_module is called just before the driver is removed
5533  * from memory.
5534  **/
5535 static void __exit ixgbe_exit_module(void)
5536 {
5537 #ifdef CONFIG_IXGBE_DCA
5538         dca_unregister_notify(&dca_notifier);
5539 #endif
5540         pci_unregister_driver(&ixgbe_driver);
5541 }
5542
5543 #ifdef CONFIG_IXGBE_DCA
5544 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5545                             void *p)
5546 {
5547         int ret_val;
5548
5549         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5550                                          __ixgbe_notify_dca);
5551
5552         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5553 }
5554
5555 #endif /* CONFIG_IXGBE_DCA */
5556 #ifdef DEBUG
5557 /**
5558  * ixgbe_get_hw_dev_name - return device name string
5559  * used by hardware layer to print debugging information
5560  **/
5561 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5562 {
5563         struct ixgbe_adapter *adapter = hw->back;
5564         return adapter->netdev->name;
5565 }
5566
5567 #endif
5568 module_exit(ixgbe_exit_module);
5569
5570 /* ixgbe_main.c */