drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "3.0.12-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62         [board_X540] = &ixgbe_X540_info,
  63 };
  64
  65 /* ixgbe_pci_tbl - PCI Device ID Table
  66  *
  67  * Wildcard entries (PCI_ANY_ID) should come last
  68  * Last entry must be all 0s
  69  *
  70  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  71  *   Class, Class Mask, private data (not used) }
  72  */
  73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 101          board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 103          board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 105          board_82599 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 121          board_82599 },
 122
 123         /* required last entry */
 124         {0, }
 125 };
 126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 127
 128 #ifdef CONFIG_IXGBE_DCA
 129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 130                             void *p);
 131 static struct notifier_block dca_notifier = {
 132         .notifier_call = ixgbe_notify_dca,
 133         .next          = NULL,
 134         .priority      = 0
 135 };
 136 #endif
 137
 138 #ifdef CONFIG_PCI_IOV
 139 static unsigned int max_vfs;
 140 module_param(max_vfs, uint, 0);
 141 MODULE_PARM_DESC(max_vfs,
 142                  "Maximum number of virtual functions to allocate per physical function");
 143 #endif /* CONFIG_PCI_IOV */
 144
 145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 147 MODULE_LICENSE("GPL");
 148 MODULE_VERSION(DRV_VERSION);
 149
 150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 151
 152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 153 {
 154         struct ixgbe_hw *hw = &adapter->hw;
 155         u32 gcr;
 156         u32 gpie;
 157         u32 vmdctl;
 158
 159 #ifdef CONFIG_PCI_IOV
 160         /* disable iov and allow time for transactions to clear */
 161         pci_disable_sriov(adapter->pdev);
 162 #endif
 163
 164         /* turn off device IOV mode */
 165         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 166         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 167         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 168         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 169         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 170         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 171
 172         /* set default pool back to 0 */
 173         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 174         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 175         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 176
 177         /* take a breather then clean up driver data */
 178         msleep(100);
 179
 180         kfree(adapter->vfinfo);
 181         adapter->vfinfo = NULL;
 182
 183         adapter->num_vfs = 0;
 184         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 185 }
 186
 187 struct ixgbe_reg_info {
 188         u32 ofs;
 189         char *name;
 190 };
 191
 192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 193
 194         /* General Registers */
 195         {IXGBE_CTRL, "CTRL"},
 196         {IXGBE_STATUS, "STATUS"},
 197         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 198
 199         /* Interrupt Registers */
 200         {IXGBE_EICR, "EICR"},
 201
 202         /* RX Registers */
 203         {IXGBE_SRRCTL(0), "SRRCTL"},
 204         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 205         {IXGBE_RDLEN(0), "RDLEN"},
 206         {IXGBE_RDH(0), "RDH"},
 207         {IXGBE_RDT(0), "RDT"},
 208         {IXGBE_RXDCTL(0), "RXDCTL"},
 209         {IXGBE_RDBAL(0), "RDBAL"},
 210         {IXGBE_RDBAH(0), "RDBAH"},
 211
 212         /* TX Registers */
 213         {IXGBE_TDBAL(0), "TDBAL"},
 214         {IXGBE_TDBAH(0), "TDBAH"},
 215         {IXGBE_TDLEN(0), "TDLEN"},
 216         {IXGBE_TDH(0), "TDH"},
 217         {IXGBE_TDT(0), "TDT"},
 218         {IXGBE_TXDCTL(0), "TXDCTL"},
 219
 220         /* List Terminator */
 221         {}
 222 };
 223
 224
 225 /*
 226  * ixgbe_regdump - register printout routine
 227  */
 228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 229 {
 230         int i = 0, j = 0;
 231         char rname[16];
 232         u32 regs[64];
 233
 234         switch (reginfo->ofs) {
 235         case IXGBE_SRRCTL(0):
 236                 for (i = 0; i < 64; i++)
 237                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 238                 break;
 239         case IXGBE_DCA_RXCTRL(0):
 240                 for (i = 0; i < 64; i++)
 241                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 242                 break;
 243         case IXGBE_RDLEN(0):
 244                 for (i = 0; i < 64; i++)
 245                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 246                 break;
 247         case IXGBE_RDH(0):
 248                 for (i = 0; i < 64; i++)
 249                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 250                 break;
 251         case IXGBE_RDT(0):
 252                 for (i = 0; i < 64; i++)
 253                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 254                 break;
 255         case IXGBE_RXDCTL(0):
 256                 for (i = 0; i < 64; i++)
 257                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 258                 break;
 259         case IXGBE_RDBAL(0):
 260                 for (i = 0; i < 64; i++)
 261                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 262                 break;
 263         case IXGBE_RDBAH(0):
 264                 for (i = 0; i < 64; i++)
 265                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 266                 break;
 267         case IXGBE_TDBAL(0):
 268                 for (i = 0; i < 64; i++)
 269                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 270                 break;
 271         case IXGBE_TDBAH(0):
 272                 for (i = 0; i < 64; i++)
 273                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 274                 break;
 275         case IXGBE_TDLEN(0):
 276                 for (i = 0; i < 64; i++)
 277                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 278                 break;
 279         case IXGBE_TDH(0):
 280                 for (i = 0; i < 64; i++)
 281                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 282                 break;
 283         case IXGBE_TDT(0):
 284                 for (i = 0; i < 64; i++)
 285                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 286                 break;
 287         case IXGBE_TXDCTL(0):
 288                 for (i = 0; i < 64; i++)
 289                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 290                 break;
 291         default:
 292                 pr_info("%-15s %08x\n", reginfo->name,
 293                         IXGBE_READ_REG(hw, reginfo->ofs));
 294                 return;
 295         }
 296
 297         for (i = 0; i < 8; i++) {
 298                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 299                 pr_err("%-15s", rname);
 300                 for (j = 0; j < 8; j++)
 301                         pr_cont(" %08x", regs[i*8+j]);
 302                 pr_cont("\n");
 303         }
 304
 305 }
 306
 307 /*
 308  * ixgbe_dump - Print registers, tx-rings and rx-rings
 309  */
 310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 311 {
 312         struct net_device *netdev = adapter->netdev;
 313         struct ixgbe_hw *hw = &adapter->hw;
 314         struct ixgbe_reg_info *reginfo;
 315         int n = 0;
 316         struct ixgbe_ring *tx_ring;
 317         struct ixgbe_tx_buffer *tx_buffer_info;
 318         union ixgbe_adv_tx_desc *tx_desc;
 319         struct my_u0 { u64 a; u64 b; } *u0;
 320         struct ixgbe_ring *rx_ring;
 321         union ixgbe_adv_rx_desc *rx_desc;
 322         struct ixgbe_rx_buffer *rx_buffer_info;
 323         u32 staterr;
 324         int i = 0;
 325
 326         if (!netif_msg_hw(adapter))
 327                 return;
 328
 329         /* Print netdevice Info */
 330         if (netdev) {
 331                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 332                 pr_info("Device Name     state            "
 333                         "trans_start      last_rx\n");
 334                 pr_info("%-15s %016lX %016lX %016lX\n",
 335                         netdev->name,
 336                         netdev->state,
 337                         netdev->trans_start,
 338                         netdev->last_rx);
 339         }
 340
 341         /* Print Registers */
 342         dev_info(&adapter->pdev->dev, "Register Dump\n");
 343         pr_info(" Register Name   Value\n");
 344         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 345              reginfo->name; reginfo++) {
 346                 ixgbe_regdump(hw, reginfo);
 347         }
 348
 349         /* Print TX Ring Summary */
 350         if (!netdev || !netif_running(netdev))
 351                 goto exit;
 352
 353         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 354         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 355         for (n = 0; n < adapter->num_tx_queues; n++) {
 356                 tx_ring = adapter->tx_ring[n];
 357                 tx_buffer_info =
 358                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 359                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 360                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 361                            (u64)tx_buffer_info->dma,
 362                            tx_buffer_info->length,
 363                            tx_buffer_info->next_to_watch,
 364                            (u64)tx_buffer_info->time_stamp);
 365         }
 366
 367         /* Print TX Rings */
 368         if (!netif_msg_tx_done(adapter))
 369                 goto rx_ring_summary;
 370
 371         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 372
 373         /* Transmit Descriptor Formats
 374          *
 375          * Advanced Transmit Descriptor
 376          *   +--------------------------------------------------------------+
 377          * 0 |         Buffer Address [63:0]                                |
 378          *   +--------------------------------------------------------------+
 379          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 380          *   +--------------------------------------------------------------+
 381          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 382          */
 383
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 pr_info("------------------------------------\n");
 387                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 388                 pr_info("------------------------------------\n");
 389                 pr_info("T [desc]     [address 63:0  ] "
 390                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 391                         "leng  ntw timestamp        bi->skb\n");
 392
 393                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 394                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 395                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 396                         u0 = (struct my_u0 *)tx_desc;
 397                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 398                                 " %04X  %3X %016llX %p", i,
 399                                 le64_to_cpu(u0->a),
 400                                 le64_to_cpu(u0->b),
 401                                 (u64)tx_buffer_info->dma,
 402                                 tx_buffer_info->length,
 403                                 tx_buffer_info->next_to_watch,
 404                                 (u64)tx_buffer_info->time_stamp,
 405                                 tx_buffer_info->skb);
 406                         if (i == tx_ring->next_to_use &&
 407                                 i == tx_ring->next_to_clean)
 408                                 pr_cont(" NTC/U\n");
 409                         else if (i == tx_ring->next_to_use)
 410                                 pr_cont(" NTU\n");
 411                         else if (i == tx_ring->next_to_clean)
 412                                 pr_cont(" NTC\n");
 413                         else
 414                                 pr_cont("\n");
 415
 416                         if (netif_msg_pktdata(adapter) &&
 417                                 tx_buffer_info->dma != 0)
 418                                 print_hex_dump(KERN_INFO, "",
 419                                         DUMP_PREFIX_ADDRESS, 16, 1,
 420                                         phys_to_virt(tx_buffer_info->dma),
 421                                         tx_buffer_info->length, true);
 422                 }
 423         }
 424
 425         /* Print RX Rings Summary */
 426 rx_ring_summary:
 427         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 428         pr_info("Queue [NTU] [NTC]\n");
 429         for (n = 0; n < adapter->num_rx_queues; n++) {
 430                 rx_ring = adapter->rx_ring[n];
 431                 pr_info("%5d %5X %5X\n",
 432                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 433         }
 434
 435         /* Print RX Rings */
 436         if (!netif_msg_rx_status(adapter))
 437                 goto exit;
 438
 439         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 440
 441         /* Advanced Receive Descriptor (Read) Format
 442          *    63                                           1        0
 443          *    +-----------------------------------------------------+
 444          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 445          *    +----------------------------------------------+------+
 446          *  8 |       Header Buffer Address [63:1]           |  DD  |
 447          *    +-----------------------------------------------------+
 448          *
 449          *
 450          * Advanced Receive Descriptor (Write-Back) Format
 451          *
 452          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 453          *   +------------------------------------------------------+
 454          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 455          *   | Checksum   Ident  |   |           |    | Type | Type |
 456          *   +------------------------------------------------------+
 457          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 458          *   +------------------------------------------------------+
 459          *   63       48 47    32 31            20 19               0
 460          */
 461         for (n = 0; n < adapter->num_rx_queues; n++) {
 462                 rx_ring = adapter->rx_ring[n];
 463                 pr_info("------------------------------------\n");
 464                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 465                 pr_info("------------------------------------\n");
 466                 pr_info("R  [desc]      [ PktBuf     A0] "
 467                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 468                         "<-- Adv Rx Read format\n");
 469                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 470                         "[vl er S cks ln] ---------------- [bi->skb] "
 471                         "<-- Adv Rx Write-Back format\n");
 472
 473                 for (i = 0; i < rx_ring->count; i++) {
 474                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 475                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 476                         u0 = (struct my_u0 *)rx_desc;
 477                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 478                         if (staterr & IXGBE_RXD_STAT_DD) {
 479                                 /* Descriptor Done */
 480                                 pr_info("RWB[0x%03X]     %016llX "
 481                                         "%016llX ---------------- %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         rx_buffer_info->skb);
 485                         } else {
 486                                 pr_info("R  [0x%03X]     %016llX "
 487                                         "%016llX %016llX %p", i,
 488                                         le64_to_cpu(u0->a),
 489                                         le64_to_cpu(u0->b),
 490                                         (u64)rx_buffer_info->dma,
 491                                         rx_buffer_info->skb);
 492
 493                                 if (netif_msg_pktdata(adapter)) {
 494                                         print_hex_dump(KERN_INFO, "",
 495                                            DUMP_PREFIX_ADDRESS, 16, 1,
 496                                            phys_to_virt(rx_buffer_info->dma),
 497                                            rx_ring->rx_buf_len, true);
 498
 499                                         if (rx_ring->rx_buf_len
 500                                                 < IXGBE_RXBUFFER_2048)
 501                                                 print_hex_dump(KERN_INFO, "",
 502                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 503                                                   phys_to_virt(
 504                                                     rx_buffer_info->page_dma +
 505                                                     rx_buffer_info->page_offset
 506                                                   ),
 507                                                   PAGE_SIZE/2, true);
 508                                 }
 509                         }
 510
 511                         if (i == rx_ring->next_to_use)
 512                                 pr_cont(" NTU\n");
 513                         else if (i == rx_ring->next_to_clean)
 514                                 pr_cont(" NTC\n");
 515                         else
 516                                 pr_cont("\n");
 517
 518                 }
 519         }
 520
 521 exit:
 522         return;
 523 }
 524
 525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 526 {
 527         u32 ctrl_ext;
 528
 529         /* Let firmware take over control of h/w */
 530         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 532                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 533 }
 534
 535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 536 {
 537         u32 ctrl_ext;
 538
 539         /* Let firmware know the driver has taken over */
 540         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 541         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 542                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 543 }
 544
 545 /*
 546  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 547  * @adapter: pointer to adapter struct
 548  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 549  * @queue: queue to map the corresponding interrupt to
 550  * @msix_vector: the vector to map to the corresponding queue
 551  *
 552  */
 553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 554                            u8 queue, u8 msix_vector)
 555 {
 556         u32 ivar, index;
 557         struct ixgbe_hw *hw = &adapter->hw;
 558         switch (hw->mac.type) {
 559         case ixgbe_mac_82598EB:
 560                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 561                 if (direction == -1)
 562                         direction = 0;
 563                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 564                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 565                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 566                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 567                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 568                 break;
 569         case ixgbe_mac_82599EB:
 570         case ixgbe_mac_X540:
 571                 if (direction == -1) {
 572                         /* other causes */
 573                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 574                         index = ((queue & 1) * 8);
 575                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 576                         ivar &= ~(0xFF << index);
 577                         ivar |= (msix_vector << index);
 578                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 579                         break;
 580                 } else {
 581                         /* tx or rx causes */
 582                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 583                         index = ((16 * (queue & 1)) + (8 * direction));
 584                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 585                         ivar &= ~(0xFF << index);
 586                         ivar |= (msix_vector << index);
 587                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 588                         break;
 589                 }
 590         default:
 591                 break;
 592         }
 593 }
 594
 595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 596                                           u64 qmask)
 597 {
 598         u32 mask;
 599
 600         switch (adapter->hw.mac.type) {
 601         case ixgbe_mac_82598EB:
 602                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 603                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 604                 break;
 605         case ixgbe_mac_82599EB:
 606         case ixgbe_mac_X540:
 607                 mask = (qmask & 0xFFFFFFFF);
 608                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 609                 mask = (qmask >> 32);
 610                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 611                 break;
 612         default:
 613                 break;
 614         }
 615 }
 616
 617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 618                                       struct ixgbe_tx_buffer *tx_buffer_info)
 619 {
 620         if (tx_buffer_info->dma) {
 621                 if (tx_buffer_info->mapped_as_page)
 622                         dma_unmap_page(tx_ring->dev,
 623                                        tx_buffer_info->dma,
 624                                        tx_buffer_info->length,
 625                                        DMA_TO_DEVICE);
 626                 else
 627                         dma_unmap_single(tx_ring->dev,
 628                                          tx_buffer_info->dma,
 629                                          tx_buffer_info->length,
 630                                          DMA_TO_DEVICE);
 631                 tx_buffer_info->dma = 0;
 632         }
 633         if (tx_buffer_info->skb) {
 634                 dev_kfree_skb_any(tx_buffer_info->skb);
 635                 tx_buffer_info->skb = NULL;
 636         }
 637         tx_buffer_info->time_stamp = 0;
 638         /* tx_buffer_info must be completely set up in the transmit path */
 639 }
 640
 641 /**
 642  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 643  * @adapter: driver private struct
 644  * @index: reg idx of queue to query (0-127)
 645  *
 646  * Helper function to determine the traffic index for a paticular
 647  * register index.
 648  *
 649  * Returns : a tc index for use in range 0-7, or 0-3
 650  */
 651 u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 652 {
 653         int tc = -1;
 654         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 655
 656         /* if DCB is not enabled the queues have no TC */
 657         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 658                 return tc;
 659
 660         /* check valid range */
 661         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 662                 return tc;
 663
 664         switch (adapter->hw.mac.type) {
 665         case ixgbe_mac_82598EB:
 666                 tc = reg_idx >> 2;
 667                 break;
 668         default:
 669                 if (dcb_i != 4 && dcb_i != 8)
 670                         break;
 671
 672                 /* if VMDq is enabled the lowest order bits determine TC */
 673                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 674                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 675                         tc = reg_idx & (dcb_i - 1);
 676                         break;
 677                 }
 678
 679                 /*
 680                  * Convert the reg_idx into the correct TC. This bitmask
 681                  * targets the last full 32 ring traffic class and assigns
 682                  * it a value of 1. From there the rest of the rings are
 683                  * based on shifting the mask further up to include the
 684                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 685                  * will only ever be 8 or 4 and that reg_idx will never
 686                  * be greater then 128. The code without the power of 2
 687                  * optimizations would be:
 688                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 689                  */
 690                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 691                 tc >>= 9 - (reg_idx >> 5);
 692         }
 693
 694         return tc;
 695 }
 696
 697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 698 {
 699         struct ixgbe_hw *hw = &adapter->hw;
 700         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 701         u32 data = 0;
 702         u32 xoff[8] = {0};
 703         int i;
 704
 705         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 706             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 707                 switch (hw->mac.type) {
 708                 case ixgbe_mac_82598EB:
 709                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 710                         break;
 711                 default:
 712                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 713                 }
 714                 hwstats->lxoffrxc += data;
 715
 716                 /* refill credits (no tx hang) if we received xoff */
 717                 if (!data)
 718                         return;
 719
 720                 for (i = 0; i < adapter->num_tx_queues; i++)
 721                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 722                                   &adapter->tx_ring[i]->state);
 723                 return;
 724         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 725                 return;
 726
 727         /* update stats for each tc, only valid with PFC enabled */
 728         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 729                 switch (hw->mac.type) {
 730                 case ixgbe_mac_82598EB:
 731                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 732                         break;
 733                 default:
 734                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 735                 }
 736                 hwstats->pxoffrxc[i] += xoff[i];
 737         }
 738
 739         /* disarm tx queues that have received xoff frames */
 740         for (i = 0; i < adapter->num_tx_queues; i++) {
 741                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 742                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 743
 744                 if (xoff[tc])
 745                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 746         }
 747 }
 748
 749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 750 {
 751         return ring->tx_stats.completed;
 752 }
 753
 754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 755 {
 756         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 757         struct ixgbe_hw *hw = &adapter->hw;
 758
 759         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 760         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 761
 762         if (head != tail)
 763                 return (head < tail) ?
 764                         tail - head : (tail + ring->count - head);
 765
 766         return 0;
 767 }
 768
 769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 770 {
 771         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 772         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 773         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 774         bool ret = false;
 775
 776         clear_check_for_tx_hang(tx_ring);
 777
 778         /*
 779          * Check for a hung queue, but be thorough. This verifies
 780          * that a transmit has been completed since the previous
 781          * check AND there is at least one packet pending. The
 782          * ARMED bit is set to indicate a potential hang. The
 783          * bit is cleared if a pause frame is received to remove
 784          * false hang detection due to PFC or 802.3x frames. By
 785          * requiring this to fail twice we avoid races with
 786          * pfc clearing the ARMED bit and conditions where we
 787          * run the check_tx_hang logic with a transmit completion
 788          * pending but without time to complete it yet.
 789          */
 790         if ((tx_done_old == tx_done) && tx_pending) {
 791                 /* make sure it is true for two checks in a row */
 792                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 793                                        &tx_ring->state);
 794         } else {
 795                 /* update completed stats and continue */
 796                 tx_ring->tx_stats.tx_done_old = tx_done;
 797                 /* reset the countdown */
 798                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 799         }
 800
 801         return ret;
 802 }
 803
 804 #define IXGBE_MAX_TXD_PWR       14
 805 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 806
 807 /* Tx Descriptors needed, worst case */
 808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 809                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 811         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 812
 813 static void ixgbe_tx_timeout(struct net_device *netdev);
 814
 815 /**
 816  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 817  * @q_vector: structure containing interrupt and ring information
 818  * @tx_ring: tx ring to clean
 819  **/
 820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 821                                struct ixgbe_ring *tx_ring)
 822 {
 823         struct ixgbe_adapter *adapter = q_vector->adapter;
 824         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 825         struct ixgbe_tx_buffer *tx_buffer_info;
 826         unsigned int total_bytes = 0, total_packets = 0;
 827         u16 i, eop, count = 0;
 828
 829         i = tx_ring->next_to_clean;
 830         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 831         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 832
 833         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 834                (count < tx_ring->work_limit)) {
 835                 bool cleaned = false;
 836                 rmb(); /* read buffer_info after eop_desc */
 837                 for ( ; !cleaned; count++) {
 838                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 839                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 840
 841                         tx_desc->wb.status = 0;
 842                         cleaned = (i == eop);
 843
 844                         i++;
 845                         if (i == tx_ring->count)
 846                                 i = 0;
 847
 848                         if (cleaned && tx_buffer_info->skb) {
 849                                 total_bytes += tx_buffer_info->bytecount;
 850                                 total_packets += tx_buffer_info->gso_segs;
 851                         }
 852
 853                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 854                                                          tx_buffer_info);
 855                 }
 856
 857                 tx_ring->tx_stats.completed++;
 858                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 859                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 860         }
 861
 862         tx_ring->next_to_clean = i;
 863         tx_ring->total_bytes += total_bytes;
 864         tx_ring->total_packets += total_packets;
 865         u64_stats_update_begin(&tx_ring->syncp);
 866         tx_ring->stats.packets += total_packets;
 867         tx_ring->stats.bytes += total_bytes;
 868         u64_stats_update_end(&tx_ring->syncp);
 869
 870         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 871                 /* schedule immediate reset if we believe we hung */
 872                 struct ixgbe_hw *hw = &adapter->hw;
 873                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 874                 e_err(drv, "Detected Tx Unit Hang\n"
 875                         "  Tx Queue             <%d>\n"
 876                         "  TDH, TDT             <%x>, <%x>\n"
 877                         "  next_to_use          <%x>\n"
 878                         "  next_to_clean        <%x>\n"
 879                         "tx_buffer_info[next_to_clean]\n"
 880                         "  time_stamp           <%lx>\n"
 881                         "  jiffies              <%lx>\n",
 882                         tx_ring->queue_index,
 883                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 884                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 885                         tx_ring->next_to_use, eop,
 886                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 887
 888                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 889
 890                 e_info(probe,
 891                        "tx hang %d detected on queue %d, resetting adapter\n",
 892                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 893
 894                 /* schedule immediate reset if we believe we hung */
 895                 ixgbe_tx_timeout(adapter->netdev);
 896
 897                 /* the adapter is about to reset, no point in enabling stuff */
 898                 return true;
 899         }
 900
 901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 902         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 903                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 904                 /* Make sure that anybody stopping the queue after this
 905                  * sees the new next_to_clean.
 906                  */
 907                 smp_mb();
 908                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 909                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 910                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 911                         ++tx_ring->tx_stats.restart_queue;
 912                 }
 913         }
 914
 915         return count < tx_ring->work_limit;
 916 }
 917
 918 #ifdef CONFIG_IXGBE_DCA
 919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 920                                 struct ixgbe_ring *rx_ring,
 921                                 int cpu)
 922 {
 923         struct ixgbe_hw *hw = &adapter->hw;
 924         u32 rxctrl;
 925         u8 reg_idx = rx_ring->reg_idx;
 926
 927         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 928         switch (hw->mac.type) {
 929         case ixgbe_mac_82598EB:
 930                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 931                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 932                 break;
 933         case ixgbe_mac_82599EB:
 934         case ixgbe_mac_X540:
 935                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 936                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 937                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 938                 break;
 939         default:
 940                 break;
 941         }
 942         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 943         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 944         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 945         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 946                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 947         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 948 }
 949
 950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 951                                 struct ixgbe_ring *tx_ring,
 952                                 int cpu)
 953 {
 954         struct ixgbe_hw *hw = &adapter->hw;
 955         u32 txctrl;
 956         u8 reg_idx = tx_ring->reg_idx;
 957
 958         switch (hw->mac.type) {
 959         case ixgbe_mac_82598EB:
 960                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 961                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 962                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 963                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 964                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 965                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 966                 break;
 967         case ixgbe_mac_82599EB:
 968         case ixgbe_mac_X540:
 969                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 970                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 971                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 972                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 973                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 974                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 975                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 976                 break;
 977         default:
 978                 break;
 979         }
 980 }
 981
 982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 983 {
 984         struct ixgbe_adapter *adapter = q_vector->adapter;
 985         int cpu = get_cpu();
 986         long r_idx;
 987         int i;
 988
 989         if (q_vector->cpu == cpu)
 990                 goto out_no_update;
 991
 992         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 993         for (i = 0; i < q_vector->txr_count; i++) {
 994                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 995                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 996                                       r_idx + 1);
 997         }
 998
 999         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000         for (i = 0; i < q_vector->rxr_count; i++) {
1001                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003                                       r_idx + 1);
1004         }
1005
1006         q_vector->cpu = cpu;
1007 out_no_update:
1008         put_cpu();
1009 }
1010
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012 {
1013         int num_q_vectors;
1014         int i;
1015
1016         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017                 return;
1018
1019         /* always use CB2 mode, difference is masked in the CB driver */
1020         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
1022         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024         else
1025                 num_q_vectors = 1;
1026
1027         for (i = 0; i < num_q_vectors; i++) {
1028                 adapter->q_vector[i]->cpu = -1;
1029                 ixgbe_update_dca(adapter->q_vector[i]);
1030         }
1031 }
1032
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1034 {
1035         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036         unsigned long event = *(unsigned long *)data;
1037
1038         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039                 return 0;
1040
1041         switch (event) {
1042         case DCA_PROVIDER_ADD:
1043                 /* if we're already enabled, don't do it again */
1044                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045                         break;
1046                 if (dca_add_requester(dev) == 0) {
1047                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048                         ixgbe_setup_dca(adapter);
1049                         break;
1050                 }
1051                 /* Fall Through since DCA is disabled. */
1052         case DCA_PROVIDER_REMOVE:
1053                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054                         dca_remove_requester(dev);
1055                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057                 }
1058                 break;
1059         }
1060
1061         return 0;
1062 }
1063
1064 #endif /* CONFIG_IXGBE_DCA */
1065 /**
1066  * ixgbe_receive_skb - Send a completed packet up the stack
1067  * @adapter: board private structure
1068  * @skb: packet to send up
1069  * @status: hardware indication of status of receive
1070  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071  * @rx_desc: rx descriptor
1072  **/
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074                               struct sk_buff *skb, u8 status,
1075                               struct ixgbe_ring *ring,
1076                               union ixgbe_adv_rx_desc *rx_desc)
1077 {
1078         struct ixgbe_adapter *adapter = q_vector->adapter;
1079         struct napi_struct *napi = &q_vector->napi;
1080         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1082
1083         if (is_vlan && (tag & VLAN_VID_MASK))
1084                 __vlan_hwaccel_put_tag(skb, tag);
1085
1086         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087                 napi_gro_receive(napi, skb);
1088         else
1089                 netif_rx(skb);
1090 }
1091
1092 /**
1093  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094  * @adapter: address of board private structure
1095  * @status_err: hardware indication of status of receive
1096  * @skb: skb currently being received and modified
1097  **/
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099                                      union ixgbe_adv_rx_desc *rx_desc,
1100                                      struct sk_buff *skb)
1101 {
1102         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
1104         skb_checksum_none_assert(skb);
1105
1106         /* Rx csum disabled */
1107         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1108                 return;
1109
1110         /* if IP and error */
1111         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113                 adapter->hw_csum_rx_error++;
1114                 return;
1115         }
1116
1117         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118                 return;
1119
1120         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123                 /*
1124                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1125                  * checksum errors.
1126                  */
1127                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129                         return;
1130
1131                 adapter->hw_csum_rx_error++;
1132                 return;
1133         }
1134
1135         /* It must be a TCP or UDP packet with a valid checksum */
1136         skb->ip_summed = CHECKSUM_UNNECESSARY;
1137 }
1138
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1140 {
1141         /*
1142          * Force memory writes to complete before letting h/w
1143          * know there are new descriptors to fetch.  (Only
1144          * applicable for weak-ordered memory model archs,
1145          * such as IA-64).
1146          */
1147         wmb();
1148         writel(val, rx_ring->tail);
1149 }
1150
1151 /**
1152  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153  * @rx_ring: ring to place buffers on
1154  * @cleaned_count: number of buffers to replace
1155  **/
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1157 {
1158         union ixgbe_adv_rx_desc *rx_desc;
1159         struct ixgbe_rx_buffer *bi;
1160         struct sk_buff *skb;
1161         u16 i = rx_ring->next_to_use;
1162
1163         /* do nothing if no valid netdev defined */
1164         if (!rx_ring->netdev)
1165                 return;
1166
1167         while (cleaned_count--) {
1168                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169                 bi = &rx_ring->rx_buffer_info[i];
1170                 skb = bi->skb;
1171
1172                 if (!skb) {
1173                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174                                                         rx_ring->rx_buf_len);
1175                         if (!skb) {
1176                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1177                                 goto no_buffers;
1178                         }
1179                         /* initialize queue mapping */
1180                         skb_record_rx_queue(skb, rx_ring->queue_index);
1181                         bi->skb = skb;
1182                 }
1183
1184                 if (!bi->dma) {
1185                         bi->dma = dma_map_single(rx_ring->dev,
1186                                                  skb->data,
1187                                                  rx_ring->rx_buf_len,
1188                                                  DMA_FROM_DEVICE);
1189                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1191                                 bi->dma = 0;
1192                                 goto no_buffers;
1193                         }
1194                 }
1195
1196                 if (ring_is_ps_enabled(rx_ring)) {
1197                         if (!bi->page) {
1198                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1199                                 if (!bi->page) {
1200                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1201                                         goto no_buffers;
1202                                 }
1203                         }
1204
1205                         if (!bi->page_dma) {
1206                                 /* use a half page if we're re-using */
1207                                 bi->page_offset ^= PAGE_SIZE / 2;
1208                                 bi->page_dma = dma_map_page(rx_ring->dev,
1209                                                             bi->page,
1210                                                             bi->page_offset,
1211                                                             PAGE_SIZE / 2,
1212                                                             DMA_FROM_DEVICE);
1213                                 if (dma_mapping_error(rx_ring->dev,
1214                                                       bi->page_dma)) {
1215                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1216                                         bi->page_dma = 0;
1217                                         goto no_buffers;
1218                                 }
1219                         }
1220
1221                         /* Refresh the desc even if buffer_addrs didn't change
1222                          * because each write-back erases this info. */
1223                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1225                 } else {
1226                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227                         rx_desc->read.hdr_addr = 0;
1228                 }
1229
1230                 i++;
1231                 if (i == rx_ring->count)
1232                         i = 0;
1233         }
1234
1235 no_buffers:
1236         if (rx_ring->next_to_use != i) {
1237                 rx_ring->next_to_use = i;
1238                 ixgbe_release_rx_desc(rx_ring, i);
1239         }
1240 }
1241
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244         /* HW will not DMA in data larger than the given buffer, even if it
1245          * parses the (NFS, of course) header to be larger.  In that case, it
1246          * fills the header buffer and spills the rest into the page.
1247          */
1248         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251         if (hlen > IXGBE_RX_HDR_SIZE)
1252                 hlen = IXGBE_RX_HDR_SIZE;
1253         return hlen;
1254 }
1255
1256 /**
1257  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258  * @skb: pointer to the last skb in the rsc queue
1259  *
1260  * This function changes a queue full of hw rsc buffers into a completed
1261  * packet.  It uses the ->prev pointers to find the first packet and then
1262  * turns it into the frag list owner.
1263  **/
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1265 {
1266         unsigned int frag_list_size = 0;
1267         unsigned int skb_cnt = 1;
1268
1269         while (skb->prev) {
1270                 struct sk_buff *prev = skb->prev;
1271                 frag_list_size += skb->len;
1272                 skb->prev = NULL;
1273                 skb = prev;
1274                 skb_cnt++;
1275         }
1276
1277         skb_shinfo(skb)->frag_list = skb->next;
1278         skb->next = NULL;
1279         skb->len += frag_list_size;
1280         skb->data_len += frag_list_size;
1281         skb->truesize += frag_list_size;
1282         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
1284         return skb;
1285 }
1286
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288 {
1289         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290                 IXGBE_RXDADV_RSCCNT_MASK);
1291 }
1292
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294                                struct ixgbe_ring *rx_ring,
1295                                int *work_done, int work_to_do)
1296 {
1297         struct ixgbe_adapter *adapter = q_vector->adapter;
1298         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300         struct sk_buff *skb;
1301         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302         const int current_node = numa_node_id();
1303 #ifdef IXGBE_FCOE
1304         int ddp_bytes = 0;
1305 #endif /* IXGBE_FCOE */
1306         u32 staterr;
1307         u16 i;
1308         u16 cleaned_count = 0;
1309         bool pkt_is_rsc = false;
1310
1311         i = rx_ring->next_to_clean;
1312         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1314
1315         while (staterr & IXGBE_RXD_STAT_DD) {
1316                 u32 upper_len = 0;
1317
1318                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1319
1320                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
1322                 skb = rx_buffer_info->skb;
1323                 rx_buffer_info->skb = NULL;
1324                 prefetch(skb->data);
1325
1326                 if (ring_is_rsc_enabled(rx_ring))
1327                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1328
1329                 /* if this is a skb from previous receive DMA will be 0 */
1330                 if (rx_buffer_info->dma) {
1331                         u16 hlen;
1332                         if (pkt_is_rsc &&
1333                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1334                             !skb->prev) {
1335                                 /*
1336                                  * When HWRSC is enabled, delay unmapping
1337                                  * of the first packet. It carries the
1338                                  * header information, HW may still
1339                                  * access the header after the writeback.
1340                                  * Only unmap it when EOP is reached
1341                                  */
1342                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1344                         } else {
1345                                 dma_unmap_single(rx_ring->dev,
1346                                                  rx_buffer_info->dma,
1347                                                  rx_ring->rx_buf_len,
1348                                                  DMA_FROM_DEVICE);
1349                         }
1350                         rx_buffer_info->dma = 0;
1351
1352                         if (ring_is_ps_enabled(rx_ring)) {
1353                                 hlen = ixgbe_get_hlen(rx_desc);
1354                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355                         } else {
1356                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357                         }
1358
1359                         skb_put(skb, hlen);
1360                 } else {
1361                         /* assume packet split since header is unmapped */
1362                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1363                 }
1364
1365                 if (upper_len) {
1366                         dma_unmap_page(rx_ring->dev,
1367                                        rx_buffer_info->page_dma,
1368                                        PAGE_SIZE / 2,
1369                                        DMA_FROM_DEVICE);
1370                         rx_buffer_info->page_dma = 0;
1371                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372                                            rx_buffer_info->page,
1373                                            rx_buffer_info->page_offset,
1374                                            upper_len);
1375
1376                         if ((page_count(rx_buffer_info->page) == 1) &&
1377                             (page_to_nid(rx_buffer_info->page) == current_node))
1378                                 get_page(rx_buffer_info->page);
1379                         else
1380                                 rx_buffer_info->page = NULL;
1381
1382                         skb->len += upper_len;
1383                         skb->data_len += upper_len;
1384                         skb->truesize += upper_len;
1385                 }
1386
1387                 i++;
1388                 if (i == rx_ring->count)
1389                         i = 0;
1390
1391                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392                 prefetch(next_rxd);
1393                 cleaned_count++;
1394
1395                 if (pkt_is_rsc) {
1396                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397                                      IXGBE_RXDADV_NEXTP_SHIFT;
1398                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1399                 } else {
1400                         next_buffer = &rx_ring->rx_buffer_info[i];
1401                 }
1402
1403                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404                         if (ring_is_ps_enabled(rx_ring)) {
1405                                 rx_buffer_info->skb = next_buffer->skb;
1406                                 rx_buffer_info->dma = next_buffer->dma;
1407                                 next_buffer->skb = skb;
1408                                 next_buffer->dma = 0;
1409                         } else {
1410                                 skb->next = next_buffer->skb;
1411                                 skb->next->prev = skb;
1412                         }
1413                         rx_ring->rx_stats.non_eop_descs++;
1414                         goto next_desc;
1415                 }
1416
1417                 if (skb->prev) {
1418                         skb = ixgbe_transform_rsc_queue(skb);
1419                         /* if we got here without RSC the packet is invalid */
1420                         if (!pkt_is_rsc) {
1421                                 __pskb_trim(skb, 0);
1422                                 rx_buffer_info->skb = skb;
1423                                 goto next_desc;
1424                         }
1425                 }
1426
1427                 if (ring_is_rsc_enabled(rx_ring)) {
1428                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429                                 dma_unmap_single(rx_ring->dev,
1430                                                  IXGBE_RSC_CB(skb)->dma,
1431                                                  rx_ring->rx_buf_len,
1432                                                  DMA_FROM_DEVICE);
1433                                 IXGBE_RSC_CB(skb)->dma = 0;
1434                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435                         }
1436                 }
1437                 if (pkt_is_rsc) {
1438                         if (ring_is_ps_enabled(rx_ring))
1439                                 rx_ring->rx_stats.rsc_count +=
1440                                         skb_shinfo(skb)->nr_frags;
1441                         else
1442                                 rx_ring->rx_stats.rsc_count +=
1443                                         IXGBE_RSC_CB(skb)->skb_cnt;
1444                         rx_ring->rx_stats.rsc_flush++;
1445                 }
1446
1447                 /* ERR_MASK will only have valid bits if EOP set */
1448                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449                         /* trim packet back to size 0 and recycle it */
1450                         __pskb_trim(skb, 0);
1451                         rx_buffer_info->skb = skb;
1452                         goto next_desc;
1453                 }
1454
1455                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1456
1457                 /* probably a little skewed due to removing CRC */
1458                 total_rx_bytes += skb->len;
1459                 total_rx_packets++;
1460
1461                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1462 #ifdef IXGBE_FCOE
1463                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466                         if (!ddp_bytes)
1467                                 goto next_desc;
1468                 }
1469 #endif /* IXGBE_FCOE */
1470                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1471
1472 next_desc:
1473                 rx_desc->wb.upper.status_error = 0;
1474
1475                 (*work_done)++;
1476                 if (*work_done >= work_to_do)
1477                         break;
1478
1479                 /* return some buffers to hardware, one at a time is too slow */
1480                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482                         cleaned_count = 0;
1483                 }
1484
1485                 /* use prefetched values */
1486                 rx_desc = next_rxd;
1487                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1488         }
1489
1490         rx_ring->next_to_clean = i;
1491         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493         if (cleaned_count)
1494                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1495
1496 #ifdef IXGBE_FCOE
1497         /* include DDPed FCoE data */
1498         if (ddp_bytes > 0) {
1499                 unsigned int mss;
1500
1501                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502                         sizeof(struct fc_frame_header) -
1503                         sizeof(struct fcoe_crc_eof);
1504                 if (mss > 512)
1505                         mss &= ~511;
1506                 total_rx_bytes += ddp_bytes;
1507                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508         }
1509 #endif /* IXGBE_FCOE */
1510
1511         rx_ring->total_packets += total_rx_packets;
1512         rx_ring->total_bytes += total_rx_bytes;
1513         u64_stats_update_begin(&rx_ring->syncp);
1514         rx_ring->stats.packets += total_rx_packets;
1515         rx_ring->stats.bytes += total_rx_bytes;
1516         u64_stats_update_end(&rx_ring->syncp);
1517 }
1518
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1520 /**
1521  * ixgbe_configure_msix - Configure MSI-X hardware
1522  * @adapter: board private structure
1523  *
1524  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525  * interrupts.
1526  **/
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528 {
1529         struct ixgbe_q_vector *q_vector;
1530         int i, q_vectors, v_idx, r_idx;
1531         u32 mask;
1532
1533         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535         /*
1536          * Populate the IVAR table and set the ITR values to the
1537          * corresponding register.
1538          */
1539         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540                 q_vector = adapter->q_vector[v_idx];
1541                 /* XXX for_each_set_bit(...) */
1542                 r_idx = find_first_bit(q_vector->rxr_idx,
1543                                        adapter->num_rx_queues);
1544
1545                 for (i = 0; i < q_vector->rxr_count; i++) {
1546                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548                         r_idx = find_next_bit(q_vector->rxr_idx,
1549                                               adapter->num_rx_queues,
1550                                               r_idx + 1);
1551                 }
1552                 r_idx = find_first_bit(q_vector->txr_idx,
1553                                        adapter->num_tx_queues);
1554
1555                 for (i = 0; i < q_vector->txr_count; i++) {
1556                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558                         r_idx = find_next_bit(q_vector->txr_idx,
1559                                               adapter->num_tx_queues,
1560                                               r_idx + 1);
1561                 }
1562
1563                 if (q_vector->txr_count && !q_vector->rxr_count)
1564                         /* tx only */
1565                         q_vector->eitr = adapter->tx_eitr_param;
1566                 else if (q_vector->rxr_count)
1567                         /* rx or mixed */
1568                         q_vector->eitr = adapter->rx_eitr_param;
1569
1570                 ixgbe_write_eitr(q_vector);
1571                 /* If Flow Director is enabled, set interrupt affinity */
1572                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574                         /*
1575                          * Allocate the affinity_hint cpumask, assign the mask
1576                          * for this vector, and set our affinity_hint for
1577                          * this irq.
1578                          */
1579                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580                                                GFP_KERNEL))
1581                                 return;
1582                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584                                               q_vector->affinity_mask);
1585                 }
1586         }
1587
1588         switch (adapter->hw.mac.type) {
1589         case ixgbe_mac_82598EB:
1590                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1591                                v_idx);
1592                 break;
1593         case ixgbe_mac_82599EB:
1594         case ixgbe_mac_X540:
1595                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1596                 break;
1597
1598         default:
1599                 break;
1600         }
1601         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
1603         /* set up to autoclear timer, and the vectors */
1604         mask = IXGBE_EIMS_ENABLE_MASK;
1605         if (adapter->num_vfs)
1606                 mask &= ~(IXGBE_EIMS_OTHER |
1607                           IXGBE_EIMS_MAILBOX |
1608                           IXGBE_EIMS_LSC);
1609         else
1610                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1612 }
1613
1614 enum latency_range {
1615         lowest_latency = 0,
1616         low_latency = 1,
1617         bulk_latency = 2,
1618         latency_invalid = 255
1619 };
1620
1621 /**
1622  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623  * @adapter: pointer to adapter
1624  * @eitr: eitr setting (ints per sec) to give last timeslice
1625  * @itr_setting: current throttle rate in ints/second
1626  * @packets: the number of packets during this measurement interval
1627  * @bytes: the number of bytes during this measurement interval
1628  *
1629  *      Stores a new ITR value based on packets and byte
1630  *      counts during the last interrupt.  The advantage of per interrupt
1631  *      computation is faster updates and more accurate ITR for the current
1632  *      traffic pattern.  Constants in this function were computed
1633  *      based on theoretical maximum wire speed and thresholds were set based
1634  *      on testing data as well as attempting to minimize response time
1635  *      while increasing bulk throughput.
1636  *      this functionality is controlled by the InterruptThrottleRate module
1637  *      parameter (see ixgbe_param.c)
1638  **/
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640                            u32 eitr, u8 itr_setting,
1641                            int packets, int bytes)
1642 {
1643         unsigned int retval = itr_setting;
1644         u32 timepassed_us;
1645         u64 bytes_perint;
1646
1647         if (packets == 0)
1648                 goto update_itr_done;
1649
1650
1651         /* simple throttlerate management
1652          *    0-20MB/s lowest (100000 ints/s)
1653          *   20-100MB/s low   (20000 ints/s)
1654          *  100-1249MB/s bulk (8000 ints/s)
1655          */
1656         /* what was last interrupt timeslice? */
1657         timepassed_us = 1000000/eitr;
1658         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660         switch (itr_setting) {
1661         case lowest_latency:
1662                 if (bytes_perint > adapter->eitr_low)
1663                         retval = low_latency;
1664                 break;
1665         case low_latency:
1666                 if (bytes_perint > adapter->eitr_high)
1667                         retval = bulk_latency;
1668                 else if (bytes_perint <= adapter->eitr_low)
1669                         retval = lowest_latency;
1670                 break;
1671         case bulk_latency:
1672                 if (bytes_perint <= adapter->eitr_high)
1673                         retval = low_latency;
1674                 break;
1675         }
1676
1677 update_itr_done:
1678         return retval;
1679 }
1680
1681 /**
1682  * ixgbe_write_eitr - write EITR register in hardware specific way
1683  * @q_vector: structure containing interrupt and ring information
1684  *
1685  * This function is made to be called by ethtool and by the driver
1686  * when it needs to update EITR registers at runtime.  Hardware
1687  * specific quirks/differences are taken care of here.
1688  */
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1690 {
1691         struct ixgbe_adapter *adapter = q_vector->adapter;
1692         struct ixgbe_hw *hw = &adapter->hw;
1693         int v_idx = q_vector->v_idx;
1694         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
1696         switch (adapter->hw.mac.type) {
1697         case ixgbe_mac_82598EB:
1698                 /* must write high and low 16 bits to reset counter */
1699                 itr_reg |= (itr_reg << 16);
1700                 break;
1701         case ixgbe_mac_82599EB:
1702         case ixgbe_mac_X540:
1703                 /*
1704                  * 82599 and X540 can support a value of zero, so allow it for
1705                  * max interrupt rate, but there is an errata where it can
1706                  * not be zero with RSC
1707                  */
1708                 if (itr_reg == 8 &&
1709                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710                         itr_reg = 0;
1711
1712                 /*
1713                  * set the WDIS bit to not clear the timer bits and cause an
1714                  * immediate assertion of the interrupt
1715                  */
1716                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1717                 break;
1718         default:
1719                 break;
1720         }
1721         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 }
1723
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725 {
1726         struct ixgbe_adapter *adapter = q_vector->adapter;
1727         int i, r_idx;
1728         u32 new_itr;
1729         u8 current_itr, ret_itr;
1730
1731         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732         for (i = 0; i < q_vector->txr_count; i++) {
1733                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1735                                            q_vector->tx_itr,
1736                                            tx_ring->total_packets,
1737                                            tx_ring->total_bytes);
1738                 /* if the result for this queue would decrease interrupt
1739                  * rate for this vector then use that result */
1740                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741                                     q_vector->tx_itr - 1 : ret_itr);
1742                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1743                                       r_idx + 1);
1744         }
1745
1746         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747         for (i = 0; i < q_vector->rxr_count; i++) {
1748                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1750                                            q_vector->rx_itr,
1751                                            rx_ring->total_packets,
1752                                            rx_ring->total_bytes);
1753                 /* if the result for this queue would decrease interrupt
1754                  * rate for this vector then use that result */
1755                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756                                     q_vector->rx_itr - 1 : ret_itr);
1757                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1758                                       r_idx + 1);
1759         }
1760
1761         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1762
1763         switch (current_itr) {
1764         /* counts and packets in update_itr are dependent on these numbers */
1765         case lowest_latency:
1766                 new_itr = 100000;
1767                 break;
1768         case low_latency:
1769                 new_itr = 20000; /* aka hwitr = ~200 */
1770                 break;
1771         case bulk_latency:
1772         default:
1773                 new_itr = 8000;
1774                 break;
1775         }
1776
1777         if (new_itr != q_vector->eitr) {
1778                 /* do an exponential smoothing */
1779                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1780
1781                 /* save the algorithm value here, not the smoothed one */
1782                 q_vector->eitr = new_itr;
1783
1784                 ixgbe_write_eitr(q_vector);
1785         }
1786 }
1787
1788 /**
1789  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790  * @work: pointer to work_struct containing our data
1791  **/
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1793 {
1794         struct ixgbe_adapter *adapter = container_of(work,
1795                                                      struct ixgbe_adapter,
1796                                                      check_overtemp_task);
1797         struct ixgbe_hw *hw = &adapter->hw;
1798         u32 eicr = adapter->interrupt_event;
1799
1800         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801                 return;
1802
1803         switch (hw->device_id) {
1804         case IXGBE_DEV_ID_82599_T3_LOM: {
1805                 u32 autoneg;
1806                 bool link_up = false;
1807
1808                 if (hw->mac.ops.check_link)
1809                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812                     (eicr & IXGBE_EICR_LSC))
1813                         /* Check if this is due to overtemp */
1814                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815                                 break;
1816                 return;
1817         }
1818         default:
1819                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1820                         return;
1821                 break;
1822         }
1823         e_crit(drv,
1824                "Network adapter has been stopped because it has over heated. "
1825                "Restart the computer. If the problem persists, "
1826                "power off the system and replace the adapter\n");
1827         /* write to clear the interrupt */
1828         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1829 }
1830
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832 {
1833         struct ixgbe_hw *hw = &adapter->hw;
1834
1835         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836             (eicr & IXGBE_EICR_GPI_SDP1)) {
1837                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838                 /* write to clear the interrupt */
1839                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840         }
1841 }
1842
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844 {
1845         struct ixgbe_hw *hw = &adapter->hw;
1846
1847         if (eicr & IXGBE_EICR_GPI_SDP2) {
1848                 /* Clear the interrupt */
1849                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851                         schedule_work(&adapter->sfp_config_module_task);
1852         }
1853
1854         if (eicr & IXGBE_EICR_GPI_SDP1) {
1855                 /* Clear the interrupt */
1856                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858                         schedule_work(&adapter->multispeed_fiber_task);
1859         }
1860 }
1861
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863 {
1864         struct ixgbe_hw *hw = &adapter->hw;
1865
1866         adapter->lsc_int++;
1867         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868         adapter->link_check_timeout = jiffies;
1869         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871                 IXGBE_WRITE_FLUSH(hw);
1872                 schedule_work(&adapter->watchdog_task);
1873         }
1874 }
1875
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877 {
1878         struct net_device *netdev = data;
1879         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880         struct ixgbe_hw *hw = &adapter->hw;
1881         u32 eicr;
1882
1883         /*
1884          * Workaround for Silicon errata.  Use clear-by-write instead
1885          * of clear-by-read.  Reading with EICS will return the
1886          * interrupt causes without clearing, which later be done
1887          * with the write to EICR.
1888          */
1889         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1891
1892         if (eicr & IXGBE_EICR_LSC)
1893                 ixgbe_check_lsc(adapter);
1894
1895         if (eicr & IXGBE_EICR_MAILBOX)
1896                 ixgbe_msg_task(adapter);
1897
1898         switch (hw->mac.type) {
1899         case ixgbe_mac_82599EB:
1900         case ixgbe_mac_X540:
1901                 /* Handle Flow Director Full threshold interrupt */
1902                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1903                         int i;
1904                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1905                         /* Disable transmits before FDIR Re-initialization */
1906                         netif_tx_stop_all_queues(netdev);
1907                         for (i = 0; i < adapter->num_tx_queues; i++) {
1908                                 struct ixgbe_ring *tx_ring =
1909                                                             adapter->tx_ring[i];
1910                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1911                                                        &tx_ring->state))
1912                                         schedule_work(&adapter->fdir_reinit_task);
1913                         }
1914                 }
1915                 ixgbe_check_sfp_event(adapter, eicr);
1916                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1917                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1918                         adapter->interrupt_event = eicr;
1919                         schedule_work(&adapter->check_overtemp_task);
1920                 }
1921                 break;
1922         default:
1923                 break;
1924         }
1925
1926         ixgbe_check_fan_failure(adapter, eicr);
1927
1928         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1929                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1930
1931         return IRQ_HANDLED;
1932 }
1933
1934 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1935                                            u64 qmask)
1936 {
1937         u32 mask;
1938         struct ixgbe_hw *hw = &adapter->hw;
1939
1940         switch (hw->mac.type) {
1941         case ixgbe_mac_82598EB:
1942                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1943                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1944                 break;
1945         case ixgbe_mac_82599EB:
1946         case ixgbe_mac_X540:
1947                 mask = (qmask & 0xFFFFFFFF);
1948                 if (mask)
1949                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1950                 mask = (qmask >> 32);
1951                 if (mask)
1952                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1953                 break;
1954         default:
1955                 break;
1956         }
1957         /* skip the flush */
1958 }
1959
1960 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1961                                             u64 qmask)
1962 {
1963         u32 mask;
1964         struct ixgbe_hw *hw = &adapter->hw;
1965
1966         switch (hw->mac.type) {
1967         case ixgbe_mac_82598EB:
1968                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1969                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1970                 break;
1971         case ixgbe_mac_82599EB:
1972         case ixgbe_mac_X540:
1973                 mask = (qmask & 0xFFFFFFFF);
1974                 if (mask)
1975                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1976                 mask = (qmask >> 32);
1977                 if (mask)
1978                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1979                 break;
1980         default:
1981                 break;
1982         }
1983         /* skip the flush */
1984 }
1985
1986 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1987 {
1988         struct ixgbe_q_vector *q_vector = data;
1989         struct ixgbe_adapter  *adapter = q_vector->adapter;
1990         struct ixgbe_ring     *tx_ring;
1991         int i, r_idx;
1992
1993         if (!q_vector->txr_count)
1994                 return IRQ_HANDLED;
1995
1996         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1997         for (i = 0; i < q_vector->txr_count; i++) {
1998                 tx_ring = adapter->tx_ring[r_idx];
1999                 tx_ring->total_bytes = 0;
2000                 tx_ring->total_packets = 0;
2001                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2002                                       r_idx + 1);
2003         }
2004
2005         /* EIAM disabled interrupts (on this vector) for us */
2006         napi_schedule(&q_vector->napi);
2007
2008         return IRQ_HANDLED;
2009 }
2010
2011 /**
2012  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2013  * @irq: unused
2014  * @data: pointer to our q_vector struct for this interrupt vector
2015  **/
2016 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2017 {
2018         struct ixgbe_q_vector *q_vector = data;
2019         struct ixgbe_adapter  *adapter = q_vector->adapter;
2020         struct ixgbe_ring  *rx_ring;
2021         int r_idx;
2022         int i;
2023
2024 #ifdef CONFIG_IXGBE_DCA
2025         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2026                 ixgbe_update_dca(q_vector);
2027 #endif
2028
2029         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2030         for (i = 0; i < q_vector->rxr_count; i++) {
2031                 rx_ring = adapter->rx_ring[r_idx];
2032                 rx_ring->total_bytes = 0;
2033                 rx_ring->total_packets = 0;
2034                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2035                                       r_idx + 1);
2036         }
2037
2038         if (!q_vector->rxr_count)
2039                 return IRQ_HANDLED;
2040
2041         /* EIAM disabled interrupts (on this vector) for us */
2042         napi_schedule(&q_vector->napi);
2043
2044         return IRQ_HANDLED;
2045 }
2046
2047 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2048 {
2049         struct ixgbe_q_vector *q_vector = data;
2050         struct ixgbe_adapter  *adapter = q_vector->adapter;
2051         struct ixgbe_ring  *ring;
2052         int r_idx;
2053         int i;
2054
2055         if (!q_vector->txr_count && !q_vector->rxr_count)
2056                 return IRQ_HANDLED;
2057
2058         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2059         for (i = 0; i < q_vector->txr_count; i++) {
2060                 ring = adapter->tx_ring[r_idx];
2061                 ring->total_bytes = 0;
2062                 ring->total_packets = 0;
2063                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2064                                       r_idx + 1);
2065         }
2066
2067         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2068         for (i = 0; i < q_vector->rxr_count; i++) {
2069                 ring = adapter->rx_ring[r_idx];
2070                 ring->total_bytes = 0;
2071                 ring->total_packets = 0;
2072                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2073                                       r_idx + 1);
2074         }
2075
2076         /* EIAM disabled interrupts (on this vector) for us */
2077         napi_schedule(&q_vector->napi);
2078
2079         return IRQ_HANDLED;
2080 }
2081
2082 /**
2083  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2084  * @napi: napi struct with our devices info in it
2085  * @budget: amount of work driver is allowed to do this pass, in packets
2086  *
2087  * This function is optimized for cleaning one queue only on a single
2088  * q_vector!!!
2089  **/
2090 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2091 {
2092         struct ixgbe_q_vector *q_vector =
2093                                container_of(napi, struct ixgbe_q_vector, napi);
2094         struct ixgbe_adapter *adapter = q_vector->adapter;
2095         struct ixgbe_ring *rx_ring = NULL;
2096         int work_done = 0;
2097         long r_idx;
2098
2099 #ifdef CONFIG_IXGBE_DCA
2100         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2101                 ixgbe_update_dca(q_vector);
2102 #endif
2103
2104         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2105         rx_ring = adapter->rx_ring[r_idx];
2106
2107         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2108
2109         /* If all Rx work done, exit the polling mode */
2110         if (work_done < budget) {
2111                 napi_complete(napi);
2112                 if (adapter->rx_itr_setting & 1)
2113                         ixgbe_set_itr_msix(q_vector);
2114                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2115                         ixgbe_irq_enable_queues(adapter,
2116                                                 ((u64)1 << q_vector->v_idx));
2117         }
2118
2119         return work_done;
2120 }
2121
2122 /**
2123  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2124  * @napi: napi struct with our devices info in it
2125  * @budget: amount of work driver is allowed to do this pass, in packets
2126  *
2127  * This function will clean more than one rx queue associated with a
2128  * q_vector.
2129  **/
2130 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2131 {
2132         struct ixgbe_q_vector *q_vector =
2133                                container_of(napi, struct ixgbe_q_vector, napi);
2134         struct ixgbe_adapter *adapter = q_vector->adapter;
2135         struct ixgbe_ring *ring = NULL;
2136         int work_done = 0, i;
2137         long r_idx;
2138         bool tx_clean_complete = true;
2139
2140 #ifdef CONFIG_IXGBE_DCA
2141         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2142                 ixgbe_update_dca(q_vector);
2143 #endif
2144
2145         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2146         for (i = 0; i < q_vector->txr_count; i++) {
2147                 ring = adapter->tx_ring[r_idx];
2148                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2149                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2150                                       r_idx + 1);
2151         }
2152
2153         /* attempt to distribute budget to each queue fairly, but don't allow
2154          * the budget to go below 1 because we'll exit polling */
2155         budget /= (q_vector->rxr_count ?: 1);
2156         budget = max(budget, 1);
2157         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2158         for (i = 0; i < q_vector->rxr_count; i++) {
2159                 ring = adapter->rx_ring[r_idx];
2160                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2161                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2162                                       r_idx + 1);
2163         }
2164
2165         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2166         ring = adapter->rx_ring[r_idx];
2167         /* If all Rx work done, exit the polling mode */
2168         if (work_done < budget) {
2169                 napi_complete(napi);
2170                 if (adapter->rx_itr_setting & 1)
2171                         ixgbe_set_itr_msix(q_vector);
2172                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2173                         ixgbe_irq_enable_queues(adapter,
2174                                                 ((u64)1 << q_vector->v_idx));
2175                 return 0;
2176         }
2177
2178         return work_done;
2179 }
2180
2181 /**
2182  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2183  * @napi: napi struct with our devices info in it
2184  * @budget: amount of work driver is allowed to do this pass, in packets
2185  *
2186  * This function is optimized for cleaning one queue only on a single
2187  * q_vector!!!
2188  **/
2189 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2190 {
2191         struct ixgbe_q_vector *q_vector =
2192                                container_of(napi, struct ixgbe_q_vector, napi);
2193         struct ixgbe_adapter *adapter = q_vector->adapter;
2194         struct ixgbe_ring *tx_ring = NULL;
2195         int work_done = 0;
2196         long r_idx;
2197
2198 #ifdef CONFIG_IXGBE_DCA
2199         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2200                 ixgbe_update_dca(q_vector);
2201 #endif
2202
2203         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2204         tx_ring = adapter->tx_ring[r_idx];
2205
2206         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2207                 work_done = budget;
2208
2209         /* If all Tx work done, exit the polling mode */
2210         if (work_done < budget) {
2211                 napi_complete(napi);
2212                 if (adapter->tx_itr_setting & 1)
2213                         ixgbe_set_itr_msix(q_vector);
2214                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2215                         ixgbe_irq_enable_queues(adapter,
2216                                                 ((u64)1 << q_vector->v_idx));
2217         }
2218
2219         return work_done;
2220 }
2221
2222 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2223                                      int r_idx)
2224 {
2225         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2226         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2227
2228         set_bit(r_idx, q_vector->rxr_idx);
2229         q_vector->rxr_count++;
2230         rx_ring->q_vector = q_vector;
2231 }
2232
2233 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2234                                      int t_idx)
2235 {
2236         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2237         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2238
2239         set_bit(t_idx, q_vector->txr_idx);
2240         q_vector->txr_count++;
2241         tx_ring->q_vector = q_vector;
2242 }
2243
2244 /**
2245  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2246  * @adapter: board private structure to initialize
2247  *
2248  * This function maps descriptor rings to the queue-specific vectors
2249  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2250  * one vector per ring/queue, but on a constrained vector budget, we
2251  * group the rings as "efficiently" as possible.  You would add new
2252  * mapping configurations in here.
2253  **/
2254 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2255 {
2256         int q_vectors;
2257         int v_start = 0;
2258         int rxr_idx = 0, txr_idx = 0;
2259         int rxr_remaining = adapter->num_rx_queues;
2260         int txr_remaining = adapter->num_tx_queues;
2261         int i, j;
2262         int rqpv, tqpv;
2263         int err = 0;
2264
2265         /* No mapping required if MSI-X is disabled. */
2266         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2267                 goto out;
2268
2269         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2270
2271         /*
2272          * The ideal configuration...
2273          * We have enough vectors to map one per queue.
2274          */
2275         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2276                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2277                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2278
2279                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2280                         map_vector_to_txq(adapter, v_start, txr_idx);
2281
2282                 goto out;
2283         }
2284
2285         /*
2286          * If we don't have enough vectors for a 1-to-1
2287          * mapping, we'll have to group them so there are
2288          * multiple queues per vector.
2289          */
2290         /* Re-adjusting *qpv takes care of the remainder. */
2291         for (i = v_start; i < q_vectors; i++) {
2292                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2293                 for (j = 0; j < rqpv; j++) {
2294                         map_vector_to_rxq(adapter, i, rxr_idx);
2295                         rxr_idx++;
2296                         rxr_remaining--;
2297                 }
2298                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2299                 for (j = 0; j < tqpv; j++) {
2300                         map_vector_to_txq(adapter, i, txr_idx);
2301                         txr_idx++;
2302                         txr_remaining--;
2303                 }
2304         }
2305 out:
2306         return err;
2307 }
2308
2309 /**
2310  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2311  * @adapter: board private structure
2312  *
2313  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2314  * interrupts from the kernel.
2315  **/
2316 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2317 {
2318         struct net_device *netdev = adapter->netdev;
2319         irqreturn_t (*handler)(int, void *);
2320         int i, vector, q_vectors, err;
2321         int ri = 0, ti = 0;
2322
2323         /* Decrement for Other and TCP Timer vectors */
2324         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2325
2326         err = ixgbe_map_rings_to_vectors(adapter);
2327         if (err)
2328                 return err;
2329
2330 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2331                                           ? &ixgbe_msix_clean_many : \
2332                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2333                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2334                           NULL)
2335         for (vector = 0; vector < q_vectors; vector++) {
2336                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2337                 handler = SET_HANDLER(q_vector);
2338
2339                 if (handler == &ixgbe_msix_clean_rx) {
2340                         sprintf(q_vector->name, "%s-%s-%d",
2341                                 netdev->name, "rx", ri++);
2342                 } else if (handler == &ixgbe_msix_clean_tx) {
2343                         sprintf(q_vector->name, "%s-%s-%d",
2344                                 netdev->name, "tx", ti++);
2345                 } else if (handler == &ixgbe_msix_clean_many) {
2346                         sprintf(q_vector->name, "%s-%s-%d",
2347                                 netdev->name, "TxRx", ri++);
2348                         ti++;
2349                 } else {
2350                         /* skip this unused q_vector */
2351                         continue;
2352                 }
2353                 err = request_irq(adapter->msix_entries[vector].vector,
2354                                   handler, 0, q_vector->name,
2355                                   q_vector);
2356                 if (err) {
2357                         e_err(probe, "request_irq failed for MSIX interrupt "
2358                               "Error: %d\n", err);
2359                         goto free_queue_irqs;
2360                 }
2361         }
2362
2363         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2364         err = request_irq(adapter->msix_entries[vector].vector,
2365                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2366         if (err) {
2367                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2368                 goto free_queue_irqs;
2369         }
2370
2371         return 0;
2372
2373 free_queue_irqs:
2374         for (i = vector - 1; i >= 0; i--)
2375                 free_irq(adapter->msix_entries[--vector].vector,
2376                          adapter->q_vector[i]);
2377         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2378         pci_disable_msix(adapter->pdev);
2379         kfree(adapter->msix_entries);
2380         adapter->msix_entries = NULL;
2381         return err;
2382 }
2383
2384 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2385 {
2386         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2387         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2388         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2389         u32 new_itr = q_vector->eitr;
2390         u8 current_itr;
2391
2392         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2393                                             q_vector->tx_itr,
2394                                             tx_ring->total_packets,
2395                                             tx_ring->total_bytes);
2396         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2397                                             q_vector->rx_itr,
2398                                             rx_ring->total_packets,
2399                                             rx_ring->total_bytes);
2400
2401         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2402
2403         switch (current_itr) {
2404         /* counts and packets in update_itr are dependent on these numbers */
2405         case lowest_latency:
2406                 new_itr = 100000;
2407                 break;
2408         case low_latency:
2409                 new_itr = 20000; /* aka hwitr = ~200 */
2410                 break;
2411         case bulk_latency:
2412                 new_itr = 8000;
2413                 break;
2414         default:
2415                 break;
2416         }
2417
2418         if (new_itr != q_vector->eitr) {
2419                 /* do an exponential smoothing */
2420                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2421
2422                 /* save the algorithm value here */
2423                 q_vector->eitr = new_itr;
2424
2425                 ixgbe_write_eitr(q_vector);
2426         }
2427 }
2428
2429 /**
2430  * ixgbe_irq_enable - Enable default interrupt generation settings
2431  * @adapter: board private structure
2432  **/
2433 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2434                                     bool flush)
2435 {
2436         u32 mask;
2437
2438         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2439         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2440                 mask |= IXGBE_EIMS_GPI_SDP0;
2441         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2442                 mask |= IXGBE_EIMS_GPI_SDP1;
2443         switch (adapter->hw.mac.type) {
2444         case ixgbe_mac_82599EB:
2445         case ixgbe_mac_X540:
2446                 mask |= IXGBE_EIMS_ECC;
2447                 mask |= IXGBE_EIMS_GPI_SDP1;
2448                 mask |= IXGBE_EIMS_GPI_SDP2;
2449                 if (adapter->num_vfs)
2450                         mask |= IXGBE_EIMS_MAILBOX;
2451                 break;
2452         default:
2453                 break;
2454         }
2455         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2456             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2457                 mask |= IXGBE_EIMS_FLOW_DIR;
2458
2459         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2460         if (queues)
2461                 ixgbe_irq_enable_queues(adapter, ~0);
2462         if (flush)
2463                 IXGBE_WRITE_FLUSH(&adapter->hw);
2464
2465         if (adapter->num_vfs > 32) {
2466                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2467                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2468         }
2469 }
2470
2471 /**
2472  * ixgbe_intr - legacy mode Interrupt Handler
2473  * @irq: interrupt number
2474  * @data: pointer to a network interface device structure
2475  **/
2476 static irqreturn_t ixgbe_intr(int irq, void *data)
2477 {
2478         struct net_device *netdev = data;
2479         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2480         struct ixgbe_hw *hw = &adapter->hw;
2481         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2482         u32 eicr;
2483
2484         /*
2485          * Workaround for silicon errata on 82598.  Mask the interrupts
2486          * before the read of EICR.
2487          */
2488         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2489
2490         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2491          * therefore no explict interrupt disable is necessary */
2492         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2493         if (!eicr) {
2494                 /*
2495                  * shared interrupt alert!
2496                  * make sure interrupts are enabled because the read will
2497                  * have disabled interrupts due to EIAM
2498                  * finish the workaround of silicon errata on 82598.  Unmask
2499                  * the interrupt that we masked before the EICR read.
2500                  */
2501                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2502                         ixgbe_irq_enable(adapter, true, true);
2503                 return IRQ_NONE;        /* Not our interrupt */
2504         }
2505
2506         if (eicr & IXGBE_EICR_LSC)
2507                 ixgbe_check_lsc(adapter);
2508
2509         switch (hw->mac.type) {
2510         case ixgbe_mac_82599EB:
2511         case ixgbe_mac_X540:
2512                 ixgbe_check_sfp_event(adapter, eicr);
2513                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515                         adapter->interrupt_event = eicr;
2516                         schedule_work(&adapter->check_overtemp_task);
2517                 }
2518                 break;
2519         default:
2520                 break;
2521         }
2522
2523         ixgbe_check_fan_failure(adapter, eicr);
2524
2525         if (napi_schedule_prep(&(q_vector->napi))) {
2526                 adapter->tx_ring[0]->total_packets = 0;
2527                 adapter->tx_ring[0]->total_bytes = 0;
2528                 adapter->rx_ring[0]->total_packets = 0;
2529                 adapter->rx_ring[0]->total_bytes = 0;
2530                 /* would disable interrupts here but EIAM disabled it */
2531                 __napi_schedule(&(q_vector->napi));
2532         }
2533
2534         /*
2535          * re-enable link(maybe) and non-queue interrupts, no flush.
2536          * ixgbe_poll will re-enable the queue interrupts
2537          */
2538
2539         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540                 ixgbe_irq_enable(adapter, false, false);
2541
2542         return IRQ_HANDLED;
2543 }
2544
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546 {
2547         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549         for (i = 0; i < q_vectors; i++) {
2550                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553                 q_vector->rxr_count = 0;
2554                 q_vector->txr_count = 0;
2555         }
2556 }
2557
2558 /**
2559  * ixgbe_request_irq - initialize interrupts
2560  * @adapter: board private structure
2561  *
2562  * Attempts to configure interrupts using the best available
2563  * capabilities of the hardware and kernel.
2564  **/
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2566 {
2567         struct net_device *netdev = adapter->netdev;
2568         int err;
2569
2570         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571                 err = ixgbe_request_msix_irqs(adapter);
2572         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574                                   netdev->name, netdev);
2575         } else {
2576                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577                                   netdev->name, netdev);
2578         }
2579
2580         if (err)
2581                 e_err(probe, "request_irq failed, Error %d\n", err);
2582
2583         return err;
2584 }
2585
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587 {
2588         struct net_device *netdev = adapter->netdev;
2589
2590         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591                 int i, q_vectors;
2592
2593                 q_vectors = adapter->num_msix_vectors;
2594
2595                 i = q_vectors - 1;
2596                 free_irq(adapter->msix_entries[i].vector, netdev);
2597
2598                 i--;
2599                 for (; i >= 0; i--) {
2600                         free_irq(adapter->msix_entries[i].vector,
2601                                  adapter->q_vector[i]);
2602                 }
2603
2604                 ixgbe_reset_q_vectors(adapter);
2605         } else {
2606                 free_irq(adapter->pdev->irq, netdev);
2607         }
2608 }
2609
2610 /**
2611  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612  * @adapter: board private structure
2613  **/
2614 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2615 {
2616         switch (adapter->hw.mac.type) {
2617         case ixgbe_mac_82598EB:
2618                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2619                 break;
2620         case ixgbe_mac_82599EB:
2621         case ixgbe_mac_X540:
2622                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2624                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2625                 if (adapter->num_vfs > 32)
2626                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2627                 break;
2628         default:
2629                 break;
2630         }
2631         IXGBE_WRITE_FLUSH(&adapter->hw);
2632         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2633                 int i;
2634                 for (i = 0; i < adapter->num_msix_vectors; i++)
2635                         synchronize_irq(adapter->msix_entries[i].vector);
2636         } else {
2637                 synchronize_irq(adapter->pdev->irq);
2638         }
2639 }
2640
2641 /**
2642  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2643  *
2644  **/
2645 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2646 {
2647         struct ixgbe_hw *hw = &adapter->hw;
2648
2649         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2650                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2651
2652         ixgbe_set_ivar(adapter, 0, 0, 0);
2653         ixgbe_set_ivar(adapter, 1, 0, 0);
2654
2655         map_vector_to_rxq(adapter, 0, 0);
2656         map_vector_to_txq(adapter, 0, 0);
2657
2658         e_info(hw, "Legacy interrupt IVAR setup done\n");
2659 }
2660
2661 /**
2662  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663  * @adapter: board private structure
2664  * @ring: structure containing ring specific data
2665  *
2666  * Configure the Tx descriptor ring after a reset.
2667  **/
2668 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669                              struct ixgbe_ring *ring)
2670 {
2671         struct ixgbe_hw *hw = &adapter->hw;
2672         u64 tdba = ring->dma;
2673         int wait_loop = 10;
2674         u32 txdctl;
2675         u8 reg_idx = ring->reg_idx;
2676
2677         /* disable queue to avoid issues while updating state */
2678         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2681         IXGBE_WRITE_FLUSH(hw);
2682
2683         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2684                         (tdba & DMA_BIT_MASK(32)));
2685         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2688         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2690         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2691
2692         /* configure fetching thresholds */
2693         if (adapter->rx_itr_setting == 0) {
2694                 /* cannot set wthresh when itr==0 */
2695                 txdctl &= ~0x007F0000;
2696         } else {
2697                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698                 txdctl |= (8 << 16);
2699         }
2700         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701                 /* PThresh workaround for Tx hang with DFP enabled. */
2702                 txdctl |= 32;
2703         }
2704
2705         /* reinitialize flowdirector state */
2706         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707             adapter->atr_sample_rate) {
2708                 ring->atr_sample_rate = adapter->atr_sample_rate;
2709                 ring->atr_count = 0;
2710                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2711         } else {
2712                 ring->atr_sample_rate = 0;
2713         }
2714
2715         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2716
2717         /* enable queue */
2718         txdctl |= IXGBE_TXDCTL_ENABLE;
2719         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2720
2721         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722         if (hw->mac.type == ixgbe_mac_82598EB &&
2723             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724                 return;
2725
2726         /* poll to verify queue is enabled */
2727         do {
2728                 msleep(1);
2729                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2731         if (!wait_loop)
2732                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2733 }
2734
2735 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2736 {
2737         struct ixgbe_hw *hw = &adapter->hw;
2738         u32 rttdcs;
2739         u32 mask;
2740
2741         if (hw->mac.type == ixgbe_mac_82598EB)
2742                 return;
2743
2744         /* disable the arbiter while setting MTQC */
2745         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748
2749         /* set transmit pool layout */
2750         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751         switch (adapter->flags & mask) {
2752
2753         case (IXGBE_FLAG_SRIOV_ENABLED):
2754                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2756                 break;
2757
2758         case (IXGBE_FLAG_DCB_ENABLED):
2759                 /* We enable 8 traffic classes, DCB only */
2760                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2762                 break;
2763
2764         default:
2765                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2766                 break;
2767         }
2768
2769         /* re-enable the arbiter */
2770         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772 }
2773
2774 /**
2775  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2776  * @adapter: board private structure
2777  *
2778  * Configure the Tx unit of the MAC after a reset.
2779  **/
2780 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2781 {
2782         struct ixgbe_hw *hw = &adapter->hw;
2783         u32 dmatxctl;
2784         u32 i;
2785
2786         ixgbe_setup_mtqc(adapter);
2787
2788         if (hw->mac.type != ixgbe_mac_82598EB) {
2789                 /* DMATXCTL.EN must be before Tx queues are enabled */
2790                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791                 dmatxctl |= IXGBE_DMATXCTL_TE;
2792                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2793         }
2794
2795         /* Setup the HW Tx Head and Tail descriptor pointers */
2796         for (i = 0; i < adapter->num_tx_queues; i++)
2797                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2798 }
2799
2800 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2801
2802 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2803                                    struct ixgbe_ring *rx_ring)
2804 {
2805         u32 srrctl;
2806         u8 reg_idx = rx_ring->reg_idx;
2807
2808         switch (adapter->hw.mac.type) {
2809         case ixgbe_mac_82598EB: {
2810                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811                 const int mask = feature[RING_F_RSS].mask;
2812                 reg_idx = reg_idx & mask;
2813         }
2814                 break;
2815         case ixgbe_mac_82599EB:
2816         case ixgbe_mac_X540:
2817         default:
2818                 break;
2819         }
2820
2821         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2822
2823         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2825         if (adapter->num_vfs)
2826                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2827
2828         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2830
2831         if (ring_is_ps_enabled(rx_ring)) {
2832 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2834 #else
2835                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2836 #endif
2837                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2838         } else {
2839                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2842         }
2843
2844         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2845 }
2846
2847 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2848 {
2849         struct ixgbe_hw *hw = &adapter->hw;
2850         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2851                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2853         u32 mrqc = 0, reta = 0;
2854         u32 rxcsum;
2855         int i, j;
2856         int mask;
2857
2858         /* Fill out hash function seeds */
2859         for (i = 0; i < 10; i++)
2860                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2861
2862         /* Fill out redirection table */
2863         for (i = 0, j = 0; i < 128; i++, j++) {
2864                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2865                         j = 0;
2866                 /* reta = 4-byte sliding window of
2867                  * 0x00..(indices-1)(indices-1)00..etc. */
2868                 reta = (reta << 8) | (j * 0x11);
2869                 if ((i & 3) == 3)
2870                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2871         }
2872
2873         /* Disable indicating checksum in descriptor, enables RSS hash */
2874         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875         rxcsum |= IXGBE_RXCSUM_PCSD;
2876         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2877
2878         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2880         else
2881                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2882 #ifdef CONFIG_IXGBE_DCB
2883                                          | IXGBE_FLAG_DCB_ENABLED
2884 #endif
2885                                          | IXGBE_FLAG_SRIOV_ENABLED
2886                                         );
2887
2888         switch (mask) {
2889         case (IXGBE_FLAG_RSS_ENABLED):
2890                 mrqc = IXGBE_MRQC_RSSEN;
2891                 break;
2892         case (IXGBE_FLAG_SRIOV_ENABLED):
2893                 mrqc = IXGBE_MRQC_VMDQEN;
2894                 break;
2895 #ifdef CONFIG_IXGBE_DCB
2896         case (IXGBE_FLAG_DCB_ENABLED):
2897                 mrqc = IXGBE_MRQC_RT8TCEN;
2898                 break;
2899 #endif /* CONFIG_IXGBE_DCB */
2900         default:
2901                 break;
2902         }
2903
2904         /* Perform hash on these packet types */
2905         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907               | IXGBE_MRQC_RSS_FIELD_IPV6
2908               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2909
2910         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2911 }
2912
2913 /**
2914  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915  * @adapter: address of board private structure
2916  * @ring: structure containing ring specific data
2917  **/
2918 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919                         struct ixgbe_ring *ring)
2920 {
2921         struct ixgbe_hw *hw = &adapter->hw;
2922         u32 rscctrl;
2923         u8 reg_idx = ring->reg_idx;
2924
2925         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2928 }
2929
2930 /**
2931  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932  * @adapter:    address of board private structure
2933  * @index:      index of ring to set
2934  **/
2935 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2936                                    struct ixgbe_ring *ring)
2937 {
2938         struct ixgbe_hw *hw = &adapter->hw;
2939         u32 rscctrl;
2940         int rx_buf_len;
2941         u8 reg_idx = ring->reg_idx;
2942
2943         if (!ring_is_rsc_enabled(ring))
2944                 return;
2945
2946         rx_buf_len = ring->rx_buf_len;
2947         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2948         rscctrl |= IXGBE_RSCCTL_RSCEN;
2949         /*
2950          * we must limit the number of descriptors so that the
2951          * total size of max desc * buf_len is not greater
2952          * than 65535
2953          */
2954         if (ring_is_ps_enabled(ring)) {
2955 #if (MAX_SKB_FRAGS > 16)
2956                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957 #elif (MAX_SKB_FRAGS > 8)
2958                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959 #elif (MAX_SKB_FRAGS > 4)
2960                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2961 #else
2962                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2963 #endif
2964         } else {
2965                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2969                 else
2970                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971         }
2972         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2973 }
2974
2975 /**
2976  *  ixgbe_set_uta - Set unicast filter table address
2977  *  @adapter: board private structure
2978  *
2979  *  The unicast table address is a register array of 32-bit registers.
2980  *  The table is meant to be used in a way similar to how the MTA is used
2981  *  however due to certain limitations in the hardware it is necessary to
2982  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2984  **/
2985 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2986 {
2987         struct ixgbe_hw *hw = &adapter->hw;
2988         int i;
2989
2990         /* The UTA table only exists on 82599 hardware and newer */
2991         if (hw->mac.type < ixgbe_mac_82599EB)
2992                 return;
2993
2994         /* we only need to do this if VMDq is enabled */
2995         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2996                 return;
2997
2998         for (i = 0; i < 128; i++)
2999                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3000 }
3001
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004                                        struct ixgbe_ring *ring)
3005 {
3006         struct ixgbe_hw *hw = &adapter->hw;
3007         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008         u32 rxdctl;
3009         u8 reg_idx = ring->reg_idx;
3010
3011         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012         if (hw->mac.type == ixgbe_mac_82598EB &&
3013             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014                 return;
3015
3016         do {
3017                 msleep(1);
3018                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021         if (!wait_loop) {
3022                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023                       "the polling period\n", reg_idx);
3024         }
3025 }
3026
3027 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3028                              struct ixgbe_ring *ring)
3029 {
3030         struct ixgbe_hw *hw = &adapter->hw;
3031         u64 rdba = ring->dma;
3032         u32 rxdctl;
3033         u8 reg_idx = ring->reg_idx;
3034
3035         /* disable queue to avoid issues while updating state */
3036         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3037         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
3038                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
3039         IXGBE_WRITE_FLUSH(hw);
3040
3041         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3042         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3043         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3044                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3045         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3046         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3047         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3048
3049         ixgbe_configure_srrctl(adapter, ring);
3050         ixgbe_configure_rscctl(adapter, ring);
3051
3052         if (hw->mac.type == ixgbe_mac_82598EB) {
3053                 /*
3054                  * enable cache line friendly hardware writes:
3055                  * PTHRESH=32 descriptors (half the internal cache),
3056                  * this also removes ugly rx_no_buffer_count increment
3057                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3058                  * WTHRESH=8 burst writeback up to two cache lines
3059                  */
3060                 rxdctl &= ~0x3FFFFF;
3061                 rxdctl |=  0x080420;
3062         }
3063
3064         /* enable receive descriptor ring */
3065         rxdctl |= IXGBE_RXDCTL_ENABLE;
3066         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3067
3068         ixgbe_rx_desc_queue_enable(adapter, ring);
3069         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3070 }
3071
3072 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3073 {
3074         struct ixgbe_hw *hw = &adapter->hw;
3075         int p;
3076
3077         /* PSRTYPE must be initialized in non 82598 adapters */
3078         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3079                       IXGBE_PSRTYPE_UDPHDR |
3080                       IXGBE_PSRTYPE_IPV4HDR |
3081                       IXGBE_PSRTYPE_L2HDR |
3082                       IXGBE_PSRTYPE_IPV6HDR;
3083
3084         if (hw->mac.type == ixgbe_mac_82598EB)
3085                 return;
3086
3087         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3088                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3089
3090         for (p = 0; p < adapter->num_rx_pools; p++)
3091                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3092                                 psrtype);
3093 }
3094
3095 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3096 {
3097         struct ixgbe_hw *hw = &adapter->hw;
3098         u32 gcr_ext;
3099         u32 vt_reg_bits;
3100         u32 reg_offset, vf_shift;
3101         u32 vmdctl;
3102
3103         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3104                 return;
3105
3106         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3107         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3108         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3109         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3110
3111         vf_shift = adapter->num_vfs % 32;
3112         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3113
3114         /* Enable only the PF's pool for Tx/Rx */
3115         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3116         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3117         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3118         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3119         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3120
3121         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3122         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3123
3124         /*
3125          * Set up VF register offsets for selected VT Mode,
3126          * i.e. 32 or 64 VFs for SR-IOV
3127          */
3128         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3129         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3130         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3131         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3132
3133         /* enable Tx loopback for VF/PF communication */
3134         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3135 }
3136
3137 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3138 {
3139         struct ixgbe_hw *hw = &adapter->hw;
3140         struct net_device *netdev = adapter->netdev;
3141         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3142         int rx_buf_len;
3143         struct ixgbe_ring *rx_ring;
3144         int i;
3145         u32 mhadd, hlreg0;
3146
3147         /* Decide whether to use packet split mode or not */
3148         /* Do not use packet split if we're in SR-IOV Mode */
3149         if (!adapter->num_vfs)
3150                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3151
3152         /* Set the RX buffer length according to the mode */
3153         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3154                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3155         } else {
3156                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3157                     (netdev->mtu <= ETH_DATA_LEN))
3158                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3159                 else
3160                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3161         }
3162
3163 #ifdef IXGBE_FCOE
3164         /* adjust max frame to be able to do baby jumbo for FCoE */
3165         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3166             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3167                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3168
3169 #endif /* IXGBE_FCOE */
3170         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3171         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3172                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3173                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3174
3175                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3176         }
3177
3178         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3179         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3180         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3181         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3182
3183         /*
3184          * Setup the HW Rx Head and Tail Descriptor Pointers and
3185          * the Base and Length of the Rx Descriptor Ring
3186          */
3187         for (i = 0; i < adapter->num_rx_queues; i++) {
3188                 rx_ring = adapter->rx_ring[i];
3189                 rx_ring->rx_buf_len = rx_buf_len;
3190
3191                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3192                         set_ring_ps_enabled(rx_ring);
3193                 else
3194                         clear_ring_ps_enabled(rx_ring);
3195
3196                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3197                         set_ring_rsc_enabled(rx_ring);
3198                 else
3199                         clear_ring_rsc_enabled(rx_ring);
3200
3201 #ifdef IXGBE_FCOE
3202                 if (netdev->features & NETIF_F_FCOE_MTU) {
3203                         struct ixgbe_ring_feature *f;
3204                         f = &adapter->ring_feature[RING_F_FCOE];
3205                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3206                                 clear_ring_ps_enabled(rx_ring);
3207                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3208                                         rx_ring->rx_buf_len =
3209                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3210                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3211                                    !ring_is_ps_enabled(rx_ring)) {
3212                                 rx_ring->rx_buf_len =
3213                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3214                         }
3215                 }
3216 #endif /* IXGBE_FCOE */
3217         }
3218 }
3219
3220 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3221 {
3222         struct ixgbe_hw *hw = &adapter->hw;
3223         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3224
3225         switch (hw->mac.type) {
3226         case ixgbe_mac_82598EB:
3227                 /*
3228                  * For VMDq support of different descriptor types or
3229                  * buffer sizes through the use of multiple SRRCTL
3230                  * registers, RDRXCTL.MVMEN must be set to 1
3231                  *
3232                  * also, the manual doesn't mention it clearly but DCA hints
3233                  * will only use queue 0's tags unless this bit is set.  Side
3234                  * effects of setting this bit are only that SRRCTL must be
3235                  * fully programmed [0..15]
3236                  */
3237                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3238                 break;
3239         case ixgbe_mac_82599EB:
3240         case ixgbe_mac_X540:
3241                 /* Disable RSC for ACK packets */
3242                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3243                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3244                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3245                 /* hardware requires some bits to be set by default */
3246                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3247                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3248                 break;
3249         default:
3250                 /* We should do nothing since we don't know this hardware */
3251                 return;
3252         }
3253
3254         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3255 }
3256
3257 /**
3258  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3259  * @adapter: board private structure
3260  *
3261  * Configure the Rx unit of the MAC after a reset.
3262  **/
3263 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3264 {
3265         struct ixgbe_hw *hw = &adapter->hw;
3266         int i;
3267         u32 rxctrl;
3268
3269         /* disable receives while setting up the descriptors */
3270         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3271         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3272
3273         ixgbe_setup_psrtype(adapter);
3274         ixgbe_setup_rdrxctl(adapter);
3275
3276         /* Program registers for the distribution of queues */
3277         ixgbe_setup_mrqc(adapter);
3278
3279         ixgbe_set_uta(adapter);
3280
3281         /* set_rx_buffer_len must be called before ring initialization */
3282         ixgbe_set_rx_buffer_len(adapter);
3283
3284         /*
3285          * Setup the HW Rx Head and Tail Descriptor Pointers and
3286          * the Base and Length of the Rx Descriptor Ring
3287          */
3288         for (i = 0; i < adapter->num_rx_queues; i++)
3289                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3290
3291         /* disable drop enable for 82598 parts */
3292         if (hw->mac.type == ixgbe_mac_82598EB)
3293                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3294
3295         /* enable all receives */
3296         rxctrl |= IXGBE_RXCTRL_RXEN;
3297         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3298 }
3299
3300 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3301 {
3302         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3303         struct ixgbe_hw *hw = &adapter->hw;
3304         int pool_ndx = adapter->num_vfs;
3305
3306         /* add VID to filter table */
3307         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3308         set_bit(vid, adapter->active_vlans);
3309 }
3310
3311 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3312 {
3313         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3314         struct ixgbe_hw *hw = &adapter->hw;
3315         int pool_ndx = adapter->num_vfs;
3316
3317         /* remove VID from filter table */
3318         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3319         clear_bit(vid, adapter->active_vlans);
3320 }
3321
3322 /**
3323  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3324  * @adapter: driver data
3325  */
3326 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3327 {
3328         struct ixgbe_hw *hw = &adapter->hw;
3329         u32 vlnctrl;
3330
3331         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3332         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3333         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3334 }
3335
3336 /**
3337  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3338  * @adapter: driver data
3339  */
3340 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3341 {
3342         struct ixgbe_hw *hw = &adapter->hw;
3343         u32 vlnctrl;
3344
3345         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3346         vlnctrl |= IXGBE_VLNCTRL_VFE;
3347         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3348         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3349 }
3350
3351 /**
3352  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3353  * @adapter: driver data
3354  */
3355 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3356 {
3357         struct ixgbe_hw *hw = &adapter->hw;
3358         u32 vlnctrl;
3359         int i, j;
3360
3361         switch (hw->mac.type) {
3362         case ixgbe_mac_82598EB:
3363                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3364                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3365                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3366                 break;
3367         case ixgbe_mac_82599EB:
3368         case ixgbe_mac_X540:
3369                 for (i = 0; i < adapter->num_rx_queues; i++) {
3370                         j = adapter->rx_ring[i]->reg_idx;
3371                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3372                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3373                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3374                 }
3375                 break;
3376         default:
3377                 break;
3378         }
3379 }
3380
3381 /**
3382  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3383  * @adapter: driver data
3384  */
3385 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3386 {
3387         struct ixgbe_hw *hw = &adapter->hw;
3388         u32 vlnctrl;
3389         int i, j;
3390
3391         switch (hw->mac.type) {
3392         case ixgbe_mac_82598EB:
3393                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3394                 vlnctrl |= IXGBE_VLNCTRL_VME;
3395                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3396                 break;
3397         case ixgbe_mac_82599EB:
3398         case ixgbe_mac_X540:
3399                 for (i = 0; i < adapter->num_rx_queues; i++) {
3400                         j = adapter->rx_ring[i]->reg_idx;
3401                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3402                         vlnctrl |= IXGBE_RXDCTL_VME;
3403                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3404                 }
3405                 break;
3406         default:
3407                 break;
3408         }
3409 }
3410
3411 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3412 {
3413         u16 vid;
3414
3415         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3416
3417         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3418                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3419 }
3420
3421 /**
3422  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3423  * @netdev: network interface device structure
3424  *
3425  * Writes unicast address list to the RAR table.
3426  * Returns: -ENOMEM on failure/insufficient address space
3427  *                0 on no addresses written
3428  *                X on writing X addresses to the RAR table
3429  **/
3430 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3431 {
3432         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3433         struct ixgbe_hw *hw = &adapter->hw;
3434         unsigned int vfn = adapter->num_vfs;
3435         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3436         int count = 0;
3437
3438         /* return ENOMEM indicating insufficient memory for addresses */
3439         if (netdev_uc_count(netdev) > rar_entries)
3440                 return -ENOMEM;
3441
3442         if (!netdev_uc_empty(netdev) && rar_entries) {
3443                 struct netdev_hw_addr *ha;
3444                 /* return error if we do not support writing to RAR table */
3445                 if (!hw->mac.ops.set_rar)
3446                         return -ENOMEM;
3447
3448                 netdev_for_each_uc_addr(ha, netdev) {
3449                         if (!rar_entries)
3450                                 break;
3451                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3452                                             vfn, IXGBE_RAH_AV);
3453                         count++;
3454                 }
3455         }
3456         /* write the addresses in reverse order to avoid write combining */
3457         for (; rar_entries > 0 ; rar_entries--)
3458                 hw->mac.ops.clear_rar(hw, rar_entries);
3459
3460         return count;
3461 }
3462
3463 /**
3464  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3465  * @netdev: network interface device structure
3466  *
3467  * The set_rx_method entry point is called whenever the unicast/multicast
3468  * address list or the network interface flags are updated.  This routine is
3469  * responsible for configuring the hardware for proper unicast, multicast and
3470  * promiscuous mode.
3471  **/
3472 void ixgbe_set_rx_mode(struct net_device *netdev)
3473 {
3474         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3475         struct ixgbe_hw *hw = &adapter->hw;
3476         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3477         int count;
3478
3479         /* Check for Promiscuous and All Multicast modes */
3480
3481         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3482
3483         /* set all bits that we expect to always be set */
3484         fctrl |= IXGBE_FCTRL_BAM;
3485         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3486         fctrl |= IXGBE_FCTRL_PMCF;
3487
3488         /* clear the bits we are changing the status of */
3489         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3490
3491         if (netdev->flags & IFF_PROMISC) {
3492                 hw->addr_ctrl.user_set_promisc = true;
3493                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3494                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3495                 /* don't hardware filter vlans in promisc mode */
3496                 ixgbe_vlan_filter_disable(adapter);
3497         } else {
3498                 if (netdev->flags & IFF_ALLMULTI) {
3499                         fctrl |= IXGBE_FCTRL_MPE;
3500                         vmolr |= IXGBE_VMOLR_MPE;
3501                 } else {
3502                         /*
3503                          * Write addresses to the MTA, if the attempt fails
3504                          * then we should just turn on promiscous mode so
3505                          * that we can at least receive multicast traffic
3506                          */
3507                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3508                         vmolr |= IXGBE_VMOLR_ROMPE;
3509                 }
3510                 ixgbe_vlan_filter_enable(adapter);
3511                 hw->addr_ctrl.user_set_promisc = false;
3512                 /*
3513                  * Write addresses to available RAR registers, if there is not
3514                  * sufficient space to store all the addresses then enable
3515                  * unicast promiscous mode
3516                  */
3517                 count = ixgbe_write_uc_addr_list(netdev);
3518                 if (count < 0) {
3519                         fctrl |= IXGBE_FCTRL_UPE;
3520                         vmolr |= IXGBE_VMOLR_ROPE;
3521                 }
3522         }
3523
3524         if (adapter->num_vfs) {
3525                 ixgbe_restore_vf_multicasts(adapter);
3526                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3527                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3528                            IXGBE_VMOLR_ROPE);
3529                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3530         }
3531
3532         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3533
3534         if (netdev->features & NETIF_F_HW_VLAN_RX)
3535                 ixgbe_vlan_strip_enable(adapter);
3536         else
3537                 ixgbe_vlan_strip_disable(adapter);
3538 }
3539
3540 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3541 {
3542         int q_idx;
3543         struct ixgbe_q_vector *q_vector;
3544         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3545
3546         /* legacy and MSI only use one vector */
3547         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3548                 q_vectors = 1;
3549
3550         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3551                 struct napi_struct *napi;
3552                 q_vector = adapter->q_vector[q_idx];
3553                 napi = &q_vector->napi;
3554                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3555                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3556                                 if (q_vector->txr_count == 1)
3557                                         napi->poll = &ixgbe_clean_txonly;
3558                                 else if (q_vector->rxr_count == 1)
3559                                         napi->poll = &ixgbe_clean_rxonly;
3560                         }
3561                 }
3562
3563                 napi_enable(napi);
3564         }
3565 }
3566
3567 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3568 {
3569         int q_idx;
3570         struct ixgbe_q_vector *q_vector;
3571         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3572
3573         /* legacy and MSI only use one vector */
3574         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3575                 q_vectors = 1;
3576
3577         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3578                 q_vector = adapter->q_vector[q_idx];
3579                 napi_disable(&q_vector->napi);
3580         }
3581 }
3582
3583 #ifdef CONFIG_IXGBE_DCB
3584 /*
3585  * ixgbe_configure_dcb - Configure DCB hardware
3586  * @adapter: ixgbe adapter struct
3587  *
3588  * This is called by the driver on open to configure the DCB hardware.
3589  * This is also called by the gennetlink interface when reconfiguring
3590  * the DCB state.
3591  */
3592 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3593 {
3594         struct ixgbe_hw *hw = &adapter->hw;
3595         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3596
3597         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3598                 if (hw->mac.type == ixgbe_mac_82598EB)
3599                         netif_set_gso_max_size(adapter->netdev, 65536);
3600                 return;
3601         }
3602
3603         if (hw->mac.type == ixgbe_mac_82598EB)
3604                 netif_set_gso_max_size(adapter->netdev, 32768);
3605
3606 #ifdef CONFIG_FCOE
3607         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3608                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3609 #endif
3610
3611         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3612                                         DCB_TX_CONFIG);
3613         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3614                                         DCB_RX_CONFIG);
3615
3616         /* Enable VLAN tag insert/strip */
3617         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3618
3619         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3620
3621         /* reconfigure the hardware */
3622         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3623 }
3624
3625 #endif
3626 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3627 {
3628         struct net_device *netdev = adapter->netdev;
3629         struct ixgbe_hw *hw = &adapter->hw;
3630         int i;
3631
3632 #ifdef CONFIG_IXGBE_DCB
3633         ixgbe_configure_dcb(adapter);
3634 #endif
3635
3636         ixgbe_set_rx_mode(netdev);
3637         ixgbe_restore_vlan(adapter);
3638
3639 #ifdef IXGBE_FCOE
3640         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3641                 ixgbe_configure_fcoe(adapter);
3642
3643 #endif /* IXGBE_FCOE */
3644         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3645                 for (i = 0; i < adapter->num_tx_queues; i++)
3646                         adapter->tx_ring[i]->atr_sample_rate =
3647                                                        adapter->atr_sample_rate;
3648                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3649         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3650                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3651         }
3652         ixgbe_configure_virtualization(adapter);
3653
3654         ixgbe_configure_tx(adapter);
3655         ixgbe_configure_rx(adapter);
3656 }
3657
3658 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3659 {
3660         switch (hw->phy.type) {
3661         case ixgbe_phy_sfp_avago:
3662         case ixgbe_phy_sfp_ftl:
3663         case ixgbe_phy_sfp_intel:
3664         case ixgbe_phy_sfp_unknown:
3665         case ixgbe_phy_sfp_passive_tyco:
3666         case ixgbe_phy_sfp_passive_unknown:
3667         case ixgbe_phy_sfp_active_unknown:
3668         case ixgbe_phy_sfp_ftl_active:
3669                 return true;
3670         default:
3671                 return false;
3672         }
3673 }
3674
3675 /**
3676  * ixgbe_sfp_link_config - set up SFP+ link
3677  * @adapter: pointer to private adapter struct
3678  **/
3679 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3680 {
3681         struct ixgbe_hw *hw = &adapter->hw;
3682
3683                 if (hw->phy.multispeed_fiber) {
3684                         /*
3685                          * In multispeed fiber setups, the device may not have
3686                          * had a physical connection when the driver loaded.
3687                          * If that's the case, the initial link configuration
3688                          * couldn't get the MAC into 10G or 1G mode, so we'll
3689                          * never have a link status change interrupt fire.
3690                          * We need to try and force an autonegotiation
3691                          * session, then bring up link.
3692                          */
3693                         hw->mac.ops.setup_sfp(hw);
3694                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3695                                 schedule_work(&adapter->multispeed_fiber_task);
3696                 } else {
3697                         /*
3698                          * Direct Attach Cu and non-multispeed fiber modules
3699                          * still need to be configured properly prior to
3700                          * attempting link.
3701                          */
3702                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3703                                 schedule_work(&adapter->sfp_config_module_task);
3704                 }
3705 }
3706
3707 /**
3708  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3709  * @hw: pointer to private hardware struct
3710  *
3711  * Returns 0 on success, negative on failure
3712  **/
3713 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3714 {
3715         u32 autoneg;
3716         bool negotiation, link_up = false;
3717         u32 ret = IXGBE_ERR_LINK_SETUP;
3718
3719         if (hw->mac.ops.check_link)
3720                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3721
3722         if (ret)
3723                 goto link_cfg_out;
3724
3725         if (hw->mac.ops.get_link_capabilities)
3726                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3727                                                         &negotiation);
3728         if (ret)
3729                 goto link_cfg_out;
3730
3731         if (hw->mac.ops.setup_link)
3732                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3733 link_cfg_out:
3734         return ret;
3735 }
3736
3737 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3738 {
3739         struct ixgbe_hw *hw = &adapter->hw;
3740         u32 gpie = 0;
3741
3742         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3743                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3744                        IXGBE_GPIE_OCD;
3745                 gpie |= IXGBE_GPIE_EIAME;
3746                 /*
3747                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3748                  * this saves a register write for every interrupt
3749                  */
3750                 switch (hw->mac.type) {
3751                 case ixgbe_mac_82598EB:
3752                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3753                         break;
3754                 case ixgbe_mac_82599EB:
3755                 case ixgbe_mac_X540:
3756                 default:
3757                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3758                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3759                         break;
3760                 }
3761         } else {
3762                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3763                  * specifically only auto mask tx and rx interrupts */
3764                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3765         }
3766
3767         /* XXX: to interrupt immediately for EICS writes, enable this */
3768         /* gpie |= IXGBE_GPIE_EIMEN; */
3769
3770         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3771                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3772                 gpie |= IXGBE_GPIE_VTMODE_64;
3773         }
3774
3775         /* Enable fan failure interrupt */
3776         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3777                 gpie |= IXGBE_SDP1_GPIEN;
3778
3779         if (hw->mac.type == ixgbe_mac_82599EB)
3780                 gpie |= IXGBE_SDP1_GPIEN;
3781                 gpie |= IXGBE_SDP2_GPIEN;
3782
3783         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3784 }
3785
3786 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3787 {
3788         struct ixgbe_hw *hw = &adapter->hw;
3789         int err;
3790         u32 ctrl_ext;
3791
3792         ixgbe_get_hw_control(adapter);
3793         ixgbe_setup_gpie(adapter);
3794
3795         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3796                 ixgbe_configure_msix(adapter);
3797         else
3798                 ixgbe_configure_msi_and_legacy(adapter);
3799
3800         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3801         if (hw->mac.ops.enable_tx_laser &&
3802             ((hw->phy.multispeed_fiber) ||
3803              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3804               (hw->mac.type == ixgbe_mac_82599EB))))
3805                 hw->mac.ops.enable_tx_laser(hw);
3806
3807         clear_bit(__IXGBE_DOWN, &adapter->state);
3808         ixgbe_napi_enable_all(adapter);
3809
3810         if (ixgbe_is_sfp(hw)) {
3811                 ixgbe_sfp_link_config(adapter);
3812         } else {
3813                 err = ixgbe_non_sfp_link_config(hw);
3814                 if (err)
3815                         e_err(probe, "link_config FAILED %d\n", err);
3816         }
3817
3818         /* clear any pending interrupts, may auto mask */
3819         IXGBE_READ_REG(hw, IXGBE_EICR);
3820         ixgbe_irq_enable(adapter, true, true);
3821
3822         /*
3823          * If this adapter has a fan, check to see if we had a failure
3824          * before we enabled the interrupt.
3825          */
3826         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3827                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3828                 if (esdp & IXGBE_ESDP_SDP1)
3829                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3830         }
3831
3832         /*
3833          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3834          * arrived before interrupts were enabled but after probe.  Such
3835          * devices wouldn't have their type identified yet. We need to
3836          * kick off the SFP+ module setup first, then try to bring up link.
3837          * If we're not hot-pluggable SFP+, we just need to configure link
3838          * and bring it up.
3839          */
3840         if (hw->phy.type == ixgbe_phy_unknown)
3841                 schedule_work(&adapter->sfp_config_module_task);
3842
3843         /* enable transmits */
3844         netif_tx_start_all_queues(adapter->netdev);
3845
3846         /* bring the link up in the watchdog, this could race with our first
3847          * link up interrupt but shouldn't be a problem */
3848         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3849         adapter->link_check_timeout = jiffies;
3850         mod_timer(&adapter->watchdog_timer, jiffies);
3851
3852         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3853         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3854         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3855         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3856
3857         return 0;
3858 }
3859
3860 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3861 {
3862         WARN_ON(in_interrupt());
3863         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3864                 msleep(1);
3865         ixgbe_down(adapter);
3866         /*
3867          * If SR-IOV enabled then wait a bit before bringing the adapter
3868          * back up to give the VFs time to respond to the reset.  The
3869          * two second wait is based upon the watchdog timer cycle in
3870          * the VF driver.
3871          */
3872         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3873                 msleep(2000);
3874         ixgbe_up(adapter);
3875         clear_bit(__IXGBE_RESETTING, &adapter->state);
3876 }
3877
3878 int ixgbe_up(struct ixgbe_adapter *adapter)
3879 {
3880         /* hardware has been reset, we need to reload some things */
3881         ixgbe_configure(adapter);
3882
3883         return ixgbe_up_complete(adapter);
3884 }
3885
3886 void ixgbe_reset(struct ixgbe_adapter *adapter)
3887 {
3888         struct ixgbe_hw *hw = &adapter->hw;
3889         int err;
3890
3891         err = hw->mac.ops.init_hw(hw);
3892         switch (err) {
3893         case 0:
3894         case IXGBE_ERR_SFP_NOT_PRESENT:
3895                 break;
3896         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3897                 e_dev_err("master disable timed out\n");
3898                 break;
3899         case IXGBE_ERR_EEPROM_VERSION:
3900                 /* We are running on a pre-production device, log a warning */
3901                 e_dev_warn("This device is a pre-production adapter/LOM. "
3902                            "Please be aware there may be issuesassociated with "
3903                            "your hardware.  If you are experiencing problems "
3904                            "please contact your Intel or hardware "
3905                            "representative who provided you with this "
3906                            "hardware.\n");
3907                 break;
3908         default:
3909                 e_dev_err("Hardware Error: %d\n", err);
3910         }
3911
3912         /* reprogram the RAR[0] in case user changed it. */
3913         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3914                             IXGBE_RAH_AV);
3915 }
3916
3917 /**
3918  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3919  * @rx_ring: ring to free buffers from
3920  **/
3921 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3922 {
3923         struct device *dev = rx_ring->dev;
3924         unsigned long size;
3925         u16 i;
3926
3927         /* ring already cleared, nothing to do */
3928         if (!rx_ring->rx_buffer_info)
3929                 return;
3930
3931         /* Free all the Rx ring sk_buffs */
3932         for (i = 0; i < rx_ring->count; i++) {
3933                 struct ixgbe_rx_buffer *rx_buffer_info;
3934
3935                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3936                 if (rx_buffer_info->dma) {
3937                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3938                                          rx_ring->rx_buf_len,
3939                                          DMA_FROM_DEVICE);
3940                         rx_buffer_info->dma = 0;
3941                 }
3942                 if (rx_buffer_info->skb) {
3943                         struct sk_buff *skb = rx_buffer_info->skb;
3944                         rx_buffer_info->skb = NULL;
3945                         do {
3946                                 struct sk_buff *this = skb;
3947                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3948                                         dma_unmap_single(dev,
3949                                                          IXGBE_RSC_CB(this)->dma,
3950                                                          rx_ring->rx_buf_len,
3951                                                          DMA_FROM_DEVICE);
3952                                         IXGBE_RSC_CB(this)->dma = 0;
3953                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3954                                 }
3955                                 skb = skb->prev;
3956                                 dev_kfree_skb(this);
3957                         } while (skb);
3958                 }
3959                 if (!rx_buffer_info->page)
3960                         continue;
3961                 if (rx_buffer_info->page_dma) {
3962                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3963                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3964                         rx_buffer_info->page_dma = 0;
3965                 }
3966                 put_page(rx_buffer_info->page);
3967                 rx_buffer_info->page = NULL;
3968                 rx_buffer_info->page_offset = 0;
3969         }
3970
3971         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3972         memset(rx_ring->rx_buffer_info, 0, size);
3973
3974         /* Zero out the descriptor ring */
3975         memset(rx_ring->desc, 0, rx_ring->size);
3976
3977         rx_ring->next_to_clean = 0;
3978         rx_ring->next_to_use = 0;
3979 }
3980
3981 /**
3982  * ixgbe_clean_tx_ring - Free Tx Buffers
3983  * @tx_ring: ring to be cleaned
3984  **/
3985 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3986 {
3987         struct ixgbe_tx_buffer *tx_buffer_info;
3988         unsigned long size;
3989         u16 i;
3990
3991         /* ring already cleared, nothing to do */
3992         if (!tx_ring->tx_buffer_info)
3993                 return;
3994
3995         /* Free all the Tx ring sk_buffs */
3996         for (i = 0; i < tx_ring->count; i++) {
3997                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3998                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3999         }
4000
4001         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4002         memset(tx_ring->tx_buffer_info, 0, size);
4003
4004         /* Zero out the descriptor ring */
4005         memset(tx_ring->desc, 0, tx_ring->size);
4006
4007         tx_ring->next_to_use = 0;
4008         tx_ring->next_to_clean = 0;
4009 }
4010
4011 /**
4012  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4013  * @adapter: board private structure
4014  **/
4015 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4016 {
4017         int i;
4018
4019         for (i = 0; i < adapter->num_rx_queues; i++)
4020                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4021 }
4022
4023 /**
4024  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4025  * @adapter: board private structure
4026  **/
4027 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4028 {
4029         int i;
4030
4031         for (i = 0; i < adapter->num_tx_queues; i++)
4032                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4033 }
4034
4035 void ixgbe_down(struct ixgbe_adapter *adapter)
4036 {
4037         struct net_device *netdev = adapter->netdev;
4038         struct ixgbe_hw *hw = &adapter->hw;
4039         u32 rxctrl;
4040         u32 txdctl;
4041         int i;
4042         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4043
4044         /* signal that we are down to the interrupt handler */
4045         set_bit(__IXGBE_DOWN, &adapter->state);
4046
4047         /* disable receive for all VFs and wait one second */
4048         if (adapter->num_vfs) {
4049                 /* ping all the active vfs to let them know we are going down */
4050                 ixgbe_ping_all_vfs(adapter);
4051
4052                 /* Disable all VFTE/VFRE TX/RX */
4053                 ixgbe_disable_tx_rx(adapter);
4054
4055                 /* Mark all the VFs as inactive */
4056                 for (i = 0 ; i < adapter->num_vfs; i++)
4057                         adapter->vfinfo[i].clear_to_send = 0;
4058         }
4059
4060         /* disable receives */
4061         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4062         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4063
4064         IXGBE_WRITE_FLUSH(hw);
4065         msleep(10);
4066
4067         netif_tx_stop_all_queues(netdev);
4068
4069         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4070         del_timer_sync(&adapter->sfp_timer);
4071         del_timer_sync(&adapter->watchdog_timer);
4072         cancel_work_sync(&adapter->watchdog_task);
4073
4074         netif_carrier_off(netdev);
4075         netif_tx_disable(netdev);
4076
4077         ixgbe_irq_disable(adapter);
4078
4079         ixgbe_napi_disable_all(adapter);
4080
4081         /* Cleanup the affinity_hint CPU mask memory and callback */
4082         for (i = 0; i < num_q_vectors; i++) {
4083                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4084                 /* clear the affinity_mask in the IRQ descriptor */
4085                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4086                 /* release the CPU mask memory */
4087                 free_cpumask_var(q_vector->affinity_mask);
4088         }
4089
4090         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4091             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4092                 cancel_work_sync(&adapter->fdir_reinit_task);
4093
4094         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4095                 cancel_work_sync(&adapter->check_overtemp_task);
4096
4097         /* disable transmits in the hardware now that interrupts are off */
4098         for (i = 0; i < adapter->num_tx_queues; i++) {
4099                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4100                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4101                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4102                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4103         }
4104         /* Disable the Tx DMA engine on 82599 */
4105         switch (hw->mac.type) {
4106         case ixgbe_mac_82599EB:
4107         case ixgbe_mac_X540:
4108                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4109                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4110                                  ~IXGBE_DMATXCTL_TE));
4111                 break;
4112         default:
4113                 break;
4114         }
4115
4116         /* clear n-tuple filters that are cached */
4117         ethtool_ntuple_flush(netdev);
4118
4119         if (!pci_channel_offline(adapter->pdev))
4120                 ixgbe_reset(adapter);
4121
4122         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4123         if (hw->mac.ops.disable_tx_laser &&
4124             ((hw->phy.multispeed_fiber) ||
4125              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4126               (hw->mac.type == ixgbe_mac_82599EB))))
4127                 hw->mac.ops.disable_tx_laser(hw);
4128
4129         ixgbe_clean_all_tx_rings(adapter);
4130         ixgbe_clean_all_rx_rings(adapter);
4131
4132 #ifdef CONFIG_IXGBE_DCA
4133         /* since we reset the hardware DCA settings were cleared */
4134         ixgbe_setup_dca(adapter);
4135 #endif
4136 }
4137
4138 /**
4139  * ixgbe_poll - NAPI Rx polling callback
4140  * @napi: structure for representing this polling device
4141  * @budget: how many packets driver is allowed to clean
4142  *
4143  * This function is used for legacy and MSI, NAPI mode
4144  **/
4145 static int ixgbe_poll(struct napi_struct *napi, int budget)
4146 {
4147         struct ixgbe_q_vector *q_vector =
4148                                 container_of(napi, struct ixgbe_q_vector, napi);
4149         struct ixgbe_adapter *adapter = q_vector->adapter;
4150         int tx_clean_complete, work_done = 0;
4151
4152 #ifdef CONFIG_IXGBE_DCA
4153         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4154                 ixgbe_update_dca(q_vector);
4155 #endif
4156
4157         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4158         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4159
4160         if (!tx_clean_complete)
4161                 work_done = budget;
4162
4163         /* If budget not fully consumed, exit the polling mode */
4164         if (work_done < budget) {
4165                 napi_complete(napi);
4166                 if (adapter->rx_itr_setting & 1)
4167                         ixgbe_set_itr(adapter);
4168                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4169                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4170         }
4171         return work_done;
4172 }
4173
4174 /**
4175  * ixgbe_tx_timeout - Respond to a Tx Hang
4176  * @netdev: network interface device structure
4177  **/
4178 static void ixgbe_tx_timeout(struct net_device *netdev)
4179 {
4180         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4181
4182         adapter->tx_timeout_count++;
4183
4184         /* Do the reset outside of interrupt context */
4185         schedule_work(&adapter->reset_task);
4186 }
4187
4188 static void ixgbe_reset_task(struct work_struct *work)
4189 {
4190         struct ixgbe_adapter *adapter;
4191         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4192
4193         /* If we're already down or resetting, just bail */
4194         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4195             test_bit(__IXGBE_RESETTING, &adapter->state))
4196                 return;
4197
4198         ixgbe_dump(adapter);
4199         netdev_err(adapter->netdev, "Reset adapter\n");
4200         ixgbe_reinit_locked(adapter);
4201 }
4202
4203 #ifdef CONFIG_IXGBE_DCB
4204 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4205 {
4206         bool ret = false;
4207         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4208
4209         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4210                 return ret;
4211
4212         f->mask = 0x7 << 3;
4213         adapter->num_rx_queues = f->indices;
4214         adapter->num_tx_queues = f->indices;
4215         ret = true;
4216
4217         return ret;
4218 }
4219 #endif
4220
4221 /**
4222  * ixgbe_set_rss_queues: Allocate queues for RSS
4223  * @adapter: board private structure to initialize
4224  *
4225  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4226  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4227  *
4228  **/
4229 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4230 {
4231         bool ret = false;
4232         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4233
4234         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4235                 f->mask = 0xF;
4236                 adapter->num_rx_queues = f->indices;
4237                 adapter->num_tx_queues = f->indices;
4238                 ret = true;
4239         } else {
4240                 ret = false;
4241         }
4242
4243         return ret;
4244 }
4245
4246 /**
4247  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4248  * @adapter: board private structure to initialize
4249  *
4250  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4251  * to the original CPU that initiated the Tx session.  This runs in addition
4252  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4253  * Rx load across CPUs using RSS.
4254  *
4255  **/
4256 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4257 {
4258         bool ret = false;
4259         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4260
4261         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4262         f_fdir->mask = 0;
4263
4264         /* Flow Director must have RSS enabled */
4265         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4266             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4267              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4268                 adapter->num_tx_queues = f_fdir->indices;
4269                 adapter->num_rx_queues = f_fdir->indices;
4270                 ret = true;
4271         } else {
4272                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4273                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4274         }
4275         return ret;
4276 }
4277
4278 #ifdef IXGBE_FCOE
4279 /**
4280  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4281  * @adapter: board private structure to initialize
4282  *
4283  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4284  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4285  * rx queues out of the max number of rx queues, instead, it is used as the
4286  * index of the first rx queue used by FCoE.
4287  *
4288  **/
4289 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4290 {
4291         bool ret = false;
4292         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4293
4294         f->indices = min((int)num_online_cpus(), f->indices);
4295         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4296                 adapter->num_rx_queues = 1;
4297                 adapter->num_tx_queues = 1;
4298 #ifdef CONFIG_IXGBE_DCB
4299                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4300                         e_info(probe, "FCoE enabled with DCB\n");
4301                         ixgbe_set_dcb_queues(adapter);
4302                 }
4303 #endif
4304                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4305                         e_info(probe, "FCoE enabled with RSS\n");
4306                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4307                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4308                                 ixgbe_set_fdir_queues(adapter);
4309                         else
4310                                 ixgbe_set_rss_queues(adapter);
4311                 }
4312                 /* adding FCoE rx rings to the end */
4313                 f->mask = adapter->num_rx_queues;
4314                 adapter->num_rx_queues += f->indices;
4315                 adapter->num_tx_queues += f->indices;
4316
4317                 ret = true;
4318         }
4319
4320         return ret;
4321 }
4322
4323 #endif /* IXGBE_FCOE */
4324 /**
4325  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4326  * @adapter: board private structure to initialize
4327  *
4328  * IOV doesn't actually use anything, so just NAK the
4329  * request for now and let the other queue routines
4330  * figure out what to do.
4331  */
4332 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4333 {
4334         return false;
4335 }
4336
4337 /*
4338  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4339  * @adapter: board private structure to initialize
4340  *
4341  * This is the top level queue allocation routine.  The order here is very
4342  * important, starting with the "most" number of features turned on at once,
4343  * and ending with the smallest set of features.  This way large combinations
4344  * can be allocated if they're turned on, and smaller combinations are the
4345  * fallthrough conditions.
4346  *
4347  **/
4348 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4349 {
4350         /* Start with base case */
4351         adapter->num_rx_queues = 1;
4352         adapter->num_tx_queues = 1;
4353         adapter->num_rx_pools = adapter->num_rx_queues;
4354         adapter->num_rx_queues_per_pool = 1;
4355
4356         if (ixgbe_set_sriov_queues(adapter))
4357                 goto done;
4358
4359 #ifdef IXGBE_FCOE
4360         if (ixgbe_set_fcoe_queues(adapter))
4361                 goto done;
4362
4363 #endif /* IXGBE_FCOE */
4364 #ifdef CONFIG_IXGBE_DCB
4365         if (ixgbe_set_dcb_queues(adapter))
4366                 goto done;
4367
4368 #endif
4369         if (ixgbe_set_fdir_queues(adapter))
4370                 goto done;
4371
4372         if (ixgbe_set_rss_queues(adapter))
4373                 goto done;
4374
4375         /* fallback to base case */
4376         adapter->num_rx_queues = 1;
4377         adapter->num_tx_queues = 1;
4378
4379 done:
4380         /* Notify the stack of the (possibly) reduced queue counts. */
4381         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4382         return netif_set_real_num_rx_queues(adapter->netdev,
4383                                             adapter->num_rx_queues);
4384 }
4385
4386 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4387                                        int vectors)
4388 {
4389         int err, vector_threshold;
4390
4391         /* We'll want at least 3 (vector_threshold):
4392          * 1) TxQ[0] Cleanup
4393          * 2) RxQ[0] Cleanup
4394          * 3) Other (Link Status Change, etc.)
4395          * 4) TCP Timer (optional)
4396          */
4397         vector_threshold = MIN_MSIX_COUNT;
4398
4399         /* The more we get, the more we will assign to Tx/Rx Cleanup
4400          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4401          * Right now, we simply care about how many we'll get; we'll
4402          * set them up later while requesting irq's.
4403          */
4404         while (vectors >= vector_threshold) {
4405                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4406                                       vectors);
4407                 if (!err) /* Success in acquiring all requested vectors. */
4408                         break;
4409                 else if (err < 0)
4410                         vectors = 0; /* Nasty failure, quit now */
4411                 else /* err == number of vectors we should try again with */
4412                         vectors = err;
4413         }
4414
4415         if (vectors < vector_threshold) {
4416                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4417                  * This just means we'll go with either a single MSI
4418                  * vector or fall back to legacy interrupts.
4419                  */
4420                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4421                              "Unable to allocate MSI-X interrupts\n");
4422                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4423                 kfree(adapter->msix_entries);
4424                 adapter->msix_entries = NULL;
4425         } else {
4426                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4427                 /*
4428                  * Adjust for only the vectors we'll use, which is minimum
4429                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4430                  * vectors we were allocated.
4431                  */
4432                 adapter->num_msix_vectors = min(vectors,
4433                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4434         }
4435 }
4436
4437 /**
4438  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4439  * @adapter: board private structure to initialize
4440  *
4441  * Cache the descriptor ring offsets for RSS to the assigned rings.
4442  *
4443  **/
4444 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4445 {
4446         int i;
4447
4448         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4449                 return false;
4450
4451         for (i = 0; i < adapter->num_rx_queues; i++)
4452                 adapter->rx_ring[i]->reg_idx = i;
4453         for (i = 0; i < adapter->num_tx_queues; i++)
4454                 adapter->tx_ring[i]->reg_idx = i;
4455
4456         return true;
4457 }
4458
4459 #ifdef CONFIG_IXGBE_DCB
4460 /**
4461  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4462  * @adapter: board private structure to initialize
4463  *
4464  * Cache the descriptor ring offsets for DCB to the assigned rings.
4465  *
4466  **/
4467 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4468 {
4469         int i;
4470         bool ret = false;
4471         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4472
4473         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4474                 return false;
4475
4476         /* the number of queues is assumed to be symmetric */
4477         switch (adapter->hw.mac.type) {
4478         case ixgbe_mac_82598EB:
4479                 for (i = 0; i < dcb_i; i++) {
4480                         adapter->rx_ring[i]->reg_idx = i << 3;
4481                         adapter->tx_ring[i]->reg_idx = i << 2;
4482                 }
4483                 ret = true;
4484                 break;
4485         case ixgbe_mac_82599EB:
4486         case ixgbe_mac_X540:
4487                 if (dcb_i == 8) {
4488                         /*
4489                          * Tx TC0 starts at: descriptor queue 0
4490                          * Tx TC1 starts at: descriptor queue 32
4491                          * Tx TC2 starts at: descriptor queue 64
4492                          * Tx TC3 starts at: descriptor queue 80
4493                          * Tx TC4 starts at: descriptor queue 96
4494                          * Tx TC5 starts at: descriptor queue 104
4495                          * Tx TC6 starts at: descriptor queue 112
4496                          * Tx TC7 starts at: descriptor queue 120
4497                          *
4498                          * Rx TC0-TC7 are offset by 16 queues each
4499                          */
4500                         for (i = 0; i < 3; i++) {
4501                                 adapter->tx_ring[i]->reg_idx = i << 5;
4502                                 adapter->rx_ring[i]->reg_idx = i << 4;
4503                         }
4504                         for ( ; i < 5; i++) {
4505                                 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4506                                 adapter->rx_ring[i]->reg_idx = i << 4;
4507                         }
4508                         for ( ; i < dcb_i; i++) {
4509                                 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4510                                 adapter->rx_ring[i]->reg_idx = i << 4;
4511                         }
4512                         ret = true;
4513                 } else if (dcb_i == 4) {
4514                         /*
4515                          * Tx TC0 starts at: descriptor queue 0
4516                          * Tx TC1 starts at: descriptor queue 64
4517                          * Tx TC2 starts at: descriptor queue 96
4518                          * Tx TC3 starts at: descriptor queue 112
4519                          *
4520                          * Rx TC0-TC3 are offset by 32 queues each
4521                          */
4522                         adapter->tx_ring[0]->reg_idx = 0;
4523                         adapter->tx_ring[1]->reg_idx = 64;
4524                         adapter->tx_ring[2]->reg_idx = 96;
4525                         adapter->tx_ring[3]->reg_idx = 112;
4526                         for (i = 0 ; i < dcb_i; i++)
4527                                 adapter->rx_ring[i]->reg_idx = i << 5;
4528                         ret = true;
4529                 }
4530                 break;
4531         default:
4532                 break;
4533         }
4534         return ret;
4535 }
4536 #endif
4537
4538 /**
4539  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4540  * @adapter: board private structure to initialize
4541  *
4542  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4543  *
4544  **/
4545 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4546 {
4547         int i;
4548         bool ret = false;
4549
4550         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4551             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4552              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4553                 for (i = 0; i < adapter->num_rx_queues; i++)
4554                         adapter->rx_ring[i]->reg_idx = i;
4555                 for (i = 0; i < adapter->num_tx_queues; i++)
4556                         adapter->tx_ring[i]->reg_idx = i;
4557                 ret = true;
4558         }
4559
4560         return ret;
4561 }
4562
4563 #ifdef IXGBE_FCOE
4564 /**
4565  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4566  * @adapter: board private structure to initialize
4567  *
4568  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4569  *
4570  */
4571 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4572 {
4573         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4574         int i;
4575         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4576
4577         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4578                 return false;
4579
4580 #ifdef CONFIG_IXGBE_DCB
4581         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4582                 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4583
4584                 ixgbe_cache_ring_dcb(adapter);
4585                 /* find out queues in TC for FCoE */
4586                 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4587                 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4588                 /*
4589                  * In 82599, the number of Tx queues for each traffic
4590                  * class for both 8-TC and 4-TC modes are:
4591                  * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4592                  * 8 TCs:  32  32  16  16   8   8   8   8
4593                  * 4 TCs:  64  64  32  32
4594                  * We have max 8 queues for FCoE, where 8 the is
4595                  * FCoE redirection table size. If TC for FCoE is
4596                  * less than or equal to TC3, we have enough queues
4597                  * to add max of 8 queues for FCoE, so we start FCoE
4598                  * Tx queue from the next one, i.e., reg_idx + 1.
4599                  * If TC for FCoE is above TC3, implying 8 TC mode,
4600                  * and we need 8 for FCoE, we have to take all queues
4601                  * in that traffic class for FCoE.
4602                  */
4603                 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4604                         fcoe_tx_i--;
4605         }
4606 #endif /* CONFIG_IXGBE_DCB */
4607         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4608                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4609                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4610                         ixgbe_cache_ring_fdir(adapter);
4611                 else
4612                         ixgbe_cache_ring_rss(adapter);
4613
4614                 fcoe_rx_i = f->mask;
4615                 fcoe_tx_i = f->mask;
4616         }
4617         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4618                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4619                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4620         }
4621         return true;
4622 }
4623
4624 #endif /* IXGBE_FCOE */
4625 /**
4626  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4627  * @adapter: board private structure to initialize
4628  *
4629  * SR-IOV doesn't use any descriptor rings but changes the default if
4630  * no other mapping is used.
4631  *
4632  */
4633 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4634 {
4635         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4636         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4637         if (adapter->num_vfs)
4638                 return true;
4639         else
4640                 return false;
4641 }
4642
4643 /**
4644  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4645  * @adapter: board private structure to initialize
4646  *
4647  * Once we know the feature-set enabled for the device, we'll cache
4648  * the register offset the descriptor ring is assigned to.
4649  *
4650  * Note, the order the various feature calls is important.  It must start with
4651  * the "most" features enabled at the same time, then trickle down to the
4652  * least amount of features turned on at once.
4653  **/
4654 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4655 {
4656         /* start with default case */
4657         adapter->rx_ring[0]->reg_idx = 0;
4658         adapter->tx_ring[0]->reg_idx = 0;
4659
4660         if (ixgbe_cache_ring_sriov(adapter))
4661                 return;
4662
4663 #ifdef IXGBE_FCOE
4664         if (ixgbe_cache_ring_fcoe(adapter))
4665                 return;
4666
4667 #endif /* IXGBE_FCOE */
4668 #ifdef CONFIG_IXGBE_DCB
4669         if (ixgbe_cache_ring_dcb(adapter))
4670                 return;
4671
4672 #endif
4673         if (ixgbe_cache_ring_fdir(adapter))
4674                 return;
4675
4676         if (ixgbe_cache_ring_rss(adapter))
4677                 return;
4678 }
4679
4680 /**
4681  * ixgbe_alloc_queues - Allocate memory for all rings
4682  * @adapter: board private structure to initialize
4683  *
4684  * We allocate one ring per queue at run-time since we don't know the
4685  * number of queues at compile-time.  The polling_netdev array is
4686  * intended for Multiqueue, but should work fine with a single queue.
4687  **/
4688 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4689 {
4690         int rx = 0, tx = 0, nid = adapter->node;
4691
4692         if (nid < 0 || !node_online(nid))
4693                 nid = first_online_node;
4694
4695         for (; tx < adapter->num_tx_queues; tx++) {
4696                 struct ixgbe_ring *ring;
4697
4698                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4699                 if (!ring)
4700                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4701                 if (!ring)
4702                         goto err_allocation;
4703                 ring->count = adapter->tx_ring_count;
4704                 ring->queue_index = tx;
4705                 ring->numa_node = nid;
4706                 ring->dev = &adapter->pdev->dev;
4707                 ring->netdev = adapter->netdev;
4708
4709                 adapter->tx_ring[tx] = ring;
4710         }
4711
4712         for (; rx < adapter->num_rx_queues; rx++) {
4713                 struct ixgbe_ring *ring;
4714
4715                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4716                 if (!ring)
4717                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4718                 if (!ring)
4719                         goto err_allocation;
4720                 ring->count = adapter->rx_ring_count;
4721                 ring->queue_index = rx;
4722                 ring->numa_node = nid;
4723                 ring->dev = &adapter->pdev->dev;
4724                 ring->netdev = adapter->netdev;
4725
4726                 adapter->rx_ring[rx] = ring;
4727         }
4728
4729         ixgbe_cache_ring_register(adapter);
4730
4731         return 0;
4732
4733 err_allocation:
4734         while (tx)
4735                 kfree(adapter->tx_ring[--tx]);
4736
4737         while (rx)
4738                 kfree(adapter->rx_ring[--rx]);
4739         return -ENOMEM;
4740 }
4741
4742 /**
4743  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4744  * @adapter: board private structure to initialize
4745  *
4746  * Attempt to configure the interrupts using the best available
4747  * capabilities of the hardware and the kernel.
4748  **/
4749 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4750 {
4751         struct ixgbe_hw *hw = &adapter->hw;
4752         int err = 0;
4753         int vector, v_budget;
4754
4755         /*
4756          * It's easy to be greedy for MSI-X vectors, but it really
4757          * doesn't do us much good if we have a lot more vectors
4758          * than CPU's.  So let's be conservative and only ask for
4759          * (roughly) the same number of vectors as there are CPU's.
4760          */
4761         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4762                        (int)num_online_cpus()) + NON_Q_VECTORS;
4763
4764         /*
4765          * At the same time, hardware can only support a maximum of
4766          * hw.mac->max_msix_vectors vectors.  With features
4767          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4768          * descriptor queues supported by our device.  Thus, we cap it off in
4769          * those rare cases where the cpu count also exceeds our vector limit.
4770          */
4771         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4772
4773         /* A failure in MSI-X entry allocation isn't fatal, but it does
4774          * mean we disable MSI-X capabilities of the adapter. */
4775         adapter->msix_entries = kcalloc(v_budget,
4776                                         sizeof(struct msix_entry), GFP_KERNEL);
4777         if (adapter->msix_entries) {
4778                 for (vector = 0; vector < v_budget; vector++)
4779                         adapter->msix_entries[vector].entry = vector;
4780
4781                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4782
4783                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4784                         goto out;
4785         }
4786
4787         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4788         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4789         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4790         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4791         adapter->atr_sample_rate = 0;
4792         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4793                 ixgbe_disable_sriov(adapter);
4794
4795         err = ixgbe_set_num_queues(adapter);
4796         if (err)
4797                 return err;
4798
4799         err = pci_enable_msi(adapter->pdev);
4800         if (!err) {
4801                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4802         } else {
4803                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4804                              "Unable to allocate MSI interrupt, "
4805                              "falling back to legacy.  Error: %d\n", err);
4806                 /* reset err */
4807                 err = 0;
4808         }
4809
4810 out:
4811         return err;
4812 }
4813
4814 /**
4815  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4816  * @adapter: board private structure to initialize
4817  *
4818  * We allocate one q_vector per queue interrupt.  If allocation fails we
4819  * return -ENOMEM.
4820  **/
4821 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4822 {
4823         int q_idx, num_q_vectors;
4824         struct ixgbe_q_vector *q_vector;
4825         int napi_vectors;
4826         int (*poll)(struct napi_struct *, int);
4827
4828         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4829                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4830                 napi_vectors = adapter->num_rx_queues;
4831                 poll = &ixgbe_clean_rxtx_many;
4832         } else {
4833                 num_q_vectors = 1;
4834                 napi_vectors = 1;
4835                 poll = &ixgbe_poll;
4836         }
4837
4838         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4839                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4840                                         GFP_KERNEL, adapter->node);
4841                 if (!q_vector)
4842                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4843                                            GFP_KERNEL);
4844                 if (!q_vector)
4845                         goto err_out;
4846                 q_vector->adapter = adapter;
4847                 if (q_vector->txr_count && !q_vector->rxr_count)
4848                         q_vector->eitr = adapter->tx_eitr_param;
4849                 else
4850                         q_vector->eitr = adapter->rx_eitr_param;
4851                 q_vector->v_idx = q_idx;
4852                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4853                 adapter->q_vector[q_idx] = q_vector;
4854         }
4855
4856         return 0;
4857
4858 err_out:
4859         while (q_idx) {
4860                 q_idx--;
4861                 q_vector = adapter->q_vector[q_idx];
4862                 netif_napi_del(&q_vector->napi);
4863                 kfree(q_vector);
4864                 adapter->q_vector[q_idx] = NULL;
4865         }
4866         return -ENOMEM;
4867 }
4868
4869 /**
4870  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4871  * @adapter: board private structure to initialize
4872  *
4873  * This function frees the memory allocated to the q_vectors.  In addition if
4874  * NAPI is enabled it will delete any references to the NAPI struct prior
4875  * to freeing the q_vector.
4876  **/
4877 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4878 {
4879         int q_idx, num_q_vectors;
4880
4881         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4882                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4883         else
4884                 num_q_vectors = 1;
4885
4886         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4887                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4888                 adapter->q_vector[q_idx] = NULL;
4889                 netif_napi_del(&q_vector->napi);
4890                 kfree(q_vector);
4891         }
4892 }
4893
4894 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4895 {
4896         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4897                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4898                 pci_disable_msix(adapter->pdev);
4899                 kfree(adapter->msix_entries);
4900                 adapter->msix_entries = NULL;
4901         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4902                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4903                 pci_disable_msi(adapter->pdev);
4904         }
4905 }
4906
4907 /**
4908  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4909  * @adapter: board private structure to initialize
4910  *
4911  * We determine which interrupt scheme to use based on...
4912  * - Kernel support (MSI, MSI-X)
4913  *   - which can be user-defined (via MODULE_PARAM)
4914  * - Hardware queue count (num_*_queues)
4915  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4916  **/
4917 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4918 {
4919         int err;
4920
4921         /* Number of supported queues */
4922         err = ixgbe_set_num_queues(adapter);
4923         if (err)
4924                 return err;
4925
4926         err = ixgbe_set_interrupt_capability(adapter);
4927         if (err) {
4928                 e_dev_err("Unable to setup interrupt capabilities\n");
4929                 goto err_set_interrupt;
4930         }
4931
4932         err = ixgbe_alloc_q_vectors(adapter);
4933         if (err) {
4934                 e_dev_err("Unable to allocate memory for queue vectors\n");
4935                 goto err_alloc_q_vectors;
4936         }
4937
4938         err = ixgbe_alloc_queues(adapter);
4939         if (err) {
4940                 e_dev_err("Unable to allocate memory for queues\n");
4941                 goto err_alloc_queues;
4942         }
4943
4944         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4945                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4946                    adapter->num_rx_queues, adapter->num_tx_queues);
4947
4948         set_bit(__IXGBE_DOWN, &adapter->state);
4949
4950         return 0;
4951
4952 err_alloc_queues:
4953         ixgbe_free_q_vectors(adapter);
4954 err_alloc_q_vectors:
4955         ixgbe_reset_interrupt_capability(adapter);
4956 err_set_interrupt:
4957         return err;
4958 }
4959
4960 static void ring_free_rcu(struct rcu_head *head)
4961 {
4962         kfree(container_of(head, struct ixgbe_ring, rcu));
4963 }
4964
4965 /**
4966  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4967  * @adapter: board private structure to clear interrupt scheme on
4968  *
4969  * We go through and clear interrupt specific resources and reset the structure
4970  * to pre-load conditions
4971  **/
4972 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4973 {
4974         int i;
4975
4976         for (i = 0; i < adapter->num_tx_queues; i++) {
4977                 kfree(adapter->tx_ring[i]);
4978                 adapter->tx_ring[i] = NULL;
4979         }
4980         for (i = 0; i < adapter->num_rx_queues; i++) {
4981                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4982
4983                 /* ixgbe_get_stats64() might access this ring, we must wait
4984                  * a grace period before freeing it.
4985                  */
4986                 call_rcu(&ring->rcu, ring_free_rcu);
4987                 adapter->rx_ring[i] = NULL;
4988         }
4989
4990         ixgbe_free_q_vectors(adapter);
4991         ixgbe_reset_interrupt_capability(adapter);
4992 }
4993
4994 /**
4995  * ixgbe_sfp_timer - worker thread to find a missing module
4996  * @data: pointer to our adapter struct
4997  **/
4998 static void ixgbe_sfp_timer(unsigned long data)
4999 {
5000         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5001
5002         /*
5003          * Do the sfp_timer outside of interrupt context due to the
5004          * delays that sfp+ detection requires
5005          */
5006         schedule_work(&adapter->sfp_task);
5007 }
5008
5009 /**
5010  * ixgbe_sfp_task - worker thread to find a missing module
5011  * @work: pointer to work_struct containing our data
5012  **/
5013 static void ixgbe_sfp_task(struct work_struct *work)
5014 {
5015         struct ixgbe_adapter *adapter = container_of(work,
5016                                                      struct ixgbe_adapter,
5017                                                      sfp_task);
5018         struct ixgbe_hw *hw = &adapter->hw;
5019
5020         if ((hw->phy.type == ixgbe_phy_nl) &&
5021             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5022                 s32 ret = hw->phy.ops.identify_sfp(hw);
5023                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5024                         goto reschedule;
5025                 ret = hw->phy.ops.reset(hw);
5026                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5027                         e_dev_err("failed to initialize because an unsupported "
5028                                   "SFP+ module type was detected.\n");
5029                         e_dev_err("Reload the driver after installing a "
5030                                   "supported module.\n");
5031                         unregister_netdev(adapter->netdev);
5032                 } else {
5033                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5034                 }
5035                 /* don't need this routine any more */
5036                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5037         }
5038         return;
5039 reschedule:
5040         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5041                 mod_timer(&adapter->sfp_timer,
5042                           round_jiffies(jiffies + (2 * HZ)));
5043 }
5044
5045 /**
5046  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5047  * @adapter: board private structure to initialize
5048  *
5049  * ixgbe_sw_init initializes the Adapter private data structure.
5050  * Fields are initialized based on PCI device information and
5051  * OS network device settings (MTU size).
5052  **/
5053 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5054 {
5055         struct ixgbe_hw *hw = &adapter->hw;
5056         struct pci_dev *pdev = adapter->pdev;
5057         struct net_device *dev = adapter->netdev;
5058         unsigned int rss;
5059 #ifdef CONFIG_IXGBE_DCB
5060         int j;
5061         struct tc_configuration *tc;
5062 #endif
5063         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5064
5065         /* PCI config space info */
5066
5067         hw->vendor_id = pdev->vendor;
5068         hw->device_id = pdev->device;
5069         hw->revision_id = pdev->revision;
5070         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5071         hw->subsystem_device_id = pdev->subsystem_device;
5072
5073         /* Set capability flags */
5074         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5075         adapter->ring_feature[RING_F_RSS].indices = rss;
5076         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5077         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5078         switch (hw->mac.type) {
5079         case ixgbe_mac_82598EB:
5080                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5081                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5082                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5083                 break;
5084         case ixgbe_mac_82599EB:
5085         case ixgbe_mac_X540:
5086                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5087                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5088                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5089                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5090                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5091                 if (dev->features & NETIF_F_NTUPLE) {
5092                         /* Flow Director perfect filter enabled */
5093                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5094                         adapter->atr_sample_rate = 0;
5095                         spin_lock_init(&adapter->fdir_perfect_lock);
5096                 } else {
5097                         /* Flow Director hash filters enabled */
5098                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5099                         adapter->atr_sample_rate = 20;
5100                 }
5101                 adapter->ring_feature[RING_F_FDIR].indices =
5102                                                          IXGBE_MAX_FDIR_INDICES;
5103                 adapter->fdir_pballoc = 0;
5104 #ifdef IXGBE_FCOE
5105                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5106                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5107                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5108 #ifdef CONFIG_IXGBE_DCB
5109                 /* Default traffic class to use for FCoE */
5110                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5111                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5112 #endif
5113 #endif /* IXGBE_FCOE */
5114                 break;
5115         default:
5116                 break;
5117         }
5118
5119 #ifdef CONFIG_IXGBE_DCB
5120         /* Configure DCB traffic classes */
5121         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5122                 tc = &adapter->dcb_cfg.tc_config[j];
5123                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5124                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5125                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5126                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5127                 tc->dcb_pfc = pfc_disabled;
5128         }
5129         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5130         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5131         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5132         adapter->dcb_cfg.pfc_mode_enable = false;
5133         adapter->dcb_cfg.round_robin_enable = false;
5134         adapter->dcb_set_bitmap = 0x00;
5135         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5136                            adapter->ring_feature[RING_F_DCB].indices);
5137
5138 #endif
5139
5140         /* default flow control settings */
5141         hw->fc.requested_mode = ixgbe_fc_full;
5142         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5143 #ifdef CONFIG_DCB
5144         adapter->last_lfc_mode = hw->fc.current_mode;
5145 #endif
5146         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5147         hw->fc.low_water = FC_LOW_WATER(max_frame);
5148         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5149         hw->fc.send_xon = true;
5150         hw->fc.disable_fc_autoneg = false;
5151
5152         /* enable itr by default in dynamic mode */
5153         adapter->rx_itr_setting = 1;
5154         adapter->rx_eitr_param = 20000;
5155         adapter->tx_itr_setting = 1;
5156         adapter->tx_eitr_param = 10000;
5157
5158         /* set defaults for eitr in MegaBytes */
5159         adapter->eitr_low = 10;
5160         adapter->eitr_high = 20;
5161
5162         /* set default ring sizes */
5163         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5164         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5165
5166         /* initialize eeprom parameters */
5167         if (ixgbe_init_eeprom_params_generic(hw)) {
5168                 e_dev_err("EEPROM initialization failed\n");
5169                 return -EIO;
5170         }
5171
5172         /* enable rx csum by default */
5173         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5174
5175         /* get assigned NUMA node */
5176         adapter->node = dev_to_node(&pdev->dev);
5177
5178         set_bit(__IXGBE_DOWN, &adapter->state);
5179
5180         return 0;
5181 }
5182
5183 /**
5184  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5185  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5186  *
5187  * Return 0 on success, negative on failure
5188  **/
5189 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5190 {
5191         struct device *dev = tx_ring->dev;
5192         int size;
5193
5194         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5195         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5196         if (!tx_ring->tx_buffer_info)
5197                 tx_ring->tx_buffer_info = vzalloc(size);
5198         if (!tx_ring->tx_buffer_info)
5199                 goto err;
5200
5201         /* round up to nearest 4K */
5202         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5203         tx_ring->size = ALIGN(tx_ring->size, 4096);
5204
5205         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5206                                            &tx_ring->dma, GFP_KERNEL);
5207         if (!tx_ring->desc)
5208                 goto err;
5209
5210         tx_ring->next_to_use = 0;
5211         tx_ring->next_to_clean = 0;
5212         tx_ring->work_limit = tx_ring->count;
5213         return 0;
5214
5215 err:
5216         vfree(tx_ring->tx_buffer_info);
5217         tx_ring->tx_buffer_info = NULL;
5218         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5219         return -ENOMEM;
5220 }
5221
5222 /**
5223  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5224  * @adapter: board private structure
5225  *
5226  * If this function returns with an error, then it's possible one or
5227  * more of the rings is populated (while the rest are not).  It is the
5228  * callers duty to clean those orphaned rings.
5229  *
5230  * Return 0 on success, negative on failure
5231  **/
5232 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5233 {
5234         int i, err = 0;
5235
5236         for (i = 0; i < adapter->num_tx_queues; i++) {
5237                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5238                 if (!err)
5239                         continue;
5240                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5241                 break;
5242         }
5243
5244         return err;
5245 }
5246
5247 /**
5248  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5249  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5250  *
5251  * Returns 0 on success, negative on failure
5252  **/
5253 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5254 {
5255         struct device *dev = rx_ring->dev;
5256         int size;
5257
5258         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5259         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5260         if (!rx_ring->rx_buffer_info)
5261                 rx_ring->rx_buffer_info = vzalloc(size);
5262         if (!rx_ring->rx_buffer_info)
5263                 goto err;
5264
5265         /* Round up to nearest 4K */
5266         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5267         rx_ring->size = ALIGN(rx_ring->size, 4096);
5268
5269         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5270                                            &rx_ring->dma, GFP_KERNEL);
5271
5272         if (!rx_ring->desc)
5273                 goto err;
5274
5275         rx_ring->next_to_clean = 0;
5276         rx_ring->next_to_use = 0;
5277
5278         return 0;
5279 err:
5280         vfree(rx_ring->rx_buffer_info);
5281         rx_ring->rx_buffer_info = NULL;
5282         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5283         return -ENOMEM;
5284 }
5285
5286 /**
5287  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5288  * @adapter: board private structure
5289  *
5290  * If this function returns with an error, then it's possible one or
5291  * more of the rings is populated (while the rest are not).  It is the
5292  * callers duty to clean those orphaned rings.
5293  *
5294  * Return 0 on success, negative on failure
5295  **/
5296 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5297 {
5298         int i, err = 0;
5299
5300         for (i = 0; i < adapter->num_rx_queues; i++) {
5301                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5302                 if (!err)
5303                         continue;
5304                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5305                 break;
5306         }
5307
5308         return err;
5309 }
5310
5311 /**
5312  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5313  * @tx_ring: Tx descriptor ring for a specific queue
5314  *
5315  * Free all transmit software resources
5316  **/
5317 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5318 {
5319         ixgbe_clean_tx_ring(tx_ring);
5320
5321         vfree(tx_ring->tx_buffer_info);
5322         tx_ring->tx_buffer_info = NULL;
5323
5324         /* if not set, then don't free */
5325         if (!tx_ring->desc)
5326                 return;
5327
5328         dma_free_coherent(tx_ring->dev, tx_ring->size,
5329                           tx_ring->desc, tx_ring->dma);
5330
5331         tx_ring->desc = NULL;
5332 }
5333
5334 /**
5335  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5336  * @adapter: board private structure
5337  *
5338  * Free all transmit software resources
5339  **/
5340 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5341 {
5342         int i;
5343
5344         for (i = 0; i < adapter->num_tx_queues; i++)
5345                 if (adapter->tx_ring[i]->desc)
5346                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5347 }
5348
5349 /**
5350  * ixgbe_free_rx_resources - Free Rx Resources
5351  * @rx_ring: ring to clean the resources from
5352  *
5353  * Free all receive software resources
5354  **/
5355 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5356 {
5357         ixgbe_clean_rx_ring(rx_ring);
5358
5359         vfree(rx_ring->rx_buffer_info);
5360         rx_ring->rx_buffer_info = NULL;
5361
5362         /* if not set, then don't free */
5363         if (!rx_ring->desc)
5364                 return;
5365
5366         dma_free_coherent(rx_ring->dev, rx_ring->size,
5367                           rx_ring->desc, rx_ring->dma);
5368
5369         rx_ring->desc = NULL;
5370 }
5371
5372 /**
5373  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5374  * @adapter: board private structure
5375  *
5376  * Free all receive software resources
5377  **/
5378 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5379 {
5380         int i;
5381
5382         for (i = 0; i < adapter->num_rx_queues; i++)
5383                 if (adapter->rx_ring[i]->desc)
5384                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5385 }
5386
5387 /**
5388  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5389  * @netdev: network interface device structure
5390  * @new_mtu: new value for maximum frame size
5391  *
5392  * Returns 0 on success, negative on failure
5393  **/
5394 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5395 {
5396         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5397         struct ixgbe_hw *hw = &adapter->hw;
5398         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5399
5400         /* MTU < 68 is an error and causes problems on some kernels */
5401         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5402                 return -EINVAL;
5403
5404         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5405         /* must set new MTU before calling down or up */
5406         netdev->mtu = new_mtu;
5407
5408         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5409         hw->fc.low_water = FC_LOW_WATER(max_frame);
5410
5411         if (netif_running(netdev))
5412                 ixgbe_reinit_locked(adapter);
5413
5414         return 0;
5415 }
5416
5417 /**
5418  * ixgbe_open - Called when a network interface is made active
5419  * @netdev: network interface device structure
5420  *
5421  * Returns 0 on success, negative value on failure
5422  *
5423  * The open entry point is called when a network interface is made
5424  * active by the system (IFF_UP).  At this point all resources needed
5425  * for transmit and receive operations are allocated, the interrupt
5426  * handler is registered with the OS, the watchdog timer is started,
5427  * and the stack is notified that the interface is ready.
5428  **/
5429 static int ixgbe_open(struct net_device *netdev)
5430 {
5431         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5432         int err;
5433
5434         /* disallow open during test */
5435         if (test_bit(__IXGBE_TESTING, &adapter->state))
5436                 return -EBUSY;
5437
5438         netif_carrier_off(netdev);
5439
5440         /* allocate transmit descriptors */
5441         err = ixgbe_setup_all_tx_resources(adapter);
5442         if (err)
5443                 goto err_setup_tx;
5444
5445         /* allocate receive descriptors */
5446         err = ixgbe_setup_all_rx_resources(adapter);
5447         if (err)
5448                 goto err_setup_rx;
5449
5450         ixgbe_configure(adapter);
5451
5452         err = ixgbe_request_irq(adapter);
5453         if (err)
5454                 goto err_req_irq;
5455
5456         err = ixgbe_up_complete(adapter);
5457         if (err)
5458                 goto err_up;
5459
5460         netif_tx_start_all_queues(netdev);
5461
5462         return 0;
5463
5464 err_up:
5465         ixgbe_release_hw_control(adapter);
5466         ixgbe_free_irq(adapter);
5467 err_req_irq:
5468 err_setup_rx:
5469         ixgbe_free_all_rx_resources(adapter);
5470 err_setup_tx:
5471         ixgbe_free_all_tx_resources(adapter);
5472         ixgbe_reset(adapter);
5473
5474         return err;
5475 }
5476
5477 /**
5478  * ixgbe_close - Disables a network interface
5479  * @netdev: network interface device structure
5480  *
5481  * Returns 0, this is not allowed to fail
5482  *
5483  * The close entry point is called when an interface is de-activated
5484  * by the OS.  The hardware is still under the drivers control, but
5485  * needs to be disabled.  A global MAC reset is issued to stop the
5486  * hardware, and all transmit and receive resources are freed.
5487  **/
5488 static int ixgbe_close(struct net_device *netdev)
5489 {
5490         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5491
5492         ixgbe_down(adapter);
5493         ixgbe_free_irq(adapter);
5494
5495         ixgbe_free_all_tx_resources(adapter);
5496         ixgbe_free_all_rx_resources(adapter);
5497
5498         ixgbe_release_hw_control(adapter);
5499
5500         return 0;
5501 }
5502
5503 #ifdef CONFIG_PM
5504 static int ixgbe_resume(struct pci_dev *pdev)
5505 {
5506         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5507         struct net_device *netdev = adapter->netdev;
5508         u32 err;
5509
5510         pci_set_power_state(pdev, PCI_D0);
5511         pci_restore_state(pdev);
5512         /*
5513          * pci_restore_state clears dev->state_saved so call
5514          * pci_save_state to restore it.
5515          */
5516         pci_save_state(pdev);
5517
5518         err = pci_enable_device_mem(pdev);
5519         if (err) {
5520                 e_dev_err("Cannot enable PCI device from suspend\n");
5521                 return err;
5522         }
5523         pci_set_master(pdev);
5524
5525         pci_wake_from_d3(pdev, false);
5526
5527         err = ixgbe_init_interrupt_scheme(adapter);
5528         if (err) {
5529                 e_dev_err("Cannot initialize interrupts for device\n");
5530                 return err;
5531         }
5532
5533         ixgbe_reset(adapter);
5534
5535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5536
5537         if (netif_running(netdev)) {
5538                 err = ixgbe_open(netdev);
5539                 if (err)
5540                         return err;
5541         }
5542
5543         netif_device_attach(netdev);
5544
5545         return 0;
5546 }
5547 #endif /* CONFIG_PM */
5548
5549 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5550 {
5551         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5552         struct net_device *netdev = adapter->netdev;
5553         struct ixgbe_hw *hw = &adapter->hw;
5554         u32 ctrl, fctrl;
5555         u32 wufc = adapter->wol;
5556 #ifdef CONFIG_PM
5557         int retval = 0;
5558 #endif
5559
5560         netif_device_detach(netdev);
5561
5562         if (netif_running(netdev)) {
5563                 ixgbe_down(adapter);
5564                 ixgbe_free_irq(adapter);
5565                 ixgbe_free_all_tx_resources(adapter);
5566                 ixgbe_free_all_rx_resources(adapter);
5567         }
5568
5569         ixgbe_clear_interrupt_scheme(adapter);
5570
5571 #ifdef CONFIG_PM
5572         retval = pci_save_state(pdev);
5573         if (retval)
5574                 return retval;
5575
5576 #endif
5577         if (wufc) {
5578                 ixgbe_set_rx_mode(netdev);
5579
5580                 /* turn on all-multi mode if wake on multicast is enabled */
5581                 if (wufc & IXGBE_WUFC_MC) {
5582                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5583                         fctrl |= IXGBE_FCTRL_MPE;
5584                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5585                 }
5586
5587                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5588                 ctrl |= IXGBE_CTRL_GIO_DIS;
5589                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5590
5591                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5592         } else {
5593                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5594                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5595         }
5596
5597         switch (hw->mac.type) {
5598         case ixgbe_mac_82598EB:
5599                 pci_wake_from_d3(pdev, false);
5600                 break;
5601         case ixgbe_mac_82599EB:
5602         case ixgbe_mac_X540:
5603                 pci_wake_from_d3(pdev, !!wufc);
5604                 break;
5605         default:
5606                 break;
5607         }
5608
5609         *enable_wake = !!wufc;
5610
5611         ixgbe_release_hw_control(adapter);
5612
5613         pci_disable_device(pdev);
5614
5615         return 0;
5616 }
5617
5618 #ifdef CONFIG_PM
5619 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5620 {
5621         int retval;
5622         bool wake;
5623
5624         retval = __ixgbe_shutdown(pdev, &wake);
5625         if (retval)
5626                 return retval;
5627
5628         if (wake) {
5629                 pci_prepare_to_sleep(pdev);
5630         } else {
5631                 pci_wake_from_d3(pdev, false);
5632                 pci_set_power_state(pdev, PCI_D3hot);
5633         }
5634
5635         return 0;
5636 }
5637 #endif /* CONFIG_PM */
5638
5639 static void ixgbe_shutdown(struct pci_dev *pdev)
5640 {
5641         bool wake;
5642
5643         __ixgbe_shutdown(pdev, &wake);
5644
5645         if (system_state == SYSTEM_POWER_OFF) {
5646                 pci_wake_from_d3(pdev, wake);
5647                 pci_set_power_state(pdev, PCI_D3hot);
5648         }
5649 }
5650
5651 /**
5652  * ixgbe_update_stats - Update the board statistics counters.
5653  * @adapter: board private structure
5654  **/
5655 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5656 {
5657         struct net_device *netdev = adapter->netdev;
5658         struct ixgbe_hw *hw = &adapter->hw;
5659         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5660         u64 total_mpc = 0;
5661         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5662         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5663         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5664         u64 bytes = 0, packets = 0;
5665
5666         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5667             test_bit(__IXGBE_RESETTING, &adapter->state))
5668                 return;
5669
5670         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5671                 u64 rsc_count = 0;
5672                 u64 rsc_flush = 0;
5673                 for (i = 0; i < 16; i++)
5674                         adapter->hw_rx_no_dma_resources +=
5675                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5676                 for (i = 0; i < adapter->num_rx_queues; i++) {
5677                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5678                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5679                 }
5680                 adapter->rsc_total_count = rsc_count;
5681                 adapter->rsc_total_flush = rsc_flush;
5682         }
5683
5684         for (i = 0; i < adapter->num_rx_queues; i++) {
5685                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5686                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5687                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5688                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5689                 bytes += rx_ring->stats.bytes;
5690                 packets += rx_ring->stats.packets;
5691         }
5692         adapter->non_eop_descs = non_eop_descs;
5693         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5694         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5695         netdev->stats.rx_bytes = bytes;
5696         netdev->stats.rx_packets = packets;
5697
5698         bytes = 0;
5699         packets = 0;
5700         /* gather some stats to the adapter struct that are per queue */
5701         for (i = 0; i < adapter->num_tx_queues; i++) {
5702                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5703                 restart_queue += tx_ring->tx_stats.restart_queue;
5704                 tx_busy += tx_ring->tx_stats.tx_busy;
5705                 bytes += tx_ring->stats.bytes;
5706                 packets += tx_ring->stats.packets;
5707         }
5708         adapter->restart_queue = restart_queue;
5709         adapter->tx_busy = tx_busy;
5710         netdev->stats.tx_bytes = bytes;
5711         netdev->stats.tx_packets = packets;
5712
5713         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5714         for (i = 0; i < 8; i++) {
5715                 /* for packet buffers not used, the register should read 0 */
5716                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5717                 missed_rx += mpc;
5718                 hwstats->mpc[i] += mpc;
5719                 total_mpc += hwstats->mpc[i];
5720                 if (hw->mac.type == ixgbe_mac_82598EB)
5721                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5722                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5723                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5724                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5725                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5726                 switch (hw->mac.type) {
5727                 case ixgbe_mac_82598EB:
5728                         hwstats->pxonrxc[i] +=
5729                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5730                         break;
5731                 case ixgbe_mac_82599EB:
5732                 case ixgbe_mac_X540:
5733                         hwstats->pxonrxc[i] +=
5734                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5735                         break;
5736                 default:
5737                         break;
5738                 }
5739                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5740                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5741         }
5742         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5743         /* work around hardware counting issue */
5744         hwstats->gprc -= missed_rx;
5745
5746         ixgbe_update_xoff_received(adapter);
5747
5748         /* 82598 hardware only has a 32 bit counter in the high register */
5749         switch (hw->mac.type) {
5750         case ixgbe_mac_82598EB:
5751                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5752                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5753                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5754                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5755                 break;
5756         case ixgbe_mac_82599EB:
5757         case ixgbe_mac_X540:
5758                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5759                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5760                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5761                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5762                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5763                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5764                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5765                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5766                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5767 #ifdef IXGBE_FCOE
5768                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5769                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5770                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5771                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5772                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5773                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5774 #endif /* IXGBE_FCOE */
5775                 break;
5776         default:
5777                 break;
5778         }
5779         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5780         hwstats->bprc += bprc;
5781         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5782         if (hw->mac.type == ixgbe_mac_82598EB)
5783                 hwstats->mprc -= bprc;
5784         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5785         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5786         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5787         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5788         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5789         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5790         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5791         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5792         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5793         hwstats->lxontxc += lxon;
5794         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5795         hwstats->lxofftxc += lxoff;
5796         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5797         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5798         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5799         /*
5800          * 82598 errata - tx of flow control packets is included in tx counters
5801          */
5802         xon_off_tot = lxon + lxoff;
5803         hwstats->gptc -= xon_off_tot;
5804         hwstats->mptc -= xon_off_tot;
5805         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5806         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5807         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5808         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5809         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5810         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5811         hwstats->ptc64 -= xon_off_tot;
5812         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5813         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5814         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5815         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5816         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5817         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5818
5819         /* Fill out the OS statistics structure */
5820         netdev->stats.multicast = hwstats->mprc;
5821
5822         /* Rx Errors */
5823         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5824         netdev->stats.rx_dropped = 0;
5825         netdev->stats.rx_length_errors = hwstats->rlec;
5826         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5827         netdev->stats.rx_missed_errors = total_mpc;
5828 }
5829
5830 /**
5831  * ixgbe_watchdog - Timer Call-back
5832  * @data: pointer to adapter cast into an unsigned long
5833  **/
5834 static void ixgbe_watchdog(unsigned long data)
5835 {
5836         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5837         struct ixgbe_hw *hw = &adapter->hw;
5838         u64 eics = 0;
5839         int i;
5840
5841         /*
5842          *  Do the watchdog outside of interrupt context due to the lovely
5843          * delays that some of the newer hardware requires
5844          */
5845
5846         if (test_bit(__IXGBE_DOWN, &adapter->state))
5847                 goto watchdog_short_circuit;
5848
5849         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5850                 /*
5851                  * for legacy and MSI interrupts don't set any bits
5852                  * that are enabled for EIAM, because this operation
5853                  * would set *both* EIMS and EICS for any bit in EIAM
5854                  */
5855                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5856                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5857                 goto watchdog_reschedule;
5858         }
5859
5860         /* get one bit for every active tx/rx interrupt vector */
5861         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5862                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5863                 if (qv->rxr_count || qv->txr_count)
5864                         eics |= ((u64)1 << i);
5865         }
5866
5867         /* Cause software interrupt to ensure rx rings are cleaned */
5868         ixgbe_irq_rearm_queues(adapter, eics);
5869
5870 watchdog_reschedule:
5871         /* Reset the timer */
5872         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5873
5874 watchdog_short_circuit:
5875         schedule_work(&adapter->watchdog_task);
5876 }
5877
5878 /**
5879  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5880  * @work: pointer to work_struct containing our data
5881  **/
5882 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5883 {
5884         struct ixgbe_adapter *adapter = container_of(work,
5885                                                      struct ixgbe_adapter,
5886                                                      multispeed_fiber_task);
5887         struct ixgbe_hw *hw = &adapter->hw;
5888         u32 autoneg;
5889         bool negotiation;
5890
5891         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5892         autoneg = hw->phy.autoneg_advertised;
5893         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5894                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5895         hw->mac.autotry_restart = false;
5896         if (hw->mac.ops.setup_link)
5897                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5898         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5899         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5900 }
5901
5902 /**
5903  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5904  * @work: pointer to work_struct containing our data
5905  **/
5906 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5907 {
5908         struct ixgbe_adapter *adapter = container_of(work,
5909                                                      struct ixgbe_adapter,
5910                                                      sfp_config_module_task);
5911         struct ixgbe_hw *hw = &adapter->hw;
5912         u32 err;
5913
5914         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5915
5916         /* Time for electrical oscillations to settle down */
5917         msleep(100);
5918         err = hw->phy.ops.identify_sfp(hw);
5919
5920         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5921                 e_dev_err("failed to initialize because an unsupported SFP+ "
5922                           "module type was detected.\n");
5923                 e_dev_err("Reload the driver after installing a supported "
5924                           "module.\n");
5925                 unregister_netdev(adapter->netdev);
5926                 return;
5927         }
5928         hw->mac.ops.setup_sfp(hw);
5929
5930         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5931                 /* This will also work for DA Twinax connections */
5932                 schedule_work(&adapter->multispeed_fiber_task);
5933         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5934 }
5935
5936 /**
5937  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5938  * @work: pointer to work_struct containing our data
5939  **/
5940 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5941 {
5942         struct ixgbe_adapter *adapter = container_of(work,
5943                                                      struct ixgbe_adapter,
5944                                                      fdir_reinit_task);
5945         struct ixgbe_hw *hw = &adapter->hw;
5946         int i;
5947
5948         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5949                 for (i = 0; i < adapter->num_tx_queues; i++)
5950                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5951                                 &(adapter->tx_ring[i]->state));
5952         } else {
5953                 e_err(probe, "failed to finish FDIR re-initialization, "
5954                       "ignored adding FDIR ATR filters\n");
5955         }
5956         /* Done FDIR Re-initialization, enable transmits */
5957         netif_tx_start_all_queues(adapter->netdev);
5958 }
5959
5960 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5961
5962 /**
5963  * ixgbe_watchdog_task - worker thread to bring link up
5964  * @work: pointer to work_struct containing our data
5965  **/
5966 static void ixgbe_watchdog_task(struct work_struct *work)
5967 {
5968         struct ixgbe_adapter *adapter = container_of(work,
5969                                                      struct ixgbe_adapter,
5970                                                      watchdog_task);
5971         struct net_device *netdev = adapter->netdev;
5972         struct ixgbe_hw *hw = &adapter->hw;
5973         u32 link_speed;
5974         bool link_up;
5975         int i;
5976         struct ixgbe_ring *tx_ring;
5977         int some_tx_pending = 0;
5978
5979         mutex_lock(&ixgbe_watchdog_lock);
5980
5981         link_up = adapter->link_up;
5982         link_speed = adapter->link_speed;
5983
5984         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5985                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5986                 if (link_up) {
5987 #ifdef CONFIG_DCB
5988                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5989                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5990                                         hw->mac.ops.fc_enable(hw, i);
5991                         } else {
5992                                 hw->mac.ops.fc_enable(hw, 0);
5993                         }
5994 #else
5995                         hw->mac.ops.fc_enable(hw, 0);
5996 #endif
5997                 }
5998
5999                 if (link_up ||
6000                     time_after(jiffies, (adapter->link_check_timeout +
6001                                          IXGBE_TRY_LINK_TIMEOUT))) {
6002                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6003                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6004                 }
6005                 adapter->link_up = link_up;
6006                 adapter->link_speed = link_speed;
6007         }
6008
6009         if (link_up) {
6010                 if (!netif_carrier_ok(netdev)) {
6011                         bool flow_rx, flow_tx;
6012
6013                         switch (hw->mac.type) {
6014                         case ixgbe_mac_82598EB: {
6015                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6016                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6017                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6018                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6019                         }
6020                                 break;
6021                         case ixgbe_mac_82599EB:
6022                         case ixgbe_mac_X540: {
6023                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6024                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6025                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6026                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6027                         }
6028                                 break;
6029                         default:
6030                                 flow_tx = false;
6031                                 flow_rx = false;
6032                                 break;
6033                         }
6034
6035                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6036                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6037                                "10 Gbps" :
6038                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6039                                "1 Gbps" : "unknown speed")),
6040                                ((flow_rx && flow_tx) ? "RX/TX" :
6041                                (flow_rx ? "RX" :
6042                                (flow_tx ? "TX" : "None"))));
6043
6044                         netif_carrier_on(netdev);
6045                 } else {
6046                         /* Force detection of hung controller */
6047                         for (i = 0; i < adapter->num_tx_queues; i++) {
6048                                 tx_ring = adapter->tx_ring[i];
6049                                 set_check_for_tx_hang(tx_ring);
6050                         }
6051                 }
6052         } else {
6053                 adapter->link_up = false;
6054                 adapter->link_speed = 0;
6055                 if (netif_carrier_ok(netdev)) {
6056                         e_info(drv, "NIC Link is Down\n");
6057                         netif_carrier_off(netdev);
6058                 }
6059         }
6060
6061         if (!netif_carrier_ok(netdev)) {
6062                 for (i = 0; i < adapter->num_tx_queues; i++) {
6063                         tx_ring = adapter->tx_ring[i];
6064                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6065                                 some_tx_pending = 1;
6066                                 break;
6067                         }
6068                 }
6069
6070                 if (some_tx_pending) {
6071                         /* We've lost link, so the controller stops DMA,
6072                          * but we've got queued Tx work that's never going
6073                          * to get done, so reset controller to flush Tx.
6074                          * (Do the reset outside of interrupt context).
6075                          */
6076                          schedule_work(&adapter->reset_task);
6077                 }
6078         }
6079
6080         ixgbe_update_stats(adapter);
6081         mutex_unlock(&ixgbe_watchdog_lock);
6082 }
6083
6084 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6085                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6086                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6087 {
6088         struct ixgbe_adv_tx_context_desc *context_desc;
6089         unsigned int i;
6090         int err;
6091         struct ixgbe_tx_buffer *tx_buffer_info;
6092         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6093         u32 mss_l4len_idx, l4len;
6094
6095         if (skb_is_gso(skb)) {
6096                 if (skb_header_cloned(skb)) {
6097                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6098                         if (err)
6099                                 return err;
6100                 }
6101                 l4len = tcp_hdrlen(skb);
6102                 *hdr_len += l4len;
6103
6104                 if (protocol == htons(ETH_P_IP)) {
6105                         struct iphdr *iph = ip_hdr(skb);
6106                         iph->tot_len = 0;
6107                         iph->check = 0;
6108                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6109                                                                  iph->daddr, 0,
6110                                                                  IPPROTO_TCP,
6111                                                                  0);
6112                 } else if (skb_is_gso_v6(skb)) {
6113                         ipv6_hdr(skb)->payload_len = 0;
6114                         tcp_hdr(skb)->check =
6115                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6116                                              &ipv6_hdr(skb)->daddr,
6117                                              0, IPPROTO_TCP, 0);
6118                 }
6119
6120                 i = tx_ring->next_to_use;
6121
6122                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6123                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6124
6125                 /* VLAN MACLEN IPLEN */
6126                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6127                         vlan_macip_lens |=
6128                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6129                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6130                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6131                 *hdr_len += skb_network_offset(skb);
6132                 vlan_macip_lens |=
6133                     (skb_transport_header(skb) - skb_network_header(skb));
6134                 *hdr_len +=
6135                     (skb_transport_header(skb) - skb_network_header(skb));
6136                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6137                 context_desc->seqnum_seed = 0;
6138
6139                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6140                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6141                                    IXGBE_ADVTXD_DTYP_CTXT);
6142
6143                 if (protocol == htons(ETH_P_IP))
6144                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6145                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6146                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6147
6148                 /* MSS L4LEN IDX */
6149                 mss_l4len_idx =
6150                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6151                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6152                 /* use index 1 for TSO */
6153                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6154                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6155
6156                 tx_buffer_info->time_stamp = jiffies;
6157                 tx_buffer_info->next_to_watch = i;
6158
6159                 i++;
6160                 if (i == tx_ring->count)
6161                         i = 0;
6162                 tx_ring->next_to_use = i;
6163
6164                 return true;
6165         }
6166         return false;
6167 }
6168
6169 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6170                       __be16 protocol)
6171 {
6172         u32 rtn = 0;
6173
6174         switch (protocol) {
6175         case cpu_to_be16(ETH_P_IP):
6176                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6177                 switch (ip_hdr(skb)->protocol) {
6178                 case IPPROTO_TCP:
6179                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6180                         break;
6181                 case IPPROTO_SCTP:
6182                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6183                         break;
6184                 }
6185                 break;
6186         case cpu_to_be16(ETH_P_IPV6):
6187                 /* XXX what about other V6 headers?? */
6188                 switch (ipv6_hdr(skb)->nexthdr) {
6189                 case IPPROTO_TCP:
6190                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6191                         break;
6192                 case IPPROTO_SCTP:
6193                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6194                         break;
6195                 }
6196                 break;
6197         default:
6198                 if (unlikely(net_ratelimit()))
6199                         e_warn(probe, "partial checksum but proto=%x!\n",
6200                                protocol);
6201                 break;
6202         }
6203
6204         return rtn;
6205 }
6206
6207 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6208                           struct ixgbe_ring *tx_ring,
6209                           struct sk_buff *skb, u32 tx_flags,
6210                           __be16 protocol)
6211 {
6212         struct ixgbe_adv_tx_context_desc *context_desc;
6213         unsigned int i;
6214         struct ixgbe_tx_buffer *tx_buffer_info;
6215         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6216
6217         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6218             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6219                 i = tx_ring->next_to_use;
6220                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6221                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6222
6223                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6224                         vlan_macip_lens |=
6225                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6226                 vlan_macip_lens |= (skb_network_offset(skb) <<
6227                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6228                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6229                         vlan_macip_lens |= (skb_transport_header(skb) -
6230                                             skb_network_header(skb));
6231
6232                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6233                 context_desc->seqnum_seed = 0;
6234
6235                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6236                                     IXGBE_ADVTXD_DTYP_CTXT);
6237
6238                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6239                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6240
6241                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6242                 /* use index zero for tx checksum offload */
6243                 context_desc->mss_l4len_idx = 0;
6244
6245                 tx_buffer_info->time_stamp = jiffies;
6246                 tx_buffer_info->next_to_watch = i;
6247
6248                 i++;
6249                 if (i == tx_ring->count)
6250                         i = 0;
6251                 tx_ring->next_to_use = i;
6252
6253                 return true;
6254         }
6255
6256         return false;
6257 }
6258
6259 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6260                         struct ixgbe_ring *tx_ring,
6261                         struct sk_buff *skb, u32 tx_flags,
6262                         unsigned int first, const u8 hdr_len)
6263 {
6264         struct device *dev = tx_ring->dev;
6265         struct ixgbe_tx_buffer *tx_buffer_info;
6266         unsigned int len;
6267         unsigned int total = skb->len;
6268         unsigned int offset = 0, size, count = 0, i;
6269         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6270         unsigned int f;
6271         unsigned int bytecount = skb->len;
6272         u16 gso_segs = 1;
6273
6274         i = tx_ring->next_to_use;
6275
6276         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6277                 /* excluding fcoe_crc_eof for FCoE */
6278                 total -= sizeof(struct fcoe_crc_eof);
6279
6280         len = min(skb_headlen(skb), total);
6281         while (len) {
6282                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6283                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6284
6285                 tx_buffer_info->length = size;
6286                 tx_buffer_info->mapped_as_page = false;
6287                 tx_buffer_info->dma = dma_map_single(dev,
6288                                                      skb->data + offset,
6289                                                      size, DMA_TO_DEVICE);
6290                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6291                         goto dma_error;
6292                 tx_buffer_info->time_stamp = jiffies;
6293                 tx_buffer_info->next_to_watch = i;
6294
6295                 len -= size;
6296                 total -= size;
6297                 offset += size;
6298                 count++;
6299
6300                 if (len) {
6301                         i++;
6302                         if (i == tx_ring->count)
6303                                 i = 0;
6304                 }
6305         }
6306
6307         for (f = 0; f < nr_frags; f++) {
6308                 struct skb_frag_struct *frag;
6309
6310                 frag = &skb_shinfo(skb)->frags[f];
6311                 len = min((unsigned int)frag->size, total);
6312                 offset = frag->page_offset;
6313
6314                 while (len) {
6315                         i++;
6316                         if (i == tx_ring->count)
6317                                 i = 0;
6318
6319                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6320                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6321
6322                         tx_buffer_info->length = size;
6323                         tx_buffer_info->dma = dma_map_page(dev,
6324                                                            frag->page,
6325                                                            offset, size,
6326                                                            DMA_TO_DEVICE);
6327                         tx_buffer_info->mapped_as_page = true;
6328                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6329                                 goto dma_error;
6330                         tx_buffer_info->time_stamp = jiffies;
6331                         tx_buffer_info->next_to_watch = i;
6332
6333                         len -= size;
6334                         total -= size;
6335                         offset += size;
6336                         count++;
6337                 }
6338                 if (total == 0)
6339                         break;
6340         }
6341
6342         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6343                 gso_segs = skb_shinfo(skb)->gso_segs;
6344 #ifdef IXGBE_FCOE
6345         /* adjust for FCoE Sequence Offload */
6346         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6347                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6348                                         skb_shinfo(skb)->gso_size);
6349 #endif /* IXGBE_FCOE */
6350         bytecount += (gso_segs - 1) * hdr_len;
6351
6352         /* multiply data chunks by size of headers */
6353         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6354         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6355         tx_ring->tx_buffer_info[i].skb = skb;
6356         tx_ring->tx_buffer_info[first].next_to_watch = i;
6357
6358         return count;
6359
6360 dma_error:
6361         e_dev_err("TX DMA map failed\n");
6362
6363         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6364         tx_buffer_info->dma = 0;
6365         tx_buffer_info->time_stamp = 0;
6366         tx_buffer_info->next_to_watch = 0;
6367         if (count)
6368                 count--;
6369
6370         /* clear timestamp and dma mappings for remaining portion of packet */
6371         while (count--) {
6372                 if (i == 0)
6373                         i += tx_ring->count;
6374                 i--;
6375                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6376                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6377         }
6378
6379         return 0;
6380 }
6381
6382 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6383                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6384 {
6385         union ixgbe_adv_tx_desc *tx_desc = NULL;
6386         struct ixgbe_tx_buffer *tx_buffer_info;
6387         u32 olinfo_status = 0, cmd_type_len = 0;
6388         unsigned int i;
6389         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6390
6391         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6392
6393         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6394
6395         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6396                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6397
6398         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6399                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6400
6401                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6402                                  IXGBE_ADVTXD_POPTS_SHIFT;
6403
6404                 /* use index 1 context for tso */
6405                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6406                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6407                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6408                                          IXGBE_ADVTXD_POPTS_SHIFT;
6409
6410         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6411                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6412                                  IXGBE_ADVTXD_POPTS_SHIFT;
6413
6414         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6415                 olinfo_status |= IXGBE_ADVTXD_CC;
6416                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6417                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6418                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6419         }
6420
6421         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6422
6423         i = tx_ring->next_to_use;
6424         while (count--) {
6425                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6426                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6427                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6428                 tx_desc->read.cmd_type_len =
6429                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6430                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6431                 i++;
6432                 if (i == tx_ring->count)
6433                         i = 0;
6434         }
6435
6436         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6437
6438         /*
6439          * Force memory writes to complete before letting h/w
6440          * know there are new descriptors to fetch.  (Only
6441          * applicable for weak-ordered memory model archs,
6442          * such as IA-64).
6443          */
6444         wmb();
6445
6446         tx_ring->next_to_use = i;
6447         writel(i, tx_ring->tail);
6448 }
6449
6450 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6451                       u8 queue, u32 tx_flags, __be16 protocol)
6452 {
6453         struct ixgbe_atr_input atr_input;
6454         struct iphdr *iph = ip_hdr(skb);
6455         struct ethhdr *eth = (struct ethhdr *)skb->data;
6456         struct tcphdr *th;
6457         u16 vlan_id;
6458
6459         /* Right now, we support IPv4 w/ TCP only */
6460         if (protocol != htons(ETH_P_IP) ||
6461             iph->protocol != IPPROTO_TCP)
6462                 return;
6463
6464         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6465
6466         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6467                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6468
6469         th = tcp_hdr(skb);
6470
6471         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6472         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6473         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6474         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6475         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6476         /* src and dst are inverted, think how the receiver sees them */
6477         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6478         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6479
6480         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6481         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6482 }
6483
6484 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6485 {
6486         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6487         /* Herbert's original patch had:
6488          *  smp_mb__after_netif_stop_queue();
6489          * but since that doesn't exist yet, just open code it. */
6490         smp_mb();
6491
6492         /* We need to check again in a case another CPU has just
6493          * made room available. */
6494         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6495                 return -EBUSY;
6496
6497         /* A reprieve! - use start_queue because it doesn't call schedule */
6498         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6499         ++tx_ring->tx_stats.restart_queue;
6500         return 0;
6501 }
6502
6503 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6504 {
6505         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6506                 return 0;
6507         return __ixgbe_maybe_stop_tx(tx_ring, size);
6508 }
6509
6510 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6511 {
6512         struct ixgbe_adapter *adapter = netdev_priv(dev);
6513         int txq = smp_processor_id();
6514 #ifdef IXGBE_FCOE
6515         __be16 protocol;
6516
6517         protocol = vlan_get_protocol(skb);
6518
6519         if ((protocol == htons(ETH_P_FCOE)) ||
6520             (protocol == htons(ETH_P_FIP))) {
6521                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6522                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6523                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6524                         return txq;
6525 #ifdef CONFIG_IXGBE_DCB
6526                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6527                         txq = adapter->fcoe.up;
6528                         return txq;
6529 #endif
6530                 }
6531         }
6532 #endif
6533
6534         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6535                 while (unlikely(txq >= dev->real_num_tx_queues))
6536                         txq -= dev->real_num_tx_queues;
6537                 return txq;
6538         }
6539
6540         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6541                 if (skb->priority == TC_PRIO_CONTROL)
6542                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6543                 else
6544                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6545                                >> 13;
6546                 return txq;
6547         }
6548
6549         return skb_tx_hash(dev, skb);
6550 }
6551
6552 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6553                           struct ixgbe_adapter *adapter,
6554                           struct ixgbe_ring *tx_ring)
6555 {
6556         struct net_device *netdev = tx_ring->netdev;
6557         struct netdev_queue *txq;
6558         unsigned int first;
6559         unsigned int tx_flags = 0;
6560         u8 hdr_len = 0;
6561         int tso;
6562         int count = 0;
6563         unsigned int f;
6564         __be16 protocol;
6565
6566         protocol = vlan_get_protocol(skb);
6567
6568         if (vlan_tx_tag_present(skb)) {
6569                 tx_flags |= vlan_tx_tag_get(skb);
6570                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6571                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6572                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6573                 }
6574                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6575                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6576         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6577                    skb->priority != TC_PRIO_CONTROL) {
6578                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6579                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6580                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6581         }
6582
6583 #ifdef IXGBE_FCOE
6584         /* for FCoE with DCB, we force the priority to what
6585          * was specified by the switch */
6586         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6587             (protocol == htons(ETH_P_FCOE) ||
6588              protocol == htons(ETH_P_FIP))) {
6589 #ifdef CONFIG_IXGBE_DCB
6590                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6591                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6592                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6593                         tx_flags |= ((adapter->fcoe.up << 13)
6594                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6595                 }
6596 #endif
6597                 /* flag for FCoE offloads */
6598                 if (protocol == htons(ETH_P_FCOE))
6599                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6600         }
6601 #endif
6602
6603         /* four things can cause us to need a context descriptor */
6604         if (skb_is_gso(skb) ||
6605             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6606             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6607             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6608                 count++;
6609
6610         count += TXD_USE_COUNT(skb_headlen(skb));
6611         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6612                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6613
6614         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6615                 tx_ring->tx_stats.tx_busy++;
6616                 return NETDEV_TX_BUSY;
6617         }
6618
6619         first = tx_ring->next_to_use;
6620         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6621 #ifdef IXGBE_FCOE
6622                 /* setup tx offload for FCoE */
6623                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6624                 if (tso < 0) {
6625                         dev_kfree_skb_any(skb);
6626                         return NETDEV_TX_OK;
6627                 }
6628                 if (tso)
6629                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6630 #endif /* IXGBE_FCOE */
6631         } else {
6632                 if (protocol == htons(ETH_P_IP))
6633                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6634                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6635                                 protocol);
6636                 if (tso < 0) {
6637                         dev_kfree_skb_any(skb);
6638                         return NETDEV_TX_OK;
6639                 }
6640
6641                 if (tso)
6642                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6643                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6644                                        protocol) &&
6645                          (skb->ip_summed == CHECKSUM_PARTIAL))
6646                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6647         }
6648
6649         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6650         if (count) {
6651                 /* add the ATR filter if ATR is on */
6652                 if (tx_ring->atr_sample_rate) {
6653                         ++tx_ring->atr_count;
6654                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6655                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6656                                       &tx_ring->state)) {
6657                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6658                                           tx_flags, protocol);
6659                                 tx_ring->atr_count = 0;
6660                         }
6661                 }
6662                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6663                 txq->tx_bytes += skb->len;
6664                 txq->tx_packets++;
6665                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6666                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6667
6668         } else {
6669                 dev_kfree_skb_any(skb);
6670                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6671                 tx_ring->next_to_use = first;
6672         }
6673
6674         return NETDEV_TX_OK;
6675 }
6676
6677 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6678 {
6679         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6680         struct ixgbe_ring *tx_ring;
6681
6682         tx_ring = adapter->tx_ring[skb->queue_mapping];
6683         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6684 }
6685
6686 /**
6687  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6688  * @netdev: network interface device structure
6689  * @p: pointer to an address structure
6690  *
6691  * Returns 0 on success, negative on failure
6692  **/
6693 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6694 {
6695         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6696         struct ixgbe_hw *hw = &adapter->hw;
6697         struct sockaddr *addr = p;
6698
6699         if (!is_valid_ether_addr(addr->sa_data))
6700                 return -EADDRNOTAVAIL;
6701
6702         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6703         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6704
6705         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6706                             IXGBE_RAH_AV);
6707
6708         return 0;
6709 }
6710
6711 static int
6712 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6713 {
6714         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6715         struct ixgbe_hw *hw = &adapter->hw;
6716         u16 value;
6717         int rc;
6718
6719         if (prtad != hw->phy.mdio.prtad)
6720                 return -EINVAL;
6721         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6722         if (!rc)
6723                 rc = value;
6724         return rc;
6725 }
6726
6727 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6728                             u16 addr, u16 value)
6729 {
6730         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6731         struct ixgbe_hw *hw = &adapter->hw;
6732
6733         if (prtad != hw->phy.mdio.prtad)
6734                 return -EINVAL;
6735         return hw->phy.ops.write_reg(hw, addr, devad, value);
6736 }
6737
6738 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6739 {
6740         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6741
6742         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6743 }
6744
6745 /**
6746  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6747  * netdev->dev_addrs
6748  * @netdev: network interface device structure
6749  *
6750  * Returns non-zero on failure
6751  **/
6752 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6753 {
6754         int err = 0;
6755         struct ixgbe_adapter *adapter = netdev_priv(dev);
6756         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6757
6758         if (is_valid_ether_addr(mac->san_addr)) {
6759                 rtnl_lock();
6760                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6761                 rtnl_unlock();
6762         }
6763         return err;
6764 }
6765
6766 /**
6767  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6768  * netdev->dev_addrs
6769  * @netdev: network interface device structure
6770  *
6771  * Returns non-zero on failure
6772  **/
6773 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6774 {
6775         int err = 0;
6776         struct ixgbe_adapter *adapter = netdev_priv(dev);
6777         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6778
6779         if (is_valid_ether_addr(mac->san_addr)) {
6780                 rtnl_lock();
6781                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6782                 rtnl_unlock();
6783         }
6784         return err;
6785 }
6786
6787 #ifdef CONFIG_NET_POLL_CONTROLLER
6788 /*
6789  * Polling 'interrupt' - used by things like netconsole to send skbs
6790  * without having to re-enable interrupts. It's not called while
6791  * the interrupt routine is executing.
6792  */
6793 static void ixgbe_netpoll(struct net_device *netdev)
6794 {
6795         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6796         int i;
6797
6798         /* if interface is down do nothing */
6799         if (test_bit(__IXGBE_DOWN, &adapter->state))
6800                 return;
6801
6802         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6803         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6804                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6805                 for (i = 0; i < num_q_vectors; i++) {
6806                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6807                         ixgbe_msix_clean_many(0, q_vector);
6808                 }
6809         } else {
6810                 ixgbe_intr(adapter->pdev->irq, netdev);
6811         }
6812         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6813 }
6814 #endif
6815
6816 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6817                                                    struct rtnl_link_stats64 *stats)
6818 {
6819         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6820         int i;
6821
6822         /* accurate rx/tx bytes/packets stats */
6823         dev_txq_stats_fold(netdev, stats);
6824         rcu_read_lock();
6825         for (i = 0; i < adapter->num_rx_queues; i++) {
6826                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6827                 u64 bytes, packets;
6828                 unsigned int start;
6829
6830                 if (ring) {
6831                         do {
6832                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6833                                 packets = ring->stats.packets;
6834                                 bytes   = ring->stats.bytes;
6835                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6836                         stats->rx_packets += packets;
6837                         stats->rx_bytes   += bytes;
6838                 }
6839         }
6840         rcu_read_unlock();
6841         /* following stats updated by ixgbe_watchdog_task() */
6842         stats->multicast        = netdev->stats.multicast;
6843         stats->rx_errors        = netdev->stats.rx_errors;
6844         stats->rx_length_errors = netdev->stats.rx_length_errors;
6845         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6846         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6847         return stats;
6848 }
6849
6850
6851 static const struct net_device_ops ixgbe_netdev_ops = {
6852         .ndo_open               = ixgbe_open,
6853         .ndo_stop               = ixgbe_close,
6854         .ndo_start_xmit         = ixgbe_xmit_frame,
6855         .ndo_select_queue       = ixgbe_select_queue,
6856         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6857         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6858         .ndo_validate_addr      = eth_validate_addr,
6859         .ndo_set_mac_address    = ixgbe_set_mac,
6860         .ndo_change_mtu         = ixgbe_change_mtu,
6861         .ndo_tx_timeout         = ixgbe_tx_timeout,
6862         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6863         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6864         .ndo_do_ioctl           = ixgbe_ioctl,
6865         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6866         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6867         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6868         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6869         .ndo_get_stats64        = ixgbe_get_stats64,
6870 #ifdef CONFIG_NET_POLL_CONTROLLER
6871         .ndo_poll_controller    = ixgbe_netpoll,
6872 #endif
6873 #ifdef IXGBE_FCOE
6874         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6875         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6876         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6877         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6878         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6879 #endif /* IXGBE_FCOE */
6880 };
6881
6882 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6883                            const struct ixgbe_info *ii)
6884 {
6885 #ifdef CONFIG_PCI_IOV
6886         struct ixgbe_hw *hw = &adapter->hw;
6887         int err;
6888
6889         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6890                 return;
6891
6892         /* The 82599 supports up to 64 VFs per physical function
6893          * but this implementation limits allocation to 63 so that
6894          * basic networking resources are still available to the
6895          * physical function
6896          */
6897         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6898         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6899         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6900         if (err) {
6901                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6902                 goto err_novfs;
6903         }
6904         /* If call to enable VFs succeeded then allocate memory
6905          * for per VF control structures.
6906          */
6907         adapter->vfinfo =
6908                 kcalloc(adapter->num_vfs,
6909                         sizeof(struct vf_data_storage), GFP_KERNEL);
6910         if (adapter->vfinfo) {
6911                 /* Now that we're sure SR-IOV is enabled
6912                  * and memory allocated set up the mailbox parameters
6913                  */
6914                 ixgbe_init_mbx_params_pf(hw);
6915                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6916                        sizeof(hw->mbx.ops));
6917
6918                 /* Disable RSC when in SR-IOV mode */
6919                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6920                                      IXGBE_FLAG2_RSC_ENABLED);
6921                 return;
6922         }
6923
6924         /* Oh oh */
6925         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6926               "SRIOV disabled\n");
6927         pci_disable_sriov(adapter->pdev);
6928
6929 err_novfs:
6930         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6931         adapter->num_vfs = 0;
6932 #endif /* CONFIG_PCI_IOV */
6933 }
6934
6935 /**
6936  * ixgbe_probe - Device Initialization Routine
6937  * @pdev: PCI device information struct
6938  * @ent: entry in ixgbe_pci_tbl
6939  *
6940  * Returns 0 on success, negative on failure
6941  *
6942  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6943  * The OS initialization, configuring of the adapter private structure,
6944  * and a hardware reset occur.
6945  **/
6946 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6947                                  const struct pci_device_id *ent)
6948 {
6949         struct net_device *netdev;
6950         struct ixgbe_adapter *adapter = NULL;
6951         struct ixgbe_hw *hw;
6952         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6953         static int cards_found;
6954         int i, err, pci_using_dac;
6955         u8 part_str[IXGBE_PBANUM_LENGTH];
6956         unsigned int indices = num_possible_cpus();
6957 #ifdef IXGBE_FCOE
6958         u16 device_caps;
6959 #endif
6960         u32 eec;
6961
6962         /* Catch broken hardware that put the wrong VF device ID in
6963          * the PCIe SR-IOV capability.
6964          */
6965         if (pdev->is_virtfn) {
6966                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6967                      pci_name(pdev), pdev->vendor, pdev->device);
6968                 return -EINVAL;
6969         }
6970
6971         err = pci_enable_device_mem(pdev);
6972         if (err)
6973                 return err;
6974
6975         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6976             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6977                 pci_using_dac = 1;
6978         } else {
6979                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6980                 if (err) {
6981                         err = dma_set_coherent_mask(&pdev->dev,
6982                                                     DMA_BIT_MASK(32));
6983                         if (err) {
6984                                 dev_err(&pdev->dev,
6985                                         "No usable DMA configuration, aborting\n");
6986                                 goto err_dma;
6987                         }
6988                 }
6989                 pci_using_dac = 0;
6990         }
6991
6992         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6993                                            IORESOURCE_MEM), ixgbe_driver_name);
6994         if (err) {
6995                 dev_err(&pdev->dev,
6996                         "pci_request_selected_regions failed 0x%x\n", err);
6997                 goto err_pci_reg;
6998         }
6999
7000         pci_enable_pcie_error_reporting(pdev);
7001
7002         pci_set_master(pdev);
7003         pci_save_state(pdev);
7004
7005         if (ii->mac == ixgbe_mac_82598EB)
7006                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7007         else
7008                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7009
7010         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7011 #ifdef IXGBE_FCOE
7012         indices += min_t(unsigned int, num_possible_cpus(),
7013                          IXGBE_MAX_FCOE_INDICES);
7014 #endif
7015         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7016         if (!netdev) {
7017                 err = -ENOMEM;
7018                 goto err_alloc_etherdev;
7019         }
7020
7021         SET_NETDEV_DEV(netdev, &pdev->dev);
7022
7023         adapter = netdev_priv(netdev);
7024         pci_set_drvdata(pdev, adapter);
7025
7026         adapter->netdev = netdev;
7027         adapter->pdev = pdev;
7028         hw = &adapter->hw;
7029         hw->back = adapter;
7030         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7031
7032         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7033                               pci_resource_len(pdev, 0));
7034         if (!hw->hw_addr) {
7035                 err = -EIO;
7036                 goto err_ioremap;
7037         }
7038
7039         for (i = 1; i <= 5; i++) {
7040                 if (pci_resource_len(pdev, i) == 0)
7041                         continue;
7042         }
7043
7044         netdev->netdev_ops = &ixgbe_netdev_ops;
7045         ixgbe_set_ethtool_ops(netdev);
7046         netdev->watchdog_timeo = 5 * HZ;
7047         strcpy(netdev->name, pci_name(pdev));
7048
7049         adapter->bd_number = cards_found;
7050
7051         /* Setup hw api */
7052         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7053         hw->mac.type  = ii->mac;
7054
7055         /* EEPROM */
7056         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7057         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7058         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7059         if (!(eec & (1 << 8)))
7060                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7061
7062         /* PHY */
7063         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7064         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7065         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7066         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7067         hw->phy.mdio.mmds = 0;
7068         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7069         hw->phy.mdio.dev = netdev;
7070         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7071         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7072
7073         /* set up this timer and work struct before calling get_invariants
7074          * which might start the timer
7075          */
7076         init_timer(&adapter->sfp_timer);
7077         adapter->sfp_timer.function = ixgbe_sfp_timer;
7078         adapter->sfp_timer.data = (unsigned long) adapter;
7079
7080         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7081
7082         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7083         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7084
7085         /* a new SFP+ module arrival, called from GPI SDP2 context */
7086         INIT_WORK(&adapter->sfp_config_module_task,
7087                   ixgbe_sfp_config_module_task);
7088
7089         ii->get_invariants(hw);
7090
7091         /* setup the private structure */
7092         err = ixgbe_sw_init(adapter);
7093         if (err)
7094                 goto err_sw_init;
7095
7096         /* Make it possible the adapter to be woken up via WOL */
7097         switch (adapter->hw.mac.type) {
7098         case ixgbe_mac_82599EB:
7099         case ixgbe_mac_X540:
7100                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7101                 break;
7102         default:
7103                 break;
7104         }
7105
7106         /*
7107          * If there is a fan on this device and it has failed log the
7108          * failure.
7109          */
7110         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7111                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7112                 if (esdp & IXGBE_ESDP_SDP1)
7113                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7114         }
7115
7116         /* reset_hw fills in the perm_addr as well */
7117         hw->phy.reset_if_overtemp = true;
7118         err = hw->mac.ops.reset_hw(hw);
7119         hw->phy.reset_if_overtemp = false;
7120         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7121             hw->mac.type == ixgbe_mac_82598EB) {
7122                 /*
7123                  * Start a kernel thread to watch for a module to arrive.
7124                  * Only do this for 82598, since 82599 will generate
7125                  * interrupts on module arrival.
7126                  */
7127                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7128                 mod_timer(&adapter->sfp_timer,
7129                           round_jiffies(jiffies + (2 * HZ)));
7130                 err = 0;
7131         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7132                 e_dev_err("failed to initialize because an unsupported SFP+ "
7133                           "module type was detected.\n");
7134                 e_dev_err("Reload the driver after installing a supported "
7135                           "module.\n");
7136                 goto err_sw_init;
7137         } else if (err) {
7138                 e_dev_err("HW Init failed: %d\n", err);
7139                 goto err_sw_init;
7140         }
7141
7142         ixgbe_probe_vf(adapter, ii);
7143
7144         netdev->features = NETIF_F_SG |
7145                            NETIF_F_IP_CSUM |
7146                            NETIF_F_HW_VLAN_TX |
7147                            NETIF_F_HW_VLAN_RX |
7148                            NETIF_F_HW_VLAN_FILTER;
7149
7150         netdev->features |= NETIF_F_IPV6_CSUM;
7151         netdev->features |= NETIF_F_TSO;
7152         netdev->features |= NETIF_F_TSO6;
7153         netdev->features |= NETIF_F_GRO;
7154
7155         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7156                 netdev->features |= NETIF_F_SCTP_CSUM;
7157
7158         netdev->vlan_features |= NETIF_F_TSO;
7159         netdev->vlan_features |= NETIF_F_TSO6;
7160         netdev->vlan_features |= NETIF_F_IP_CSUM;
7161         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7162         netdev->vlan_features |= NETIF_F_SG;
7163
7164         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7165                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7166                                     IXGBE_FLAG_DCB_ENABLED);
7167         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7168                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7169
7170 #ifdef CONFIG_IXGBE_DCB
7171         netdev->dcbnl_ops = &dcbnl_ops;
7172 #endif
7173
7174 #ifdef IXGBE_FCOE
7175         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7176                 if (hw->mac.ops.get_device_caps) {
7177                         hw->mac.ops.get_device_caps(hw, &device_caps);
7178                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7179                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7180                 }
7181         }
7182         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7183                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7184                 netdev->vlan_features |= NETIF_F_FSO;
7185                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7186         }
7187 #endif /* IXGBE_FCOE */
7188         if (pci_using_dac) {
7189                 netdev->features |= NETIF_F_HIGHDMA;
7190                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7191         }
7192
7193         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7194                 netdev->features |= NETIF_F_LRO;
7195
7196         /* make sure the EEPROM is good */
7197         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7198                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7199                 err = -EIO;
7200                 goto err_eeprom;
7201         }
7202
7203         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7204         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7205
7206         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7207                 e_dev_err("invalid MAC address\n");
7208                 err = -EIO;
7209                 goto err_eeprom;
7210         }
7211
7212         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7213         if (hw->mac.ops.disable_tx_laser &&
7214             ((hw->phy.multispeed_fiber) ||
7215              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7216               (hw->mac.type == ixgbe_mac_82599EB))))
7217                 hw->mac.ops.disable_tx_laser(hw);
7218
7219         init_timer(&adapter->watchdog_timer);
7220         adapter->watchdog_timer.function = ixgbe_watchdog;
7221         adapter->watchdog_timer.data = (unsigned long)adapter;
7222
7223         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7224         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7225
7226         err = ixgbe_init_interrupt_scheme(adapter);
7227         if (err)
7228                 goto err_sw_init;
7229
7230         switch (pdev->device) {
7231         case IXGBE_DEV_ID_82599_SFP:
7232                 /* Only this subdevice supports WOL */
7233                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7234                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7235                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7236                 break;
7237         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7238                 /* All except this subdevice support WOL */
7239                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7240                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7241                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7242                 break;
7243         case IXGBE_DEV_ID_82599_KX4:
7244                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7245                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7246                 break;
7247         default:
7248                 adapter->wol = 0;
7249                 break;
7250         }
7251         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7252
7253         /* pick up the PCI bus settings for reporting later */
7254         hw->mac.ops.get_bus_info(hw);
7255
7256         /* print bus type/speed/width info */
7257         e_dev_info("(PCI Express:%s:%s) %pM\n",
7258                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7259                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7260                     "Unknown"),
7261                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7262                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7263                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7264                     "Unknown"),
7265                    netdev->dev_addr);
7266
7267         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7268         if (err)
7269                 strcpy(part_str, "Unknown");
7270         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7271                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7272                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7273                            part_str);
7274         else
7275                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7276                            hw->mac.type, hw->phy.type, part_str);
7277
7278         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7279                 e_dev_warn("PCI-Express bandwidth available for this card is "
7280                            "not sufficient for optimal performance.\n");
7281                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7282                            "is required.\n");
7283         }
7284
7285         /* save off EEPROM version number */
7286         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7287
7288         /* reset the hardware with the new settings */
7289         err = hw->mac.ops.start_hw(hw);
7290
7291         if (err == IXGBE_ERR_EEPROM_VERSION) {
7292                 /* We are running on a pre-production device, log a warning */
7293                 e_dev_warn("This device is a pre-production adapter/LOM. "
7294                            "Please be aware there may be issues associated "
7295                            "with your hardware.  If you are experiencing "
7296                            "problems please contact your Intel or hardware "
7297                            "representative who provided you with this "
7298                            "hardware.\n");
7299         }
7300         strcpy(netdev->name, "eth%d");
7301         err = register_netdev(netdev);
7302         if (err)
7303                 goto err_register;
7304
7305         /* carrier off reporting is important to ethtool even BEFORE open */
7306         netif_carrier_off(netdev);
7307
7308         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7309             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7310                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7311
7312         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7313                 INIT_WORK(&adapter->check_overtemp_task,
7314                           ixgbe_check_overtemp_task);
7315 #ifdef CONFIG_IXGBE_DCA
7316         if (dca_add_requester(&pdev->dev) == 0) {
7317                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7318                 ixgbe_setup_dca(adapter);
7319         }
7320 #endif
7321         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7322                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7323                 for (i = 0; i < adapter->num_vfs; i++)
7324                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7325         }
7326
7327         /* add san mac addr to netdev */
7328         ixgbe_add_sanmac_netdev(netdev);
7329
7330         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7331         cards_found++;
7332         return 0;
7333
7334 err_register:
7335         ixgbe_release_hw_control(adapter);
7336         ixgbe_clear_interrupt_scheme(adapter);
7337 err_sw_init:
7338 err_eeprom:
7339         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7340                 ixgbe_disable_sriov(adapter);
7341         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7342         del_timer_sync(&adapter->sfp_timer);
7343         cancel_work_sync(&adapter->sfp_task);
7344         cancel_work_sync(&adapter->multispeed_fiber_task);
7345         cancel_work_sync(&adapter->sfp_config_module_task);
7346         iounmap(hw->hw_addr);
7347 err_ioremap:
7348         free_netdev(netdev);
7349 err_alloc_etherdev:
7350         pci_release_selected_regions(pdev,
7351                                      pci_select_bars(pdev, IORESOURCE_MEM));
7352 err_pci_reg:
7353 err_dma:
7354         pci_disable_device(pdev);
7355         return err;
7356 }
7357
7358 /**
7359  * ixgbe_remove - Device Removal Routine
7360  * @pdev: PCI device information struct
7361  *
7362  * ixgbe_remove is called by the PCI subsystem to alert the driver
7363  * that it should release a PCI device.  The could be caused by a
7364  * Hot-Plug event, or because the driver is going to be removed from
7365  * memory.
7366  **/
7367 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7368 {
7369         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7370         struct net_device *netdev = adapter->netdev;
7371
7372         set_bit(__IXGBE_DOWN, &adapter->state);
7373         /* clear the module not found bit to make sure the worker won't
7374          * reschedule
7375          */
7376         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7377         del_timer_sync(&adapter->watchdog_timer);
7378
7379         del_timer_sync(&adapter->sfp_timer);
7380         cancel_work_sync(&adapter->watchdog_task);
7381         cancel_work_sync(&adapter->sfp_task);
7382         cancel_work_sync(&adapter->multispeed_fiber_task);
7383         cancel_work_sync(&adapter->sfp_config_module_task);
7384         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7385             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7386                 cancel_work_sync(&adapter->fdir_reinit_task);
7387         flush_scheduled_work();
7388
7389 #ifdef CONFIG_IXGBE_DCA
7390         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7391                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7392                 dca_remove_requester(&pdev->dev);
7393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7394         }
7395
7396 #endif
7397 #ifdef IXGBE_FCOE
7398         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7399                 ixgbe_cleanup_fcoe(adapter);
7400
7401 #endif /* IXGBE_FCOE */
7402
7403         /* remove the added san mac */
7404         ixgbe_del_sanmac_netdev(netdev);
7405
7406         if (netdev->reg_state == NETREG_REGISTERED)
7407                 unregister_netdev(netdev);
7408
7409         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7410                 ixgbe_disable_sriov(adapter);
7411
7412         ixgbe_clear_interrupt_scheme(adapter);
7413
7414         ixgbe_release_hw_control(adapter);
7415
7416         iounmap(adapter->hw.hw_addr);
7417         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7418                                      IORESOURCE_MEM));
7419
7420         e_dev_info("complete\n");
7421
7422         free_netdev(netdev);
7423
7424         pci_disable_pcie_error_reporting(pdev);
7425
7426         pci_disable_device(pdev);
7427 }
7428
7429 /**
7430  * ixgbe_io_error_detected - called when PCI error is detected
7431  * @pdev: Pointer to PCI device
7432  * @state: The current pci connection state
7433  *
7434  * This function is called after a PCI bus error affecting
7435  * this device has been detected.
7436  */
7437 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7438                                                 pci_channel_state_t state)
7439 {
7440         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7441         struct net_device *netdev = adapter->netdev;
7442
7443         netif_device_detach(netdev);
7444
7445         if (state == pci_channel_io_perm_failure)
7446                 return PCI_ERS_RESULT_DISCONNECT;
7447
7448         if (netif_running(netdev))
7449                 ixgbe_down(adapter);
7450         pci_disable_device(pdev);
7451
7452         /* Request a slot reset. */
7453         return PCI_ERS_RESULT_NEED_RESET;
7454 }
7455
7456 /**
7457  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7458  * @pdev: Pointer to PCI device
7459  *
7460  * Restart the card from scratch, as if from a cold-boot.
7461  */
7462 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7463 {
7464         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7465         pci_ers_result_t result;
7466         int err;
7467
7468         if (pci_enable_device_mem(pdev)) {
7469                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7470                 result = PCI_ERS_RESULT_DISCONNECT;
7471         } else {
7472                 pci_set_master(pdev);
7473                 pci_restore_state(pdev);
7474                 pci_save_state(pdev);
7475
7476                 pci_wake_from_d3(pdev, false);
7477
7478                 ixgbe_reset(adapter);
7479                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7480                 result = PCI_ERS_RESULT_RECOVERED;
7481         }
7482
7483         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7484         if (err) {
7485                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7486                           "failed 0x%0x\n", err);
7487                 /* non-fatal, continue */
7488         }
7489
7490         return result;
7491 }
7492
7493 /**
7494  * ixgbe_io_resume - called when traffic can start flowing again.
7495  * @pdev: Pointer to PCI device
7496  *
7497  * This callback is called when the error recovery driver tells us that
7498  * its OK to resume normal operation.
7499  */
7500 static void ixgbe_io_resume(struct pci_dev *pdev)
7501 {
7502         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7503         struct net_device *netdev = adapter->netdev;
7504
7505         if (netif_running(netdev)) {
7506                 if (ixgbe_up(adapter)) {
7507                         e_info(probe, "ixgbe_up failed after reset\n");
7508                         return;
7509                 }
7510         }
7511
7512         netif_device_attach(netdev);
7513 }
7514
7515 static struct pci_error_handlers ixgbe_err_handler = {
7516         .error_detected = ixgbe_io_error_detected,
7517         .slot_reset = ixgbe_io_slot_reset,
7518         .resume = ixgbe_io_resume,
7519 };
7520
7521 static struct pci_driver ixgbe_driver = {
7522         .name     = ixgbe_driver_name,
7523         .id_table = ixgbe_pci_tbl,
7524         .probe    = ixgbe_probe,
7525         .remove   = __devexit_p(ixgbe_remove),
7526 #ifdef CONFIG_PM
7527         .suspend  = ixgbe_suspend,
7528         .resume   = ixgbe_resume,
7529 #endif
7530         .shutdown = ixgbe_shutdown,
7531         .err_handler = &ixgbe_err_handler
7532 };
7533
7534 /**
7535  * ixgbe_init_module - Driver Registration Routine
7536  *
7537  * ixgbe_init_module is the first routine called when the driver is
7538  * loaded. All it does is register with the PCI subsystem.
7539  **/
7540 static int __init ixgbe_init_module(void)
7541 {
7542         int ret;
7543         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7544         pr_info("%s\n", ixgbe_copyright);
7545
7546 #ifdef CONFIG_IXGBE_DCA
7547         dca_register_notify(&dca_notifier);
7548 #endif
7549
7550         ret = pci_register_driver(&ixgbe_driver);
7551         return ret;
7552 }
7553
7554 module_init(ixgbe_init_module);
7555
7556 /**
7557  * ixgbe_exit_module - Driver Exit Cleanup Routine
7558  *
7559  * ixgbe_exit_module is called just before the driver is removed
7560  * from memory.
7561  **/
7562 static void __exit ixgbe_exit_module(void)
7563 {
7564 #ifdef CONFIG_IXGBE_DCA
7565         dca_unregister_notify(&dca_notifier);
7566 #endif
7567         pci_unregister_driver(&ixgbe_driver);
7568         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7569 }
7570
7571 #ifdef CONFIG_IXGBE_DCA
7572 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7573                             void *p)
7574 {
7575         int ret_val;
7576
7577         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7578                                          __ixgbe_notify_dca);
7579
7580         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7581 }
7582
7583 #endif /* CONFIG_IXGBE_DCA */
7584
7585 /**
7586  * ixgbe_get_hw_dev return device
7587  * used by hardware layer to print debugging information
7588  **/
7589 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7590 {
7591         struct ixgbe_adapter *adapter = hw->back;
7592         return adapter->netdev;
7593 }
7594
7595 module_exit(ixgbe_exit_module);
7596
7597 /* ixgbe_main.c */