drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "ixgbe.h"
  44 #include "ixgbe_common.h"
  45
  46 char ixgbe_driver_name[] = "ixgbe";
  47 static const char ixgbe_driver_string[] =
  48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  49
  50 #define DRV_VERSION "2.0.16-k2"
  51 const char ixgbe_driver_version[] = DRV_VERSION;
  52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  53
  54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  55         [board_82598] = &ixgbe_82598_info,
  56         [board_82599] = &ixgbe_82599_info,
  57 };
  58
  59 /* ixgbe_pci_tbl - PCI Device ID Table
  60  *
  61  * Wildcard entries (PCI_ANY_ID) should come last
  62  * Last entry must be all 0s
  63  *
  64  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  65  *   Class, Class Mask, private data (not used) }
  66  */
  67 static struct pci_device_id ixgbe_pci_tbl[] = {
  68         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  69          board_82598 },
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  91          board_82599 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  93          board_82599 },
  94
  95         /* required last entry */
  96         {0, }
  97 };
  98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  99
 100 #ifdef CONFIG_IXGBE_DCA
 101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 102                             void *p);
 103 static struct notifier_block dca_notifier = {
 104         .notifier_call = ixgbe_notify_dca,
 105         .next          = NULL,
 106         .priority      = 0
 107 };
 108 #endif
 109
 110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 112 MODULE_LICENSE("GPL");
 113 MODULE_VERSION(DRV_VERSION);
 114
 115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 116
 117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 118 {
 119         u32 ctrl_ext;
 120
 121         /* Let firmware take over control of h/w */
 122         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 123         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 124                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 125 }
 126
 127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 128 {
 129         u32 ctrl_ext;
 130
 131         /* Let firmware know the driver has taken over */
 132         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 133         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 134                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 135 }
 136
 137 /*
 138  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 139  * @adapter: pointer to adapter struct
 140  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 141  * @queue: queue to map the corresponding interrupt to
 142  * @msix_vector: the vector to map to the corresponding queue
 143  *
 144  */
 145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 146                            u8 queue, u8 msix_vector)
 147 {
 148         u32 ivar, index;
 149         struct ixgbe_hw *hw = &adapter->hw;
 150         switch (hw->mac.type) {
 151         case ixgbe_mac_82598EB:
 152                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 153                 if (direction == -1)
 154                         direction = 0;
 155                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 156                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 157                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 158                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 159                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 160                 break;
 161         case ixgbe_mac_82599EB:
 162                 if (direction == -1) {
 163                         /* other causes */
 164                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 165                         index = ((queue & 1) * 8);
 166                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 167                         ivar &= ~(0xFF << index);
 168                         ivar |= (msix_vector << index);
 169                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 170                         break;
 171                 } else {
 172                         /* tx or rx causes */
 173                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 174                         index = ((16 * (queue & 1)) + (8 * direction));
 175                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 176                         ivar &= ~(0xFF << index);
 177                         ivar |= (msix_vector << index);
 178                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 179                         break;
 180                 }
 181         default:
 182                 break;
 183         }
 184 }
 185
 186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 187                                              struct ixgbe_tx_buffer
 188                                              *tx_buffer_info)
 189 {
 190         tx_buffer_info->dma = 0;
 191         if (tx_buffer_info->skb) {
 192                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 193                               DMA_TO_DEVICE);
 194                 dev_kfree_skb_any(tx_buffer_info->skb);
 195                 tx_buffer_info->skb = NULL;
 196         }
 197         tx_buffer_info->time_stamp = 0;
 198         /* tx_buffer_info must be completely set up in the transmit path */
 199 }
 200
 201 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 202                                        struct ixgbe_ring *tx_ring,
 203                                        unsigned int eop)
 204 {
 205         struct ixgbe_hw *hw = &adapter->hw;
 206
 207         /* Detect a transmit hang in hardware, this serializes the
 208          * check with the clearing of time_stamp and movement of eop */
 209         adapter->detect_tx_hung = false;
 210         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 211             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 212             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 213                 /* detected Tx unit hang */
 214                 union ixgbe_adv_tx_desc *tx_desc;
 215                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 216                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 217                         "  Tx Queue             <%d>\n"
 218                         "  TDH, TDT             <%x>, <%x>\n"
 219                         "  next_to_use          <%x>\n"
 220                         "  next_to_clean        <%x>\n"
 221                         "tx_buffer_info[next_to_clean]\n"
 222                         "  time_stamp           <%lx>\n"
 223                         "  jiffies              <%lx>\n",
 224                         tx_ring->queue_index,
 225                         IXGBE_READ_REG(hw, tx_ring->head),
 226                         IXGBE_READ_REG(hw, tx_ring->tail),
 227                         tx_ring->next_to_use, eop,
 228                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 229                 return true;
 230         }
 231
 232         return false;
 233 }
 234
 235 #define IXGBE_MAX_TXD_PWR       14
 236 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 237
 238 /* Tx Descriptors needed, worst case */
 239 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 240                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 241 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 242         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 243
 244 static void ixgbe_tx_timeout(struct net_device *netdev);
 245
 246 /**
 247  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 248  * @adapter: board private structure
 249  * @tx_ring: tx ring to clean
 250  *
 251  * returns true if transmit work is done
 252  **/
 253 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 254                                struct ixgbe_ring *tx_ring)
 255 {
 256         struct net_device *netdev = adapter->netdev;
 257         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 258         struct ixgbe_tx_buffer *tx_buffer_info;
 259         unsigned int i, eop, count = 0;
 260         unsigned int total_bytes = 0, total_packets = 0;
 261
 262         i = tx_ring->next_to_clean;
 263         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 264         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 265
 266         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 267                (count < tx_ring->work_limit)) {
 268                 bool cleaned = false;
 269                 for ( ; !cleaned; count++) {
 270                         struct sk_buff *skb;
 271                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 272                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 273                         cleaned = (i == eop);
 274                         skb = tx_buffer_info->skb;
 275
 276                         if (cleaned && skb) {
 277                                 unsigned int segs, bytecount;
 278
 279                                 /* gso_segs is currently only valid for tcp */
 280                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 281                                 /* multiply data chunks by size of headers */
 282                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 283                                             skb->len;
 284                                 total_packets += segs;
 285                                 total_bytes += bytecount;
 286                         }
 287
 288                         ixgbe_unmap_and_free_tx_resource(adapter,
 289                                                          tx_buffer_info);
 290
 291                         tx_desc->wb.status = 0;
 292
 293                         i++;
 294                         if (i == tx_ring->count)
 295                                 i = 0;
 296                 }
 297
 298                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 299                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 300         }
 301
 302         tx_ring->next_to_clean = i;
 303
 304 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 305         if (unlikely(count && netif_carrier_ok(netdev) &&
 306                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 307                 /* Make sure that anybody stopping the queue after this
 308                  * sees the new next_to_clean.
 309                  */
 310                 smp_mb();
 311                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 312                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 313                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 314                         ++adapter->restart_queue;
 315                 }
 316         }
 317
 318         if (adapter->detect_tx_hung) {
 319                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 320                         /* schedule immediate reset if we believe we hung */
 321                         DPRINTK(PROBE, INFO,
 322                                 "tx hang %d detected, resetting adapter\n",
 323                                 adapter->tx_timeout_count + 1);
 324                         ixgbe_tx_timeout(adapter->netdev);
 325                 }
 326         }
 327
 328         /* re-arm the interrupt */
 329         if (count >= tx_ring->work_limit) {
 330                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 331                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
 332                                         tx_ring->v_idx);
 333                 else if (tx_ring->v_idx & 0xFFFFFFFF)
 334                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
 335                                         tx_ring->v_idx);
 336                 else
 337                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
 338                                         (tx_ring->v_idx >> 32));
 339         }
 340
 341
 342         tx_ring->total_bytes += total_bytes;
 343         tx_ring->total_packets += total_packets;
 344         tx_ring->stats.packets += total_packets;
 345         tx_ring->stats.bytes += total_bytes;
 346         adapter->net_stats.tx_bytes += total_bytes;
 347         adapter->net_stats.tx_packets += total_packets;
 348         return (count < tx_ring->work_limit);
 349 }
 350
 351 #ifdef CONFIG_IXGBE_DCA
 352 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 353                                 struct ixgbe_ring *rx_ring)
 354 {
 355         u32 rxctrl;
 356         int cpu = get_cpu();
 357         int q = rx_ring - adapter->rx_ring;
 358
 359         if (rx_ring->cpu != cpu) {
 360                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 361                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 362                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 363                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 364                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 365                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 366                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 367                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 368                 }
 369                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 370                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 371                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 372                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 373                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 374                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 375                 rx_ring->cpu = cpu;
 376         }
 377         put_cpu();
 378 }
 379
 380 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 381                                 struct ixgbe_ring *tx_ring)
 382 {
 383         u32 txctrl;
 384         int cpu = get_cpu();
 385         int q = tx_ring - adapter->tx_ring;
 386
 387         if (tx_ring->cpu != cpu) {
 388                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 389                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 390                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 391                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 392                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 393                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 394                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 395                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 396                 }
 397                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 398                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 399                 tx_ring->cpu = cpu;
 400         }
 401         put_cpu();
 402 }
 403
 404 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 405 {
 406         int i;
 407
 408         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 409                 return;
 410
 411         for (i = 0; i < adapter->num_tx_queues; i++) {
 412                 adapter->tx_ring[i].cpu = -1;
 413                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 414         }
 415         for (i = 0; i < adapter->num_rx_queues; i++) {
 416                 adapter->rx_ring[i].cpu = -1;
 417                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 418         }
 419 }
 420
 421 static int __ixgbe_notify_dca(struct device *dev, void *data)
 422 {
 423         struct net_device *netdev = dev_get_drvdata(dev);
 424         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 425         unsigned long event = *(unsigned long *)data;
 426
 427         switch (event) {
 428         case DCA_PROVIDER_ADD:
 429                 /* if we're already enabled, don't do it again */
 430                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 431                         break;
 432                 /* Always use CB2 mode, difference is masked
 433                  * in the CB driver. */
 434                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 435                 if (dca_add_requester(dev) == 0) {
 436                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 437                         ixgbe_setup_dca(adapter);
 438                         break;
 439                 }
 440                 /* Fall Through since DCA is disabled. */
 441         case DCA_PROVIDER_REMOVE:
 442                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 443                         dca_remove_requester(dev);
 444                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 445                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 446                 }
 447                 break;
 448         }
 449
 450         return 0;
 451 }
 452
 453 #endif /* CONFIG_IXGBE_DCA */
 454 /**
 455  * ixgbe_receive_skb - Send a completed packet up the stack
 456  * @adapter: board private structure
 457  * @skb: packet to send up
 458  * @status: hardware indication of status of receive
 459  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 460  * @rx_desc: rx descriptor
 461  **/
 462 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 463                               struct sk_buff *skb, u8 status,
 464                               union ixgbe_adv_rx_desc *rx_desc)
 465 {
 466         struct ixgbe_adapter *adapter = q_vector->adapter;
 467         struct napi_struct *napi = &q_vector->napi;
 468         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 469         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 470
 471         skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
 472         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 473                 if (adapter->vlgrp && is_vlan && (tag != 0))
 474                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 475                 else
 476                         napi_gro_receive(napi, skb);
 477         } else {
 478                 if (adapter->vlgrp && is_vlan && (tag != 0))
 479                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 480                 else
 481                         netif_rx(skb);
 482         }
 483 }
 484
 485 /**
 486  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 487  * @adapter: address of board private structure
 488  * @status_err: hardware indication of status of receive
 489  * @skb: skb currently being received and modified
 490  **/
 491 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 492                                      u32 status_err, struct sk_buff *skb)
 493 {
 494         skb->ip_summed = CHECKSUM_NONE;
 495
 496         /* Rx csum disabled */
 497         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 498                 return;
 499
 500         /* if IP and error */
 501         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 502             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 503                 adapter->hw_csum_rx_error++;
 504                 return;
 505         }
 506
 507         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 508                 return;
 509
 510         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 511                 adapter->hw_csum_rx_error++;
 512                 return;
 513         }
 514
 515         /* It must be a TCP or UDP packet with a valid checksum */
 516         skb->ip_summed = CHECKSUM_UNNECESSARY;
 517         adapter->hw_csum_rx_good++;
 518 }
 519
 520 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 521                                          struct ixgbe_ring *rx_ring, u32 val)
 522 {
 523         /*
 524          * Force memory writes to complete before letting h/w
 525          * know there are new descriptors to fetch.  (Only
 526          * applicable for weak-ordered memory model archs,
 527          * such as IA-64).
 528          */
 529         wmb();
 530         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 531 }
 532
 533 /**
 534  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 535  * @adapter: address of board private structure
 536  **/
 537 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 538                                    struct ixgbe_ring *rx_ring,
 539                                    int cleaned_count)
 540 {
 541         struct pci_dev *pdev = adapter->pdev;
 542         union ixgbe_adv_rx_desc *rx_desc;
 543         struct ixgbe_rx_buffer *bi;
 544         unsigned int i;
 545         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 546
 547         i = rx_ring->next_to_use;
 548         bi = &rx_ring->rx_buffer_info[i];
 549
 550         while (cleaned_count--) {
 551                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 552
 553                 if (!bi->page_dma &&
 554                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 555                         if (!bi->page) {
 556                                 bi->page = alloc_page(GFP_ATOMIC);
 557                                 if (!bi->page) {
 558                                         adapter->alloc_rx_page_failed++;
 559                                         goto no_buffers;
 560                                 }
 561                                 bi->page_offset = 0;
 562                         } else {
 563                                 /* use a half page if we're re-using */
 564                                 bi->page_offset ^= (PAGE_SIZE / 2);
 565                         }
 566
 567                         bi->page_dma = pci_map_page(pdev, bi->page,
 568                                                     bi->page_offset,
 569                                                     (PAGE_SIZE / 2),
 570                                                     PCI_DMA_FROMDEVICE);
 571                 }
 572
 573                 if (!bi->skb) {
 574                         struct sk_buff *skb;
 575                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 576
 577                         if (!skb) {
 578                                 adapter->alloc_rx_buff_failed++;
 579                                 goto no_buffers;
 580                         }
 581
 582                         /*
 583                          * Make buffer alignment 2 beyond a 16 byte boundary
 584                          * this will result in a 16 byte aligned IP header after
 585                          * the 14 byte MAC header is removed
 586                          */
 587                         skb_reserve(skb, NET_IP_ALIGN);
 588
 589                         bi->skb = skb;
 590                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 591                                                  PCI_DMA_FROMDEVICE);
 592                 }
 593                 /* Refresh the desc even if buffer_addrs didn't change because
 594                  * each write-back erases this info. */
 595                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 596                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 597                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 598                 } else {
 599                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 600                 }
 601
 602                 i++;
 603                 if (i == rx_ring->count)
 604                         i = 0;
 605                 bi = &rx_ring->rx_buffer_info[i];
 606         }
 607
 608 no_buffers:
 609         if (rx_ring->next_to_use != i) {
 610                 rx_ring->next_to_use = i;
 611                 if (i-- == 0)
 612                         i = (rx_ring->count - 1);
 613
 614                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 615         }
 616 }
 617
 618 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 619 {
 620         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 621 }
 622
 623 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 624 {
 625         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 626 }
 627
 628 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 629 {
 630         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 631                 IXGBE_RXDADV_RSCCNT_MASK) >>
 632                 IXGBE_RXDADV_RSCCNT_SHIFT;
 633 }
 634
 635 /**
 636  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 637  * @skb: pointer to the last skb in the rsc queue
 638  *
 639  * This function changes a queue full of hw rsc buffers into a completed
 640  * packet.  It uses the ->prev pointers to find the first packet and then
 641  * turns it into the frag list owner.
 642  **/
 643 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 644 {
 645         unsigned int frag_list_size = 0;
 646
 647         while (skb->prev) {
 648                 struct sk_buff *prev = skb->prev;
 649                 frag_list_size += skb->len;
 650                 skb->prev = NULL;
 651                 skb = prev;
 652         }
 653
 654         skb_shinfo(skb)->frag_list = skb->next;
 655         skb->next = NULL;
 656         skb->len += frag_list_size;
 657         skb->data_len += frag_list_size;
 658         skb->truesize += frag_list_size;
 659         return skb;
 660 }
 661
 662 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 663                                struct ixgbe_ring *rx_ring,
 664                                int *work_done, int work_to_do)
 665 {
 666         struct ixgbe_adapter *adapter = q_vector->adapter;
 667         struct pci_dev *pdev = adapter->pdev;
 668         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 669         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 670         struct sk_buff *skb;
 671         unsigned int i, rsc_count = 0;
 672         u32 len, staterr;
 673         u16 hdr_info;
 674         bool cleaned = false;
 675         int cleaned_count = 0;
 676         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 677
 678         i = rx_ring->next_to_clean;
 679         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 680         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 681         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 682
 683         while (staterr & IXGBE_RXD_STAT_DD) {
 684                 u32 upper_len = 0;
 685                 if (*work_done >= work_to_do)
 686                         break;
 687                 (*work_done)++;
 688
 689                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 690                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 691                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 692                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 693                         if (hdr_info & IXGBE_RXDADV_SPH)
 694                                 adapter->rx_hdr_split++;
 695                         if (len > IXGBE_RX_HDR_SIZE)
 696                                 len = IXGBE_RX_HDR_SIZE;
 697                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 698                 } else {
 699                         len = le16_to_cpu(rx_desc->wb.upper.length);
 700                 }
 701
 702                 cleaned = true;
 703                 skb = rx_buffer_info->skb;
 704                 prefetch(skb->data - NET_IP_ALIGN);
 705                 rx_buffer_info->skb = NULL;
 706
 707                 if (len && !skb_shinfo(skb)->nr_frags) {
 708                         pci_unmap_single(pdev, rx_buffer_info->dma,
 709                                          rx_ring->rx_buf_len,
 710                                          PCI_DMA_FROMDEVICE);
 711                         skb_put(skb, len);
 712                 }
 713
 714                 if (upper_len) {
 715                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 716                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 717                         rx_buffer_info->page_dma = 0;
 718                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 719                                            rx_buffer_info->page,
 720                                            rx_buffer_info->page_offset,
 721                                            upper_len);
 722
 723                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 724                             (page_count(rx_buffer_info->page) != 1))
 725                                 rx_buffer_info->page = NULL;
 726                         else
 727                                 get_page(rx_buffer_info->page);
 728
 729                         skb->len += upper_len;
 730                         skb->data_len += upper_len;
 731                         skb->truesize += upper_len;
 732                 }
 733
 734                 i++;
 735                 if (i == rx_ring->count)
 736                         i = 0;
 737
 738                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 739                 prefetch(next_rxd);
 740                 cleaned_count++;
 741
 742                 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
 743                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 744
 745                 if (rsc_count) {
 746                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 747                                      IXGBE_RXDADV_NEXTP_SHIFT;
 748                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 749                         rx_ring->rsc_count += (rsc_count - 1);
 750                 } else {
 751                         next_buffer = &rx_ring->rx_buffer_info[i];
 752                 }
 753
 754                 if (staterr & IXGBE_RXD_STAT_EOP) {
 755                         if (skb->prev)
 756                                 skb = ixgbe_transform_rsc_queue(skb);
 757                         rx_ring->stats.packets++;
 758                         rx_ring->stats.bytes += skb->len;
 759                 } else {
 760                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 761                                 rx_buffer_info->skb = next_buffer->skb;
 762                                 rx_buffer_info->dma = next_buffer->dma;
 763                                 next_buffer->skb = skb;
 764                                 next_buffer->dma = 0;
 765                         } else {
 766                                 skb->next = next_buffer->skb;
 767                                 skb->next->prev = skb;
 768                         }
 769                         adapter->non_eop_descs++;
 770                         goto next_desc;
 771                 }
 772
 773                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 774                         dev_kfree_skb_irq(skb);
 775                         goto next_desc;
 776                 }
 777
 778                 ixgbe_rx_checksum(adapter, staterr, skb);
 779
 780                 /* probably a little skewed due to removing CRC */
 781                 total_rx_bytes += skb->len;
 782                 total_rx_packets++;
 783
 784                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 785                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
 786
 787 next_desc:
 788                 rx_desc->wb.upper.status_error = 0;
 789
 790                 /* return some buffers to hardware, one at a time is too slow */
 791                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 792                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 793                         cleaned_count = 0;
 794                 }
 795
 796                 /* use prefetched values */
 797                 rx_desc = next_rxd;
 798                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 799
 800                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 801         }
 802
 803         rx_ring->next_to_clean = i;
 804         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 805
 806         if (cleaned_count)
 807                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 808
 809         rx_ring->total_packets += total_rx_packets;
 810         rx_ring->total_bytes += total_rx_bytes;
 811         adapter->net_stats.rx_bytes += total_rx_bytes;
 812         adapter->net_stats.rx_packets += total_rx_packets;
 813
 814         return cleaned;
 815 }
 816
 817 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 818 /**
 819  * ixgbe_configure_msix - Configure MSI-X hardware
 820  * @adapter: board private structure
 821  *
 822  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 823  * interrupts.
 824  **/
 825 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 826 {
 827         struct ixgbe_q_vector *q_vector;
 828         int i, j, q_vectors, v_idx, r_idx;
 829         u32 mask;
 830
 831         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 832
 833         /*
 834          * Populate the IVAR table and set the ITR values to the
 835          * corresponding register.
 836          */
 837         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 838                 q_vector = &adapter->q_vector[v_idx];
 839                 /* XXX for_each_bit(...) */
 840                 r_idx = find_first_bit(q_vector->rxr_idx,
 841                                        adapter->num_rx_queues);
 842
 843                 for (i = 0; i < q_vector->rxr_count; i++) {
 844                         j = adapter->rx_ring[r_idx].reg_idx;
 845                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 846                         r_idx = find_next_bit(q_vector->rxr_idx,
 847                                               adapter->num_rx_queues,
 848                                               r_idx + 1);
 849                 }
 850                 r_idx = find_first_bit(q_vector->txr_idx,
 851                                        adapter->num_tx_queues);
 852
 853                 for (i = 0; i < q_vector->txr_count; i++) {
 854                         j = adapter->tx_ring[r_idx].reg_idx;
 855                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 856                         r_idx = find_next_bit(q_vector->txr_idx,
 857                                               adapter->num_tx_queues,
 858                                               r_idx + 1);
 859                 }
 860
 861                 /* if this is a tx only vector halve the interrupt rate */
 862                 if (q_vector->txr_count && !q_vector->rxr_count)
 863                         q_vector->eitr = (adapter->eitr_param >> 1);
 864                 else if (q_vector->rxr_count)
 865                         /* rx only */
 866                         q_vector->eitr = adapter->eitr_param;
 867
 868                 /*
 869                  * since this is initial set up don't need to call
 870                  * ixgbe_write_eitr helper
 871                  */
 872                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 873                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 874         }
 875
 876         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 877                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 878                                v_idx);
 879         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 880                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 881         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 882
 883         /* set up to autoclear timer, and the vectors */
 884         mask = IXGBE_EIMS_ENABLE_MASK;
 885         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 886         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 887 }
 888
 889 enum latency_range {
 890         lowest_latency = 0,
 891         low_latency = 1,
 892         bulk_latency = 2,
 893         latency_invalid = 255
 894 };
 895
 896 /**
 897  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 898  * @adapter: pointer to adapter
 899  * @eitr: eitr setting (ints per sec) to give last timeslice
 900  * @itr_setting: current throttle rate in ints/second
 901  * @packets: the number of packets during this measurement interval
 902  * @bytes: the number of bytes during this measurement interval
 903  *
 904  *      Stores a new ITR value based on packets and byte
 905  *      counts during the last interrupt.  The advantage of per interrupt
 906  *      computation is faster updates and more accurate ITR for the current
 907  *      traffic pattern.  Constants in this function were computed
 908  *      based on theoretical maximum wire speed and thresholds were set based
 909  *      on testing data as well as attempting to minimize response time
 910  *      while increasing bulk throughput.
 911  *      this functionality is controlled by the InterruptThrottleRate module
 912  *      parameter (see ixgbe_param.c)
 913  **/
 914 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 915                            u32 eitr, u8 itr_setting,
 916                            int packets, int bytes)
 917 {
 918         unsigned int retval = itr_setting;
 919         u32 timepassed_us;
 920         u64 bytes_perint;
 921
 922         if (packets == 0)
 923                 goto update_itr_done;
 924
 925
 926         /* simple throttlerate management
 927          *    0-20MB/s lowest (100000 ints/s)
 928          *   20-100MB/s low   (20000 ints/s)
 929          *  100-1249MB/s bulk (8000 ints/s)
 930          */
 931         /* what was last interrupt timeslice? */
 932         timepassed_us = 1000000/eitr;
 933         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 934
 935         switch (itr_setting) {
 936         case lowest_latency:
 937                 if (bytes_perint > adapter->eitr_low)
 938                         retval = low_latency;
 939                 break;
 940         case low_latency:
 941                 if (bytes_perint > adapter->eitr_high)
 942                         retval = bulk_latency;
 943                 else if (bytes_perint <= adapter->eitr_low)
 944                         retval = lowest_latency;
 945                 break;
 946         case bulk_latency:
 947                 if (bytes_perint <= adapter->eitr_high)
 948                         retval = low_latency;
 949                 break;
 950         }
 951
 952 update_itr_done:
 953         return retval;
 954 }
 955
 956 /**
 957  * ixgbe_write_eitr - write EITR register in hardware specific way
 958  * @adapter: pointer to adapter struct
 959  * @v_idx: vector index into q_vector array
 960  * @itr_reg: new value to be written in *register* format, not ints/s
 961  *
 962  * This function is made to be called by ethtool and by the driver
 963  * when it needs to update EITR registers at runtime.  Hardware
 964  * specific quirks/differences are taken care of here.
 965  */
 966 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
 967 {
 968         struct ixgbe_hw *hw = &adapter->hw;
 969         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 970                 /* must write high and low 16 bits to reset counter */
 971                 itr_reg |= (itr_reg << 16);
 972         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 973                 /*
 974                  * set the WDIS bit to not clear the timer bits and cause an
 975                  * immediate assertion of the interrupt
 976                  */
 977                 itr_reg |= IXGBE_EITR_CNT_WDIS;
 978         }
 979         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 980 }
 981
 982 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 983 {
 984         struct ixgbe_adapter *adapter = q_vector->adapter;
 985         u32 new_itr;
 986         u8 current_itr, ret_itr;
 987         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 988                                sizeof(struct ixgbe_q_vector);
 989         struct ixgbe_ring *rx_ring, *tx_ring;
 990
 991         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 992         for (i = 0; i < q_vector->txr_count; i++) {
 993                 tx_ring = &(adapter->tx_ring[r_idx]);
 994                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 995                                            q_vector->tx_itr,
 996                                            tx_ring->total_packets,
 997                                            tx_ring->total_bytes);
 998                 /* if the result for this queue would decrease interrupt
 999                  * rate for this vector then use that result */
1000                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1001                                     q_vector->tx_itr - 1 : ret_itr);
1002                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1003                                       r_idx + 1);
1004         }
1005
1006         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1007         for (i = 0; i < q_vector->rxr_count; i++) {
1008                 rx_ring = &(adapter->rx_ring[r_idx]);
1009                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1010                                            q_vector->rx_itr,
1011                                            rx_ring->total_packets,
1012                                            rx_ring->total_bytes);
1013                 /* if the result for this queue would decrease interrupt
1014                  * rate for this vector then use that result */
1015                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1016                                     q_vector->rx_itr - 1 : ret_itr);
1017                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1018                                       r_idx + 1);
1019         }
1020
1021         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1022
1023         switch (current_itr) {
1024         /* counts and packets in update_itr are dependent on these numbers */
1025         case lowest_latency:
1026                 new_itr = 100000;
1027                 break;
1028         case low_latency:
1029                 new_itr = 20000; /* aka hwitr = ~200 */
1030                 break;
1031         case bulk_latency:
1032         default:
1033                 new_itr = 8000;
1034                 break;
1035         }
1036
1037         if (new_itr != q_vector->eitr) {
1038                 u32 itr_reg;
1039
1040                 /* save the algorithm value here, not the smoothed one */
1041                 q_vector->eitr = new_itr;
1042                 /* do an exponential smoothing */
1043                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1044                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1045                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1046         }
1047
1048         return;
1049 }
1050
1051 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1052 {
1053         struct ixgbe_hw *hw = &adapter->hw;
1054
1055         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1056             (eicr & IXGBE_EICR_GPI_SDP1)) {
1057                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1058                 /* write to clear the interrupt */
1059                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060         }
1061 }
1062
1063 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1064 {
1065         struct ixgbe_hw *hw = &adapter->hw;
1066
1067         if (eicr & IXGBE_EICR_GPI_SDP1) {
1068                 /* Clear the interrupt */
1069                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070                 schedule_work(&adapter->multispeed_fiber_task);
1071         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1072                 /* Clear the interrupt */
1073                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1074                 schedule_work(&adapter->sfp_config_module_task);
1075         } else {
1076                 /* Interrupt isn't for us... */
1077                 return;
1078         }
1079 }
1080
1081 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1082 {
1083         struct ixgbe_hw *hw = &adapter->hw;
1084
1085         adapter->lsc_int++;
1086         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1087         adapter->link_check_timeout = jiffies;
1088         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1089                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1090                 schedule_work(&adapter->watchdog_task);
1091         }
1092 }
1093
1094 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1095 {
1096         struct net_device *netdev = data;
1097         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1098         struct ixgbe_hw *hw = &adapter->hw;
1099         u32 eicr;
1100
1101         /*
1102          * Workaround for Silicon errata.  Use clear-by-write instead
1103          * of clear-by-read.  Reading with EICS will return the
1104          * interrupt causes without clearing, which later be done
1105          * with the write to EICR.
1106          */
1107         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1108         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1109
1110         if (eicr & IXGBE_EICR_LSC)
1111                 ixgbe_check_lsc(adapter);
1112
1113         if (hw->mac.type == ixgbe_mac_82598EB)
1114                 ixgbe_check_fan_failure(adapter, eicr);
1115
1116         if (hw->mac.type == ixgbe_mac_82599EB)
1117                 ixgbe_check_sfp_event(adapter, eicr);
1118         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1119                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1120
1121         return IRQ_HANDLED;
1122 }
1123
1124 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1125 {
1126         struct ixgbe_q_vector *q_vector = data;
1127         struct ixgbe_adapter  *adapter = q_vector->adapter;
1128         struct ixgbe_ring     *tx_ring;
1129         int i, r_idx;
1130
1131         if (!q_vector->txr_count)
1132                 return IRQ_HANDLED;
1133
1134         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1135         for (i = 0; i < q_vector->txr_count; i++) {
1136                 tx_ring = &(adapter->tx_ring[r_idx]);
1137 #ifdef CONFIG_IXGBE_DCA
1138                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1139                         ixgbe_update_tx_dca(adapter, tx_ring);
1140 #endif
1141                 tx_ring->total_bytes = 0;
1142                 tx_ring->total_packets = 0;
1143                 ixgbe_clean_tx_irq(adapter, tx_ring);
1144                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1145                                       r_idx + 1);
1146         }
1147
1148         return IRQ_HANDLED;
1149 }
1150
1151 /**
1152  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1153  * @irq: unused
1154  * @data: pointer to our q_vector struct for this interrupt vector
1155  **/
1156 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1157 {
1158         struct ixgbe_q_vector *q_vector = data;
1159         struct ixgbe_adapter  *adapter = q_vector->adapter;
1160         struct ixgbe_ring  *rx_ring;
1161         int r_idx;
1162         int i;
1163
1164         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1165         for (i = 0;  i < q_vector->rxr_count; i++) {
1166                 rx_ring = &(adapter->rx_ring[r_idx]);
1167                 rx_ring->total_bytes = 0;
1168                 rx_ring->total_packets = 0;
1169                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1170                                       r_idx + 1);
1171         }
1172
1173         if (!q_vector->rxr_count)
1174                 return IRQ_HANDLED;
1175
1176         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1177         rx_ring = &(adapter->rx_ring[r_idx]);
1178         /* disable interrupts on this vector only */
1179         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1180                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1181         else if (rx_ring->v_idx & 0xFFFFFFFF)
1182                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1183         else
1184                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1185                                 (rx_ring->v_idx >> 32));
1186         napi_schedule(&q_vector->napi);
1187
1188         return IRQ_HANDLED;
1189 }
1190
1191 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1192 {
1193         ixgbe_msix_clean_rx(irq, data);
1194         ixgbe_msix_clean_tx(irq, data);
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200                                            u64 qmask)
1201 {
1202         u32 mask;
1203
1204         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207         } else {
1208                 mask = (qmask & 0xFFFFFFFF);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210                 mask = (qmask >> 32);
1211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212         }
1213         /* skip the flush */
1214 }
1215
1216 /**
1217  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1218  * @napi: napi struct with our devices info in it
1219  * @budget: amount of work driver is allowed to do this pass, in packets
1220  *
1221  * This function is optimized for cleaning one queue only on a single
1222  * q_vector!!!
1223  **/
1224 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1225 {
1226         struct ixgbe_q_vector *q_vector =
1227                                container_of(napi, struct ixgbe_q_vector, napi);
1228         struct ixgbe_adapter *adapter = q_vector->adapter;
1229         struct ixgbe_ring *rx_ring = NULL;
1230         int work_done = 0;
1231         long r_idx;
1232
1233         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1234         rx_ring = &(adapter->rx_ring[r_idx]);
1235 #ifdef CONFIG_IXGBE_DCA
1236         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1237                 ixgbe_update_rx_dca(adapter, rx_ring);
1238 #endif
1239
1240         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1241
1242         /* If all Rx work done, exit the polling mode */
1243         if (work_done < budget) {
1244                 napi_complete(napi);
1245                 if (adapter->itr_setting & 1)
1246                         ixgbe_set_itr_msix(q_vector);
1247                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1248                         ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1249         }
1250
1251         return work_done;
1252 }
1253
1254 /**
1255  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1256  * @napi: napi struct with our devices info in it
1257  * @budget: amount of work driver is allowed to do this pass, in packets
1258  *
1259  * This function will clean more than one rx queue associated with a
1260  * q_vector.
1261  **/
1262 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1263 {
1264         struct ixgbe_q_vector *q_vector =
1265                                container_of(napi, struct ixgbe_q_vector, napi);
1266         struct ixgbe_adapter *adapter = q_vector->adapter;
1267         struct ixgbe_ring *rx_ring = NULL;
1268         int work_done = 0, i;
1269         long r_idx;
1270         u64 enable_mask = 0;
1271
1272         /* attempt to distribute budget to each queue fairly, but don't allow
1273          * the budget to go below 1 because we'll exit polling */
1274         budget /= (q_vector->rxr_count ?: 1);
1275         budget = max(budget, 1);
1276         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277         for (i = 0; i < q_vector->rxr_count; i++) {
1278                 rx_ring = &(adapter->rx_ring[r_idx]);
1279 #ifdef CONFIG_IXGBE_DCA
1280                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281                         ixgbe_update_rx_dca(adapter, rx_ring);
1282 #endif
1283                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1284                 enable_mask |= rx_ring->v_idx;
1285                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286                                       r_idx + 1);
1287         }
1288
1289         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1290         rx_ring = &(adapter->rx_ring[r_idx]);
1291         /* If all Rx work done, exit the polling mode */
1292         if (work_done < budget) {
1293                 napi_complete(napi);
1294                 if (adapter->itr_setting & 1)
1295                         ixgbe_set_itr_msix(q_vector);
1296                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1297                         ixgbe_irq_enable_queues(adapter, enable_mask);
1298                 return 0;
1299         }
1300
1301         return work_done;
1302 }
1303 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1304                                      int r_idx)
1305 {
1306         a->q_vector[v_idx].adapter = a;
1307         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1308         a->q_vector[v_idx].rxr_count++;
1309         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1310 }
1311
1312 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1313                                      int r_idx)
1314 {
1315         a->q_vector[v_idx].adapter = a;
1316         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1317         a->q_vector[v_idx].txr_count++;
1318         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1319 }
1320
1321 /**
1322  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1323  * @adapter: board private structure to initialize
1324  * @vectors: allotted vector count for descriptor rings
1325  *
1326  * This function maps descriptor rings to the queue-specific vectors
1327  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1328  * one vector per ring/queue, but on a constrained vector budget, we
1329  * group the rings as "efficiently" as possible.  You would add new
1330  * mapping configurations in here.
1331  **/
1332 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1333                                       int vectors)
1334 {
1335         int v_start = 0;
1336         int rxr_idx = 0, txr_idx = 0;
1337         int rxr_remaining = adapter->num_rx_queues;
1338         int txr_remaining = adapter->num_tx_queues;
1339         int i, j;
1340         int rqpv, tqpv;
1341         int err = 0;
1342
1343         /* No mapping required if MSI-X is disabled. */
1344         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1345                 goto out;
1346
1347         /*
1348          * The ideal configuration...
1349          * We have enough vectors to map one per queue.
1350          */
1351         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1352                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1353                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1354
1355                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1356                         map_vector_to_txq(adapter, v_start, txr_idx);
1357
1358                 goto out;
1359         }
1360
1361         /*
1362          * If we don't have enough vectors for a 1-to-1
1363          * mapping, we'll have to group them so there are
1364          * multiple queues per vector.
1365          */
1366         /* Re-adjusting *qpv takes care of the remainder. */
1367         for (i = v_start; i < vectors; i++) {
1368                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1369                 for (j = 0; j < rqpv; j++) {
1370                         map_vector_to_rxq(adapter, i, rxr_idx);
1371                         rxr_idx++;
1372                         rxr_remaining--;
1373                 }
1374         }
1375         for (i = v_start; i < vectors; i++) {
1376                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1377                 for (j = 0; j < tqpv; j++) {
1378                         map_vector_to_txq(adapter, i, txr_idx);
1379                         txr_idx++;
1380                         txr_remaining--;
1381                 }
1382         }
1383
1384 out:
1385         return err;
1386 }
1387
1388 /**
1389  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1390  * @adapter: board private structure
1391  *
1392  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1393  * interrupts from the kernel.
1394  **/
1395 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1396 {
1397         struct net_device *netdev = adapter->netdev;
1398         irqreturn_t (*handler)(int, void *);
1399         int i, vector, q_vectors, err;
1400         int ri=0, ti=0;
1401
1402         /* Decrement for Other and TCP Timer vectors */
1403         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1404
1405         /* Map the Tx/Rx rings to the vectors we were allotted. */
1406         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1407         if (err)
1408                 goto out;
1409
1410 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1411                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1412                          &ixgbe_msix_clean_many)
1413         for (vector = 0; vector < q_vectors; vector++) {
1414                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1415
1416                 if(handler == &ixgbe_msix_clean_rx) {
1417                         sprintf(adapter->name[vector], "%s-%s-%d",
1418                                 netdev->name, "rx", ri++);
1419                 }
1420                 else if(handler == &ixgbe_msix_clean_tx) {
1421                         sprintf(adapter->name[vector], "%s-%s-%d",
1422                                 netdev->name, "tx", ti++);
1423                 }
1424                 else
1425                         sprintf(adapter->name[vector], "%s-%s-%d",
1426                                 netdev->name, "TxRx", vector);
1427
1428                 err = request_irq(adapter->msix_entries[vector].vector,
1429                                   handler, 0, adapter->name[vector],
1430                                   &(adapter->q_vector[vector]));
1431                 if (err) {
1432                         DPRINTK(PROBE, ERR,
1433                                 "request_irq failed for MSIX interrupt "
1434                                 "Error: %d\n", err);
1435                         goto free_queue_irqs;
1436                 }
1437         }
1438
1439         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1440         err = request_irq(adapter->msix_entries[vector].vector,
1441                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1442         if (err) {
1443                 DPRINTK(PROBE, ERR,
1444                         "request_irq for msix_lsc failed: %d\n", err);
1445                 goto free_queue_irqs;
1446         }
1447
1448         return 0;
1449
1450 free_queue_irqs:
1451         for (i = vector - 1; i >= 0; i--)
1452                 free_irq(adapter->msix_entries[--vector].vector,
1453                          &(adapter->q_vector[i]));
1454         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1455         pci_disable_msix(adapter->pdev);
1456         kfree(adapter->msix_entries);
1457         adapter->msix_entries = NULL;
1458 out:
1459         return err;
1460 }
1461
1462 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1463 {
1464         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1465         u8 current_itr;
1466         u32 new_itr = q_vector->eitr;
1467         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1468         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1469
1470         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1471                                             q_vector->tx_itr,
1472                                             tx_ring->total_packets,
1473                                             tx_ring->total_bytes);
1474         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1475                                             q_vector->rx_itr,
1476                                             rx_ring->total_packets,
1477                                             rx_ring->total_bytes);
1478
1479         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1480
1481         switch (current_itr) {
1482         /* counts and packets in update_itr are dependent on these numbers */
1483         case lowest_latency:
1484                 new_itr = 100000;
1485                 break;
1486         case low_latency:
1487                 new_itr = 20000; /* aka hwitr = ~200 */
1488                 break;
1489         case bulk_latency:
1490                 new_itr = 8000;
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         if (new_itr != q_vector->eitr) {
1497                 u32 itr_reg;
1498
1499                 /* save the algorithm value here, not the smoothed one */
1500                 q_vector->eitr = new_itr;
1501                 /* do an exponential smoothing */
1502                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1503                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1504                 ixgbe_write_eitr(adapter, 0, itr_reg);
1505         }
1506
1507         return;
1508 }
1509
1510 /**
1511  * ixgbe_irq_enable - Enable default interrupt generation settings
1512  * @adapter: board private structure
1513  **/
1514 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1515 {
1516         u32 mask;
1517
1518         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1519         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1520                 mask |= IXGBE_EIMS_GPI_SDP1;
1521         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1522                 mask |= IXGBE_EIMS_ECC;
1523                 mask |= IXGBE_EIMS_GPI_SDP1;
1524                 mask |= IXGBE_EIMS_GPI_SDP2;
1525         }
1526
1527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1528         ixgbe_irq_enable_queues(adapter, ~0);
1529         IXGBE_WRITE_FLUSH(&adapter->hw);
1530 }
1531
1532 /**
1533  * ixgbe_intr - legacy mode Interrupt Handler
1534  * @irq: interrupt number
1535  * @data: pointer to a network interface device structure
1536  **/
1537 static irqreturn_t ixgbe_intr(int irq, void *data)
1538 {
1539         struct net_device *netdev = data;
1540         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1541         struct ixgbe_hw *hw = &adapter->hw;
1542         u32 eicr;
1543
1544         /*
1545          * Workaround for silicon errata.  Mask the interrupts
1546          * before the read of EICR.
1547          */
1548         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1549
1550         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1551          * therefore no explict interrupt disable is necessary */
1552         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1553         if (!eicr) {
1554                 /* shared interrupt alert!
1555                  * make sure interrupts are enabled because the read will
1556                  * have disabled interrupts due to EIAM */
1557                 ixgbe_irq_enable(adapter);
1558                 return IRQ_NONE;        /* Not our interrupt */
1559         }
1560
1561         if (eicr & IXGBE_EICR_LSC)
1562                 ixgbe_check_lsc(adapter);
1563
1564         if (hw->mac.type == ixgbe_mac_82599EB)
1565                 ixgbe_check_sfp_event(adapter, eicr);
1566
1567         ixgbe_check_fan_failure(adapter, eicr);
1568
1569         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1570                 adapter->tx_ring[0].total_packets = 0;
1571                 adapter->tx_ring[0].total_bytes = 0;
1572                 adapter->rx_ring[0].total_packets = 0;
1573                 adapter->rx_ring[0].total_bytes = 0;
1574                 /* would disable interrupts here but EIAM disabled it */
1575                 __napi_schedule(&adapter->q_vector[0].napi);
1576         }
1577
1578         return IRQ_HANDLED;
1579 }
1580
1581 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1582 {
1583         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1584
1585         for (i = 0; i < q_vectors; i++) {
1586                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1587                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1588                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1589                 q_vector->rxr_count = 0;
1590                 q_vector->txr_count = 0;
1591         }
1592 }
1593
1594 /**
1595  * ixgbe_request_irq - initialize interrupts
1596  * @adapter: board private structure
1597  *
1598  * Attempts to configure interrupts using the best available
1599  * capabilities of the hardware and kernel.
1600  **/
1601 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1602 {
1603         struct net_device *netdev = adapter->netdev;
1604         int err;
1605
1606         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1607                 err = ixgbe_request_msix_irqs(adapter);
1608         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1609                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1610                                   netdev->name, netdev);
1611         } else {
1612                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1613                                   netdev->name, netdev);
1614         }
1615
1616         if (err)
1617                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1618
1619         return err;
1620 }
1621
1622 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1623 {
1624         struct net_device *netdev = adapter->netdev;
1625
1626         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1627                 int i, q_vectors;
1628
1629                 q_vectors = adapter->num_msix_vectors;
1630
1631                 i = q_vectors - 1;
1632                 free_irq(adapter->msix_entries[i].vector, netdev);
1633
1634                 i--;
1635                 for (; i >= 0; i--) {
1636                         free_irq(adapter->msix_entries[i].vector,
1637                                  &(adapter->q_vector[i]));
1638                 }
1639
1640                 ixgbe_reset_q_vectors(adapter);
1641         } else {
1642                 free_irq(adapter->pdev->irq, netdev);
1643         }
1644 }
1645
1646 /**
1647  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1648  * @adapter: board private structure
1649  **/
1650 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1651 {
1652         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1653                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1654         } else {
1655                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1656                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1657                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1658         }
1659         IXGBE_WRITE_FLUSH(&adapter->hw);
1660         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1661                 int i;
1662                 for (i = 0; i < adapter->num_msix_vectors; i++)
1663                         synchronize_irq(adapter->msix_entries[i].vector);
1664         } else {
1665                 synchronize_irq(adapter->pdev->irq);
1666         }
1667 }
1668
1669 /**
1670  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1671  *
1672  **/
1673 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1674 {
1675         struct ixgbe_hw *hw = &adapter->hw;
1676
1677         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1678                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1679
1680         ixgbe_set_ivar(adapter, 0, 0, 0);
1681         ixgbe_set_ivar(adapter, 1, 0, 0);
1682
1683         map_vector_to_rxq(adapter, 0, 0);
1684         map_vector_to_txq(adapter, 0, 0);
1685
1686         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1687 }
1688
1689 /**
1690  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1691  * @adapter: board private structure
1692  *
1693  * Configure the Tx unit of the MAC after a reset.
1694  **/
1695 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1696 {
1697         u64 tdba;
1698         struct ixgbe_hw *hw = &adapter->hw;
1699         u32 i, j, tdlen, txctrl;
1700
1701         /* Setup the HW Tx Head and Tail descriptor pointers */
1702         for (i = 0; i < adapter->num_tx_queues; i++) {
1703                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1704                 j = ring->reg_idx;
1705                 tdba = ring->dma;
1706                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1707                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1708                                 (tdba & DMA_BIT_MASK(32)));
1709                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1710                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1711                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1712                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1713                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1714                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1715                 /* Disable Tx Head Writeback RO bit, since this hoses
1716                  * bookkeeping if things aren't delivered in order.
1717                  */
1718                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1719                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1720                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1721         }
1722         if (hw->mac.type == ixgbe_mac_82599EB) {
1723                 /* We enable 8 traffic classes, DCB only */
1724                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1725                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1726                                         IXGBE_MTQC_8TC_8TQ));
1727         }
1728 }
1729
1730 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1731
1732 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1733 {
1734         struct ixgbe_ring *rx_ring;
1735         u32 srrctl;
1736         int queue0 = 0;
1737         unsigned long mask;
1738
1739         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1740                 queue0 = index;
1741         } else {
1742                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1743                 queue0 = index & mask;
1744                 index = index & mask;
1745         }
1746
1747         rx_ring = &adapter->rx_ring[queue0];
1748
1749         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1750
1751         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1752         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1753
1754         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1755                 u16 bufsz = IXGBE_RXBUFFER_2048;
1756                 /* grow the amount we can receive on large page machines */
1757                 if (bufsz < (PAGE_SIZE / 2))
1758                         bufsz = (PAGE_SIZE / 2);
1759                 /* cap the bufsz at our largest descriptor size */
1760                 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1761
1762                 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1763                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1764                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1765                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1766                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1767         } else {
1768                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1769
1770                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1771                         srrctl |= IXGBE_RXBUFFER_2048 >>
1772                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1773                 else
1774                         srrctl |= rx_ring->rx_buf_len >>
1775                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1776         }
1777
1778         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1779 }
1780
1781 /**
1782  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1783  * @adapter: board private structure
1784  *
1785  * Configure the Rx unit of the MAC after a reset.
1786  **/
1787 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1788 {
1789         u64 rdba;
1790         struct ixgbe_hw *hw = &adapter->hw;
1791         struct net_device *netdev = adapter->netdev;
1792         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1793         int i, j;
1794         u32 rdlen, rxctrl, rxcsum;
1795         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1796                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1797                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1798         u32 fctrl, hlreg0;
1799         u32 reta = 0, mrqc = 0;
1800         u32 rdrxctl;
1801         u32 rscctrl;
1802         int rx_buf_len;
1803
1804         /* Decide whether to use packet split mode or not */
1805         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1806
1807         /* Set the RX buffer length according to the mode */
1808         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1809                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1810                 if (hw->mac.type == ixgbe_mac_82599EB) {
1811                         /* PSRTYPE must be initialized in 82599 */
1812                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1813                                       IXGBE_PSRTYPE_UDPHDR |
1814                                       IXGBE_PSRTYPE_IPV4HDR |
1815                                       IXGBE_PSRTYPE_IPV6HDR;
1816                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1817                 }
1818         } else {
1819                 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1820                     (netdev->mtu <= ETH_DATA_LEN))
1821                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1822                 else
1823                         rx_buf_len = ALIGN(max_frame, 1024);
1824         }
1825
1826         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1827         fctrl |= IXGBE_FCTRL_BAM;
1828         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1829         fctrl |= IXGBE_FCTRL_PMCF;
1830         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1831
1832         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1833         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1834                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1835         else
1836                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1837         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1838
1839         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1840         /* disable receives while setting up the descriptors */
1841         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1842         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1843
1844         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1845          * the Base and Length of the Rx Descriptor Ring */
1846         for (i = 0; i < adapter->num_rx_queues; i++) {
1847                 rdba = adapter->rx_ring[i].dma;
1848                 j = adapter->rx_ring[i].reg_idx;
1849                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1850                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1851                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1852                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1853                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1854                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1855                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1856                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1857
1858                 ixgbe_configure_srrctl(adapter, j);
1859         }
1860
1861         if (hw->mac.type == ixgbe_mac_82598EB) {
1862                 /*
1863                  * For VMDq support of different descriptor types or
1864                  * buffer sizes through the use of multiple SRRCTL
1865                  * registers, RDRXCTL.MVMEN must be set to 1
1866                  *
1867                  * also, the manual doesn't mention it clearly but DCA hints
1868                  * will only use queue 0's tags unless this bit is set.  Side
1869                  * effects of setting this bit are only that SRRCTL must be
1870                  * fully programmed [0..15]
1871                  */
1872                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1873                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1874                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1875         }
1876
1877         /* Program MRQC for the distribution of queues */
1878         if (hw->mac.type == ixgbe_mac_82599EB) {
1879                 int mask = adapter->flags & (
1880                                 IXGBE_FLAG_RSS_ENABLED
1881                                 | IXGBE_FLAG_DCB_ENABLED
1882                                 );
1883
1884                 switch (mask) {
1885                 case (IXGBE_FLAG_RSS_ENABLED):
1886                         mrqc = IXGBE_MRQC_RSSEN;
1887                         break;
1888                 case (IXGBE_FLAG_DCB_ENABLED):
1889                         mrqc = IXGBE_MRQC_RT8TCEN;
1890                         break;
1891                 default:
1892                         break;
1893                 }
1894         }
1895         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1896                 /* Fill out redirection table */
1897                 for (i = 0, j = 0; i < 128; i++, j++) {
1898                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1899                                 j = 0;
1900                         /* reta = 4-byte sliding window of
1901                          * 0x00..(indices-1)(indices-1)00..etc. */
1902                         reta = (reta << 8) | (j * 0x11);
1903                         if ((i & 3) == 3)
1904                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1905                 }
1906
1907                 /* Fill out hash function seeds */
1908                 for (i = 0; i < 10; i++)
1909                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1910
1911                 if (hw->mac.type == ixgbe_mac_82598EB)
1912                         mrqc |= IXGBE_MRQC_RSSEN;
1913                     /* Perform hash on these packet types */
1914                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1915                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1916                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1917                       | IXGBE_MRQC_RSS_FIELD_IPV6
1918                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1919                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1920         }
1921         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1922
1923         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1924
1925         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1926             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1927                 /* Disable indicating checksum in descriptor, enables
1928                  * RSS hash */
1929                 rxcsum |= IXGBE_RXCSUM_PCSD;
1930         }
1931         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1932                 /* Enable IPv4 payload checksum for UDP fragments
1933                  * if PCSD is not set */
1934                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1935         }
1936
1937         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1938
1939         if (hw->mac.type == ixgbe_mac_82599EB) {
1940                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1941                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1942                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
1943                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1944         }
1945
1946         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1947                 /* Enable 82599 HW-RSC */
1948                 for (i = 0; i < adapter->num_rx_queues; i++) {
1949                         j = adapter->rx_ring[i].reg_idx;
1950                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1951                         rscctrl |= IXGBE_RSCCTL_RSCEN;
1952                         /*
1953                          *  if packet split is enabled we can only support up
1954                          *  to max frags + 1 descriptors.
1955                          */
1956                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1957 #if (MAX_SKB_FRAGS < 3)
1958                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1959 #elif (MAX_SKB_FRAGS < 7)
1960                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1961 #elif (MAX_SKB_FRAGS < 15)
1962                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1963 #else
1964                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1965 #endif
1966                         else
1967                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1968                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1969                 }
1970                 /* Disable RSC for ACK packets */
1971                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1972                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1973         }
1974 }
1975
1976 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1977 {
1978         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1979         struct ixgbe_hw *hw = &adapter->hw;
1980
1981         /* add VID to filter table */
1982         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1983 }
1984
1985 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1986 {
1987         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1988         struct ixgbe_hw *hw = &adapter->hw;
1989
1990         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1991                 ixgbe_irq_disable(adapter);
1992
1993         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1994
1995         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1996                 ixgbe_irq_enable(adapter);
1997
1998         /* remove VID from filter table */
1999         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2000 }
2001
2002 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2003                                    struct vlan_group *grp)
2004 {
2005         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2006         u32 ctrl;
2007         int i, j;
2008
2009         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2010                 ixgbe_irq_disable(adapter);
2011         adapter->vlgrp = grp;
2012
2013         /*
2014          * For a DCB driver, always enable VLAN tag stripping so we can
2015          * still receive traffic from a DCB-enabled host even if we're
2016          * not in DCB mode.
2017          */
2018         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2019         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2020                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2021                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2022                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2023         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2024                 ctrl |= IXGBE_VLNCTRL_VFE;
2025                 /* enable VLAN tag insert/strip */
2026                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2027                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2028                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2029                 for (i = 0; i < adapter->num_rx_queues; i++) {
2030                         j = adapter->rx_ring[i].reg_idx;
2031                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2032                         ctrl |= IXGBE_RXDCTL_VME;
2033                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2034                 }
2035         }
2036         ixgbe_vlan_rx_add_vid(netdev, 0);
2037
2038         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2039                 ixgbe_irq_enable(adapter);
2040 }
2041
2042 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2043 {
2044         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2045
2046         if (adapter->vlgrp) {
2047                 u16 vid;
2048                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2049                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2050                                 continue;
2051                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2052                 }
2053         }
2054 }
2055
2056 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2057 {
2058         struct dev_mc_list *mc_ptr;
2059         u8 *addr = *mc_addr_ptr;
2060         *vmdq = 0;
2061
2062         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2063         if (mc_ptr->next)
2064                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2065         else
2066                 *mc_addr_ptr = NULL;
2067
2068         return addr;
2069 }
2070
2071 /**
2072  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2073  * @netdev: network interface device structure
2074  *
2075  * The set_rx_method entry point is called whenever the unicast/multicast
2076  * address list or the network interface flags are updated.  This routine is
2077  * responsible for configuring the hardware for proper unicast, multicast and
2078  * promiscuous mode.
2079  **/
2080 static void ixgbe_set_rx_mode(struct net_device *netdev)
2081 {
2082         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2083         struct ixgbe_hw *hw = &adapter->hw;
2084         u32 fctrl, vlnctrl;
2085         u8 *addr_list = NULL;
2086         int addr_count = 0;
2087
2088         /* Check for Promiscuous and All Multicast modes */
2089
2090         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2091         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2092
2093         if (netdev->flags & IFF_PROMISC) {
2094                 hw->addr_ctrl.user_set_promisc = 1;
2095                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2096                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2097         } else {
2098                 if (netdev->flags & IFF_ALLMULTI) {
2099                         fctrl |= IXGBE_FCTRL_MPE;
2100                         fctrl &= ~IXGBE_FCTRL_UPE;
2101                 } else {
2102                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2103                 }
2104                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2105                 hw->addr_ctrl.user_set_promisc = 0;
2106         }
2107
2108         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2109         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2110
2111         /* reprogram secondary unicast list */
2112         addr_count = netdev->uc_count;
2113         if (addr_count)
2114                 addr_list = netdev->uc_list->dmi_addr;
2115         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2116                                           ixgbe_addr_list_itr);
2117
2118         /* reprogram multicast list */
2119         addr_count = netdev->mc_count;
2120         if (addr_count)
2121                 addr_list = netdev->mc_list->dmi_addr;
2122         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2123                                         ixgbe_addr_list_itr);
2124 }
2125
2126 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2127 {
2128         int q_idx;
2129         struct ixgbe_q_vector *q_vector;
2130         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2131
2132         /* legacy and MSI only use one vector */
2133         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2134                 q_vectors = 1;
2135
2136         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2137                 struct napi_struct *napi;
2138                 q_vector = &adapter->q_vector[q_idx];
2139                 if (!q_vector->rxr_count)
2140                         continue;
2141                 napi = &q_vector->napi;
2142                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2143                     (q_vector->rxr_count > 1))
2144                         napi->poll = &ixgbe_clean_rxonly_many;
2145
2146                 napi_enable(napi);
2147         }
2148 }
2149
2150 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2151 {
2152         int q_idx;
2153         struct ixgbe_q_vector *q_vector;
2154         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2155
2156         /* legacy and MSI only use one vector */
2157         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2158                 q_vectors = 1;
2159
2160         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2161                 q_vector = &adapter->q_vector[q_idx];
2162                 if (!q_vector->rxr_count)
2163                         continue;
2164                 napi_disable(&q_vector->napi);
2165         }
2166 }
2167
2168 #ifdef CONFIG_IXGBE_DCB
2169 /*
2170  * ixgbe_configure_dcb - Configure DCB hardware
2171  * @adapter: ixgbe adapter struct
2172  *
2173  * This is called by the driver on open to configure the DCB hardware.
2174  * This is also called by the gennetlink interface when reconfiguring
2175  * the DCB state.
2176  */
2177 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2178 {
2179         struct ixgbe_hw *hw = &adapter->hw;
2180         u32 txdctl, vlnctrl;
2181         int i, j;
2182
2183         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2184         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2185         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2186
2187         /* reconfigure the hardware */
2188         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2189
2190         for (i = 0; i < adapter->num_tx_queues; i++) {
2191                 j = adapter->tx_ring[i].reg_idx;
2192                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2193                 /* PThresh workaround for Tx hang with DFP enabled. */
2194                 txdctl |= 32;
2195                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2196         }
2197         /* Enable VLAN tag insert/strip */
2198         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2199         if (hw->mac.type == ixgbe_mac_82598EB) {
2200                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2201                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2202                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2203         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2204                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2205                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2206                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2207                 for (i = 0; i < adapter->num_rx_queues; i++) {
2208                         j = adapter->rx_ring[i].reg_idx;
2209                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2210                         vlnctrl |= IXGBE_RXDCTL_VME;
2211                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2212                 }
2213         }
2214         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2215 }
2216
2217 #endif
2218 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2219 {
2220         struct net_device *netdev = adapter->netdev;
2221         int i;
2222
2223         ixgbe_set_rx_mode(netdev);
2224
2225         ixgbe_restore_vlan(adapter);
2226 #ifdef CONFIG_IXGBE_DCB
2227         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2228                 netif_set_gso_max_size(netdev, 32768);
2229                 ixgbe_configure_dcb(adapter);
2230         } else {
2231                 netif_set_gso_max_size(netdev, 65536);
2232         }
2233 #else
2234         netif_set_gso_max_size(netdev, 65536);
2235 #endif
2236
2237         ixgbe_configure_tx(adapter);
2238         ixgbe_configure_rx(adapter);
2239         for (i = 0; i < adapter->num_rx_queues; i++)
2240                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2241                                        (adapter->rx_ring[i].count - 1));
2242 }
2243
2244 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2245 {
2246         switch (hw->phy.type) {
2247         case ixgbe_phy_sfp_avago:
2248         case ixgbe_phy_sfp_ftl:
2249         case ixgbe_phy_sfp_intel:
2250         case ixgbe_phy_sfp_unknown:
2251         case ixgbe_phy_tw_tyco:
2252         case ixgbe_phy_tw_unknown:
2253                 return true;
2254         default:
2255                 return false;
2256         }
2257 }
2258
2259 /**
2260  * ixgbe_sfp_link_config - set up SFP+ link
2261  * @adapter: pointer to private adapter struct
2262  **/
2263 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2264 {
2265         struct ixgbe_hw *hw = &adapter->hw;
2266
2267                 if (hw->phy.multispeed_fiber) {
2268                         /*
2269                          * In multispeed fiber setups, the device may not have
2270                          * had a physical connection when the driver loaded.
2271                          * If that's the case, the initial link configuration
2272                          * couldn't get the MAC into 10G or 1G mode, so we'll
2273                          * never have a link status change interrupt fire.
2274                          * We need to try and force an autonegotiation
2275                          * session, then bring up link.
2276                          */
2277                         hw->mac.ops.setup_sfp(hw);
2278                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2279                                 schedule_work(&adapter->multispeed_fiber_task);
2280                 } else {
2281                         /*
2282                          * Direct Attach Cu and non-multispeed fiber modules
2283                          * still need to be configured properly prior to
2284                          * attempting link.
2285                          */
2286                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2287                                 schedule_work(&adapter->sfp_config_module_task);
2288                 }
2289 }
2290
2291 /**
2292  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2293  * @hw: pointer to private hardware struct
2294  *
2295  * Returns 0 on success, negative on failure
2296  **/
2297 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2298 {
2299         u32 autoneg;
2300         bool link_up = false;
2301         u32 ret = IXGBE_ERR_LINK_SETUP;
2302
2303         if (hw->mac.ops.check_link)
2304                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2305
2306         if (ret)
2307                 goto link_cfg_out;
2308
2309         if (hw->mac.ops.get_link_capabilities)
2310                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2311                                                         &hw->mac.autoneg);
2312         if (ret)
2313                 goto link_cfg_out;
2314
2315         if (hw->mac.ops.setup_link_speed)
2316                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2317 link_cfg_out:
2318         return ret;
2319 }
2320
2321 #define IXGBE_MAX_RX_DESC_POLL 10
2322 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2323                                               int rxr)
2324 {
2325         int j = adapter->rx_ring[rxr].reg_idx;
2326         int k;
2327
2328         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2329                 if (IXGBE_READ_REG(&adapter->hw,
2330                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2331                         break;
2332                 else
2333                         msleep(1);
2334         }
2335         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2336                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2337                         "not set within the polling period\n", rxr);
2338         }
2339         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2340                               (adapter->rx_ring[rxr].count - 1));
2341 }
2342
2343 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2344 {
2345         struct net_device *netdev = adapter->netdev;
2346         struct ixgbe_hw *hw = &adapter->hw;
2347         int i, j = 0;
2348         int num_rx_rings = adapter->num_rx_queues;
2349         int err;
2350         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2351         u32 txdctl, rxdctl, mhadd;
2352         u32 dmatxctl;
2353         u32 gpie;
2354
2355         ixgbe_get_hw_control(adapter);
2356
2357         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2358             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2359                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2360                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2361                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2362                 } else {
2363                         /* MSI only */
2364                         gpie = 0;
2365                 }
2366                 /* XXX: to interrupt immediately for EICS writes, enable this */
2367                 /* gpie |= IXGBE_GPIE_EIMEN; */
2368                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2369         }
2370
2371         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2372                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2373                  * specifically only auto mask tx and rx interrupts */
2374                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2375         }
2376
2377         /* Enable fan failure interrupt if media type is copper */
2378         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2379                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2380                 gpie |= IXGBE_SDP1_GPIEN;
2381                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2382         }
2383
2384         if (hw->mac.type == ixgbe_mac_82599EB) {
2385                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386                 gpie |= IXGBE_SDP1_GPIEN;
2387                 gpie |= IXGBE_SDP2_GPIEN;
2388                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2389         }
2390
2391         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2392         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2393                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2394                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2395
2396                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2397         }
2398
2399         for (i = 0; i < adapter->num_tx_queues; i++) {
2400                 j = adapter->tx_ring[i].reg_idx;
2401                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2402                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2403                 txdctl |= (8 << 16);
2404                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2405         }
2406
2407         if (hw->mac.type == ixgbe_mac_82599EB) {
2408                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2409                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2410                 dmatxctl |= IXGBE_DMATXCTL_TE;
2411                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2412         }
2413         for (i = 0; i < adapter->num_tx_queues; i++) {
2414                 j = adapter->tx_ring[i].reg_idx;
2415                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2416                 txdctl |= IXGBE_TXDCTL_ENABLE;
2417                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2418         }
2419
2420         for (i = 0; i < num_rx_rings; i++) {
2421                 j = adapter->rx_ring[i].reg_idx;
2422                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2423                 /* enable PTHRESH=32 descriptors (half the internal cache)
2424                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2425                  * this also removes a pesky rx_no_buffer_count increment */
2426                 rxdctl |= 0x0020;
2427                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2428                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2429                 if (hw->mac.type == ixgbe_mac_82599EB)
2430                         ixgbe_rx_desc_queue_enable(adapter, i);
2431         }
2432         /* enable all receives */
2433         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2434         if (hw->mac.type == ixgbe_mac_82598EB)
2435                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2436         else
2437                 rxdctl |= IXGBE_RXCTRL_RXEN;
2438         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2439
2440         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2441                 ixgbe_configure_msix(adapter);
2442         else
2443                 ixgbe_configure_msi_and_legacy(adapter);
2444
2445         clear_bit(__IXGBE_DOWN, &adapter->state);
2446         ixgbe_napi_enable_all(adapter);
2447
2448         /* clear any pending interrupts, may auto mask */
2449         IXGBE_READ_REG(hw, IXGBE_EICR);
2450
2451         ixgbe_irq_enable(adapter);
2452
2453         /*
2454          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2455          * arrived before interrupts were enabled.  We need to kick off
2456          * the SFP+ module setup first, then try to bring up link.
2457          * If we're not hot-pluggable SFP+, we just need to configure link
2458          * and bring it up.
2459          */
2460         err = hw->phy.ops.identify(hw);
2461         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2462                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2463                 ixgbe_down(adapter);
2464                 return err;
2465         }
2466
2467         if (ixgbe_is_sfp(hw)) {
2468                 ixgbe_sfp_link_config(adapter);
2469         } else {
2470                 err = ixgbe_non_sfp_link_config(hw);
2471                 if (err)
2472                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2473         }
2474
2475         /* enable transmits */
2476         netif_tx_start_all_queues(netdev);
2477
2478         /* bring the link up in the watchdog, this could race with our first
2479          * link up interrupt but shouldn't be a problem */
2480         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2481         adapter->link_check_timeout = jiffies;
2482         mod_timer(&adapter->watchdog_timer, jiffies);
2483         return 0;
2484 }
2485
2486 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2487 {
2488         WARN_ON(in_interrupt());
2489         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2490                 msleep(1);
2491         ixgbe_down(adapter);
2492         ixgbe_up(adapter);
2493         clear_bit(__IXGBE_RESETTING, &adapter->state);
2494 }
2495
2496 int ixgbe_up(struct ixgbe_adapter *adapter)
2497 {
2498         /* hardware has been reset, we need to reload some things */
2499         ixgbe_configure(adapter);
2500
2501         ixgbe_napi_add_all(adapter);
2502
2503         return ixgbe_up_complete(adapter);
2504 }
2505
2506 void ixgbe_reset(struct ixgbe_adapter *adapter)
2507 {
2508         struct ixgbe_hw *hw = &adapter->hw;
2509         if (hw->mac.ops.init_hw(hw))
2510                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2511
2512         /* reprogram the RAR[0] in case user changed it. */
2513         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2514
2515 }
2516
2517 /**
2518  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2519  * @adapter: board private structure
2520  * @rx_ring: ring to free buffers from
2521  **/
2522 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2523                                 struct ixgbe_ring *rx_ring)
2524 {
2525         struct pci_dev *pdev = adapter->pdev;
2526         unsigned long size;
2527         unsigned int i;
2528
2529         /* Free all the Rx ring sk_buffs */
2530
2531         for (i = 0; i < rx_ring->count; i++) {
2532                 struct ixgbe_rx_buffer *rx_buffer_info;
2533
2534                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2535                 if (rx_buffer_info->dma) {
2536                         pci_unmap_single(pdev, rx_buffer_info->dma,
2537                                          rx_ring->rx_buf_len,
2538                                          PCI_DMA_FROMDEVICE);
2539                         rx_buffer_info->dma = 0;
2540                 }
2541                 if (rx_buffer_info->skb) {
2542                         struct sk_buff *skb = rx_buffer_info->skb;
2543                         rx_buffer_info->skb = NULL;
2544                         do {
2545                                 struct sk_buff *this = skb;
2546                                 skb = skb->prev;
2547                                 dev_kfree_skb(this);
2548                         } while (skb);
2549                 }
2550                 if (!rx_buffer_info->page)
2551                         continue;
2552                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2553                                PCI_DMA_FROMDEVICE);
2554                 rx_buffer_info->page_dma = 0;
2555                 put_page(rx_buffer_info->page);
2556                 rx_buffer_info->page = NULL;
2557                 rx_buffer_info->page_offset = 0;
2558         }
2559
2560         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2561         memset(rx_ring->rx_buffer_info, 0, size);
2562
2563         /* Zero out the descriptor ring */
2564         memset(rx_ring->desc, 0, rx_ring->size);
2565
2566         rx_ring->next_to_clean = 0;
2567         rx_ring->next_to_use = 0;
2568
2569         if (rx_ring->head)
2570                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2571         if (rx_ring->tail)
2572                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2573 }
2574
2575 /**
2576  * ixgbe_clean_tx_ring - Free Tx Buffers
2577  * @adapter: board private structure
2578  * @tx_ring: ring to be cleaned
2579  **/
2580 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2581                                 struct ixgbe_ring *tx_ring)
2582 {
2583         struct ixgbe_tx_buffer *tx_buffer_info;
2584         unsigned long size;
2585         unsigned int i;
2586
2587         /* Free all the Tx ring sk_buffs */
2588
2589         for (i = 0; i < tx_ring->count; i++) {
2590                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2591                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2592         }
2593
2594         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2595         memset(tx_ring->tx_buffer_info, 0, size);
2596
2597         /* Zero out the descriptor ring */
2598         memset(tx_ring->desc, 0, tx_ring->size);
2599
2600         tx_ring->next_to_use = 0;
2601         tx_ring->next_to_clean = 0;
2602
2603         if (tx_ring->head)
2604                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2605         if (tx_ring->tail)
2606                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2607 }
2608
2609 /**
2610  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2611  * @adapter: board private structure
2612  **/
2613 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2614 {
2615         int i;
2616
2617         for (i = 0; i < adapter->num_rx_queues; i++)
2618                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2619 }
2620
2621 /**
2622  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2623  * @adapter: board private structure
2624  **/
2625 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2626 {
2627         int i;
2628
2629         for (i = 0; i < adapter->num_tx_queues; i++)
2630                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2631 }
2632
2633 void ixgbe_down(struct ixgbe_adapter *adapter)
2634 {
2635         struct net_device *netdev = adapter->netdev;
2636         struct ixgbe_hw *hw = &adapter->hw;
2637         u32 rxctrl;
2638         u32 txdctl;
2639         int i, j;
2640
2641         /* signal that we are down to the interrupt handler */
2642         set_bit(__IXGBE_DOWN, &adapter->state);
2643
2644         /* disable receives */
2645         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2646         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2647
2648         netif_tx_disable(netdev);
2649
2650         IXGBE_WRITE_FLUSH(hw);
2651         msleep(10);
2652
2653         netif_tx_stop_all_queues(netdev);
2654
2655         ixgbe_irq_disable(adapter);
2656
2657         ixgbe_napi_disable_all(adapter);
2658
2659         del_timer_sync(&adapter->watchdog_timer);
2660         cancel_work_sync(&adapter->watchdog_task);
2661
2662         /* disable transmits in the hardware now that interrupts are off */
2663         for (i = 0; i < adapter->num_tx_queues; i++) {
2664                 j = adapter->tx_ring[i].reg_idx;
2665                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2666                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2667                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2668         }
2669         /* Disable the Tx DMA engine on 82599 */
2670         if (hw->mac.type == ixgbe_mac_82599EB)
2671                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2672                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2673                                  ~IXGBE_DMATXCTL_TE));
2674
2675         netif_carrier_off(netdev);
2676
2677 #ifdef CONFIG_IXGBE_DCA
2678         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2679                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2680                 dca_remove_requester(&adapter->pdev->dev);
2681         }
2682
2683 #endif
2684         if (!pci_channel_offline(adapter->pdev))
2685                 ixgbe_reset(adapter);
2686         ixgbe_clean_all_tx_rings(adapter);
2687         ixgbe_clean_all_rx_rings(adapter);
2688
2689 #ifdef CONFIG_IXGBE_DCA
2690         /* since we reset the hardware DCA settings were cleared */
2691         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2692                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2693                 /* always use CB2 mode, difference is masked
2694                  * in the CB driver */
2695                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2696                 ixgbe_setup_dca(adapter);
2697         }
2698 #endif
2699 }
2700
2701 /**
2702  * ixgbe_poll - NAPI Rx polling callback
2703  * @napi: structure for representing this polling device
2704  * @budget: how many packets driver is allowed to clean
2705  *
2706  * This function is used for legacy and MSI, NAPI mode
2707  **/
2708 static int ixgbe_poll(struct napi_struct *napi, int budget)
2709 {
2710         struct ixgbe_q_vector *q_vector =
2711                                 container_of(napi, struct ixgbe_q_vector, napi);
2712         struct ixgbe_adapter *adapter = q_vector->adapter;
2713         int tx_clean_complete, work_done = 0;
2714
2715 #ifdef CONFIG_IXGBE_DCA
2716         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2717                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2718                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2719         }
2720 #endif
2721
2722         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2723         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2724
2725         if (!tx_clean_complete)
2726                 work_done = budget;
2727
2728         /* If budget not fully consumed, exit the polling mode */
2729         if (work_done < budget) {
2730                 napi_complete(napi);
2731                 if (adapter->itr_setting & 1)
2732                         ixgbe_set_itr(adapter);
2733                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2734                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2735         }
2736         return work_done;
2737 }
2738
2739 /**
2740  * ixgbe_tx_timeout - Respond to a Tx Hang
2741  * @netdev: network interface device structure
2742  **/
2743 static void ixgbe_tx_timeout(struct net_device *netdev)
2744 {
2745         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2746
2747         /* Do the reset outside of interrupt context */
2748         schedule_work(&adapter->reset_task);
2749 }
2750
2751 static void ixgbe_reset_task(struct work_struct *work)
2752 {
2753         struct ixgbe_adapter *adapter;
2754         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2755
2756         /* If we're already down or resetting, just bail */
2757         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2758             test_bit(__IXGBE_RESETTING, &adapter->state))
2759                 return;
2760
2761         adapter->tx_timeout_count++;
2762
2763         ixgbe_reinit_locked(adapter);
2764 }
2765
2766 #ifdef CONFIG_IXGBE_DCB
2767 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2768 {
2769         bool ret = false;
2770
2771         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2772                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2773                 adapter->num_rx_queues =
2774                                       adapter->ring_feature[RING_F_DCB].indices;
2775                 adapter->num_tx_queues =
2776                                       adapter->ring_feature[RING_F_DCB].indices;
2777                 ret = true;
2778         } else {
2779                 ret = false;
2780         }
2781
2782         return ret;
2783 }
2784 #endif
2785
2786 /**
2787  * ixgbe_set_rss_queues: Allocate queues for RSS
2788  * @adapter: board private structure to initialize
2789  *
2790  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2791  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2792  *
2793  **/
2794 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2795 {
2796         bool ret = false;
2797
2798         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2799                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2800                 adapter->num_rx_queues =
2801                                       adapter->ring_feature[RING_F_RSS].indices;
2802                 adapter->num_tx_queues =
2803                                       adapter->ring_feature[RING_F_RSS].indices;
2804                 ret = true;
2805         } else {
2806                 ret = false;
2807         }
2808
2809         return ret;
2810 }
2811
2812 /*
2813  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2814  * @adapter: board private structure to initialize
2815  *
2816  * This is the top level queue allocation routine.  The order here is very
2817  * important, starting with the "most" number of features turned on at once,
2818  * and ending with the smallest set of features.  This way large combinations
2819  * can be allocated if they're turned on, and smaller combinations are the
2820  * fallthrough conditions.
2821  *
2822  **/
2823 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2824 {
2825 #ifdef CONFIG_IXGBE_DCB
2826         if (ixgbe_set_dcb_queues(adapter))
2827                 goto done;
2828
2829 #endif
2830         if (ixgbe_set_rss_queues(adapter))
2831                 goto done;
2832
2833         /* fallback to base case */
2834         adapter->num_rx_queues = 1;
2835         adapter->num_tx_queues = 1;
2836
2837 done:
2838         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2839         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2840 }
2841
2842 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2843                                        int vectors)
2844 {
2845         int err, vector_threshold;
2846
2847         /* We'll want at least 3 (vector_threshold):
2848          * 1) TxQ[0] Cleanup
2849          * 2) RxQ[0] Cleanup
2850          * 3) Other (Link Status Change, etc.)
2851          * 4) TCP Timer (optional)
2852          */
2853         vector_threshold = MIN_MSIX_COUNT;
2854
2855         /* The more we get, the more we will assign to Tx/Rx Cleanup
2856          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2857          * Right now, we simply care about how many we'll get; we'll
2858          * set them up later while requesting irq's.
2859          */
2860         while (vectors >= vector_threshold) {
2861                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2862                                       vectors);
2863                 if (!err) /* Success in acquiring all requested vectors. */
2864                         break;
2865                 else if (err < 0)
2866                         vectors = 0; /* Nasty failure, quit now */
2867                 else /* err == number of vectors we should try again with */
2868                         vectors = err;
2869         }
2870
2871         if (vectors < vector_threshold) {
2872                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2873                  * This just means we'll go with either a single MSI
2874                  * vector or fall back to legacy interrupts.
2875                  */
2876                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2877                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2878                 kfree(adapter->msix_entries);
2879                 adapter->msix_entries = NULL;
2880                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2881                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2882                 ixgbe_set_num_queues(adapter);
2883         } else {
2884                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2885                 /*
2886                  * Adjust for only the vectors we'll use, which is minimum
2887                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2888                  * vectors we were allocated.
2889                  */
2890                 adapter->num_msix_vectors = min(vectors,
2891                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2892         }
2893 }
2894
2895 /**
2896  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2897  * @adapter: board private structure to initialize
2898  *
2899  * Cache the descriptor ring offsets for RSS to the assigned rings.
2900  *
2901  **/
2902 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2903 {
2904         int i;
2905         bool ret = false;
2906
2907         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2908                 for (i = 0; i < adapter->num_rx_queues; i++)
2909                         adapter->rx_ring[i].reg_idx = i;
2910                 for (i = 0; i < adapter->num_tx_queues; i++)
2911                         adapter->tx_ring[i].reg_idx = i;
2912                 ret = true;
2913         } else {
2914                 ret = false;
2915         }
2916
2917         return ret;
2918 }
2919
2920 #ifdef CONFIG_IXGBE_DCB
2921 /**
2922  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2923  * @adapter: board private structure to initialize
2924  *
2925  * Cache the descriptor ring offsets for DCB to the assigned rings.
2926  *
2927  **/
2928 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2929 {
2930         int i;
2931         bool ret = false;
2932         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2933
2934         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2935                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2936                         /* the number of queues is assumed to be symmetric */
2937                         for (i = 0; i < dcb_i; i++) {
2938                                 adapter->rx_ring[i].reg_idx = i << 3;
2939                                 adapter->tx_ring[i].reg_idx = i << 2;
2940                         }
2941                         ret = true;
2942                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2943                         if (dcb_i == 8) {
2944                                 /*
2945                                  * Tx TC0 starts at: descriptor queue 0
2946                                  * Tx TC1 starts at: descriptor queue 32
2947                                  * Tx TC2 starts at: descriptor queue 64
2948                                  * Tx TC3 starts at: descriptor queue 80
2949                                  * Tx TC4 starts at: descriptor queue 96
2950                                  * Tx TC5 starts at: descriptor queue 104
2951                                  * Tx TC6 starts at: descriptor queue 112
2952                                  * Tx TC7 starts at: descriptor queue 120
2953                                  *
2954                                  * Rx TC0-TC7 are offset by 16 queues each
2955                                  */
2956                                 for (i = 0; i < 3; i++) {
2957                                         adapter->tx_ring[i].reg_idx = i << 5;
2958                                         adapter->rx_ring[i].reg_idx = i << 4;
2959                                 }
2960                                 for ( ; i < 5; i++) {
2961                                         adapter->tx_ring[i].reg_idx =
2962                                                                  ((i + 2) << 4);
2963                                         adapter->rx_ring[i].reg_idx = i << 4;
2964                                 }
2965                                 for ( ; i < dcb_i; i++) {
2966                                         adapter->tx_ring[i].reg_idx =
2967                                                                  ((i + 8) << 3);
2968                                         adapter->rx_ring[i].reg_idx = i << 4;
2969                                 }
2970
2971                                 ret = true;
2972                         } else if (dcb_i == 4) {
2973                                 /*
2974                                  * Tx TC0 starts at: descriptor queue 0
2975                                  * Tx TC1 starts at: descriptor queue 64
2976                                  * Tx TC2 starts at: descriptor queue 96
2977                                  * Tx TC3 starts at: descriptor queue 112
2978                                  *
2979                                  * Rx TC0-TC3 are offset by 32 queues each
2980                                  */
2981                                 adapter->tx_ring[0].reg_idx = 0;
2982                                 adapter->tx_ring[1].reg_idx = 64;
2983                                 adapter->tx_ring[2].reg_idx = 96;
2984                                 adapter->tx_ring[3].reg_idx = 112;
2985                                 for (i = 0 ; i < dcb_i; i++)
2986                                         adapter->rx_ring[i].reg_idx = i << 5;
2987
2988                                 ret = true;
2989                         } else {
2990                                 ret = false;
2991                         }
2992                 } else {
2993                         ret = false;
2994                 }
2995         } else {
2996                 ret = false;
2997         }
2998
2999         return ret;
3000 }
3001 #endif
3002
3003 /**
3004  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3005  * @adapter: board private structure to initialize
3006  *
3007  * Once we know the feature-set enabled for the device, we'll cache
3008  * the register offset the descriptor ring is assigned to.
3009  *
3010  * Note, the order the various feature calls is important.  It must start with
3011  * the "most" features enabled at the same time, then trickle down to the
3012  * least amount of features turned on at once.
3013  **/
3014 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3015 {
3016         /* start with default case */
3017         adapter->rx_ring[0].reg_idx = 0;
3018         adapter->tx_ring[0].reg_idx = 0;
3019
3020 #ifdef CONFIG_IXGBE_DCB
3021         if (ixgbe_cache_ring_dcb(adapter))
3022                 return;
3023
3024 #endif
3025         if (ixgbe_cache_ring_rss(adapter))
3026                 return;
3027 }
3028
3029 /**
3030  * ixgbe_alloc_queues - Allocate memory for all rings
3031  * @adapter: board private structure to initialize
3032  *
3033  * We allocate one ring per queue at run-time since we don't know the
3034  * number of queues at compile-time.  The polling_netdev array is
3035  * intended for Multiqueue, but should work fine with a single queue.
3036  **/
3037 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3038 {
3039         int i;
3040
3041         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3042                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3043         if (!adapter->tx_ring)
3044                 goto err_tx_ring_allocation;
3045
3046         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3047                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3048         if (!adapter->rx_ring)
3049                 goto err_rx_ring_allocation;
3050
3051         for (i = 0; i < adapter->num_tx_queues; i++) {
3052                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3053                 adapter->tx_ring[i].queue_index = i;
3054         }
3055
3056         for (i = 0; i < adapter->num_rx_queues; i++) {
3057                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3058                 adapter->rx_ring[i].queue_index = i;
3059         }
3060
3061         ixgbe_cache_ring_register(adapter);
3062
3063         return 0;
3064
3065 err_rx_ring_allocation:
3066         kfree(adapter->tx_ring);
3067 err_tx_ring_allocation:
3068         return -ENOMEM;
3069 }
3070
3071 /**
3072  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3073  * @adapter: board private structure to initialize
3074  *
3075  * Attempt to configure the interrupts using the best available
3076  * capabilities of the hardware and the kernel.
3077  **/
3078 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3079 {
3080         struct ixgbe_hw *hw = &adapter->hw;
3081         int err = 0;
3082         int vector, v_budget;
3083
3084         /*
3085          * It's easy to be greedy for MSI-X vectors, but it really
3086          * doesn't do us much good if we have a lot more vectors
3087          * than CPU's.  So let's be conservative and only ask for
3088          * (roughly) twice the number of vectors as there are CPU's.
3089          */
3090         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3091                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3092
3093         /*
3094          * At the same time, hardware can only support a maximum of
3095          * hw.mac->max_msix_vectors vectors.  With features
3096          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3097          * descriptor queues supported by our device.  Thus, we cap it off in
3098          * those rare cases where the cpu count also exceeds our vector limit.
3099          */
3100         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3101
3102         /* A failure in MSI-X entry allocation isn't fatal, but it does
3103          * mean we disable MSI-X capabilities of the adapter. */
3104         adapter->msix_entries = kcalloc(v_budget,
3105                                         sizeof(struct msix_entry), GFP_KERNEL);
3106         if (!adapter->msix_entries) {
3107                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3108                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3109                 ixgbe_set_num_queues(adapter);
3110                 kfree(adapter->tx_ring);
3111                 kfree(adapter->rx_ring);
3112                 err = ixgbe_alloc_queues(adapter);
3113                 if (err) {
3114                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
3115                                 "for queues\n");
3116                         goto out;
3117                 }
3118
3119                 goto try_msi;
3120         }
3121
3122         for (vector = 0; vector < v_budget; vector++)
3123                 adapter->msix_entries[vector].entry = vector;
3124
3125         ixgbe_acquire_msix_vectors(adapter, v_budget);
3126
3127         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3128                 goto out;
3129
3130 try_msi:
3131         err = pci_enable_msi(adapter->pdev);
3132         if (!err) {
3133                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3134         } else {
3135                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3136                         "falling back to legacy.  Error: %d\n", err);
3137                 /* reset err */
3138                 err = 0;
3139         }
3140
3141 out:
3142         return err;
3143 }
3144
3145 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3146 {
3147         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3148                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3149                 pci_disable_msix(adapter->pdev);
3150                 kfree(adapter->msix_entries);
3151                 adapter->msix_entries = NULL;
3152         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3153                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3154                 pci_disable_msi(adapter->pdev);
3155         }
3156         return;
3157 }
3158
3159 /**
3160  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3161  * @adapter: board private structure to initialize
3162  *
3163  * We determine which interrupt scheme to use based on...
3164  * - Kernel support (MSI, MSI-X)
3165  *   - which can be user-defined (via MODULE_PARAM)
3166  * - Hardware queue count (num_*_queues)
3167  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3168  **/
3169 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3170 {
3171         int err;
3172
3173         /* Number of supported queues */
3174         ixgbe_set_num_queues(adapter);
3175
3176         err = ixgbe_alloc_queues(adapter);
3177         if (err) {
3178                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3179                 goto err_alloc_queues;
3180         }
3181
3182         err = ixgbe_set_interrupt_capability(adapter);
3183         if (err) {
3184                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3185                 goto err_set_interrupt;
3186         }
3187
3188         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3189                 "Tx Queue count = %u\n",
3190                 (adapter->num_rx_queues > 1) ? "Enabled" :
3191                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3192
3193         set_bit(__IXGBE_DOWN, &adapter->state);
3194
3195         return 0;
3196
3197 err_set_interrupt:
3198         kfree(adapter->tx_ring);
3199         kfree(adapter->rx_ring);
3200 err_alloc_queues:
3201         return err;
3202 }
3203
3204 /**
3205  * ixgbe_sfp_timer - worker thread to find a missing module
3206  * @data: pointer to our adapter struct
3207  **/
3208 static void ixgbe_sfp_timer(unsigned long data)
3209 {
3210         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3211
3212         /*
3213          * Do the sfp_timer outside of interrupt context due to the
3214          * delays that sfp+ detection requires
3215          */
3216         schedule_work(&adapter->sfp_task);
3217 }
3218
3219 /**
3220  * ixgbe_sfp_task - worker thread to find a missing module
3221  * @work: pointer to work_struct containing our data
3222  **/
3223 static void ixgbe_sfp_task(struct work_struct *work)
3224 {
3225         struct ixgbe_adapter *adapter = container_of(work,
3226                                                      struct ixgbe_adapter,
3227                                                      sfp_task);
3228         struct ixgbe_hw *hw = &adapter->hw;
3229
3230         if ((hw->phy.type == ixgbe_phy_nl) &&
3231             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3232                 s32 ret = hw->phy.ops.identify_sfp(hw);
3233                 if (ret)
3234                         goto reschedule;
3235                 ret = hw->phy.ops.reset(hw);
3236                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3237                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3238                                 "unsupported SFP+ module type was detected.\n"
3239                                 "Reload the driver after installing a "
3240                                 "supported module.\n");
3241                         unregister_netdev(adapter->netdev);
3242                 } else {
3243                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3244                                 hw->phy.sfp_type);
3245                 }
3246                 /* don't need this routine any more */
3247                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3248         }
3249         return;
3250 reschedule:
3251         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3252                 mod_timer(&adapter->sfp_timer,
3253                           round_jiffies(jiffies + (2 * HZ)));
3254 }
3255
3256 /**
3257  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3258  * @adapter: board private structure to initialize
3259  *
3260  * ixgbe_sw_init initializes the Adapter private data structure.
3261  * Fields are initialized based on PCI device information and
3262  * OS network device settings (MTU size).
3263  **/
3264 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3265 {
3266         struct ixgbe_hw *hw = &adapter->hw;
3267         struct pci_dev *pdev = adapter->pdev;
3268         unsigned int rss;
3269 #ifdef CONFIG_IXGBE_DCB
3270         int j;
3271         struct tc_configuration *tc;
3272 #endif
3273
3274         /* PCI config space info */
3275
3276         hw->vendor_id = pdev->vendor;
3277         hw->device_id = pdev->device;
3278         hw->revision_id = pdev->revision;
3279         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3280         hw->subsystem_device_id = pdev->subsystem_device;
3281
3282         /* Set capability flags */
3283         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3284         adapter->ring_feature[RING_F_RSS].indices = rss;
3285         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3286         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3287         if (hw->mac.type == ixgbe_mac_82598EB)
3288                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3289         else if (hw->mac.type == ixgbe_mac_82599EB) {
3290                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3291                 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3292                 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3293         }
3294
3295 #ifdef CONFIG_IXGBE_DCB
3296         /* Configure DCB traffic classes */
3297         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3298                 tc = &adapter->dcb_cfg.tc_config[j];
3299                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3300                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3301                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3302                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3303                 tc->dcb_pfc = pfc_disabled;
3304         }
3305         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3306         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3307         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3308         adapter->dcb_cfg.round_robin_enable = false;
3309         adapter->dcb_set_bitmap = 0x00;
3310         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3311                            adapter->ring_feature[RING_F_DCB].indices);
3312
3313 #endif
3314
3315         /* default flow control settings */
3316         hw->fc.requested_mode = ixgbe_fc_full;
3317         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3318         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3319         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3320         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3321         hw->fc.send_xon = true;
3322         hw->fc.disable_fc_autoneg = false;
3323
3324         /* enable itr by default in dynamic mode */
3325         adapter->itr_setting = 1;
3326         adapter->eitr_param = 20000;
3327
3328         /* set defaults for eitr in MegaBytes */
3329         adapter->eitr_low = 10;
3330         adapter->eitr_high = 20;
3331
3332         /* set default ring sizes */
3333         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3334         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3335
3336         /* initialize eeprom parameters */
3337         if (ixgbe_init_eeprom_params_generic(hw)) {
3338                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3339                 return -EIO;
3340         }
3341
3342         /* enable rx csum by default */
3343         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3344
3345         set_bit(__IXGBE_DOWN, &adapter->state);
3346
3347         return 0;
3348 }
3349
3350 /**
3351  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3352  * @adapter: board private structure
3353  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3354  *
3355  * Return 0 on success, negative on failure
3356  **/
3357 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3358                              struct ixgbe_ring *tx_ring)
3359 {
3360         struct pci_dev *pdev = adapter->pdev;
3361         int size;
3362
3363         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3364         tx_ring->tx_buffer_info = vmalloc(size);
3365         if (!tx_ring->tx_buffer_info)
3366                 goto err;
3367         memset(tx_ring->tx_buffer_info, 0, size);
3368
3369         /* round up to nearest 4K */
3370         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3371         tx_ring->size = ALIGN(tx_ring->size, 4096);
3372
3373         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3374                                              &tx_ring->dma);
3375         if (!tx_ring->desc)
3376                 goto err;
3377
3378         tx_ring->next_to_use = 0;
3379         tx_ring->next_to_clean = 0;
3380         tx_ring->work_limit = tx_ring->count;
3381         return 0;
3382
3383 err:
3384         vfree(tx_ring->tx_buffer_info);
3385         tx_ring->tx_buffer_info = NULL;
3386         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3387                             "descriptor ring\n");
3388         return -ENOMEM;
3389 }
3390
3391 /**
3392  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3393  * @adapter: board private structure
3394  *
3395  * If this function returns with an error, then it's possible one or
3396  * more of the rings is populated (while the rest are not).  It is the
3397  * callers duty to clean those orphaned rings.
3398  *
3399  * Return 0 on success, negative on failure
3400  **/
3401 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3402 {
3403         int i, err = 0;
3404
3405         for (i = 0; i < adapter->num_tx_queues; i++) {
3406                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3407                 if (!err)
3408                         continue;
3409                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3410                 break;
3411         }
3412
3413         return err;
3414 }
3415
3416 /**
3417  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3418  * @adapter: board private structure
3419  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3420  *
3421  * Returns 0 on success, negative on failure
3422  **/
3423 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3424                              struct ixgbe_ring *rx_ring)
3425 {
3426         struct pci_dev *pdev = adapter->pdev;
3427         int size;
3428
3429         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3430         rx_ring->rx_buffer_info = vmalloc(size);
3431         if (!rx_ring->rx_buffer_info) {
3432                 DPRINTK(PROBE, ERR,
3433                         "vmalloc allocation failed for the rx desc ring\n");
3434                 goto alloc_failed;
3435         }
3436         memset(rx_ring->rx_buffer_info, 0, size);
3437
3438         /* Round up to nearest 4K */
3439         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3440         rx_ring->size = ALIGN(rx_ring->size, 4096);
3441
3442         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3443
3444         if (!rx_ring->desc) {
3445                 DPRINTK(PROBE, ERR,
3446                         "Memory allocation failed for the rx desc ring\n");
3447                 vfree(rx_ring->rx_buffer_info);
3448                 goto alloc_failed;
3449         }
3450
3451         rx_ring->next_to_clean = 0;
3452         rx_ring->next_to_use = 0;
3453
3454         return 0;
3455
3456 alloc_failed:
3457         return -ENOMEM;
3458 }
3459
3460 /**
3461  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3462  * @adapter: board private structure
3463  *
3464  * If this function returns with an error, then it's possible one or
3465  * more of the rings is populated (while the rest are not).  It is the
3466  * callers duty to clean those orphaned rings.
3467  *
3468  * Return 0 on success, negative on failure
3469  **/
3470
3471 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3472 {
3473         int i, err = 0;
3474
3475         for (i = 0; i < adapter->num_rx_queues; i++) {
3476                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3477                 if (!err)
3478                         continue;
3479                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3480                 break;
3481         }
3482
3483         return err;
3484 }
3485
3486 /**
3487  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3488  * @adapter: board private structure
3489  * @tx_ring: Tx descriptor ring for a specific queue
3490  *
3491  * Free all transmit software resources
3492  **/
3493 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3494                              struct ixgbe_ring *tx_ring)
3495 {
3496         struct pci_dev *pdev = adapter->pdev;
3497
3498         ixgbe_clean_tx_ring(adapter, tx_ring);
3499
3500         vfree(tx_ring->tx_buffer_info);
3501         tx_ring->tx_buffer_info = NULL;
3502
3503         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3504
3505         tx_ring->desc = NULL;
3506 }
3507
3508 /**
3509  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3510  * @adapter: board private structure
3511  *
3512  * Free all transmit software resources
3513  **/
3514 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3515 {
3516         int i;
3517
3518         for (i = 0; i < adapter->num_tx_queues; i++)
3519                 if (adapter->tx_ring[i].desc)
3520                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3521 }
3522
3523 /**
3524  * ixgbe_free_rx_resources - Free Rx Resources
3525  * @adapter: board private structure
3526  * @rx_ring: ring to clean the resources from
3527  *
3528  * Free all receive software resources
3529  **/
3530 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3531                              struct ixgbe_ring *rx_ring)
3532 {
3533         struct pci_dev *pdev = adapter->pdev;
3534
3535         ixgbe_clean_rx_ring(adapter, rx_ring);
3536
3537         vfree(rx_ring->rx_buffer_info);
3538         rx_ring->rx_buffer_info = NULL;
3539
3540         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3541
3542         rx_ring->desc = NULL;
3543 }
3544
3545 /**
3546  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3547  * @adapter: board private structure
3548  *
3549  * Free all receive software resources
3550  **/
3551 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3552 {
3553         int i;
3554
3555         for (i = 0; i < adapter->num_rx_queues; i++)
3556                 if (adapter->rx_ring[i].desc)
3557                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3558 }
3559
3560 /**
3561  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3562  * @netdev: network interface device structure
3563  * @new_mtu: new value for maximum frame size
3564  *
3565  * Returns 0 on success, negative on failure
3566  **/
3567 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3568 {
3569         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3570         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3571
3572         /* MTU < 68 is an error and causes problems on some kernels */
3573         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3574                 return -EINVAL;
3575
3576         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3577                 netdev->mtu, new_mtu);
3578         /* must set new MTU before calling down or up */
3579         netdev->mtu = new_mtu;
3580
3581         if (netif_running(netdev))
3582                 ixgbe_reinit_locked(adapter);
3583
3584         return 0;
3585 }
3586
3587 /**
3588  * ixgbe_open - Called when a network interface is made active
3589  * @netdev: network interface device structure
3590  *
3591  * Returns 0 on success, negative value on failure
3592  *
3593  * The open entry point is called when a network interface is made
3594  * active by the system (IFF_UP).  At this point all resources needed
3595  * for transmit and receive operations are allocated, the interrupt
3596  * handler is registered with the OS, the watchdog timer is started,
3597  * and the stack is notified that the interface is ready.
3598  **/
3599 static int ixgbe_open(struct net_device *netdev)
3600 {
3601         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3602         int err;
3603
3604         /* disallow open during test */
3605         if (test_bit(__IXGBE_TESTING, &adapter->state))
3606                 return -EBUSY;
3607
3608         netif_carrier_off(netdev);
3609
3610         /* allocate transmit descriptors */
3611         err = ixgbe_setup_all_tx_resources(adapter);
3612         if (err)
3613                 goto err_setup_tx;
3614
3615         /* allocate receive descriptors */
3616         err = ixgbe_setup_all_rx_resources(adapter);
3617         if (err)
3618                 goto err_setup_rx;
3619
3620         ixgbe_configure(adapter);
3621
3622         ixgbe_napi_add_all(adapter);
3623
3624         err = ixgbe_request_irq(adapter);
3625         if (err)
3626                 goto err_req_irq;
3627
3628         err = ixgbe_up_complete(adapter);
3629         if (err)
3630                 goto err_up;
3631
3632         netif_tx_start_all_queues(netdev);
3633
3634         return 0;
3635
3636 err_up:
3637         ixgbe_release_hw_control(adapter);
3638         ixgbe_free_irq(adapter);
3639 err_req_irq:
3640 err_setup_rx:
3641         ixgbe_free_all_rx_resources(adapter);
3642 err_setup_tx:
3643         ixgbe_free_all_tx_resources(adapter);
3644         ixgbe_reset(adapter);
3645
3646         return err;
3647 }
3648
3649 /**
3650  * ixgbe_close - Disables a network interface
3651  * @netdev: network interface device structure
3652  *
3653  * Returns 0, this is not allowed to fail
3654  *
3655  * The close entry point is called when an interface is de-activated
3656  * by the OS.  The hardware is still under the drivers control, but
3657  * needs to be disabled.  A global MAC reset is issued to stop the
3658  * hardware, and all transmit and receive resources are freed.
3659  **/
3660 static int ixgbe_close(struct net_device *netdev)
3661 {
3662         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3663
3664         ixgbe_down(adapter);
3665         ixgbe_free_irq(adapter);
3666
3667         ixgbe_free_all_tx_resources(adapter);
3668         ixgbe_free_all_rx_resources(adapter);
3669
3670         ixgbe_release_hw_control(adapter);
3671
3672         return 0;
3673 }
3674
3675 /**
3676  * ixgbe_napi_add_all - prep napi structs for use
3677  * @adapter: private struct
3678  *
3679  * helper function to napi_add each possible q_vector->napi
3680  */
3681 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3682 {
3683         int q_idx, q_vectors;
3684         struct net_device *netdev = adapter->netdev;
3685         int (*poll)(struct napi_struct *, int);
3686
3687         /* check if we already have our netdev->napi_list populated */
3688         if (&netdev->napi_list != netdev->napi_list.next)
3689                 return;
3690
3691         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3692                 poll = &ixgbe_clean_rxonly;
3693                 /* Only enable as many vectors as we have rx queues. */
3694                 q_vectors = adapter->num_rx_queues;
3695         } else {
3696                 poll = &ixgbe_poll;
3697                 /* only one q_vector for legacy modes */
3698                 q_vectors = 1;
3699         }
3700
3701         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3702                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3703                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3704         }
3705 }
3706
3707 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3708 {
3709         int q_idx;
3710         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3711
3712         /* legacy and MSI only use one vector */
3713         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3714                 q_vectors = 1;
3715
3716         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3717                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3718                 if (!q_vector->rxr_count)
3719                         continue;
3720                 netif_napi_del(&q_vector->napi);
3721         }
3722 }
3723
3724 #ifdef CONFIG_PM
3725 static int ixgbe_resume(struct pci_dev *pdev)
3726 {
3727         struct net_device *netdev = pci_get_drvdata(pdev);
3728         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3729         u32 err;
3730
3731         pci_set_power_state(pdev, PCI_D0);
3732         pci_restore_state(pdev);
3733         err = pci_enable_device(pdev);
3734         if (err) {
3735                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3736                                 "suspend\n");
3737                 return err;
3738         }
3739         pci_set_master(pdev);
3740
3741         pci_wake_from_d3(pdev, false);
3742
3743         err = ixgbe_init_interrupt_scheme(adapter);
3744         if (err) {
3745                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3746                                 "device\n");
3747                 return err;
3748         }
3749
3750         ixgbe_reset(adapter);
3751
3752         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3753
3754         if (netif_running(netdev)) {
3755                 err = ixgbe_open(adapter->netdev);
3756                 if (err)
3757                         return err;
3758         }
3759
3760         netif_device_attach(netdev);
3761
3762         return 0;
3763 }
3764 #endif /* CONFIG_PM */
3765
3766 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3767 {
3768         struct net_device *netdev = pci_get_drvdata(pdev);
3769         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3770         struct ixgbe_hw *hw = &adapter->hw;
3771         u32 ctrl, fctrl;
3772         u32 wufc = adapter->wol;
3773 #ifdef CONFIG_PM
3774         int retval = 0;
3775 #endif
3776
3777         netif_device_detach(netdev);
3778
3779         if (netif_running(netdev)) {
3780                 ixgbe_down(adapter);
3781                 ixgbe_free_irq(adapter);
3782                 ixgbe_free_all_tx_resources(adapter);
3783                 ixgbe_free_all_rx_resources(adapter);
3784         }
3785         ixgbe_reset_interrupt_capability(adapter);
3786         ixgbe_napi_del_all(adapter);
3787         INIT_LIST_HEAD(&netdev->napi_list);
3788         kfree(adapter->tx_ring);
3789         kfree(adapter->rx_ring);
3790
3791 #ifdef CONFIG_PM
3792         retval = pci_save_state(pdev);
3793         if (retval)
3794                 return retval;
3795
3796 #endif
3797         if (wufc) {
3798                 ixgbe_set_rx_mode(netdev);
3799
3800                 /* turn on all-multi mode if wake on multicast is enabled */
3801                 if (wufc & IXGBE_WUFC_MC) {
3802                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3803                         fctrl |= IXGBE_FCTRL_MPE;
3804                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3805                 }
3806
3807                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3808                 ctrl |= IXGBE_CTRL_GIO_DIS;
3809                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3810
3811                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3812         } else {
3813                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3814                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3815         }
3816
3817         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3818                 pci_wake_from_d3(pdev, true);
3819         else
3820                 pci_wake_from_d3(pdev, false);
3821
3822         *enable_wake = !!wufc;
3823
3824         ixgbe_release_hw_control(adapter);
3825
3826         pci_disable_device(pdev);
3827
3828         return 0;
3829 }
3830
3831 #ifdef CONFIG_PM
3832 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3833 {
3834         int retval;
3835         bool wake;
3836
3837         retval = __ixgbe_shutdown(pdev, &wake);
3838         if (retval)
3839                 return retval;
3840
3841         if (wake) {
3842                 pci_prepare_to_sleep(pdev);
3843         } else {
3844                 pci_wake_from_d3(pdev, false);
3845                 pci_set_power_state(pdev, PCI_D3hot);
3846         }
3847
3848         return 0;
3849 }
3850 #endif /* CONFIG_PM */
3851
3852 static void ixgbe_shutdown(struct pci_dev *pdev)
3853 {
3854         bool wake;
3855
3856         __ixgbe_shutdown(pdev, &wake);
3857
3858         if (system_state == SYSTEM_POWER_OFF) {
3859                 pci_wake_from_d3(pdev, wake);
3860                 pci_set_power_state(pdev, PCI_D3hot);
3861         }
3862 }
3863
3864 /**
3865  * ixgbe_update_stats - Update the board statistics counters.
3866  * @adapter: board private structure
3867  **/
3868 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3869 {
3870         struct ixgbe_hw *hw = &adapter->hw;
3871         u64 total_mpc = 0;
3872         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3873
3874         if (hw->mac.type == ixgbe_mac_82599EB) {
3875                 u64 rsc_count = 0;
3876                 for (i = 0; i < 16; i++)
3877                         adapter->hw_rx_no_dma_resources +=
3878                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3879                 for (i = 0; i < adapter->num_rx_queues; i++)
3880                         rsc_count += adapter->rx_ring[i].rsc_count;
3881                 adapter->rsc_count = rsc_count;
3882         }
3883
3884         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3885         for (i = 0; i < 8; i++) {
3886                 /* for packet buffers not used, the register should read 0 */
3887                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3888                 missed_rx += mpc;
3889                 adapter->stats.mpc[i] += mpc;
3890                 total_mpc += adapter->stats.mpc[i];
3891                 if (hw->mac.type == ixgbe_mac_82598EB)
3892                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3893                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3894                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3895                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3896                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3897                 if (hw->mac.type == ixgbe_mac_82599EB) {
3898                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3899                                                             IXGBE_PXONRXCNT(i));
3900                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3901                                                            IXGBE_PXOFFRXCNT(i));
3902                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3903                 } else {
3904                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3905                                                               IXGBE_PXONRXC(i));
3906                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3907                                                              IXGBE_PXOFFRXC(i));
3908                 }
3909                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3910                                                             IXGBE_PXONTXC(i));
3911                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3912                                                              IXGBE_PXOFFTXC(i));
3913         }
3914         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3915         /* work around hardware counting issue */
3916         adapter->stats.gprc -= missed_rx;
3917
3918         /* 82598 hardware only has a 32 bit counter in the high register */
3919         if (hw->mac.type == ixgbe_mac_82599EB) {
3920                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3921                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3922                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3923                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3924                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3925                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3926                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3927                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3928         } else {
3929                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3930                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3931                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3932                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3933                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3934         }
3935         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3936         adapter->stats.bprc += bprc;
3937         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3938         if (hw->mac.type == ixgbe_mac_82598EB)
3939                 adapter->stats.mprc -= bprc;
3940         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3941         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3942         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3943         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3944         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3945         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3946         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3947         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3948         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3949         adapter->stats.lxontxc += lxon;
3950         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3951         adapter->stats.lxofftxc += lxoff;
3952         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3953         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3954         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3955         /*
3956          * 82598 errata - tx of flow control packets is included in tx counters
3957          */
3958         xon_off_tot = lxon + lxoff;
3959         adapter->stats.gptc -= xon_off_tot;
3960         adapter->stats.mptc -= xon_off_tot;
3961         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3962         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3963         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3964         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3965         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3966         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3967         adapter->stats.ptc64 -= xon_off_tot;
3968         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3969         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3970         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3971         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3972         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3973         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3974
3975         /* Fill out the OS statistics structure */
3976         adapter->net_stats.multicast = adapter->stats.mprc;
3977
3978         /* Rx Errors */
3979         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3980                                        adapter->stats.rlec;
3981         adapter->net_stats.rx_dropped = 0;
3982         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3983         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3984         adapter->net_stats.rx_missed_errors = total_mpc;
3985 }
3986
3987 /**
3988  * ixgbe_watchdog - Timer Call-back
3989  * @data: pointer to adapter cast into an unsigned long
3990  **/
3991 static void ixgbe_watchdog(unsigned long data)
3992 {
3993         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3994         struct ixgbe_hw *hw = &adapter->hw;
3995
3996         /* Do the watchdog outside of interrupt context due to the lovely
3997          * delays that some of the newer hardware requires */
3998         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3999                 u64 eics = 0;
4000                 int i;
4001
4002                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4003                         eics |= (1 << i);
4004
4005                 /* Cause software interrupt to ensure rx rings are cleaned */
4006                 switch (hw->mac.type) {
4007                 case ixgbe_mac_82598EB:
4008                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4009                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4010                         } else {
4011                                 /*
4012                                  * for legacy and MSI interrupts don't set any
4013                                  * bits that are enabled for EIAM, because this
4014                                  * operation would set *both* EIMS and EICS for
4015                                  * any bit in EIAM
4016                                  */
4017                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4018                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4019                         }
4020                         break;
4021                 case ixgbe_mac_82599EB:
4022                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4023                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4024                                                 (u32)(eics & 0xFFFFFFFF));
4025                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4026                                                 (u32)(eics >> 32));
4027                         } else {
4028                                 /*
4029                                  * for legacy and MSI interrupts don't set any
4030                                  * bits that are enabled for EIAM, because this
4031                                  * operation would set *both* EIMS and EICS for
4032                                  * any bit in EIAM
4033                                  */
4034                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4035                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4036                         }
4037                         break;
4038                 default:
4039                         break;
4040                 }
4041                 /* Reset the timer */
4042                 mod_timer(&adapter->watchdog_timer,
4043                           round_jiffies(jiffies + 2 * HZ));
4044         }
4045
4046         schedule_work(&adapter->watchdog_task);
4047 }
4048
4049 /**
4050  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4051  * @work: pointer to work_struct containing our data
4052  **/
4053 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4054 {
4055         struct ixgbe_adapter *adapter = container_of(work,
4056                                                      struct ixgbe_adapter,
4057                                                      multispeed_fiber_task);
4058         struct ixgbe_hw *hw = &adapter->hw;
4059         u32 autoneg;
4060
4061         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4062         if (hw->mac.ops.get_link_capabilities)
4063                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4064                                                   &hw->mac.autoneg);
4065         if (hw->mac.ops.setup_link_speed)
4066                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4067         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4068         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4069 }
4070
4071 /**
4072  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4073  * @work: pointer to work_struct containing our data
4074  **/
4075 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4076 {
4077         struct ixgbe_adapter *adapter = container_of(work,
4078                                                      struct ixgbe_adapter,
4079                                                      sfp_config_module_task);
4080         struct ixgbe_hw *hw = &adapter->hw;
4081         u32 err;
4082
4083         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4084         err = hw->phy.ops.identify_sfp(hw);
4085         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4086                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4087                 ixgbe_down(adapter);
4088                 return;
4089         }
4090         hw->mac.ops.setup_sfp(hw);
4091
4092         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4093                 /* This will also work for DA Twinax connections */
4094                 schedule_work(&adapter->multispeed_fiber_task);
4095         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4096 }
4097
4098 /**
4099  * ixgbe_watchdog_task - worker thread to bring link up
4100  * @work: pointer to work_struct containing our data
4101  **/
4102 static void ixgbe_watchdog_task(struct work_struct *work)
4103 {
4104         struct ixgbe_adapter *adapter = container_of(work,
4105                                                      struct ixgbe_adapter,
4106                                                      watchdog_task);
4107         struct net_device *netdev = adapter->netdev;
4108         struct ixgbe_hw *hw = &adapter->hw;
4109         u32 link_speed = adapter->link_speed;
4110         bool link_up = adapter->link_up;
4111         int i;
4112         struct ixgbe_ring *tx_ring;
4113         int some_tx_pending = 0;
4114
4115         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4116
4117         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4118                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4119                 if (link_up ||
4120                     time_after(jiffies, (adapter->link_check_timeout +
4121                                          IXGBE_TRY_LINK_TIMEOUT))) {
4122                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4123                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4124                 }
4125                 adapter->link_up = link_up;
4126                 adapter->link_speed = link_speed;
4127         }
4128
4129         if (link_up) {
4130                 if (!netif_carrier_ok(netdev)) {
4131                         bool flow_rx, flow_tx;
4132
4133                         if (hw->mac.type == ixgbe_mac_82599EB) {
4134                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4135                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4136                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4137                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4138                         } else {
4139                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4140                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4141                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4142                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4143                         }
4144
4145                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4146                                "Flow Control: %s\n",
4147                                netdev->name,
4148                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4149                                 "10 Gbps" :
4150                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4151                                  "1 Gbps" : "unknown speed")),
4152                                ((flow_rx && flow_tx) ? "RX/TX" :
4153                                 (flow_rx ? "RX" :
4154                                 (flow_tx ? "TX" : "None"))));
4155
4156                         netif_carrier_on(netdev);
4157                 } else {
4158                         /* Force detection of hung controller */
4159                         adapter->detect_tx_hung = true;
4160                 }
4161         } else {
4162                 adapter->link_up = false;
4163                 adapter->link_speed = 0;
4164                 if (netif_carrier_ok(netdev)) {
4165                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4166                                netdev->name);
4167                         netif_carrier_off(netdev);
4168                 }
4169         }
4170
4171         if (!netif_carrier_ok(netdev)) {
4172                 for (i = 0; i < adapter->num_tx_queues; i++) {
4173                         tx_ring = &adapter->tx_ring[i];
4174                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4175                                 some_tx_pending = 1;
4176                                 break;
4177                         }
4178                 }
4179
4180                 if (some_tx_pending) {
4181                         /* We've lost link, so the controller stops DMA,
4182                          * but we've got queued Tx work that's never going
4183                          * to get done, so reset controller to flush Tx.
4184                          * (Do the reset outside of interrupt context).
4185                          */
4186                          schedule_work(&adapter->reset_task);
4187                 }
4188         }
4189
4190         ixgbe_update_stats(adapter);
4191         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4192 }
4193
4194 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4195                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4196                      u32 tx_flags, u8 *hdr_len)
4197 {
4198         struct ixgbe_adv_tx_context_desc *context_desc;
4199         unsigned int i;
4200         int err;
4201         struct ixgbe_tx_buffer *tx_buffer_info;
4202         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4203         u32 mss_l4len_idx, l4len;
4204
4205         if (skb_is_gso(skb)) {
4206                 if (skb_header_cloned(skb)) {
4207                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4208                         if (err)
4209                                 return err;
4210                 }
4211                 l4len = tcp_hdrlen(skb);
4212                 *hdr_len += l4len;
4213
4214                 if (skb->protocol == htons(ETH_P_IP)) {
4215                         struct iphdr *iph = ip_hdr(skb);
4216                         iph->tot_len = 0;
4217                         iph->check = 0;
4218                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4219                                                                  iph->daddr, 0,
4220                                                                  IPPROTO_TCP,
4221                                                                  0);
4222                         adapter->hw_tso_ctxt++;
4223                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4224                         ipv6_hdr(skb)->payload_len = 0;
4225                         tcp_hdr(skb)->check =
4226                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4227                                              &ipv6_hdr(skb)->daddr,
4228                                              0, IPPROTO_TCP, 0);
4229                         adapter->hw_tso6_ctxt++;
4230                 }
4231
4232                 i = tx_ring->next_to_use;
4233
4234                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4235                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4236
4237                 /* VLAN MACLEN IPLEN */
4238                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4239                         vlan_macip_lens |=
4240                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4241                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4242                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4243                 *hdr_len += skb_network_offset(skb);
4244                 vlan_macip_lens |=
4245                     (skb_transport_header(skb) - skb_network_header(skb));
4246                 *hdr_len +=
4247                     (skb_transport_header(skb) - skb_network_header(skb));
4248                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4249                 context_desc->seqnum_seed = 0;
4250
4251                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4252                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4253                                    IXGBE_ADVTXD_DTYP_CTXT);
4254
4255                 if (skb->protocol == htons(ETH_P_IP))
4256                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4257                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4258                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4259
4260                 /* MSS L4LEN IDX */
4261                 mss_l4len_idx =
4262                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4263                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4264                 /* use index 1 for TSO */
4265                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4266                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4267
4268                 tx_buffer_info->time_stamp = jiffies;
4269                 tx_buffer_info->next_to_watch = i;
4270
4271                 i++;
4272                 if (i == tx_ring->count)
4273                         i = 0;
4274                 tx_ring->next_to_use = i;
4275
4276                 return true;
4277         }
4278         return false;
4279 }
4280
4281 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4282                           struct ixgbe_ring *tx_ring,
4283                           struct sk_buff *skb, u32 tx_flags)
4284 {
4285         struct ixgbe_adv_tx_context_desc *context_desc;
4286         unsigned int i;
4287         struct ixgbe_tx_buffer *tx_buffer_info;
4288         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4289
4290         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4291             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4292                 i = tx_ring->next_to_use;
4293                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4294                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4295
4296                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4297                         vlan_macip_lens |=
4298                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4299                 vlan_macip_lens |= (skb_network_offset(skb) <<
4300                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4301                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4302                         vlan_macip_lens |= (skb_transport_header(skb) -
4303                                             skb_network_header(skb));
4304
4305                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4306                 context_desc->seqnum_seed = 0;
4307
4308                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4309                                     IXGBE_ADVTXD_DTYP_CTXT);
4310
4311                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4312                         switch (skb->protocol) {
4313                         case cpu_to_be16(ETH_P_IP):
4314                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4315                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4316                                         type_tucmd_mlhl |=
4317                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4318                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4319                                         type_tucmd_mlhl |=
4320                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4321                                 break;
4322                         case cpu_to_be16(ETH_P_IPV6):
4323                                 /* XXX what about other V6 headers?? */
4324                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4325                                         type_tucmd_mlhl |=
4326                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4327                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4328                                         type_tucmd_mlhl |=
4329                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4330                                 break;
4331                         default:
4332                                 if (unlikely(net_ratelimit())) {
4333                                         DPRINTK(PROBE, WARNING,
4334                                          "partial checksum but proto=%x!\n",
4335                                          skb->protocol);
4336                                 }
4337                                 break;
4338                         }
4339                 }
4340
4341                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4342                 /* use index zero for tx checksum offload */
4343                 context_desc->mss_l4len_idx = 0;
4344
4345                 tx_buffer_info->time_stamp = jiffies;
4346                 tx_buffer_info->next_to_watch = i;
4347
4348                 adapter->hw_csum_tx_good++;
4349                 i++;
4350                 if (i == tx_ring->count)
4351                         i = 0;
4352                 tx_ring->next_to_use = i;
4353
4354                 return true;
4355         }
4356
4357         return false;
4358 }
4359
4360 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4361                         struct ixgbe_ring *tx_ring,
4362                         struct sk_buff *skb, unsigned int first)
4363 {
4364         struct ixgbe_tx_buffer *tx_buffer_info;
4365         unsigned int len = skb_headlen(skb);
4366         unsigned int offset = 0, size, count = 0, i;
4367         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4368         unsigned int f;
4369         dma_addr_t *map;
4370
4371         i = tx_ring->next_to_use;
4372
4373         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4374                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4375                 return 0;
4376         }
4377
4378         map = skb_shinfo(skb)->dma_maps;
4379
4380         while (len) {
4381                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4382                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4383
4384                 tx_buffer_info->length = size;
4385                 tx_buffer_info->dma = map[0] + offset;
4386                 tx_buffer_info->time_stamp = jiffies;
4387                 tx_buffer_info->next_to_watch = i;
4388
4389                 len -= size;
4390                 offset += size;
4391                 count++;
4392
4393                 if (len) {
4394                         i++;
4395                         if (i == tx_ring->count)
4396                                 i = 0;
4397                 }
4398         }
4399
4400         for (f = 0; f < nr_frags; f++) {
4401                 struct skb_frag_struct *frag;
4402
4403                 frag = &skb_shinfo(skb)->frags[f];
4404                 len = frag->size;
4405                 offset = 0;
4406
4407                 while (len) {
4408                         i++;
4409                         if (i == tx_ring->count)
4410                                 i = 0;
4411
4412                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4413                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4414
4415                         tx_buffer_info->length = size;
4416                         tx_buffer_info->dma = map[f + 1] + offset;
4417                         tx_buffer_info->time_stamp = jiffies;
4418                         tx_buffer_info->next_to_watch = i;
4419
4420                         len -= size;
4421                         offset += size;
4422                         count++;
4423                 }
4424         }
4425
4426         tx_ring->tx_buffer_info[i].skb = skb;
4427         tx_ring->tx_buffer_info[first].next_to_watch = i;
4428
4429         return count;
4430 }
4431
4432 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4433                            struct ixgbe_ring *tx_ring,
4434                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4435 {
4436         union ixgbe_adv_tx_desc *tx_desc = NULL;
4437         struct ixgbe_tx_buffer *tx_buffer_info;
4438         u32 olinfo_status = 0, cmd_type_len = 0;
4439         unsigned int i;
4440         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4441
4442         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4443
4444         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4445
4446         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4447                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4448
4449         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4450                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4451
4452                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4453                                  IXGBE_ADVTXD_POPTS_SHIFT;
4454
4455                 /* use index 1 context for tso */
4456                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4457                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4458                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4459                                          IXGBE_ADVTXD_POPTS_SHIFT;
4460
4461         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4462                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4463                                  IXGBE_ADVTXD_POPTS_SHIFT;
4464
4465         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4466
4467         i = tx_ring->next_to_use;
4468         while (count--) {
4469                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4470                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4471                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4472                 tx_desc->read.cmd_type_len =
4473                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4474                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4475                 i++;
4476                 if (i == tx_ring->count)
4477                         i = 0;
4478         }
4479
4480         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4481
4482         /*
4483          * Force memory writes to complete before letting h/w
4484          * know there are new descriptors to fetch.  (Only
4485          * applicable for weak-ordered memory model archs,
4486          * such as IA-64).
4487          */
4488         wmb();
4489
4490         tx_ring->next_to_use = i;
4491         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4492 }
4493
4494 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4495                                  struct ixgbe_ring *tx_ring, int size)
4496 {
4497         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4498
4499         netif_stop_subqueue(netdev, tx_ring->queue_index);
4500         /* Herbert's original patch had:
4501          *  smp_mb__after_netif_stop_queue();
4502          * but since that doesn't exist yet, just open code it. */
4503         smp_mb();
4504
4505         /* We need to check again in a case another CPU has just
4506          * made room available. */
4507         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4508                 return -EBUSY;
4509
4510         /* A reprieve! - use start_queue because it doesn't call schedule */
4511         netif_start_subqueue(netdev, tx_ring->queue_index);
4512         ++adapter->restart_queue;
4513         return 0;
4514 }
4515
4516 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4517                               struct ixgbe_ring *tx_ring, int size)
4518 {
4519         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4520                 return 0;
4521         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4522 }
4523
4524 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4525 {
4526         struct ixgbe_adapter *adapter = netdev_priv(dev);
4527
4528         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4529                 return 0;  /* All traffic should default to class 0 */
4530
4531         return skb_tx_hash(dev, skb);
4532 }
4533
4534 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4535 {
4536         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4537         struct ixgbe_ring *tx_ring;
4538         unsigned int first;
4539         unsigned int tx_flags = 0;
4540         u8 hdr_len = 0;
4541         int r_idx = 0, tso;
4542         int count = 0;
4543         unsigned int f;
4544
4545         r_idx = skb->queue_mapping;
4546         tx_ring = &adapter->tx_ring[r_idx];
4547
4548         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4549                 tx_flags |= vlan_tx_tag_get(skb);
4550                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4551                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4552                         tx_flags |= (skb->queue_mapping << 13);
4553                 }
4554                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4555                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4556         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4557                 tx_flags |= (skb->queue_mapping << 13);
4558                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4559                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4560         }
4561         /* three things can cause us to need a context descriptor */
4562         if (skb_is_gso(skb) ||
4563             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4564             (tx_flags & IXGBE_TX_FLAGS_VLAN))
4565                 count++;
4566
4567         count += TXD_USE_COUNT(skb_headlen(skb));
4568         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4569                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4570
4571         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4572                 adapter->tx_busy++;
4573                 return NETDEV_TX_BUSY;
4574         }
4575
4576         if (skb->protocol == htons(ETH_P_IP))
4577                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4578         first = tx_ring->next_to_use;
4579         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4580         if (tso < 0) {
4581                 dev_kfree_skb_any(skb);
4582                 return NETDEV_TX_OK;
4583         }
4584
4585         if (tso)
4586                 tx_flags |= IXGBE_TX_FLAGS_TSO;
4587         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4588                  (skb->ip_summed == CHECKSUM_PARTIAL))
4589                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4590
4591         count = ixgbe_tx_map(adapter, tx_ring, skb, first);
4592
4593         if (count) {
4594                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4595                                hdr_len);
4596                 netdev->trans_start = jiffies;
4597                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4598
4599         } else {
4600                 dev_kfree_skb_any(skb);
4601                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4602                 tx_ring->next_to_use = first;
4603         }
4604
4605         return NETDEV_TX_OK;
4606 }
4607
4608 /**
4609  * ixgbe_get_stats - Get System Network Statistics
4610  * @netdev: network interface device structure
4611  *
4612  * Returns the address of the device statistics structure.
4613  * The statistics are actually updated from the timer callback.
4614  **/
4615 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4616 {
4617         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4618
4619         /* only return the current stats */
4620         return &adapter->net_stats;
4621 }
4622
4623 /**
4624  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4625  * @netdev: network interface device structure
4626  * @p: pointer to an address structure
4627  *
4628  * Returns 0 on success, negative on failure
4629  **/
4630 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4631 {
4632         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4633         struct ixgbe_hw *hw = &adapter->hw;
4634         struct sockaddr *addr = p;
4635
4636         if (!is_valid_ether_addr(addr->sa_data))
4637                 return -EADDRNOTAVAIL;
4638
4639         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4640         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4641
4642         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4643
4644         return 0;
4645 }
4646
4647 static int
4648 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4649 {
4650         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4651         struct ixgbe_hw *hw = &adapter->hw;
4652         u16 value;
4653         int rc;
4654
4655         if (prtad != hw->phy.mdio.prtad)
4656                 return -EINVAL;
4657         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4658         if (!rc)
4659                 rc = value;
4660         return rc;
4661 }
4662
4663 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4664                             u16 addr, u16 value)
4665 {
4666         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4667         struct ixgbe_hw *hw = &adapter->hw;
4668
4669         if (prtad != hw->phy.mdio.prtad)
4670                 return -EINVAL;
4671         return hw->phy.ops.write_reg(hw, addr, devad, value);
4672 }
4673
4674 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4675 {
4676         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4677
4678         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4679 }
4680
4681 #ifdef CONFIG_NET_POLL_CONTROLLER
4682 /*
4683  * Polling 'interrupt' - used by things like netconsole to send skbs
4684  * without having to re-enable interrupts. It's not called while
4685  * the interrupt routine is executing.
4686  */
4687 static void ixgbe_netpoll(struct net_device *netdev)
4688 {
4689         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4690
4691         disable_irq(adapter->pdev->irq);
4692         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4693         ixgbe_intr(adapter->pdev->irq, netdev);
4694         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4695         enable_irq(adapter->pdev->irq);
4696 }
4697 #endif
4698
4699 static const struct net_device_ops ixgbe_netdev_ops = {
4700         .ndo_open               = ixgbe_open,
4701         .ndo_stop               = ixgbe_close,
4702         .ndo_start_xmit         = ixgbe_xmit_frame,
4703         .ndo_select_queue       = ixgbe_select_queue,
4704         .ndo_get_stats          = ixgbe_get_stats,
4705         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
4706         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4707         .ndo_validate_addr      = eth_validate_addr,
4708         .ndo_set_mac_address    = ixgbe_set_mac,
4709         .ndo_change_mtu         = ixgbe_change_mtu,
4710         .ndo_tx_timeout         = ixgbe_tx_timeout,
4711         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4712         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4713         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4714         .ndo_do_ioctl           = ixgbe_ioctl,
4715 #ifdef CONFIG_NET_POLL_CONTROLLER
4716         .ndo_poll_controller    = ixgbe_netpoll,
4717 #endif
4718 };
4719
4720 /**
4721  * ixgbe_probe - Device Initialization Routine
4722  * @pdev: PCI device information struct
4723  * @ent: entry in ixgbe_pci_tbl
4724  *
4725  * Returns 0 on success, negative on failure
4726  *
4727  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4728  * The OS initialization, configuring of the adapter private structure,
4729  * and a hardware reset occur.
4730  **/
4731 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4732                                  const struct pci_device_id *ent)
4733 {
4734         struct net_device *netdev;
4735         struct ixgbe_adapter *adapter = NULL;
4736         struct ixgbe_hw *hw;
4737         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4738         static int cards_found;
4739         int i, err, pci_using_dac;
4740         u32 part_num, eec;
4741
4742         err = pci_enable_device(pdev);
4743         if (err)
4744                 return err;
4745
4746         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4747             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
4748                 pci_using_dac = 1;
4749         } else {
4750                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4751                 if (err) {
4752                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4753                         if (err) {
4754                                 dev_err(&pdev->dev, "No usable DMA "
4755                                         "configuration, aborting\n");
4756                                 goto err_dma;
4757                         }
4758                 }
4759                 pci_using_dac = 0;
4760         }
4761
4762         err = pci_request_regions(pdev, ixgbe_driver_name);
4763         if (err) {
4764                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4765                 goto err_pci_reg;
4766         }
4767
4768         err = pci_enable_pcie_error_reporting(pdev);
4769         if (err) {
4770                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4771                                     "0x%x\n", err);
4772                 /* non-fatal, continue */
4773         }
4774
4775         pci_set_master(pdev);
4776         pci_save_state(pdev);
4777
4778         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4779         if (!netdev) {
4780                 err = -ENOMEM;
4781                 goto err_alloc_etherdev;
4782         }
4783
4784         SET_NETDEV_DEV(netdev, &pdev->dev);
4785
4786         pci_set_drvdata(pdev, netdev);
4787         adapter = netdev_priv(netdev);
4788
4789         adapter->netdev = netdev;
4790         adapter->pdev = pdev;
4791         hw = &adapter->hw;
4792         hw->back = adapter;
4793         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4794
4795         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4796                               pci_resource_len(pdev, 0));
4797         if (!hw->hw_addr) {
4798                 err = -EIO;
4799                 goto err_ioremap;
4800         }
4801
4802         for (i = 1; i <= 5; i++) {
4803                 if (pci_resource_len(pdev, i) == 0)
4804                         continue;
4805         }
4806
4807         netdev->netdev_ops = &ixgbe_netdev_ops;
4808         ixgbe_set_ethtool_ops(netdev);
4809         netdev->watchdog_timeo = 5 * HZ;
4810         strcpy(netdev->name, pci_name(pdev));
4811
4812         adapter->bd_number = cards_found;
4813
4814         /* Setup hw api */
4815         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4816         hw->mac.type  = ii->mac;
4817
4818         /* EEPROM */
4819         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4820         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4821         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4822         if (!(eec & (1 << 8)))
4823                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4824
4825         /* PHY */
4826         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4827         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4828         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
4829         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
4830         hw->phy.mdio.mmds = 0;
4831         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
4832         hw->phy.mdio.dev = netdev;
4833         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
4834         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
4835
4836         /* set up this timer and work struct before calling get_invariants
4837          * which might start the timer
4838          */
4839         init_timer(&adapter->sfp_timer);
4840         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4841         adapter->sfp_timer.data = (unsigned long) adapter;
4842
4843         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4844
4845         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4846         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4847
4848         /* a new SFP+ module arrival, called from GPI SDP2 context */
4849         INIT_WORK(&adapter->sfp_config_module_task,
4850                   ixgbe_sfp_config_module_task);
4851
4852         err = ii->get_invariants(hw);
4853         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4854                 /* start a kernel thread to watch for a module to arrive */
4855                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4856                 mod_timer(&adapter->sfp_timer,
4857                           round_jiffies(jiffies + (2 * HZ)));
4858                 err = 0;
4859         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4860                 DPRINTK(PROBE, ERR, "failed to load because an "
4861                         "unsupported SFP+ module type was detected.\n");
4862                 goto err_hw_init;
4863         } else if (err) {
4864                 goto err_hw_init;
4865         }
4866
4867         /* setup the private structure */
4868         err = ixgbe_sw_init(adapter);
4869         if (err)
4870                 goto err_sw_init;
4871
4872         /* reset_hw fills in the perm_addr as well */
4873         err = hw->mac.ops.reset_hw(hw);
4874         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4875                 dev_err(&adapter->pdev->dev, "failed to load because an "
4876                         "unsupported SFP+ module type was detected.\n");
4877                 goto err_sw_init;
4878         } else if (err) {
4879                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4880                 goto err_sw_init;
4881         }
4882
4883         netdev->features = NETIF_F_SG |
4884                            NETIF_F_IP_CSUM |
4885                            NETIF_F_HW_VLAN_TX |
4886                            NETIF_F_HW_VLAN_RX |
4887                            NETIF_F_HW_VLAN_FILTER;
4888
4889         netdev->features |= NETIF_F_IPV6_CSUM;
4890         netdev->features |= NETIF_F_TSO;
4891         netdev->features |= NETIF_F_TSO6;
4892         netdev->features |= NETIF_F_GRO;
4893
4894         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4895                 netdev->features |= NETIF_F_SCTP_CSUM;
4896
4897         netdev->vlan_features |= NETIF_F_TSO;
4898         netdev->vlan_features |= NETIF_F_TSO6;
4899         netdev->vlan_features |= NETIF_F_IP_CSUM;
4900         netdev->vlan_features |= NETIF_F_SG;
4901
4902         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4903                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4904
4905 #ifdef CONFIG_IXGBE_DCB
4906         netdev->dcbnl_ops = &dcbnl_ops;
4907 #endif
4908
4909         if (pci_using_dac)
4910                 netdev->features |= NETIF_F_HIGHDMA;
4911
4912         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4913                 netdev->features |= NETIF_F_LRO;
4914
4915         /* make sure the EEPROM is good */
4916         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4917                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4918                 err = -EIO;
4919                 goto err_eeprom;
4920         }
4921
4922         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4923         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4924
4925         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4926                 dev_err(&pdev->dev, "invalid MAC address\n");
4927                 err = -EIO;
4928                 goto err_eeprom;
4929         }
4930
4931         init_timer(&adapter->watchdog_timer);
4932         adapter->watchdog_timer.function = &ixgbe_watchdog;
4933         adapter->watchdog_timer.data = (unsigned long)adapter;
4934
4935         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4936         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4937
4938         err = ixgbe_init_interrupt_scheme(adapter);
4939         if (err)
4940                 goto err_sw_init;
4941
4942         switch (pdev->device) {
4943         case IXGBE_DEV_ID_82599_KX4:
4944                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
4945                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
4946                 break;
4947         default:
4948                 adapter->wol = 0;
4949                 break;
4950         }
4951         device_init_wakeup(&adapter->pdev->dev, true);
4952         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4953
4954         /* pick up the PCI bus settings for reporting later */
4955         hw->mac.ops.get_bus_info(hw);
4956
4957         /* print bus type/speed/width info */
4958         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4959                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4960                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4961                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4962                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4963                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4964                  "Unknown"),
4965                 netdev->dev_addr);
4966         ixgbe_read_pba_num_generic(hw, &part_num);
4967         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4968                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4969                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4970                          (part_num >> 8), (part_num & 0xff));
4971         else
4972                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4973                          hw->mac.type, hw->phy.type,
4974                          (part_num >> 8), (part_num & 0xff));
4975
4976         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
4977                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4978                          "this card is not sufficient for optimal "
4979                          "performance.\n");
4980                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4981                          "PCI-Express slot is required.\n");
4982         }
4983
4984         /* save off EEPROM version number */
4985         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4986
4987         /* reset the hardware with the new settings */
4988         hw->mac.ops.start_hw(hw);
4989
4990         strcpy(netdev->name, "eth%d");
4991         err = register_netdev(netdev);
4992         if (err)
4993                 goto err_register;
4994
4995         /* carrier off reporting is important to ethtool even BEFORE open */
4996         netif_carrier_off(netdev);
4997
4998 #ifdef CONFIG_IXGBE_DCA
4999         if (dca_add_requester(&pdev->dev) == 0) {
5000                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5001                 /* always use CB2 mode, difference is masked
5002                  * in the CB driver */
5003                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5004                 ixgbe_setup_dca(adapter);
5005         }
5006 #endif
5007
5008         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5009         cards_found++;
5010         return 0;
5011
5012 err_register:
5013         ixgbe_release_hw_control(adapter);
5014 err_hw_init:
5015 err_sw_init:
5016         ixgbe_reset_interrupt_capability(adapter);
5017 err_eeprom:
5018         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5019         del_timer_sync(&adapter->sfp_timer);
5020         cancel_work_sync(&adapter->sfp_task);
5021         cancel_work_sync(&adapter->multispeed_fiber_task);
5022         cancel_work_sync(&adapter->sfp_config_module_task);
5023         iounmap(hw->hw_addr);
5024 err_ioremap:
5025         free_netdev(netdev);
5026 err_alloc_etherdev:
5027         pci_release_regions(pdev);
5028 err_pci_reg:
5029 err_dma:
5030         pci_disable_device(pdev);
5031         return err;
5032 }
5033
5034 /**
5035  * ixgbe_remove - Device Removal Routine
5036  * @pdev: PCI device information struct
5037  *
5038  * ixgbe_remove is called by the PCI subsystem to alert the driver
5039  * that it should release a PCI device.  The could be caused by a
5040  * Hot-Plug event, or because the driver is going to be removed from
5041  * memory.
5042  **/
5043 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5044 {
5045         struct net_device *netdev = pci_get_drvdata(pdev);
5046         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5047         int err;
5048
5049         set_bit(__IXGBE_DOWN, &adapter->state);
5050         /* clear the module not found bit to make sure the worker won't
5051          * reschedule
5052          */
5053         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5054         del_timer_sync(&adapter->watchdog_timer);
5055
5056         del_timer_sync(&adapter->sfp_timer);
5057         cancel_work_sync(&adapter->watchdog_task);
5058         cancel_work_sync(&adapter->sfp_task);
5059         cancel_work_sync(&adapter->multispeed_fiber_task);
5060         cancel_work_sync(&adapter->sfp_config_module_task);
5061         flush_scheduled_work();
5062
5063 #ifdef CONFIG_IXGBE_DCA
5064         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5065                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5066                 dca_remove_requester(&pdev->dev);
5067                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5068         }
5069
5070 #endif
5071         if (netdev->reg_state == NETREG_REGISTERED)
5072                 unregister_netdev(netdev);
5073
5074         ixgbe_reset_interrupt_capability(adapter);
5075
5076         ixgbe_release_hw_control(adapter);
5077
5078         iounmap(adapter->hw.hw_addr);
5079         pci_release_regions(pdev);
5080
5081         DPRINTK(PROBE, INFO, "complete\n");
5082         kfree(adapter->tx_ring);
5083         kfree(adapter->rx_ring);
5084
5085         free_netdev(netdev);
5086
5087         err = pci_disable_pcie_error_reporting(pdev);
5088         if (err)
5089                 dev_err(&pdev->dev,
5090                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5091
5092         pci_disable_device(pdev);
5093 }
5094
5095 /**
5096  * ixgbe_io_error_detected - called when PCI error is detected
5097  * @pdev: Pointer to PCI device
5098  * @state: The current pci connection state
5099  *
5100  * This function is called after a PCI bus error affecting
5101  * this device has been detected.
5102  */
5103 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5104                                                 pci_channel_state_t state)
5105 {
5106         struct net_device *netdev = pci_get_drvdata(pdev);
5107         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5108
5109         netif_device_detach(netdev);
5110
5111         if (netif_running(netdev))
5112                 ixgbe_down(adapter);
5113         pci_disable_device(pdev);
5114
5115         /* Request a slot reset. */
5116         return PCI_ERS_RESULT_NEED_RESET;
5117 }
5118
5119 /**
5120  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5121  * @pdev: Pointer to PCI device
5122  *
5123  * Restart the card from scratch, as if from a cold-boot.
5124  */
5125 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5126 {
5127         struct net_device *netdev = pci_get_drvdata(pdev);
5128         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5129         pci_ers_result_t result;
5130         int err;
5131
5132         if (pci_enable_device(pdev)) {
5133                 DPRINTK(PROBE, ERR,
5134                         "Cannot re-enable PCI device after reset.\n");
5135                 result = PCI_ERS_RESULT_DISCONNECT;
5136         } else {
5137                 pci_set_master(pdev);
5138                 pci_restore_state(pdev);
5139
5140                 pci_wake_from_d3(pdev, false);
5141
5142                 ixgbe_reset(adapter);
5143                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5144                 result = PCI_ERS_RESULT_RECOVERED;
5145         }
5146
5147         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5148         if (err) {
5149                 dev_err(&pdev->dev,
5150                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5151                 /* non-fatal, continue */
5152         }
5153
5154         return result;
5155 }
5156
5157 /**
5158  * ixgbe_io_resume - called when traffic can start flowing again.
5159  * @pdev: Pointer to PCI device
5160  *
5161  * This callback is called when the error recovery driver tells us that
5162  * its OK to resume normal operation.
5163  */
5164 static void ixgbe_io_resume(struct pci_dev *pdev)
5165 {
5166         struct net_device *netdev = pci_get_drvdata(pdev);
5167         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5168
5169         if (netif_running(netdev)) {
5170                 if (ixgbe_up(adapter)) {
5171                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5172                         return;
5173                 }
5174         }
5175
5176         netif_device_attach(netdev);
5177 }
5178
5179 static struct pci_error_handlers ixgbe_err_handler = {
5180         .error_detected = ixgbe_io_error_detected,
5181         .slot_reset = ixgbe_io_slot_reset,
5182         .resume = ixgbe_io_resume,
5183 };
5184
5185 static struct pci_driver ixgbe_driver = {
5186         .name     = ixgbe_driver_name,
5187         .id_table = ixgbe_pci_tbl,
5188         .probe    = ixgbe_probe,
5189         .remove   = __devexit_p(ixgbe_remove),
5190 #ifdef CONFIG_PM
5191         .suspend  = ixgbe_suspend,
5192         .resume   = ixgbe_resume,
5193 #endif
5194         .shutdown = ixgbe_shutdown,
5195         .err_handler = &ixgbe_err_handler
5196 };
5197
5198 /**
5199  * ixgbe_init_module - Driver Registration Routine
5200  *
5201  * ixgbe_init_module is the first routine called when the driver is
5202  * loaded. All it does is register with the PCI subsystem.
5203  **/
5204 static int __init ixgbe_init_module(void)
5205 {
5206         int ret;
5207         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5208                ixgbe_driver_string, ixgbe_driver_version);
5209
5210         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5211
5212 #ifdef CONFIG_IXGBE_DCA
5213         dca_register_notify(&dca_notifier);
5214 #endif
5215
5216         ret = pci_register_driver(&ixgbe_driver);
5217         return ret;
5218 }
5219
5220 module_init(ixgbe_init_module);
5221
5222 /**
5223  * ixgbe_exit_module - Driver Exit Cleanup Routine
5224  *
5225  * ixgbe_exit_module is called just before the driver is removed
5226  * from memory.
5227  **/
5228 static void __exit ixgbe_exit_module(void)
5229 {
5230 #ifdef CONFIG_IXGBE_DCA
5231         dca_unregister_notify(&dca_notifier);
5232 #endif
5233         pci_unregister_driver(&ixgbe_driver);
5234 }
5235
5236 #ifdef CONFIG_IXGBE_DCA
5237 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5238                             void *p)
5239 {
5240         int ret_val;
5241
5242         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5243                                          __ixgbe_notify_dca);
5244
5245         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5246 }
5247
5248 #endif /* CONFIG_IXGBE_DCA */
5249 #ifdef DEBUG
5250 /**
5251  * ixgbe_get_hw_dev_name - return device name string
5252  * used by hardware layer to print debugging information
5253  **/
5254 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5255 {
5256         struct ixgbe_adapter *adapter = hw->back;
5257         return adapter->netdev->name;
5258 }
5259
5260 #endif
5261 module_exit(ixgbe_exit_module);
5262
5263 /* ixgbe_main.c */