drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.16-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  92          board_82599 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  94          board_82599 },
  95
  96         /* required last entry */
  97         {0, }
  98 };
  99 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 100
 101 #ifdef CONFIG_IXGBE_DCA
 102 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 103                             void *p);
 104 static struct notifier_block dca_notifier = {
 105         .notifier_call = ixgbe_notify_dca,
 106         .next          = NULL,
 107         .priority      = 0
 108 };
 109 #endif
 110
 111 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 112 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 113 MODULE_LICENSE("GPL");
 114 MODULE_VERSION(DRV_VERSION);
 115
 116 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 117
 118 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 119 {
 120         u32 ctrl_ext;
 121
 122         /* Let firmware take over control of h/w */
 123         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 124         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 125                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 126 }
 127
 128 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 129 {
 130         u32 ctrl_ext;
 131
 132         /* Let firmware know the driver has taken over */
 133         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 134         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 135                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 136 }
 137
 138 /*
 139  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 140  * @adapter: pointer to adapter struct
 141  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 142  * @queue: queue to map the corresponding interrupt to
 143  * @msix_vector: the vector to map to the corresponding queue
 144  *
 145  */
 146 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 147                            u8 queue, u8 msix_vector)
 148 {
 149         u32 ivar, index;
 150         struct ixgbe_hw *hw = &adapter->hw;
 151         switch (hw->mac.type) {
 152         case ixgbe_mac_82598EB:
 153                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 154                 if (direction == -1)
 155                         direction = 0;
 156                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 157                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 158                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 159                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 160                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 161                 break;
 162         case ixgbe_mac_82599EB:
 163                 if (direction == -1) {
 164                         /* other causes */
 165                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 166                         index = ((queue & 1) * 8);
 167                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 168                         ivar &= ~(0xFF << index);
 169                         ivar |= (msix_vector << index);
 170                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 171                         break;
 172                 } else {
 173                         /* tx or rx causes */
 174                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 175                         index = ((16 * (queue & 1)) + (8 * direction));
 176                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 177                         ivar &= ~(0xFF << index);
 178                         ivar |= (msix_vector << index);
 179                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 180                         break;
 181                 }
 182         default:
 183                 break;
 184         }
 185 }
 186
 187 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 188                                              struct ixgbe_tx_buffer
 189                                              *tx_buffer_info)
 190 {
 191         tx_buffer_info->dma = 0;
 192         if (tx_buffer_info->skb) {
 193                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 194                               DMA_TO_DEVICE);
 195                 dev_kfree_skb_any(tx_buffer_info->skb);
 196                 tx_buffer_info->skb = NULL;
 197         }
 198         tx_buffer_info->time_stamp = 0;
 199         /* tx_buffer_info must be completely set up in the transmit path */
 200 }
 201
 202 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 203                                        struct ixgbe_ring *tx_ring,
 204                                        unsigned int eop)
 205 {
 206         struct ixgbe_hw *hw = &adapter->hw;
 207
 208         /* Detect a transmit hang in hardware, this serializes the
 209          * check with the clearing of time_stamp and movement of eop */
 210         adapter->detect_tx_hung = false;
 211         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 212             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 213             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 214                 /* detected Tx unit hang */
 215                 union ixgbe_adv_tx_desc *tx_desc;
 216                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 217                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 218                         "  Tx Queue             <%d>\n"
 219                         "  TDH, TDT             <%x>, <%x>\n"
 220                         "  next_to_use          <%x>\n"
 221                         "  next_to_clean        <%x>\n"
 222                         "tx_buffer_info[next_to_clean]\n"
 223                         "  time_stamp           <%lx>\n"
 224                         "  jiffies              <%lx>\n",
 225                         tx_ring->queue_index,
 226                         IXGBE_READ_REG(hw, tx_ring->head),
 227                         IXGBE_READ_REG(hw, tx_ring->tail),
 228                         tx_ring->next_to_use, eop,
 229                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 230                 return true;
 231         }
 232
 233         return false;
 234 }
 235
 236 #define IXGBE_MAX_TXD_PWR       14
 237 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 238
 239 /* Tx Descriptors needed, worst case */
 240 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 241                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 242 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 243         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 244
 245 static void ixgbe_tx_timeout(struct net_device *netdev);
 246
 247 /**
 248  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 249  * @adapter: board private structure
 250  * @tx_ring: tx ring to clean
 251  *
 252  * returns true if transmit work is done
 253  **/
 254 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 255                                struct ixgbe_ring *tx_ring)
 256 {
 257         struct net_device *netdev = adapter->netdev;
 258         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 259         struct ixgbe_tx_buffer *tx_buffer_info;
 260         unsigned int i, eop, count = 0;
 261         unsigned int total_bytes = 0, total_packets = 0;
 262
 263         i = tx_ring->next_to_clean;
 264         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 265         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 266
 267         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 268                (count < tx_ring->work_limit)) {
 269                 bool cleaned = false;
 270                 for ( ; !cleaned; count++) {
 271                         struct sk_buff *skb;
 272                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 273                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 274                         cleaned = (i == eop);
 275                         skb = tx_buffer_info->skb;
 276
 277                         if (cleaned && skb) {
 278                                 unsigned int segs, bytecount;
 279
 280                                 /* gso_segs is currently only valid for tcp */
 281                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 282                                 /* multiply data chunks by size of headers */
 283                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 284                                             skb->len;
 285                                 total_packets += segs;
 286                                 total_bytes += bytecount;
 287                         }
 288
 289                         ixgbe_unmap_and_free_tx_resource(adapter,
 290                                                          tx_buffer_info);
 291
 292                         tx_desc->wb.status = 0;
 293
 294                         i++;
 295                         if (i == tx_ring->count)
 296                                 i = 0;
 297                 }
 298
 299                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 300                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 301         }
 302
 303         tx_ring->next_to_clean = i;
 304
 305 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 306         if (unlikely(count && netif_carrier_ok(netdev) &&
 307                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 308                 /* Make sure that anybody stopping the queue after this
 309                  * sees the new next_to_clean.
 310                  */
 311                 smp_mb();
 312                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 313                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 314                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 315                         ++adapter->restart_queue;
 316                 }
 317         }
 318
 319         if (adapter->detect_tx_hung) {
 320                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 321                         /* schedule immediate reset if we believe we hung */
 322                         DPRINTK(PROBE, INFO,
 323                                 "tx hang %d detected, resetting adapter\n",
 324                                 adapter->tx_timeout_count + 1);
 325                         ixgbe_tx_timeout(adapter->netdev);
 326                 }
 327         }
 328
 329         /* re-arm the interrupt */
 330         if (count >= tx_ring->work_limit) {
 331                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 332                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
 333                                         tx_ring->v_idx);
 334                 else if (tx_ring->v_idx & 0xFFFFFFFF)
 335                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
 336                                         tx_ring->v_idx);
 337                 else
 338                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
 339                                         (tx_ring->v_idx >> 32));
 340         }
 341
 342
 343         tx_ring->total_bytes += total_bytes;
 344         tx_ring->total_packets += total_packets;
 345         tx_ring->stats.packets += total_packets;
 346         tx_ring->stats.bytes += total_bytes;
 347         adapter->net_stats.tx_bytes += total_bytes;
 348         adapter->net_stats.tx_packets += total_packets;
 349         return (count < tx_ring->work_limit);
 350 }
 351
 352 #ifdef CONFIG_IXGBE_DCA
 353 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 354                                 struct ixgbe_ring *rx_ring)
 355 {
 356         u32 rxctrl;
 357         int cpu = get_cpu();
 358         int q = rx_ring - adapter->rx_ring;
 359
 360         if (rx_ring->cpu != cpu) {
 361                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 362                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 363                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 364                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 365                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 366                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 367                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 368                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 369                 }
 370                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 371                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 372                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 373                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 374                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 375                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 376                 rx_ring->cpu = cpu;
 377         }
 378         put_cpu();
 379 }
 380
 381 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 382                                 struct ixgbe_ring *tx_ring)
 383 {
 384         u32 txctrl;
 385         int cpu = get_cpu();
 386         int q = tx_ring - adapter->tx_ring;
 387
 388         if (tx_ring->cpu != cpu) {
 389                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 390                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 391                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 392                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 393                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 394                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 395                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 396                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 397                 }
 398                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 399                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 400                 tx_ring->cpu = cpu;
 401         }
 402         put_cpu();
 403 }
 404
 405 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 406 {
 407         int i;
 408
 409         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 410                 return;
 411
 412         for (i = 0; i < adapter->num_tx_queues; i++) {
 413                 adapter->tx_ring[i].cpu = -1;
 414                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 415         }
 416         for (i = 0; i < adapter->num_rx_queues; i++) {
 417                 adapter->rx_ring[i].cpu = -1;
 418                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 419         }
 420 }
 421
 422 static int __ixgbe_notify_dca(struct device *dev, void *data)
 423 {
 424         struct net_device *netdev = dev_get_drvdata(dev);
 425         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 426         unsigned long event = *(unsigned long *)data;
 427
 428         switch (event) {
 429         case DCA_PROVIDER_ADD:
 430                 /* if we're already enabled, don't do it again */
 431                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 432                         break;
 433                 /* Always use CB2 mode, difference is masked
 434                  * in the CB driver. */
 435                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 436                 if (dca_add_requester(dev) == 0) {
 437                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 438                         ixgbe_setup_dca(adapter);
 439                         break;
 440                 }
 441                 /* Fall Through since DCA is disabled. */
 442         case DCA_PROVIDER_REMOVE:
 443                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 444                         dca_remove_requester(dev);
 445                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 446                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 447                 }
 448                 break;
 449         }
 450
 451         return 0;
 452 }
 453
 454 #endif /* CONFIG_IXGBE_DCA */
 455 /**
 456  * ixgbe_receive_skb - Send a completed packet up the stack
 457  * @adapter: board private structure
 458  * @skb: packet to send up
 459  * @status: hardware indication of status of receive
 460  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 461  * @rx_desc: rx descriptor
 462  **/
 463 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 464                               struct sk_buff *skb, u8 status,
 465                               struct ixgbe_ring *ring,
 466                               union ixgbe_adv_rx_desc *rx_desc)
 467 {
 468         struct ixgbe_adapter *adapter = q_vector->adapter;
 469         struct napi_struct *napi = &q_vector->napi;
 470         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 471         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 472
 473         skb_record_rx_queue(skb, ring->queue_index);
 474         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 475                 if (adapter->vlgrp && is_vlan && (tag != 0))
 476                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 477                 else
 478                         napi_gro_receive(napi, skb);
 479         } else {
 480                 if (adapter->vlgrp && is_vlan && (tag != 0))
 481                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 482                 else
 483                         netif_rx(skb);
 484         }
 485 }
 486
 487 /**
 488  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 489  * @adapter: address of board private structure
 490  * @status_err: hardware indication of status of receive
 491  * @skb: skb currently being received and modified
 492  **/
 493 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 494                                      u32 status_err, struct sk_buff *skb)
 495 {
 496         skb->ip_summed = CHECKSUM_NONE;
 497
 498         /* Rx csum disabled */
 499         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 500                 return;
 501
 502         /* if IP and error */
 503         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 504             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 505                 adapter->hw_csum_rx_error++;
 506                 return;
 507         }
 508
 509         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 510                 return;
 511
 512         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 513                 adapter->hw_csum_rx_error++;
 514                 return;
 515         }
 516
 517         /* It must be a TCP or UDP packet with a valid checksum */
 518         skb->ip_summed = CHECKSUM_UNNECESSARY;
 519         adapter->hw_csum_rx_good++;
 520 }
 521
 522 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 523                                          struct ixgbe_ring *rx_ring, u32 val)
 524 {
 525         /*
 526          * Force memory writes to complete before letting h/w
 527          * know there are new descriptors to fetch.  (Only
 528          * applicable for weak-ordered memory model archs,
 529          * such as IA-64).
 530          */
 531         wmb();
 532         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 533 }
 534
 535 /**
 536  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 537  * @adapter: address of board private structure
 538  **/
 539 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 540                                    struct ixgbe_ring *rx_ring,
 541                                    int cleaned_count)
 542 {
 543         struct pci_dev *pdev = adapter->pdev;
 544         union ixgbe_adv_rx_desc *rx_desc;
 545         struct ixgbe_rx_buffer *bi;
 546         unsigned int i;
 547         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 548
 549         i = rx_ring->next_to_use;
 550         bi = &rx_ring->rx_buffer_info[i];
 551
 552         while (cleaned_count--) {
 553                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 554
 555                 if (!bi->page_dma &&
 556                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 557                         if (!bi->page) {
 558                                 bi->page = alloc_page(GFP_ATOMIC);
 559                                 if (!bi->page) {
 560                                         adapter->alloc_rx_page_failed++;
 561                                         goto no_buffers;
 562                                 }
 563                                 bi->page_offset = 0;
 564                         } else {
 565                                 /* use a half page if we're re-using */
 566                                 bi->page_offset ^= (PAGE_SIZE / 2);
 567                         }
 568
 569                         bi->page_dma = pci_map_page(pdev, bi->page,
 570                                                     bi->page_offset,
 571                                                     (PAGE_SIZE / 2),
 572                                                     PCI_DMA_FROMDEVICE);
 573                 }
 574
 575                 if (!bi->skb) {
 576                         struct sk_buff *skb;
 577                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 578
 579                         if (!skb) {
 580                                 adapter->alloc_rx_buff_failed++;
 581                                 goto no_buffers;
 582                         }
 583
 584                         /*
 585                          * Make buffer alignment 2 beyond a 16 byte boundary
 586                          * this will result in a 16 byte aligned IP header after
 587                          * the 14 byte MAC header is removed
 588                          */
 589                         skb_reserve(skb, NET_IP_ALIGN);
 590
 591                         bi->skb = skb;
 592                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 593                                                  PCI_DMA_FROMDEVICE);
 594                 }
 595                 /* Refresh the desc even if buffer_addrs didn't change because
 596                  * each write-back erases this info. */
 597                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 598                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 599                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 600                 } else {
 601                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 602                 }
 603
 604                 i++;
 605                 if (i == rx_ring->count)
 606                         i = 0;
 607                 bi = &rx_ring->rx_buffer_info[i];
 608         }
 609
 610 no_buffers:
 611         if (rx_ring->next_to_use != i) {
 612                 rx_ring->next_to_use = i;
 613                 if (i-- == 0)
 614                         i = (rx_ring->count - 1);
 615
 616                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 617         }
 618 }
 619
 620 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 621 {
 622         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 623 }
 624
 625 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 626 {
 627         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 628 }
 629
 630 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 631 {
 632         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 633                 IXGBE_RXDADV_RSCCNT_MASK) >>
 634                 IXGBE_RXDADV_RSCCNT_SHIFT;
 635 }
 636
 637 /**
 638  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 639  * @skb: pointer to the last skb in the rsc queue
 640  *
 641  * This function changes a queue full of hw rsc buffers into a completed
 642  * packet.  It uses the ->prev pointers to find the first packet and then
 643  * turns it into the frag list owner.
 644  **/
 645 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 646 {
 647         unsigned int frag_list_size = 0;
 648
 649         while (skb->prev) {
 650                 struct sk_buff *prev = skb->prev;
 651                 frag_list_size += skb->len;
 652                 skb->prev = NULL;
 653                 skb = prev;
 654         }
 655
 656         skb_shinfo(skb)->frag_list = skb->next;
 657         skb->next = NULL;
 658         skb->len += frag_list_size;
 659         skb->data_len += frag_list_size;
 660         skb->truesize += frag_list_size;
 661         return skb;
 662 }
 663
 664 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 665                                struct ixgbe_ring *rx_ring,
 666                                int *work_done, int work_to_do)
 667 {
 668         struct ixgbe_adapter *adapter = q_vector->adapter;
 669         struct pci_dev *pdev = adapter->pdev;
 670         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 671         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 672         struct sk_buff *skb;
 673         unsigned int i, rsc_count = 0;
 674         u32 len, staterr;
 675         u16 hdr_info;
 676         bool cleaned = false;
 677         int cleaned_count = 0;
 678         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 679
 680         i = rx_ring->next_to_clean;
 681         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 682         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 683         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 684
 685         while (staterr & IXGBE_RXD_STAT_DD) {
 686                 u32 upper_len = 0;
 687                 if (*work_done >= work_to_do)
 688                         break;
 689                 (*work_done)++;
 690
 691                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 692                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 693                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 694                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 695                         if (hdr_info & IXGBE_RXDADV_SPH)
 696                                 adapter->rx_hdr_split++;
 697                         if (len > IXGBE_RX_HDR_SIZE)
 698                                 len = IXGBE_RX_HDR_SIZE;
 699                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 700                 } else {
 701                         len = le16_to_cpu(rx_desc->wb.upper.length);
 702                 }
 703
 704                 cleaned = true;
 705                 skb = rx_buffer_info->skb;
 706                 prefetch(skb->data - NET_IP_ALIGN);
 707                 rx_buffer_info->skb = NULL;
 708
 709                 if (len && !skb_shinfo(skb)->nr_frags) {
 710                         pci_unmap_single(pdev, rx_buffer_info->dma,
 711                                          rx_ring->rx_buf_len,
 712                                          PCI_DMA_FROMDEVICE);
 713                         skb_put(skb, len);
 714                 }
 715
 716                 if (upper_len) {
 717                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 718                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 719                         rx_buffer_info->page_dma = 0;
 720                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 721                                            rx_buffer_info->page,
 722                                            rx_buffer_info->page_offset,
 723                                            upper_len);
 724
 725                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 726                             (page_count(rx_buffer_info->page) != 1))
 727                                 rx_buffer_info->page = NULL;
 728                         else
 729                                 get_page(rx_buffer_info->page);
 730
 731                         skb->len += upper_len;
 732                         skb->data_len += upper_len;
 733                         skb->truesize += upper_len;
 734                 }
 735
 736                 i++;
 737                 if (i == rx_ring->count)
 738                         i = 0;
 739
 740                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 741                 prefetch(next_rxd);
 742                 cleaned_count++;
 743
 744                 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
 745                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 746
 747                 if (rsc_count) {
 748                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 749                                      IXGBE_RXDADV_NEXTP_SHIFT;
 750                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 751                         rx_ring->rsc_count += (rsc_count - 1);
 752                 } else {
 753                         next_buffer = &rx_ring->rx_buffer_info[i];
 754                 }
 755
 756                 if (staterr & IXGBE_RXD_STAT_EOP) {
 757                         if (skb->prev)
 758                                 skb = ixgbe_transform_rsc_queue(skb);
 759                         rx_ring->stats.packets++;
 760                         rx_ring->stats.bytes += skb->len;
 761                 } else {
 762                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 763                                 rx_buffer_info->skb = next_buffer->skb;
 764                                 rx_buffer_info->dma = next_buffer->dma;
 765                                 next_buffer->skb = skb;
 766                                 next_buffer->dma = 0;
 767                         } else {
 768                                 skb->next = next_buffer->skb;
 769                                 skb->next->prev = skb;
 770                         }
 771                         adapter->non_eop_descs++;
 772                         goto next_desc;
 773                 }
 774
 775                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 776                         dev_kfree_skb_irq(skb);
 777                         goto next_desc;
 778                 }
 779
 780                 ixgbe_rx_checksum(adapter, staterr, skb);
 781
 782                 /* probably a little skewed due to removing CRC */
 783                 total_rx_bytes += skb->len;
 784                 total_rx_packets++;
 785
 786                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 787                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 788
 789 next_desc:
 790                 rx_desc->wb.upper.status_error = 0;
 791
 792                 /* return some buffers to hardware, one at a time is too slow */
 793                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 794                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 795                         cleaned_count = 0;
 796                 }
 797
 798                 /* use prefetched values */
 799                 rx_desc = next_rxd;
 800                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 801
 802                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 803         }
 804
 805         rx_ring->next_to_clean = i;
 806         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 807
 808         if (cleaned_count)
 809                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 810
 811         rx_ring->total_packets += total_rx_packets;
 812         rx_ring->total_bytes += total_rx_bytes;
 813         adapter->net_stats.rx_bytes += total_rx_bytes;
 814         adapter->net_stats.rx_packets += total_rx_packets;
 815
 816         return cleaned;
 817 }
 818
 819 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 820 /**
 821  * ixgbe_configure_msix - Configure MSI-X hardware
 822  * @adapter: board private structure
 823  *
 824  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 825  * interrupts.
 826  **/
 827 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 828 {
 829         struct ixgbe_q_vector *q_vector;
 830         int i, j, q_vectors, v_idx, r_idx;
 831         u32 mask;
 832
 833         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 834
 835         /*
 836          * Populate the IVAR table and set the ITR values to the
 837          * corresponding register.
 838          */
 839         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 840                 q_vector = adapter->q_vector[v_idx];
 841                 /* XXX for_each_bit(...) */
 842                 r_idx = find_first_bit(q_vector->rxr_idx,
 843                                        adapter->num_rx_queues);
 844
 845                 for (i = 0; i < q_vector->rxr_count; i++) {
 846                         j = adapter->rx_ring[r_idx].reg_idx;
 847                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 848                         r_idx = find_next_bit(q_vector->rxr_idx,
 849                                               adapter->num_rx_queues,
 850                                               r_idx + 1);
 851                 }
 852                 r_idx = find_first_bit(q_vector->txr_idx,
 853                                        adapter->num_tx_queues);
 854
 855                 for (i = 0; i < q_vector->txr_count; i++) {
 856                         j = adapter->tx_ring[r_idx].reg_idx;
 857                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 858                         r_idx = find_next_bit(q_vector->txr_idx,
 859                                               adapter->num_tx_queues,
 860                                               r_idx + 1);
 861                 }
 862
 863                 /* if this is a tx only vector halve the interrupt rate */
 864                 if (q_vector->txr_count && !q_vector->rxr_count)
 865                         q_vector->eitr = (adapter->eitr_param >> 1);
 866                 else if (q_vector->rxr_count)
 867                         /* rx only */
 868                         q_vector->eitr = adapter->eitr_param;
 869
 870                 /*
 871                  * since this is initial set up don't need to call
 872                  * ixgbe_write_eitr helper
 873                  */
 874                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 875                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 876         }
 877
 878         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 879                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 880                                v_idx);
 881         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 882                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 883         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 884
 885         /* set up to autoclear timer, and the vectors */
 886         mask = IXGBE_EIMS_ENABLE_MASK;
 887         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 888         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 889 }
 890
 891 enum latency_range {
 892         lowest_latency = 0,
 893         low_latency = 1,
 894         bulk_latency = 2,
 895         latency_invalid = 255
 896 };
 897
 898 /**
 899  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 900  * @adapter: pointer to adapter
 901  * @eitr: eitr setting (ints per sec) to give last timeslice
 902  * @itr_setting: current throttle rate in ints/second
 903  * @packets: the number of packets during this measurement interval
 904  * @bytes: the number of bytes during this measurement interval
 905  *
 906  *      Stores a new ITR value based on packets and byte
 907  *      counts during the last interrupt.  The advantage of per interrupt
 908  *      computation is faster updates and more accurate ITR for the current
 909  *      traffic pattern.  Constants in this function were computed
 910  *      based on theoretical maximum wire speed and thresholds were set based
 911  *      on testing data as well as attempting to minimize response time
 912  *      while increasing bulk throughput.
 913  *      this functionality is controlled by the InterruptThrottleRate module
 914  *      parameter (see ixgbe_param.c)
 915  **/
 916 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 917                            u32 eitr, u8 itr_setting,
 918                            int packets, int bytes)
 919 {
 920         unsigned int retval = itr_setting;
 921         u32 timepassed_us;
 922         u64 bytes_perint;
 923
 924         if (packets == 0)
 925                 goto update_itr_done;
 926
 927
 928         /* simple throttlerate management
 929          *    0-20MB/s lowest (100000 ints/s)
 930          *   20-100MB/s low   (20000 ints/s)
 931          *  100-1249MB/s bulk (8000 ints/s)
 932          */
 933         /* what was last interrupt timeslice? */
 934         timepassed_us = 1000000/eitr;
 935         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 936
 937         switch (itr_setting) {
 938         case lowest_latency:
 939                 if (bytes_perint > adapter->eitr_low)
 940                         retval = low_latency;
 941                 break;
 942         case low_latency:
 943                 if (bytes_perint > adapter->eitr_high)
 944                         retval = bulk_latency;
 945                 else if (bytes_perint <= adapter->eitr_low)
 946                         retval = lowest_latency;
 947                 break;
 948         case bulk_latency:
 949                 if (bytes_perint <= adapter->eitr_high)
 950                         retval = low_latency;
 951                 break;
 952         }
 953
 954 update_itr_done:
 955         return retval;
 956 }
 957
 958 /**
 959  * ixgbe_write_eitr - write EITR register in hardware specific way
 960  * @adapter: pointer to adapter struct
 961  * @v_idx: vector index into q_vector array
 962  * @itr_reg: new value to be written in *register* format, not ints/s
 963  *
 964  * This function is made to be called by ethtool and by the driver
 965  * when it needs to update EITR registers at runtime.  Hardware
 966  * specific quirks/differences are taken care of here.
 967  */
 968 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
 969 {
 970         struct ixgbe_hw *hw = &adapter->hw;
 971         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 972                 /* must write high and low 16 bits to reset counter */
 973                 itr_reg |= (itr_reg << 16);
 974         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 975                 /*
 976                  * set the WDIS bit to not clear the timer bits and cause an
 977                  * immediate assertion of the interrupt
 978                  */
 979                 itr_reg |= IXGBE_EITR_CNT_WDIS;
 980         }
 981         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 982 }
 983
 984 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 985 {
 986         struct ixgbe_adapter *adapter = q_vector->adapter;
 987         u32 new_itr;
 988         u8 current_itr, ret_itr;
 989         int i, r_idx, v_idx = q_vector->v_idx;
 990         struct ixgbe_ring *rx_ring, *tx_ring;
 991
 992         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 993         for (i = 0; i < q_vector->txr_count; i++) {
 994                 tx_ring = &(adapter->tx_ring[r_idx]);
 995                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 996                                            q_vector->tx_itr,
 997                                            tx_ring->total_packets,
 998                                            tx_ring->total_bytes);
 999                 /* if the result for this queue would decrease interrupt
1000                  * rate for this vector then use that result */
1001                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1002                                     q_vector->tx_itr - 1 : ret_itr);
1003                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1004                                       r_idx + 1);
1005         }
1006
1007         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1008         for (i = 0; i < q_vector->rxr_count; i++) {
1009                 rx_ring = &(adapter->rx_ring[r_idx]);
1010                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1011                                            q_vector->rx_itr,
1012                                            rx_ring->total_packets,
1013                                            rx_ring->total_bytes);
1014                 /* if the result for this queue would decrease interrupt
1015                  * rate for this vector then use that result */
1016                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1017                                     q_vector->rx_itr - 1 : ret_itr);
1018                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1019                                       r_idx + 1);
1020         }
1021
1022         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1023
1024         switch (current_itr) {
1025         /* counts and packets in update_itr are dependent on these numbers */
1026         case lowest_latency:
1027                 new_itr = 100000;
1028                 break;
1029         case low_latency:
1030                 new_itr = 20000; /* aka hwitr = ~200 */
1031                 break;
1032         case bulk_latency:
1033         default:
1034                 new_itr = 8000;
1035                 break;
1036         }
1037
1038         if (new_itr != q_vector->eitr) {
1039                 u32 itr_reg;
1040
1041                 /* save the algorithm value here, not the smoothed one */
1042                 q_vector->eitr = new_itr;
1043                 /* do an exponential smoothing */
1044                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1045                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1046                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1047         }
1048
1049         return;
1050 }
1051
1052 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1053 {
1054         struct ixgbe_hw *hw = &adapter->hw;
1055
1056         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1057             (eicr & IXGBE_EICR_GPI_SDP1)) {
1058                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1059                 /* write to clear the interrupt */
1060                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1061         }
1062 }
1063
1064 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1065 {
1066         struct ixgbe_hw *hw = &adapter->hw;
1067
1068         if (eicr & IXGBE_EICR_GPI_SDP1) {
1069                 /* Clear the interrupt */
1070                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1071                 schedule_work(&adapter->multispeed_fiber_task);
1072         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1073                 /* Clear the interrupt */
1074                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1075                 schedule_work(&adapter->sfp_config_module_task);
1076         } else {
1077                 /* Interrupt isn't for us... */
1078                 return;
1079         }
1080 }
1081
1082 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1083 {
1084         struct ixgbe_hw *hw = &adapter->hw;
1085
1086         adapter->lsc_int++;
1087         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1088         adapter->link_check_timeout = jiffies;
1089         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1090                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1091                 schedule_work(&adapter->watchdog_task);
1092         }
1093 }
1094
1095 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1096 {
1097         struct net_device *netdev = data;
1098         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1099         struct ixgbe_hw *hw = &adapter->hw;
1100         u32 eicr;
1101
1102         /*
1103          * Workaround for Silicon errata.  Use clear-by-write instead
1104          * of clear-by-read.  Reading with EICS will return the
1105          * interrupt causes without clearing, which later be done
1106          * with the write to EICR.
1107          */
1108         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1109         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1110
1111         if (eicr & IXGBE_EICR_LSC)
1112                 ixgbe_check_lsc(adapter);
1113
1114         if (hw->mac.type == ixgbe_mac_82598EB)
1115                 ixgbe_check_fan_failure(adapter, eicr);
1116
1117         if (hw->mac.type == ixgbe_mac_82599EB)
1118                 ixgbe_check_sfp_event(adapter, eicr);
1119         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1120                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1121
1122         return IRQ_HANDLED;
1123 }
1124
1125 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1126 {
1127         struct ixgbe_q_vector *q_vector = data;
1128         struct ixgbe_adapter  *adapter = q_vector->adapter;
1129         struct ixgbe_ring     *tx_ring;
1130         int i, r_idx;
1131
1132         if (!q_vector->txr_count)
1133                 return IRQ_HANDLED;
1134
1135         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1136         for (i = 0; i < q_vector->txr_count; i++) {
1137                 tx_ring = &(adapter->tx_ring[r_idx]);
1138 #ifdef CONFIG_IXGBE_DCA
1139                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1140                         ixgbe_update_tx_dca(adapter, tx_ring);
1141 #endif
1142                 tx_ring->total_bytes = 0;
1143                 tx_ring->total_packets = 0;
1144                 ixgbe_clean_tx_irq(adapter, tx_ring);
1145                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1146                                       r_idx + 1);
1147         }
1148
1149         return IRQ_HANDLED;
1150 }
1151
1152 /**
1153  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1154  * @irq: unused
1155  * @data: pointer to our q_vector struct for this interrupt vector
1156  **/
1157 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1158 {
1159         struct ixgbe_q_vector *q_vector = data;
1160         struct ixgbe_adapter  *adapter = q_vector->adapter;
1161         struct ixgbe_ring  *rx_ring;
1162         int r_idx;
1163         int i;
1164
1165         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1166         for (i = 0;  i < q_vector->rxr_count; i++) {
1167                 rx_ring = &(adapter->rx_ring[r_idx]);
1168                 rx_ring->total_bytes = 0;
1169                 rx_ring->total_packets = 0;
1170                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1171                                       r_idx + 1);
1172         }
1173
1174         if (!q_vector->rxr_count)
1175                 return IRQ_HANDLED;
1176
1177         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1178         rx_ring = &(adapter->rx_ring[r_idx]);
1179         /* disable interrupts on this vector only */
1180         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1181                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1182         else if (rx_ring->v_idx & 0xFFFFFFFF)
1183                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1184         else
1185                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1186                                 (rx_ring->v_idx >> 32));
1187         napi_schedule(&q_vector->napi);
1188
1189         return IRQ_HANDLED;
1190 }
1191
1192 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1193 {
1194         ixgbe_msix_clean_rx(irq, data);
1195         ixgbe_msix_clean_tx(irq, data);
1196
1197         return IRQ_HANDLED;
1198 }
1199
1200 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1201                                            u64 qmask)
1202 {
1203         u32 mask;
1204
1205         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1206                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1207                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1208         } else {
1209                 mask = (qmask & 0xFFFFFFFF);
1210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1211                 mask = (qmask >> 32);
1212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1213         }
1214         /* skip the flush */
1215 }
1216
1217 /**
1218  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1219  * @napi: napi struct with our devices info in it
1220  * @budget: amount of work driver is allowed to do this pass, in packets
1221  *
1222  * This function is optimized for cleaning one queue only on a single
1223  * q_vector!!!
1224  **/
1225 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1226 {
1227         struct ixgbe_q_vector *q_vector =
1228                                container_of(napi, struct ixgbe_q_vector, napi);
1229         struct ixgbe_adapter *adapter = q_vector->adapter;
1230         struct ixgbe_ring *rx_ring = NULL;
1231         int work_done = 0;
1232         long r_idx;
1233
1234         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1235         rx_ring = &(adapter->rx_ring[r_idx]);
1236 #ifdef CONFIG_IXGBE_DCA
1237         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1238                 ixgbe_update_rx_dca(adapter, rx_ring);
1239 #endif
1240
1241         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1242
1243         /* If all Rx work done, exit the polling mode */
1244         if (work_done < budget) {
1245                 napi_complete(napi);
1246                 if (adapter->itr_setting & 1)
1247                         ixgbe_set_itr_msix(q_vector);
1248                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1249                         ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1250         }
1251
1252         return work_done;
1253 }
1254
1255 /**
1256  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1257  * @napi: napi struct with our devices info in it
1258  * @budget: amount of work driver is allowed to do this pass, in packets
1259  *
1260  * This function will clean more than one rx queue associated with a
1261  * q_vector.
1262  **/
1263 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1264 {
1265         struct ixgbe_q_vector *q_vector =
1266                                container_of(napi, struct ixgbe_q_vector, napi);
1267         struct ixgbe_adapter *adapter = q_vector->adapter;
1268         struct ixgbe_ring *rx_ring = NULL;
1269         int work_done = 0, i;
1270         long r_idx;
1271         u64 enable_mask = 0;
1272
1273         /* attempt to distribute budget to each queue fairly, but don't allow
1274          * the budget to go below 1 because we'll exit polling */
1275         budget /= (q_vector->rxr_count ?: 1);
1276         budget = max(budget, 1);
1277         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1278         for (i = 0; i < q_vector->rxr_count; i++) {
1279                 rx_ring = &(adapter->rx_ring[r_idx]);
1280 #ifdef CONFIG_IXGBE_DCA
1281                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1282                         ixgbe_update_rx_dca(adapter, rx_ring);
1283 #endif
1284                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1285                 enable_mask |= rx_ring->v_idx;
1286                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1287                                       r_idx + 1);
1288         }
1289
1290         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1291         rx_ring = &(adapter->rx_ring[r_idx]);
1292         /* If all Rx work done, exit the polling mode */
1293         if (work_done < budget) {
1294                 napi_complete(napi);
1295                 if (adapter->itr_setting & 1)
1296                         ixgbe_set_itr_msix(q_vector);
1297                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1298                         ixgbe_irq_enable_queues(adapter, enable_mask);
1299                 return 0;
1300         }
1301
1302         return work_done;
1303 }
1304 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1305                                      int r_idx)
1306 {
1307         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1308
1309         set_bit(r_idx, q_vector->rxr_idx);
1310         q_vector->rxr_count++;
1311         a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
1312 }
1313
1314 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1315                                      int t_idx)
1316 {
1317         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1318
1319         set_bit(t_idx, q_vector->txr_idx);
1320         q_vector->txr_count++;
1321         a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
1322 }
1323
1324 /**
1325  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1326  * @adapter: board private structure to initialize
1327  * @vectors: allotted vector count for descriptor rings
1328  *
1329  * This function maps descriptor rings to the queue-specific vectors
1330  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1331  * one vector per ring/queue, but on a constrained vector budget, we
1332  * group the rings as "efficiently" as possible.  You would add new
1333  * mapping configurations in here.
1334  **/
1335 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1336                                       int vectors)
1337 {
1338         int v_start = 0;
1339         int rxr_idx = 0, txr_idx = 0;
1340         int rxr_remaining = adapter->num_rx_queues;
1341         int txr_remaining = adapter->num_tx_queues;
1342         int i, j;
1343         int rqpv, tqpv;
1344         int err = 0;
1345
1346         /* No mapping required if MSI-X is disabled. */
1347         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1348                 goto out;
1349
1350         /*
1351          * The ideal configuration...
1352          * We have enough vectors to map one per queue.
1353          */
1354         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1355                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1356                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1357
1358                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1359                         map_vector_to_txq(adapter, v_start, txr_idx);
1360
1361                 goto out;
1362         }
1363
1364         /*
1365          * If we don't have enough vectors for a 1-to-1
1366          * mapping, we'll have to group them so there are
1367          * multiple queues per vector.
1368          */
1369         /* Re-adjusting *qpv takes care of the remainder. */
1370         for (i = v_start; i < vectors; i++) {
1371                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1372                 for (j = 0; j < rqpv; j++) {
1373                         map_vector_to_rxq(adapter, i, rxr_idx);
1374                         rxr_idx++;
1375                         rxr_remaining--;
1376                 }
1377         }
1378         for (i = v_start; i < vectors; i++) {
1379                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1380                 for (j = 0; j < tqpv; j++) {
1381                         map_vector_to_txq(adapter, i, txr_idx);
1382                         txr_idx++;
1383                         txr_remaining--;
1384                 }
1385         }
1386
1387 out:
1388         return err;
1389 }
1390
1391 /**
1392  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1393  * @adapter: board private structure
1394  *
1395  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1396  * interrupts from the kernel.
1397  **/
1398 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1399 {
1400         struct net_device *netdev = adapter->netdev;
1401         irqreturn_t (*handler)(int, void *);
1402         int i, vector, q_vectors, err;
1403         int ri=0, ti=0;
1404
1405         /* Decrement for Other and TCP Timer vectors */
1406         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1407
1408         /* Map the Tx/Rx rings to the vectors we were allotted. */
1409         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1410         if (err)
1411                 goto out;
1412
1413 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1414                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1415                          &ixgbe_msix_clean_many)
1416         for (vector = 0; vector < q_vectors; vector++) {
1417                 handler = SET_HANDLER(adapter->q_vector[vector]);
1418
1419                 if(handler == &ixgbe_msix_clean_rx) {
1420                         sprintf(adapter->name[vector], "%s-%s-%d",
1421                                 netdev->name, "rx", ri++);
1422                 }
1423                 else if(handler == &ixgbe_msix_clean_tx) {
1424                         sprintf(adapter->name[vector], "%s-%s-%d",
1425                                 netdev->name, "tx", ti++);
1426                 }
1427                 else
1428                         sprintf(adapter->name[vector], "%s-%s-%d",
1429                                 netdev->name, "TxRx", vector);
1430
1431                 err = request_irq(adapter->msix_entries[vector].vector,
1432                                   handler, 0, adapter->name[vector],
1433                                   adapter->q_vector[vector]);
1434                 if (err) {
1435                         DPRINTK(PROBE, ERR,
1436                                 "request_irq failed for MSIX interrupt "
1437                                 "Error: %d\n", err);
1438                         goto free_queue_irqs;
1439                 }
1440         }
1441
1442         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1443         err = request_irq(adapter->msix_entries[vector].vector,
1444                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1445         if (err) {
1446                 DPRINTK(PROBE, ERR,
1447                         "request_irq for msix_lsc failed: %d\n", err);
1448                 goto free_queue_irqs;
1449         }
1450
1451         return 0;
1452
1453 free_queue_irqs:
1454         for (i = vector - 1; i >= 0; i--)
1455                 free_irq(adapter->msix_entries[--vector].vector,
1456                          adapter->q_vector[i]);
1457         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1458         pci_disable_msix(adapter->pdev);
1459         kfree(adapter->msix_entries);
1460         adapter->msix_entries = NULL;
1461 out:
1462         return err;
1463 }
1464
1465 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1466 {
1467         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1468         u8 current_itr;
1469         u32 new_itr = q_vector->eitr;
1470         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1471         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1472
1473         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1474                                             q_vector->tx_itr,
1475                                             tx_ring->total_packets,
1476                                             tx_ring->total_bytes);
1477         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1478                                             q_vector->rx_itr,
1479                                             rx_ring->total_packets,
1480                                             rx_ring->total_bytes);
1481
1482         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1483
1484         switch (current_itr) {
1485         /* counts and packets in update_itr are dependent on these numbers */
1486         case lowest_latency:
1487                 new_itr = 100000;
1488                 break;
1489         case low_latency:
1490                 new_itr = 20000; /* aka hwitr = ~200 */
1491                 break;
1492         case bulk_latency:
1493                 new_itr = 8000;
1494                 break;
1495         default:
1496                 break;
1497         }
1498
1499         if (new_itr != q_vector->eitr) {
1500                 u32 itr_reg;
1501
1502                 /* save the algorithm value here, not the smoothed one */
1503                 q_vector->eitr = new_itr;
1504                 /* do an exponential smoothing */
1505                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1506                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1507                 ixgbe_write_eitr(adapter, 0, itr_reg);
1508         }
1509
1510         return;
1511 }
1512
1513 /**
1514  * ixgbe_irq_enable - Enable default interrupt generation settings
1515  * @adapter: board private structure
1516  **/
1517 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1518 {
1519         u32 mask;
1520
1521         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1522         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1523                 mask |= IXGBE_EIMS_GPI_SDP1;
1524         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1525                 mask |= IXGBE_EIMS_ECC;
1526                 mask |= IXGBE_EIMS_GPI_SDP1;
1527                 mask |= IXGBE_EIMS_GPI_SDP2;
1528         }
1529
1530         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1531         ixgbe_irq_enable_queues(adapter, ~0);
1532         IXGBE_WRITE_FLUSH(&adapter->hw);
1533 }
1534
1535 /**
1536  * ixgbe_intr - legacy mode Interrupt Handler
1537  * @irq: interrupt number
1538  * @data: pointer to a network interface device structure
1539  **/
1540 static irqreturn_t ixgbe_intr(int irq, void *data)
1541 {
1542         struct net_device *netdev = data;
1543         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1544         struct ixgbe_hw *hw = &adapter->hw;
1545         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1546         u32 eicr;
1547
1548         /*
1549          * Workaround for silicon errata.  Mask the interrupts
1550          * before the read of EICR.
1551          */
1552         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1553
1554         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1555          * therefore no explict interrupt disable is necessary */
1556         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1557         if (!eicr) {
1558                 /* shared interrupt alert!
1559                  * make sure interrupts are enabled because the read will
1560                  * have disabled interrupts due to EIAM */
1561                 ixgbe_irq_enable(adapter);
1562                 return IRQ_NONE;        /* Not our interrupt */
1563         }
1564
1565         if (eicr & IXGBE_EICR_LSC)
1566                 ixgbe_check_lsc(adapter);
1567
1568         if (hw->mac.type == ixgbe_mac_82599EB)
1569                 ixgbe_check_sfp_event(adapter, eicr);
1570
1571         ixgbe_check_fan_failure(adapter, eicr);
1572
1573         if (napi_schedule_prep(&(q_vector->napi))) {
1574                 adapter->tx_ring[0].total_packets = 0;
1575                 adapter->tx_ring[0].total_bytes = 0;
1576                 adapter->rx_ring[0].total_packets = 0;
1577                 adapter->rx_ring[0].total_bytes = 0;
1578                 /* would disable interrupts here but EIAM disabled it */
1579                 __napi_schedule(&(q_vector->napi));
1580         }
1581
1582         return IRQ_HANDLED;
1583 }
1584
1585 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1586 {
1587         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1588
1589         for (i = 0; i < q_vectors; i++) {
1590                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1591                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1592                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1593                 q_vector->rxr_count = 0;
1594                 q_vector->txr_count = 0;
1595         }
1596 }
1597
1598 /**
1599  * ixgbe_request_irq - initialize interrupts
1600  * @adapter: board private structure
1601  *
1602  * Attempts to configure interrupts using the best available
1603  * capabilities of the hardware and kernel.
1604  **/
1605 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1606 {
1607         struct net_device *netdev = adapter->netdev;
1608         int err;
1609
1610         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1611                 err = ixgbe_request_msix_irqs(adapter);
1612         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1613                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1614                                   netdev->name, netdev);
1615         } else {
1616                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1617                                   netdev->name, netdev);
1618         }
1619
1620         if (err)
1621                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1622
1623         return err;
1624 }
1625
1626 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1627 {
1628         struct net_device *netdev = adapter->netdev;
1629
1630         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1631                 int i, q_vectors;
1632
1633                 q_vectors = adapter->num_msix_vectors;
1634
1635                 i = q_vectors - 1;
1636                 free_irq(adapter->msix_entries[i].vector, netdev);
1637
1638                 i--;
1639                 for (; i >= 0; i--) {
1640                         free_irq(adapter->msix_entries[i].vector,
1641                                  adapter->q_vector[i]);
1642                 }
1643
1644                 ixgbe_reset_q_vectors(adapter);
1645         } else {
1646                 free_irq(adapter->pdev->irq, netdev);
1647         }
1648 }
1649
1650 /**
1651  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1652  * @adapter: board private structure
1653  **/
1654 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1655 {
1656         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1657                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1658         } else {
1659                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1660                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1661                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1662         }
1663         IXGBE_WRITE_FLUSH(&adapter->hw);
1664         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1665                 int i;
1666                 for (i = 0; i < adapter->num_msix_vectors; i++)
1667                         synchronize_irq(adapter->msix_entries[i].vector);
1668         } else {
1669                 synchronize_irq(adapter->pdev->irq);
1670         }
1671 }
1672
1673 /**
1674  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1675  *
1676  **/
1677 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1682                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1683
1684         ixgbe_set_ivar(adapter, 0, 0, 0);
1685         ixgbe_set_ivar(adapter, 1, 0, 0);
1686
1687         map_vector_to_rxq(adapter, 0, 0);
1688         map_vector_to_txq(adapter, 0, 0);
1689
1690         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1691 }
1692
1693 /**
1694  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1695  * @adapter: board private structure
1696  *
1697  * Configure the Tx unit of the MAC after a reset.
1698  **/
1699 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1700 {
1701         u64 tdba;
1702         struct ixgbe_hw *hw = &adapter->hw;
1703         u32 i, j, tdlen, txctrl;
1704
1705         /* Setup the HW Tx Head and Tail descriptor pointers */
1706         for (i = 0; i < adapter->num_tx_queues; i++) {
1707                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1708                 j = ring->reg_idx;
1709                 tdba = ring->dma;
1710                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1711                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1712                                 (tdba & DMA_BIT_MASK(32)));
1713                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1714                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1715                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1716                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1717                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1718                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1719                 /* Disable Tx Head Writeback RO bit, since this hoses
1720                  * bookkeeping if things aren't delivered in order.
1721                  */
1722                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1723                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1724                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1725         }
1726         if (hw->mac.type == ixgbe_mac_82599EB) {
1727                 /* We enable 8 traffic classes, DCB only */
1728                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1729                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1730                                         IXGBE_MTQC_8TC_8TQ));
1731         }
1732 }
1733
1734 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1735
1736 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1737 {
1738         struct ixgbe_ring *rx_ring;
1739         u32 srrctl;
1740         int queue0 = 0;
1741         unsigned long mask;
1742
1743         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1744                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1745                         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1746                         if (dcb_i == 8)
1747                                 queue0 = index >> 4;
1748                         else if (dcb_i == 4)
1749                                 queue0 = index >> 5;
1750                         else
1751                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1752                                         "configuration\n");
1753                 } else {
1754                         queue0 = index;
1755                 }
1756         } else {
1757                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1758                 queue0 = index & mask;
1759                 index = index & mask;
1760         }
1761
1762         rx_ring = &adapter->rx_ring[queue0];
1763
1764         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1765
1766         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1767         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1768
1769         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1770                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1771
1772         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1773 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1774                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1775 #else
1776                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1777 #endif
1778                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1779         } else {
1780                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1781                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1782                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1783         }
1784
1785         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1786 }
1787
1788 /**
1789  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1790  * @adapter: board private structure
1791  *
1792  * Configure the Rx unit of the MAC after a reset.
1793  **/
1794 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1795 {
1796         u64 rdba;
1797         struct ixgbe_hw *hw = &adapter->hw;
1798         struct net_device *netdev = adapter->netdev;
1799         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1800         int i, j;
1801         u32 rdlen, rxctrl, rxcsum;
1802         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1803                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1804                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1805         u32 fctrl, hlreg0;
1806         u32 reta = 0, mrqc = 0;
1807         u32 rdrxctl;
1808         u32 rscctrl;
1809         int rx_buf_len;
1810
1811         /* Decide whether to use packet split mode or not */
1812         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1813
1814 #ifdef IXGBE_FCOE
1815         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1816                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1817 #endif /* IXGBE_FCOE */
1818
1819         /* Set the RX buffer length according to the mode */
1820         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1821                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1822                 if (hw->mac.type == ixgbe_mac_82599EB) {
1823                         /* PSRTYPE must be initialized in 82599 */
1824                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1825                                       IXGBE_PSRTYPE_UDPHDR |
1826                                       IXGBE_PSRTYPE_IPV4HDR |
1827                                       IXGBE_PSRTYPE_IPV6HDR |
1828                                       IXGBE_PSRTYPE_L2HDR;
1829                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1830                 }
1831         } else {
1832                 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1833                     (netdev->mtu <= ETH_DATA_LEN))
1834                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1835                 else
1836                         rx_buf_len = ALIGN(max_frame, 1024);
1837         }
1838
1839         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1840         fctrl |= IXGBE_FCTRL_BAM;
1841         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1842         fctrl |= IXGBE_FCTRL_PMCF;
1843         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1844
1845         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1846         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1847                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1848         else
1849                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1850         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1851
1852         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1853         /* disable receives while setting up the descriptors */
1854         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1855         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1856
1857         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1858          * the Base and Length of the Rx Descriptor Ring */
1859         for (i = 0; i < adapter->num_rx_queues; i++) {
1860                 rdba = adapter->rx_ring[i].dma;
1861                 j = adapter->rx_ring[i].reg_idx;
1862                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1863                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1864                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1865                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1866                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1867                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1868                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1869                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1870
1871                 ixgbe_configure_srrctl(adapter, j);
1872         }
1873
1874         if (hw->mac.type == ixgbe_mac_82598EB) {
1875                 /*
1876                  * For VMDq support of different descriptor types or
1877                  * buffer sizes through the use of multiple SRRCTL
1878                  * registers, RDRXCTL.MVMEN must be set to 1
1879                  *
1880                  * also, the manual doesn't mention it clearly but DCA hints
1881                  * will only use queue 0's tags unless this bit is set.  Side
1882                  * effects of setting this bit are only that SRRCTL must be
1883                  * fully programmed [0..15]
1884                  */
1885                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1886                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1887                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1888         }
1889
1890         /* Program MRQC for the distribution of queues */
1891         if (hw->mac.type == ixgbe_mac_82599EB) {
1892                 int mask = adapter->flags & (
1893                                 IXGBE_FLAG_RSS_ENABLED
1894                                 | IXGBE_FLAG_DCB_ENABLED
1895                                 );
1896
1897                 switch (mask) {
1898                 case (IXGBE_FLAG_RSS_ENABLED):
1899                         mrqc = IXGBE_MRQC_RSSEN;
1900                         break;
1901                 case (IXGBE_FLAG_DCB_ENABLED):
1902                         mrqc = IXGBE_MRQC_RT8TCEN;
1903                         break;
1904                 default:
1905                         break;
1906                 }
1907         }
1908         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1909                 /* Fill out redirection table */
1910                 for (i = 0, j = 0; i < 128; i++, j++) {
1911                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1912                                 j = 0;
1913                         /* reta = 4-byte sliding window of
1914                          * 0x00..(indices-1)(indices-1)00..etc. */
1915                         reta = (reta << 8) | (j * 0x11);
1916                         if ((i & 3) == 3)
1917                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1918                 }
1919
1920                 /* Fill out hash function seeds */
1921                 for (i = 0; i < 10; i++)
1922                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1923
1924                 if (hw->mac.type == ixgbe_mac_82598EB)
1925                         mrqc |= IXGBE_MRQC_RSSEN;
1926                     /* Perform hash on these packet types */
1927                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1928                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1929                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1930                       | IXGBE_MRQC_RSS_FIELD_IPV6
1931                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1932                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1933         }
1934         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1935
1936         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1937
1938         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1939             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1940                 /* Disable indicating checksum in descriptor, enables
1941                  * RSS hash */
1942                 rxcsum |= IXGBE_RXCSUM_PCSD;
1943         }
1944         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1945                 /* Enable IPv4 payload checksum for UDP fragments
1946                  * if PCSD is not set */
1947                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1948         }
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1951
1952         if (hw->mac.type == ixgbe_mac_82599EB) {
1953                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1954                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1955                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
1956                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1957         }
1958
1959         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1960                 /* Enable 82599 HW-RSC */
1961                 for (i = 0; i < adapter->num_rx_queues; i++) {
1962                         j = adapter->rx_ring[i].reg_idx;
1963                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1964                         rscctrl |= IXGBE_RSCCTL_RSCEN;
1965                         /*
1966                          *  if packet split is enabled we can only support up
1967                          *  to max frags + 1 descriptors.
1968                          */
1969                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1970 #if (MAX_SKB_FRAGS < 3)
1971                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1972 #elif (MAX_SKB_FRAGS < 7)
1973                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1974 #elif (MAX_SKB_FRAGS < 15)
1975                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1976 #else
1977                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1978 #endif
1979                         else
1980                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1981                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1982                 }
1983                 /* Disable RSC for ACK packets */
1984                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1985                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1986         }
1987 }
1988
1989 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1990 {
1991         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1992         struct ixgbe_hw *hw = &adapter->hw;
1993
1994         /* add VID to filter table */
1995         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1996 }
1997
1998 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1999 {
2000         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2001         struct ixgbe_hw *hw = &adapter->hw;
2002
2003         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2004                 ixgbe_irq_disable(adapter);
2005
2006         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2007
2008         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2009                 ixgbe_irq_enable(adapter);
2010
2011         /* remove VID from filter table */
2012         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2013 }
2014
2015 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2016                                    struct vlan_group *grp)
2017 {
2018         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2019         u32 ctrl;
2020         int i, j;
2021
2022         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2023                 ixgbe_irq_disable(adapter);
2024         adapter->vlgrp = grp;
2025
2026         /*
2027          * For a DCB driver, always enable VLAN tag stripping so we can
2028          * still receive traffic from a DCB-enabled host even if we're
2029          * not in DCB mode.
2030          */
2031         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2032         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2033                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2034                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2035                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2036         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2037                 ctrl |= IXGBE_VLNCTRL_VFE;
2038                 /* enable VLAN tag insert/strip */
2039                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2040                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2041                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2042                 for (i = 0; i < adapter->num_rx_queues; i++) {
2043                         j = adapter->rx_ring[i].reg_idx;
2044                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2045                         ctrl |= IXGBE_RXDCTL_VME;
2046                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2047                 }
2048         }
2049         ixgbe_vlan_rx_add_vid(netdev, 0);
2050
2051         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2052                 ixgbe_irq_enable(adapter);
2053 }
2054
2055 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2056 {
2057         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2058
2059         if (adapter->vlgrp) {
2060                 u16 vid;
2061                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2062                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2063                                 continue;
2064                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2065                 }
2066         }
2067 }
2068
2069 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2070 {
2071         struct dev_mc_list *mc_ptr;
2072         u8 *addr = *mc_addr_ptr;
2073         *vmdq = 0;
2074
2075         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2076         if (mc_ptr->next)
2077                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2078         else
2079                 *mc_addr_ptr = NULL;
2080
2081         return addr;
2082 }
2083
2084 /**
2085  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2086  * @netdev: network interface device structure
2087  *
2088  * The set_rx_method entry point is called whenever the unicast/multicast
2089  * address list or the network interface flags are updated.  This routine is
2090  * responsible for configuring the hardware for proper unicast, multicast and
2091  * promiscuous mode.
2092  **/
2093 static void ixgbe_set_rx_mode(struct net_device *netdev)
2094 {
2095         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2096         struct ixgbe_hw *hw = &adapter->hw;
2097         u32 fctrl, vlnctrl;
2098         u8 *addr_list = NULL;
2099         int addr_count = 0;
2100
2101         /* Check for Promiscuous and All Multicast modes */
2102
2103         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2104         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105
2106         if (netdev->flags & IFF_PROMISC) {
2107                 hw->addr_ctrl.user_set_promisc = 1;
2108                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2109                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2110         } else {
2111                 if (netdev->flags & IFF_ALLMULTI) {
2112                         fctrl |= IXGBE_FCTRL_MPE;
2113                         fctrl &= ~IXGBE_FCTRL_UPE;
2114                 } else {
2115                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2116                 }
2117                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2118                 hw->addr_ctrl.user_set_promisc = 0;
2119         }
2120
2121         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2122         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2123
2124         /* reprogram secondary unicast list */
2125         addr_count = netdev->uc_count;
2126         if (addr_count)
2127                 addr_list = netdev->uc_list->dmi_addr;
2128         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2129                                           ixgbe_addr_list_itr);
2130
2131         /* reprogram multicast list */
2132         addr_count = netdev->mc_count;
2133         if (addr_count)
2134                 addr_list = netdev->mc_list->dmi_addr;
2135         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2136                                         ixgbe_addr_list_itr);
2137 }
2138
2139 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2140 {
2141         int q_idx;
2142         struct ixgbe_q_vector *q_vector;
2143         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2144
2145         /* legacy and MSI only use one vector */
2146         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2147                 q_vectors = 1;
2148
2149         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2150                 struct napi_struct *napi;
2151                 q_vector = adapter->q_vector[q_idx];
2152                 if (!q_vector->rxr_count)
2153                         continue;
2154                 napi = &q_vector->napi;
2155                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2156                     (q_vector->rxr_count > 1))
2157                         napi->poll = &ixgbe_clean_rxonly_many;
2158
2159                 napi_enable(napi);
2160         }
2161 }
2162
2163 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2164 {
2165         int q_idx;
2166         struct ixgbe_q_vector *q_vector;
2167         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2168
2169         /* legacy and MSI only use one vector */
2170         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2171                 q_vectors = 1;
2172
2173         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2174                 q_vector = adapter->q_vector[q_idx];
2175                 if (!q_vector->rxr_count)
2176                         continue;
2177                 napi_disable(&q_vector->napi);
2178         }
2179 }
2180
2181 #ifdef CONFIG_IXGBE_DCB
2182 /*
2183  * ixgbe_configure_dcb - Configure DCB hardware
2184  * @adapter: ixgbe adapter struct
2185  *
2186  * This is called by the driver on open to configure the DCB hardware.
2187  * This is also called by the gennetlink interface when reconfiguring
2188  * the DCB state.
2189  */
2190 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2191 {
2192         struct ixgbe_hw *hw = &adapter->hw;
2193         u32 txdctl, vlnctrl;
2194         int i, j;
2195
2196         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2197         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2198         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2199
2200         /* reconfigure the hardware */
2201         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2202
2203         for (i = 0; i < adapter->num_tx_queues; i++) {
2204                 j = adapter->tx_ring[i].reg_idx;
2205                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2206                 /* PThresh workaround for Tx hang with DFP enabled. */
2207                 txdctl |= 32;
2208                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2209         }
2210         /* Enable VLAN tag insert/strip */
2211         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2212         if (hw->mac.type == ixgbe_mac_82598EB) {
2213                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2214                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2215                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2216         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2217                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2218                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2219                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2220                 for (i = 0; i < adapter->num_rx_queues; i++) {
2221                         j = adapter->rx_ring[i].reg_idx;
2222                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2223                         vlnctrl |= IXGBE_RXDCTL_VME;
2224                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2225                 }
2226         }
2227         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2228 }
2229
2230 #endif
2231 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2232 {
2233         struct net_device *netdev = adapter->netdev;
2234         int i;
2235
2236         ixgbe_set_rx_mode(netdev);
2237
2238         ixgbe_restore_vlan(adapter);
2239 #ifdef CONFIG_IXGBE_DCB
2240         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2241                 netif_set_gso_max_size(netdev, 32768);
2242                 ixgbe_configure_dcb(adapter);
2243         } else {
2244                 netif_set_gso_max_size(netdev, 65536);
2245         }
2246 #else
2247         netif_set_gso_max_size(netdev, 65536);
2248 #endif
2249
2250 #ifdef IXGBE_FCOE
2251         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2252                 ixgbe_configure_fcoe(adapter);
2253
2254 #endif /* IXGBE_FCOE */
2255         ixgbe_configure_tx(adapter);
2256         ixgbe_configure_rx(adapter);
2257         for (i = 0; i < adapter->num_rx_queues; i++)
2258                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2259                                        (adapter->rx_ring[i].count - 1));
2260 }
2261
2262 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2263 {
2264         switch (hw->phy.type) {
2265         case ixgbe_phy_sfp_avago:
2266         case ixgbe_phy_sfp_ftl:
2267         case ixgbe_phy_sfp_intel:
2268         case ixgbe_phy_sfp_unknown:
2269         case ixgbe_phy_tw_tyco:
2270         case ixgbe_phy_tw_unknown:
2271                 return true;
2272         default:
2273                 return false;
2274         }
2275 }
2276
2277 /**
2278  * ixgbe_sfp_link_config - set up SFP+ link
2279  * @adapter: pointer to private adapter struct
2280  **/
2281 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2282 {
2283         struct ixgbe_hw *hw = &adapter->hw;
2284
2285                 if (hw->phy.multispeed_fiber) {
2286                         /*
2287                          * In multispeed fiber setups, the device may not have
2288                          * had a physical connection when the driver loaded.
2289                          * If that's the case, the initial link configuration
2290                          * couldn't get the MAC into 10G or 1G mode, so we'll
2291                          * never have a link status change interrupt fire.
2292                          * We need to try and force an autonegotiation
2293                          * session, then bring up link.
2294                          */
2295                         hw->mac.ops.setup_sfp(hw);
2296                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2297                                 schedule_work(&adapter->multispeed_fiber_task);
2298                 } else {
2299                         /*
2300                          * Direct Attach Cu and non-multispeed fiber modules
2301                          * still need to be configured properly prior to
2302                          * attempting link.
2303                          */
2304                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2305                                 schedule_work(&adapter->sfp_config_module_task);
2306                 }
2307 }
2308
2309 /**
2310  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2311  * @hw: pointer to private hardware struct
2312  *
2313  * Returns 0 on success, negative on failure
2314  **/
2315 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2316 {
2317         u32 autoneg;
2318         bool link_up = false;
2319         u32 ret = IXGBE_ERR_LINK_SETUP;
2320
2321         if (hw->mac.ops.check_link)
2322                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2323
2324         if (ret)
2325                 goto link_cfg_out;
2326
2327         if (hw->mac.ops.get_link_capabilities)
2328                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2329                                                         &hw->mac.autoneg);
2330         if (ret)
2331                 goto link_cfg_out;
2332
2333         if (hw->mac.ops.setup_link_speed)
2334                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2335 link_cfg_out:
2336         return ret;
2337 }
2338
2339 #define IXGBE_MAX_RX_DESC_POLL 10
2340 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2341                                               int rxr)
2342 {
2343         int j = adapter->rx_ring[rxr].reg_idx;
2344         int k;
2345
2346         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2347                 if (IXGBE_READ_REG(&adapter->hw,
2348                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2349                         break;
2350                 else
2351                         msleep(1);
2352         }
2353         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2354                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2355                         "not set within the polling period\n", rxr);
2356         }
2357         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2358                               (adapter->rx_ring[rxr].count - 1));
2359 }
2360
2361 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2362 {
2363         struct net_device *netdev = adapter->netdev;
2364         struct ixgbe_hw *hw = &adapter->hw;
2365         int i, j = 0;
2366         int num_rx_rings = adapter->num_rx_queues;
2367         int err;
2368         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2369         u32 txdctl, rxdctl, mhadd;
2370         u32 dmatxctl;
2371         u32 gpie;
2372
2373         ixgbe_get_hw_control(adapter);
2374
2375         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2376             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2377                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2378                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2379                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2380                 } else {
2381                         /* MSI only */
2382                         gpie = 0;
2383                 }
2384                 /* XXX: to interrupt immediately for EICS writes, enable this */
2385                 /* gpie |= IXGBE_GPIE_EIMEN; */
2386                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2387         }
2388
2389         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2390                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2391                  * specifically only auto mask tx and rx interrupts */
2392                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2393         }
2394
2395         /* Enable fan failure interrupt if media type is copper */
2396         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2397                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2398                 gpie |= IXGBE_SDP1_GPIEN;
2399                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2400         }
2401
2402         if (hw->mac.type == ixgbe_mac_82599EB) {
2403                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2404                 gpie |= IXGBE_SDP1_GPIEN;
2405                 gpie |= IXGBE_SDP2_GPIEN;
2406                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407         }
2408
2409         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2410         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2411                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2412                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2413
2414                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2415         }
2416
2417         for (i = 0; i < adapter->num_tx_queues; i++) {
2418                 j = adapter->tx_ring[i].reg_idx;
2419                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2420                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2421                 txdctl |= (8 << 16);
2422                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2423         }
2424
2425         if (hw->mac.type == ixgbe_mac_82599EB) {
2426                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2427                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2428                 dmatxctl |= IXGBE_DMATXCTL_TE;
2429                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2430         }
2431         for (i = 0; i < adapter->num_tx_queues; i++) {
2432                 j = adapter->tx_ring[i].reg_idx;
2433                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2434                 txdctl |= IXGBE_TXDCTL_ENABLE;
2435                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2436         }
2437
2438         for (i = 0; i < num_rx_rings; i++) {
2439                 j = adapter->rx_ring[i].reg_idx;
2440                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2441                 /* enable PTHRESH=32 descriptors (half the internal cache)
2442                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2443                  * this also removes a pesky rx_no_buffer_count increment */
2444                 rxdctl |= 0x0020;
2445                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2446                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2447                 if (hw->mac.type == ixgbe_mac_82599EB)
2448                         ixgbe_rx_desc_queue_enable(adapter, i);
2449         }
2450         /* enable all receives */
2451         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2452         if (hw->mac.type == ixgbe_mac_82598EB)
2453                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2454         else
2455                 rxdctl |= IXGBE_RXCTRL_RXEN;
2456         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2457
2458         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2459                 ixgbe_configure_msix(adapter);
2460         else
2461                 ixgbe_configure_msi_and_legacy(adapter);
2462
2463         clear_bit(__IXGBE_DOWN, &adapter->state);
2464         ixgbe_napi_enable_all(adapter);
2465
2466         /* clear any pending interrupts, may auto mask */
2467         IXGBE_READ_REG(hw, IXGBE_EICR);
2468
2469         ixgbe_irq_enable(adapter);
2470
2471         /*
2472          * If this adapter has a fan, check to see if we had a failure
2473          * before we enabled the interrupt.
2474          */
2475         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2476                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2477                 if (esdp & IXGBE_ESDP_SDP1)
2478                         DPRINTK(DRV, CRIT,
2479                                 "Fan has stopped, replace the adapter\n");
2480         }
2481
2482         /*
2483          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2484          * arrived before interrupts were enabled.  We need to kick off
2485          * the SFP+ module setup first, then try to bring up link.
2486          * If we're not hot-pluggable SFP+, we just need to configure link
2487          * and bring it up.
2488          */
2489         err = hw->phy.ops.identify(hw);
2490         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2491                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2492                 ixgbe_down(adapter);
2493                 return err;
2494         }
2495
2496         if (ixgbe_is_sfp(hw)) {
2497                 ixgbe_sfp_link_config(adapter);
2498         } else {
2499                 err = ixgbe_non_sfp_link_config(hw);
2500                 if (err)
2501                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2502         }
2503
2504         /* enable transmits */
2505         netif_tx_start_all_queues(netdev);
2506
2507         /* bring the link up in the watchdog, this could race with our first
2508          * link up interrupt but shouldn't be a problem */
2509         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2510         adapter->link_check_timeout = jiffies;
2511         mod_timer(&adapter->watchdog_timer, jiffies);
2512         return 0;
2513 }
2514
2515 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2516 {
2517         WARN_ON(in_interrupt());
2518         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2519                 msleep(1);
2520         ixgbe_down(adapter);
2521         ixgbe_up(adapter);
2522         clear_bit(__IXGBE_RESETTING, &adapter->state);
2523 }
2524
2525 int ixgbe_up(struct ixgbe_adapter *adapter)
2526 {
2527         /* hardware has been reset, we need to reload some things */
2528         ixgbe_configure(adapter);
2529
2530         return ixgbe_up_complete(adapter);
2531 }
2532
2533 void ixgbe_reset(struct ixgbe_adapter *adapter)
2534 {
2535         struct ixgbe_hw *hw = &adapter->hw;
2536         if (hw->mac.ops.init_hw(hw))
2537                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2538
2539         /* reprogram the RAR[0] in case user changed it. */
2540         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2541
2542 }
2543
2544 /**
2545  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2546  * @adapter: board private structure
2547  * @rx_ring: ring to free buffers from
2548  **/
2549 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2550                                 struct ixgbe_ring *rx_ring)
2551 {
2552         struct pci_dev *pdev = adapter->pdev;
2553         unsigned long size;
2554         unsigned int i;
2555
2556         /* Free all the Rx ring sk_buffs */
2557
2558         for (i = 0; i < rx_ring->count; i++) {
2559                 struct ixgbe_rx_buffer *rx_buffer_info;
2560
2561                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2562                 if (rx_buffer_info->dma) {
2563                         pci_unmap_single(pdev, rx_buffer_info->dma,
2564                                          rx_ring->rx_buf_len,
2565                                          PCI_DMA_FROMDEVICE);
2566                         rx_buffer_info->dma = 0;
2567                 }
2568                 if (rx_buffer_info->skb) {
2569                         struct sk_buff *skb = rx_buffer_info->skb;
2570                         rx_buffer_info->skb = NULL;
2571                         do {
2572                                 struct sk_buff *this = skb;
2573                                 skb = skb->prev;
2574                                 dev_kfree_skb(this);
2575                         } while (skb);
2576                 }
2577                 if (!rx_buffer_info->page)
2578                         continue;
2579                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2580                                PCI_DMA_FROMDEVICE);
2581                 rx_buffer_info->page_dma = 0;
2582                 put_page(rx_buffer_info->page);
2583                 rx_buffer_info->page = NULL;
2584                 rx_buffer_info->page_offset = 0;
2585         }
2586
2587         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2588         memset(rx_ring->rx_buffer_info, 0, size);
2589
2590         /* Zero out the descriptor ring */
2591         memset(rx_ring->desc, 0, rx_ring->size);
2592
2593         rx_ring->next_to_clean = 0;
2594         rx_ring->next_to_use = 0;
2595
2596         if (rx_ring->head)
2597                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2598         if (rx_ring->tail)
2599                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2600 }
2601
2602 /**
2603  * ixgbe_clean_tx_ring - Free Tx Buffers
2604  * @adapter: board private structure
2605  * @tx_ring: ring to be cleaned
2606  **/
2607 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2608                                 struct ixgbe_ring *tx_ring)
2609 {
2610         struct ixgbe_tx_buffer *tx_buffer_info;
2611         unsigned long size;
2612         unsigned int i;
2613
2614         /* Free all the Tx ring sk_buffs */
2615
2616         for (i = 0; i < tx_ring->count; i++) {
2617                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2618                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2619         }
2620
2621         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2622         memset(tx_ring->tx_buffer_info, 0, size);
2623
2624         /* Zero out the descriptor ring */
2625         memset(tx_ring->desc, 0, tx_ring->size);
2626
2627         tx_ring->next_to_use = 0;
2628         tx_ring->next_to_clean = 0;
2629
2630         if (tx_ring->head)
2631                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2632         if (tx_ring->tail)
2633                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2634 }
2635
2636 /**
2637  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2638  * @adapter: board private structure
2639  **/
2640 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2641 {
2642         int i;
2643
2644         for (i = 0; i < adapter->num_rx_queues; i++)
2645                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2646 }
2647
2648 /**
2649  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2650  * @adapter: board private structure
2651  **/
2652 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2653 {
2654         int i;
2655
2656         for (i = 0; i < adapter->num_tx_queues; i++)
2657                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2658 }
2659
2660 void ixgbe_down(struct ixgbe_adapter *adapter)
2661 {
2662         struct net_device *netdev = adapter->netdev;
2663         struct ixgbe_hw *hw = &adapter->hw;
2664         u32 rxctrl;
2665         u32 txdctl;
2666         int i, j;
2667
2668         /* signal that we are down to the interrupt handler */
2669         set_bit(__IXGBE_DOWN, &adapter->state);
2670
2671         /* disable receives */
2672         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2673         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2674
2675         netif_tx_disable(netdev);
2676
2677         IXGBE_WRITE_FLUSH(hw);
2678         msleep(10);
2679
2680         netif_tx_stop_all_queues(netdev);
2681
2682         ixgbe_irq_disable(adapter);
2683
2684         ixgbe_napi_disable_all(adapter);
2685
2686         del_timer_sync(&adapter->watchdog_timer);
2687         cancel_work_sync(&adapter->watchdog_task);
2688
2689         /* disable transmits in the hardware now that interrupts are off */
2690         for (i = 0; i < adapter->num_tx_queues; i++) {
2691                 j = adapter->tx_ring[i].reg_idx;
2692                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2693                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2694                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2695         }
2696         /* Disable the Tx DMA engine on 82599 */
2697         if (hw->mac.type == ixgbe_mac_82599EB)
2698                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2699                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2700                                  ~IXGBE_DMATXCTL_TE));
2701
2702         netif_carrier_off(netdev);
2703
2704 #ifdef CONFIG_IXGBE_DCA
2705         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2706                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2707                 dca_remove_requester(&adapter->pdev->dev);
2708         }
2709
2710 #endif
2711         if (!pci_channel_offline(adapter->pdev))
2712                 ixgbe_reset(adapter);
2713         ixgbe_clean_all_tx_rings(adapter);
2714         ixgbe_clean_all_rx_rings(adapter);
2715
2716 #ifdef CONFIG_IXGBE_DCA
2717         /* since we reset the hardware DCA settings were cleared */
2718         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2719                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2720                 /* always use CB2 mode, difference is masked
2721                  * in the CB driver */
2722                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2723                 ixgbe_setup_dca(adapter);
2724         }
2725 #endif
2726 }
2727
2728 /**
2729  * ixgbe_poll - NAPI Rx polling callback
2730  * @napi: structure for representing this polling device
2731  * @budget: how many packets driver is allowed to clean
2732  *
2733  * This function is used for legacy and MSI, NAPI mode
2734  **/
2735 static int ixgbe_poll(struct napi_struct *napi, int budget)
2736 {
2737         struct ixgbe_q_vector *q_vector =
2738                                 container_of(napi, struct ixgbe_q_vector, napi);
2739         struct ixgbe_adapter *adapter = q_vector->adapter;
2740         int tx_clean_complete, work_done = 0;
2741
2742 #ifdef CONFIG_IXGBE_DCA
2743         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2744                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2745                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2746         }
2747 #endif
2748
2749         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2750         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2751
2752         if (!tx_clean_complete)
2753                 work_done = budget;
2754
2755         /* If budget not fully consumed, exit the polling mode */
2756         if (work_done < budget) {
2757                 napi_complete(napi);
2758                 if (adapter->itr_setting & 1)
2759                         ixgbe_set_itr(adapter);
2760                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2761                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2762         }
2763         return work_done;
2764 }
2765
2766 /**
2767  * ixgbe_tx_timeout - Respond to a Tx Hang
2768  * @netdev: network interface device structure
2769  **/
2770 static void ixgbe_tx_timeout(struct net_device *netdev)
2771 {
2772         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2773
2774         /* Do the reset outside of interrupt context */
2775         schedule_work(&adapter->reset_task);
2776 }
2777
2778 static void ixgbe_reset_task(struct work_struct *work)
2779 {
2780         struct ixgbe_adapter *adapter;
2781         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2782
2783         /* If we're already down or resetting, just bail */
2784         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2785             test_bit(__IXGBE_RESETTING, &adapter->state))
2786                 return;
2787
2788         adapter->tx_timeout_count++;
2789
2790         ixgbe_reinit_locked(adapter);
2791 }
2792
2793 #ifdef CONFIG_IXGBE_DCB
2794 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2795 {
2796         bool ret = false;
2797
2798         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2799                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2800                 adapter->num_rx_queues =
2801                                       adapter->ring_feature[RING_F_DCB].indices;
2802                 adapter->num_tx_queues =
2803                                       adapter->ring_feature[RING_F_DCB].indices;
2804                 ret = true;
2805         } else {
2806                 ret = false;
2807         }
2808
2809         return ret;
2810 }
2811 #endif
2812
2813 /**
2814  * ixgbe_set_rss_queues: Allocate queues for RSS
2815  * @adapter: board private structure to initialize
2816  *
2817  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2818  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2819  *
2820  **/
2821 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2822 {
2823         bool ret = false;
2824
2825         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2826                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2827                 adapter->num_rx_queues =
2828                                       adapter->ring_feature[RING_F_RSS].indices;
2829                 adapter->num_tx_queues =
2830                                       adapter->ring_feature[RING_F_RSS].indices;
2831                 ret = true;
2832         } else {
2833                 ret = false;
2834         }
2835
2836         return ret;
2837 }
2838
2839 /*
2840  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2841  * @adapter: board private structure to initialize
2842  *
2843  * This is the top level queue allocation routine.  The order here is very
2844  * important, starting with the "most" number of features turned on at once,
2845  * and ending with the smallest set of features.  This way large combinations
2846  * can be allocated if they're turned on, and smaller combinations are the
2847  * fallthrough conditions.
2848  *
2849  **/
2850 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2851 {
2852 #ifdef CONFIG_IXGBE_DCB
2853         if (ixgbe_set_dcb_queues(adapter))
2854                 goto done;
2855
2856 #endif
2857         if (ixgbe_set_rss_queues(adapter))
2858                 goto done;
2859
2860         /* fallback to base case */
2861         adapter->num_rx_queues = 1;
2862         adapter->num_tx_queues = 1;
2863
2864 done:
2865         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2866         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2867 }
2868
2869 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2870                                        int vectors)
2871 {
2872         int err, vector_threshold;
2873
2874         /* We'll want at least 3 (vector_threshold):
2875          * 1) TxQ[0] Cleanup
2876          * 2) RxQ[0] Cleanup
2877          * 3) Other (Link Status Change, etc.)
2878          * 4) TCP Timer (optional)
2879          */
2880         vector_threshold = MIN_MSIX_COUNT;
2881
2882         /* The more we get, the more we will assign to Tx/Rx Cleanup
2883          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2884          * Right now, we simply care about how many we'll get; we'll
2885          * set them up later while requesting irq's.
2886          */
2887         while (vectors >= vector_threshold) {
2888                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2889                                       vectors);
2890                 if (!err) /* Success in acquiring all requested vectors. */
2891                         break;
2892                 else if (err < 0)
2893                         vectors = 0; /* Nasty failure, quit now */
2894                 else /* err == number of vectors we should try again with */
2895                         vectors = err;
2896         }
2897
2898         if (vectors < vector_threshold) {
2899                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2900                  * This just means we'll go with either a single MSI
2901                  * vector or fall back to legacy interrupts.
2902                  */
2903                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2904                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2905                 kfree(adapter->msix_entries);
2906                 adapter->msix_entries = NULL;
2907         } else {
2908                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2909                 /*
2910                  * Adjust for only the vectors we'll use, which is minimum
2911                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2912                  * vectors we were allocated.
2913                  */
2914                 adapter->num_msix_vectors = min(vectors,
2915                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2916         }
2917 }
2918
2919 /**
2920  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2921  * @adapter: board private structure to initialize
2922  *
2923  * Cache the descriptor ring offsets for RSS to the assigned rings.
2924  *
2925  **/
2926 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2927 {
2928         int i;
2929         bool ret = false;
2930
2931         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2932                 for (i = 0; i < adapter->num_rx_queues; i++)
2933                         adapter->rx_ring[i].reg_idx = i;
2934                 for (i = 0; i < adapter->num_tx_queues; i++)
2935                         adapter->tx_ring[i].reg_idx = i;
2936                 ret = true;
2937         } else {
2938                 ret = false;
2939         }
2940
2941         return ret;
2942 }
2943
2944 #ifdef CONFIG_IXGBE_DCB
2945 /**
2946  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2947  * @adapter: board private structure to initialize
2948  *
2949  * Cache the descriptor ring offsets for DCB to the assigned rings.
2950  *
2951  **/
2952 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2953 {
2954         int i;
2955         bool ret = false;
2956         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2957
2958         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2959                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2960                         /* the number of queues is assumed to be symmetric */
2961                         for (i = 0; i < dcb_i; i++) {
2962                                 adapter->rx_ring[i].reg_idx = i << 3;
2963                                 adapter->tx_ring[i].reg_idx = i << 2;
2964                         }
2965                         ret = true;
2966                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2967                         if (dcb_i == 8) {
2968                                 /*
2969                                  * Tx TC0 starts at: descriptor queue 0
2970                                  * Tx TC1 starts at: descriptor queue 32
2971                                  * Tx TC2 starts at: descriptor queue 64
2972                                  * Tx TC3 starts at: descriptor queue 80
2973                                  * Tx TC4 starts at: descriptor queue 96
2974                                  * Tx TC5 starts at: descriptor queue 104
2975                                  * Tx TC6 starts at: descriptor queue 112
2976                                  * Tx TC7 starts at: descriptor queue 120
2977                                  *
2978                                  * Rx TC0-TC7 are offset by 16 queues each
2979                                  */
2980                                 for (i = 0; i < 3; i++) {
2981                                         adapter->tx_ring[i].reg_idx = i << 5;
2982                                         adapter->rx_ring[i].reg_idx = i << 4;
2983                                 }
2984                                 for ( ; i < 5; i++) {
2985                                         adapter->tx_ring[i].reg_idx =
2986                                                                  ((i + 2) << 4);
2987                                         adapter->rx_ring[i].reg_idx = i << 4;
2988                                 }
2989                                 for ( ; i < dcb_i; i++) {
2990                                         adapter->tx_ring[i].reg_idx =
2991                                                                  ((i + 8) << 3);
2992                                         adapter->rx_ring[i].reg_idx = i << 4;
2993                                 }
2994
2995                                 ret = true;
2996                         } else if (dcb_i == 4) {
2997                                 /*
2998                                  * Tx TC0 starts at: descriptor queue 0
2999                                  * Tx TC1 starts at: descriptor queue 64
3000                                  * Tx TC2 starts at: descriptor queue 96
3001                                  * Tx TC3 starts at: descriptor queue 112
3002                                  *
3003                                  * Rx TC0-TC3 are offset by 32 queues each
3004                                  */
3005                                 adapter->tx_ring[0].reg_idx = 0;
3006                                 adapter->tx_ring[1].reg_idx = 64;
3007                                 adapter->tx_ring[2].reg_idx = 96;
3008                                 adapter->tx_ring[3].reg_idx = 112;
3009                                 for (i = 0 ; i < dcb_i; i++)
3010                                         adapter->rx_ring[i].reg_idx = i << 5;
3011
3012                                 ret = true;
3013                         } else {
3014                                 ret = false;
3015                         }
3016                 } else {
3017                         ret = false;
3018                 }
3019         } else {
3020                 ret = false;
3021         }
3022
3023         return ret;
3024 }
3025 #endif
3026
3027 /**
3028  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3029  * @adapter: board private structure to initialize
3030  *
3031  * Once we know the feature-set enabled for the device, we'll cache
3032  * the register offset the descriptor ring is assigned to.
3033  *
3034  * Note, the order the various feature calls is important.  It must start with
3035  * the "most" features enabled at the same time, then trickle down to the
3036  * least amount of features turned on at once.
3037  **/
3038 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3039 {
3040         /* start with default case */
3041         adapter->rx_ring[0].reg_idx = 0;
3042         adapter->tx_ring[0].reg_idx = 0;
3043
3044 #ifdef CONFIG_IXGBE_DCB
3045         if (ixgbe_cache_ring_dcb(adapter))
3046                 return;
3047
3048 #endif
3049         if (ixgbe_cache_ring_rss(adapter))
3050                 return;
3051 }
3052
3053 /**
3054  * ixgbe_alloc_queues - Allocate memory for all rings
3055  * @adapter: board private structure to initialize
3056  *
3057  * We allocate one ring per queue at run-time since we don't know the
3058  * number of queues at compile-time.  The polling_netdev array is
3059  * intended for Multiqueue, but should work fine with a single queue.
3060  **/
3061 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3062 {
3063         int i;
3064
3065         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3066                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3067         if (!adapter->tx_ring)
3068                 goto err_tx_ring_allocation;
3069
3070         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3071                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3072         if (!adapter->rx_ring)
3073                 goto err_rx_ring_allocation;
3074
3075         for (i = 0; i < adapter->num_tx_queues; i++) {
3076                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3077                 adapter->tx_ring[i].queue_index = i;
3078         }
3079
3080         for (i = 0; i < adapter->num_rx_queues; i++) {
3081                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3082                 adapter->rx_ring[i].queue_index = i;
3083         }
3084
3085         ixgbe_cache_ring_register(adapter);
3086
3087         return 0;
3088
3089 err_rx_ring_allocation:
3090         kfree(adapter->tx_ring);
3091 err_tx_ring_allocation:
3092         return -ENOMEM;
3093 }
3094
3095 /**
3096  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3097  * @adapter: board private structure to initialize
3098  *
3099  * Attempt to configure the interrupts using the best available
3100  * capabilities of the hardware and the kernel.
3101  **/
3102 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3103 {
3104         struct ixgbe_hw *hw = &adapter->hw;
3105         int err = 0;
3106         int vector, v_budget;
3107
3108         /*
3109          * It's easy to be greedy for MSI-X vectors, but it really
3110          * doesn't do us much good if we have a lot more vectors
3111          * than CPU's.  So let's be conservative and only ask for
3112          * (roughly) twice the number of vectors as there are CPU's.
3113          */
3114         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3115                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3116
3117         /*
3118          * At the same time, hardware can only support a maximum of
3119          * hw.mac->max_msix_vectors vectors.  With features
3120          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3121          * descriptor queues supported by our device.  Thus, we cap it off in
3122          * those rare cases where the cpu count also exceeds our vector limit.
3123          */
3124         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3125
3126         /* A failure in MSI-X entry allocation isn't fatal, but it does
3127          * mean we disable MSI-X capabilities of the adapter. */
3128         adapter->msix_entries = kcalloc(v_budget,
3129                                         sizeof(struct msix_entry), GFP_KERNEL);
3130         if (adapter->msix_entries) {
3131                 for (vector = 0; vector < v_budget; vector++)
3132                         adapter->msix_entries[vector].entry = vector;
3133
3134                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3135
3136                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3137                         goto out;
3138         }
3139
3140         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3141         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3142         ixgbe_set_num_queues(adapter);
3143
3144         err = pci_enable_msi(adapter->pdev);
3145         if (!err) {
3146                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3147         } else {
3148                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3149                         "falling back to legacy.  Error: %d\n", err);
3150                 /* reset err */
3151                 err = 0;
3152         }
3153
3154 out:
3155         return err;
3156 }
3157
3158 /**
3159  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3160  * @adapter: board private structure to initialize
3161  *
3162  * We allocate one q_vector per queue interrupt.  If allocation fails we
3163  * return -ENOMEM.
3164  **/
3165 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3166 {
3167         int q_idx, num_q_vectors;
3168         struct ixgbe_q_vector *q_vector;
3169         int napi_vectors;
3170         int (*poll)(struct napi_struct *, int);
3171
3172         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3173                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3174                 napi_vectors = adapter->num_rx_queues;
3175                 poll = &ixgbe_clean_rxonly;
3176         } else {
3177                 num_q_vectors = 1;
3178                 napi_vectors = 1;
3179                 poll = &ixgbe_poll;
3180         }
3181
3182         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3183                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3184                 if (!q_vector)
3185                         goto err_out;
3186                 q_vector->adapter = adapter;
3187                 q_vector->v_idx = q_idx;
3188                 q_vector->eitr = adapter->eitr_param;
3189                 if (q_idx < napi_vectors)
3190                         netif_napi_add(adapter->netdev, &q_vector->napi,
3191                                        (*poll), 64);
3192                 adapter->q_vector[q_idx] = q_vector;
3193         }
3194
3195         return 0;
3196
3197 err_out:
3198         while (q_idx) {
3199                 q_idx--;
3200                 q_vector = adapter->q_vector[q_idx];
3201                 netif_napi_del(&q_vector->napi);
3202                 kfree(q_vector);
3203                 adapter->q_vector[q_idx] = NULL;
3204         }
3205         return -ENOMEM;
3206 }
3207
3208 /**
3209  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3210  * @adapter: board private structure to initialize
3211  *
3212  * This function frees the memory allocated to the q_vectors.  In addition if
3213  * NAPI is enabled it will delete any references to the NAPI struct prior
3214  * to freeing the q_vector.
3215  **/
3216 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3217 {
3218         int q_idx, num_q_vectors;
3219         int napi_vectors;
3220
3221         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3222                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3223                 napi_vectors = adapter->num_rx_queues;
3224         } else {
3225                 num_q_vectors = 1;
3226                 napi_vectors = 1;
3227         }
3228
3229         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3230                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3231
3232                 adapter->q_vector[q_idx] = NULL;
3233                 if (q_idx < napi_vectors)
3234                         netif_napi_del(&q_vector->napi);
3235                 kfree(q_vector);
3236         }
3237 }
3238
3239 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3240 {
3241         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3242                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3243                 pci_disable_msix(adapter->pdev);
3244                 kfree(adapter->msix_entries);
3245                 adapter->msix_entries = NULL;
3246         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3247                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3248                 pci_disable_msi(adapter->pdev);
3249         }
3250         return;
3251 }
3252
3253 /**
3254  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3255  * @adapter: board private structure to initialize
3256  *
3257  * We determine which interrupt scheme to use based on...
3258  * - Kernel support (MSI, MSI-X)
3259  *   - which can be user-defined (via MODULE_PARAM)
3260  * - Hardware queue count (num_*_queues)
3261  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3262  **/
3263 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3264 {
3265         int err;
3266
3267         /* Number of supported queues */
3268         ixgbe_set_num_queues(adapter);
3269
3270         err = ixgbe_set_interrupt_capability(adapter);
3271         if (err) {
3272                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3273                 goto err_set_interrupt;
3274         }
3275
3276         err = ixgbe_alloc_q_vectors(adapter);
3277         if (err) {
3278                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3279                         "vectors\n");
3280                 goto err_alloc_q_vectors;
3281         }
3282
3283         err = ixgbe_alloc_queues(adapter);
3284         if (err) {
3285                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3286                 goto err_alloc_queues;
3287         }
3288
3289         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3290                 "Tx Queue count = %u\n",
3291                 (adapter->num_rx_queues > 1) ? "Enabled" :
3292                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3293
3294         set_bit(__IXGBE_DOWN, &adapter->state);
3295
3296         return 0;
3297
3298 err_alloc_queues:
3299         ixgbe_free_q_vectors(adapter);
3300 err_alloc_q_vectors:
3301         ixgbe_reset_interrupt_capability(adapter);
3302 err_set_interrupt:
3303         return err;
3304 }
3305
3306 /**
3307  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3308  * @adapter: board private structure to clear interrupt scheme on
3309  *
3310  * We go through and clear interrupt specific resources and reset the structure
3311  * to pre-load conditions
3312  **/
3313 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3314 {
3315         kfree(adapter->tx_ring);
3316         kfree(adapter->rx_ring);
3317         adapter->tx_ring = NULL;
3318         adapter->rx_ring = NULL;
3319
3320         ixgbe_free_q_vectors(adapter);
3321         ixgbe_reset_interrupt_capability(adapter);
3322 }
3323
3324 /**
3325  * ixgbe_sfp_timer - worker thread to find a missing module
3326  * @data: pointer to our adapter struct
3327  **/
3328 static void ixgbe_sfp_timer(unsigned long data)
3329 {
3330         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3331
3332         /*
3333          * Do the sfp_timer outside of interrupt context due to the
3334          * delays that sfp+ detection requires
3335          */
3336         schedule_work(&adapter->sfp_task);
3337 }
3338
3339 /**
3340  * ixgbe_sfp_task - worker thread to find a missing module
3341  * @work: pointer to work_struct containing our data
3342  **/
3343 static void ixgbe_sfp_task(struct work_struct *work)
3344 {
3345         struct ixgbe_adapter *adapter = container_of(work,
3346                                                      struct ixgbe_adapter,
3347                                                      sfp_task);
3348         struct ixgbe_hw *hw = &adapter->hw;
3349
3350         if ((hw->phy.type == ixgbe_phy_nl) &&
3351             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3352                 s32 ret = hw->phy.ops.identify_sfp(hw);
3353                 if (ret)
3354                         goto reschedule;
3355                 ret = hw->phy.ops.reset(hw);
3356                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3357                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3358                                 "unsupported SFP+ module type was detected.\n"
3359                                 "Reload the driver after installing a "
3360                                 "supported module.\n");
3361                         unregister_netdev(adapter->netdev);
3362                 } else {
3363                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3364                                 hw->phy.sfp_type);
3365                 }
3366                 /* don't need this routine any more */
3367                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3368         }
3369         return;
3370 reschedule:
3371         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3372                 mod_timer(&adapter->sfp_timer,
3373                           round_jiffies(jiffies + (2 * HZ)));
3374 }
3375
3376 /**
3377  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3378  * @adapter: board private structure to initialize
3379  *
3380  * ixgbe_sw_init initializes the Adapter private data structure.
3381  * Fields are initialized based on PCI device information and
3382  * OS network device settings (MTU size).
3383  **/
3384 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3385 {
3386         struct ixgbe_hw *hw = &adapter->hw;
3387         struct pci_dev *pdev = adapter->pdev;
3388         unsigned int rss;
3389 #ifdef CONFIG_IXGBE_DCB
3390         int j;
3391         struct tc_configuration *tc;
3392 #endif
3393
3394         /* PCI config space info */
3395
3396         hw->vendor_id = pdev->vendor;
3397         hw->device_id = pdev->device;
3398         hw->revision_id = pdev->revision;
3399         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3400         hw->subsystem_device_id = pdev->subsystem_device;
3401
3402         /* Set capability flags */
3403         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3404         adapter->ring_feature[RING_F_RSS].indices = rss;
3405         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3406         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3407         if (hw->mac.type == ixgbe_mac_82598EB) {
3408                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3409                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3410                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3411         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3412                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3413                 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3414                 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3415 #ifdef IXGBE_FCOE
3416                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3417 #endif /* IXGBE_FCOE */
3418         }
3419
3420 #ifdef CONFIG_IXGBE_DCB
3421         /* Configure DCB traffic classes */
3422         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3423                 tc = &adapter->dcb_cfg.tc_config[j];
3424                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3425                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3426                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3427                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3428                 tc->dcb_pfc = pfc_disabled;
3429         }
3430         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3431         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3432         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3433         adapter->dcb_cfg.round_robin_enable = false;
3434         adapter->dcb_set_bitmap = 0x00;
3435         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3436                            adapter->ring_feature[RING_F_DCB].indices);
3437
3438 #endif
3439
3440         /* default flow control settings */
3441         hw->fc.requested_mode = ixgbe_fc_full;
3442         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3443         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3444         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3445         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3446         hw->fc.send_xon = true;
3447         hw->fc.disable_fc_autoneg = false;
3448
3449         /* enable itr by default in dynamic mode */
3450         adapter->itr_setting = 1;
3451         adapter->eitr_param = 20000;
3452
3453         /* set defaults for eitr in MegaBytes */
3454         adapter->eitr_low = 10;
3455         adapter->eitr_high = 20;
3456
3457         /* set default ring sizes */
3458         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3459         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3460
3461         /* initialize eeprom parameters */
3462         if (ixgbe_init_eeprom_params_generic(hw)) {
3463                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3464                 return -EIO;
3465         }
3466
3467         /* enable rx csum by default */
3468         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3469
3470         set_bit(__IXGBE_DOWN, &adapter->state);
3471
3472         return 0;
3473 }
3474
3475 /**
3476  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3477  * @adapter: board private structure
3478  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3479  *
3480  * Return 0 on success, negative on failure
3481  **/
3482 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3483                              struct ixgbe_ring *tx_ring)
3484 {
3485         struct pci_dev *pdev = adapter->pdev;
3486         int size;
3487
3488         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3489         tx_ring->tx_buffer_info = vmalloc(size);
3490         if (!tx_ring->tx_buffer_info)
3491                 goto err;
3492         memset(tx_ring->tx_buffer_info, 0, size);
3493
3494         /* round up to nearest 4K */
3495         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3496         tx_ring->size = ALIGN(tx_ring->size, 4096);
3497
3498         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3499                                              &tx_ring->dma);
3500         if (!tx_ring->desc)
3501                 goto err;
3502
3503         tx_ring->next_to_use = 0;
3504         tx_ring->next_to_clean = 0;
3505         tx_ring->work_limit = tx_ring->count;
3506         return 0;
3507
3508 err:
3509         vfree(tx_ring->tx_buffer_info);
3510         tx_ring->tx_buffer_info = NULL;
3511         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3512                             "descriptor ring\n");
3513         return -ENOMEM;
3514 }
3515
3516 /**
3517  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3518  * @adapter: board private structure
3519  *
3520  * If this function returns with an error, then it's possible one or
3521  * more of the rings is populated (while the rest are not).  It is the
3522  * callers duty to clean those orphaned rings.
3523  *
3524  * Return 0 on success, negative on failure
3525  **/
3526 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3527 {
3528         int i, err = 0;
3529
3530         for (i = 0; i < adapter->num_tx_queues; i++) {
3531                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3532                 if (!err)
3533                         continue;
3534                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3535                 break;
3536         }
3537
3538         return err;
3539 }
3540
3541 /**
3542  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3543  * @adapter: board private structure
3544  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3545  *
3546  * Returns 0 on success, negative on failure
3547  **/
3548 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3549                              struct ixgbe_ring *rx_ring)
3550 {
3551         struct pci_dev *pdev = adapter->pdev;
3552         int size;
3553
3554         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3555         rx_ring->rx_buffer_info = vmalloc(size);
3556         if (!rx_ring->rx_buffer_info) {
3557                 DPRINTK(PROBE, ERR,
3558                         "vmalloc allocation failed for the rx desc ring\n");
3559                 goto alloc_failed;
3560         }
3561         memset(rx_ring->rx_buffer_info, 0, size);
3562
3563         /* Round up to nearest 4K */
3564         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3565         rx_ring->size = ALIGN(rx_ring->size, 4096);
3566
3567         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3568
3569         if (!rx_ring->desc) {
3570                 DPRINTK(PROBE, ERR,
3571                         "Memory allocation failed for the rx desc ring\n");
3572                 vfree(rx_ring->rx_buffer_info);
3573                 goto alloc_failed;
3574         }
3575
3576         rx_ring->next_to_clean = 0;
3577         rx_ring->next_to_use = 0;
3578
3579         return 0;
3580
3581 alloc_failed:
3582         return -ENOMEM;
3583 }
3584
3585 /**
3586  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3587  * @adapter: board private structure
3588  *
3589  * If this function returns with an error, then it's possible one or
3590  * more of the rings is populated (while the rest are not).  It is the
3591  * callers duty to clean those orphaned rings.
3592  *
3593  * Return 0 on success, negative on failure
3594  **/
3595
3596 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3597 {
3598         int i, err = 0;
3599
3600         for (i = 0; i < adapter->num_rx_queues; i++) {
3601                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3602                 if (!err)
3603                         continue;
3604                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3605                 break;
3606         }
3607
3608         return err;
3609 }
3610
3611 /**
3612  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3613  * @adapter: board private structure
3614  * @tx_ring: Tx descriptor ring for a specific queue
3615  *
3616  * Free all transmit software resources
3617  **/
3618 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3619                              struct ixgbe_ring *tx_ring)
3620 {
3621         struct pci_dev *pdev = adapter->pdev;
3622
3623         ixgbe_clean_tx_ring(adapter, tx_ring);
3624
3625         vfree(tx_ring->tx_buffer_info);
3626         tx_ring->tx_buffer_info = NULL;
3627
3628         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3629
3630         tx_ring->desc = NULL;
3631 }
3632
3633 /**
3634  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3635  * @adapter: board private structure
3636  *
3637  * Free all transmit software resources
3638  **/
3639 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3640 {
3641         int i;
3642
3643         for (i = 0; i < adapter->num_tx_queues; i++)
3644                 if (adapter->tx_ring[i].desc)
3645                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3646 }
3647
3648 /**
3649  * ixgbe_free_rx_resources - Free Rx Resources
3650  * @adapter: board private structure
3651  * @rx_ring: ring to clean the resources from
3652  *
3653  * Free all receive software resources
3654  **/
3655 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3656                              struct ixgbe_ring *rx_ring)
3657 {
3658         struct pci_dev *pdev = adapter->pdev;
3659
3660         ixgbe_clean_rx_ring(adapter, rx_ring);
3661
3662         vfree(rx_ring->rx_buffer_info);
3663         rx_ring->rx_buffer_info = NULL;
3664
3665         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3666
3667         rx_ring->desc = NULL;
3668 }
3669
3670 /**
3671  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3672  * @adapter: board private structure
3673  *
3674  * Free all receive software resources
3675  **/
3676 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3677 {
3678         int i;
3679
3680         for (i = 0; i < adapter->num_rx_queues; i++)
3681                 if (adapter->rx_ring[i].desc)
3682                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3683 }
3684
3685 /**
3686  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3687  * @netdev: network interface device structure
3688  * @new_mtu: new value for maximum frame size
3689  *
3690  * Returns 0 on success, negative on failure
3691  **/
3692 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3693 {
3694         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3695         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3696
3697         /* MTU < 68 is an error and causes problems on some kernels */
3698         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3699                 return -EINVAL;
3700
3701         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3702                 netdev->mtu, new_mtu);
3703         /* must set new MTU before calling down or up */
3704         netdev->mtu = new_mtu;
3705
3706         if (netif_running(netdev))
3707                 ixgbe_reinit_locked(adapter);
3708
3709         return 0;
3710 }
3711
3712 /**
3713  * ixgbe_open - Called when a network interface is made active
3714  * @netdev: network interface device structure
3715  *
3716  * Returns 0 on success, negative value on failure
3717  *
3718  * The open entry point is called when a network interface is made
3719  * active by the system (IFF_UP).  At this point all resources needed
3720  * for transmit and receive operations are allocated, the interrupt
3721  * handler is registered with the OS, the watchdog timer is started,
3722  * and the stack is notified that the interface is ready.
3723  **/
3724 static int ixgbe_open(struct net_device *netdev)
3725 {
3726         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3727         int err;
3728
3729         /* disallow open during test */
3730         if (test_bit(__IXGBE_TESTING, &adapter->state))
3731                 return -EBUSY;
3732
3733         netif_carrier_off(netdev);
3734
3735         /* allocate transmit descriptors */
3736         err = ixgbe_setup_all_tx_resources(adapter);
3737         if (err)
3738                 goto err_setup_tx;
3739
3740         /* allocate receive descriptors */
3741         err = ixgbe_setup_all_rx_resources(adapter);
3742         if (err)
3743                 goto err_setup_rx;
3744
3745         ixgbe_configure(adapter);
3746
3747         err = ixgbe_request_irq(adapter);
3748         if (err)
3749                 goto err_req_irq;
3750
3751         err = ixgbe_up_complete(adapter);
3752         if (err)
3753                 goto err_up;
3754
3755         netif_tx_start_all_queues(netdev);
3756
3757         return 0;
3758
3759 err_up:
3760         ixgbe_release_hw_control(adapter);
3761         ixgbe_free_irq(adapter);
3762 err_req_irq:
3763 err_setup_rx:
3764         ixgbe_free_all_rx_resources(adapter);
3765 err_setup_tx:
3766         ixgbe_free_all_tx_resources(adapter);
3767         ixgbe_reset(adapter);
3768
3769         return err;
3770 }
3771
3772 /**
3773  * ixgbe_close - Disables a network interface
3774  * @netdev: network interface device structure
3775  *
3776  * Returns 0, this is not allowed to fail
3777  *
3778  * The close entry point is called when an interface is de-activated
3779  * by the OS.  The hardware is still under the drivers control, but
3780  * needs to be disabled.  A global MAC reset is issued to stop the
3781  * hardware, and all transmit and receive resources are freed.
3782  **/
3783 static int ixgbe_close(struct net_device *netdev)
3784 {
3785         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3786
3787         ixgbe_down(adapter);
3788         ixgbe_free_irq(adapter);
3789
3790         ixgbe_free_all_tx_resources(adapter);
3791         ixgbe_free_all_rx_resources(adapter);
3792
3793         ixgbe_release_hw_control(adapter);
3794
3795         return 0;
3796 }
3797
3798 #ifdef CONFIG_PM
3799 static int ixgbe_resume(struct pci_dev *pdev)
3800 {
3801         struct net_device *netdev = pci_get_drvdata(pdev);
3802         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3803         u32 err;
3804
3805         pci_set_power_state(pdev, PCI_D0);
3806         pci_restore_state(pdev);
3807
3808         err = pci_enable_device_mem(pdev);
3809         if (err) {
3810                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3811                                 "suspend\n");
3812                 return err;
3813         }
3814         pci_set_master(pdev);
3815
3816         pci_wake_from_d3(pdev, false);
3817
3818         err = ixgbe_init_interrupt_scheme(adapter);
3819         if (err) {
3820                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3821                                 "device\n");
3822                 return err;
3823         }
3824
3825         ixgbe_reset(adapter);
3826
3827         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3828
3829         if (netif_running(netdev)) {
3830                 err = ixgbe_open(adapter->netdev);
3831                 if (err)
3832                         return err;
3833         }
3834
3835         netif_device_attach(netdev);
3836
3837         return 0;
3838 }
3839 #endif /* CONFIG_PM */
3840
3841 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3842 {
3843         struct net_device *netdev = pci_get_drvdata(pdev);
3844         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3845         struct ixgbe_hw *hw = &adapter->hw;
3846         u32 ctrl, fctrl;
3847         u32 wufc = adapter->wol;
3848 #ifdef CONFIG_PM
3849         int retval = 0;
3850 #endif
3851
3852         netif_device_detach(netdev);
3853
3854         if (netif_running(netdev)) {
3855                 ixgbe_down(adapter);
3856                 ixgbe_free_irq(adapter);
3857                 ixgbe_free_all_tx_resources(adapter);
3858                 ixgbe_free_all_rx_resources(adapter);
3859         }
3860         ixgbe_clear_interrupt_scheme(adapter);
3861
3862 #ifdef CONFIG_PM
3863         retval = pci_save_state(pdev);
3864         if (retval)
3865                 return retval;
3866
3867 #endif
3868         if (wufc) {
3869                 ixgbe_set_rx_mode(netdev);
3870
3871                 /* turn on all-multi mode if wake on multicast is enabled */
3872                 if (wufc & IXGBE_WUFC_MC) {
3873                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3874                         fctrl |= IXGBE_FCTRL_MPE;
3875                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3876                 }
3877
3878                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3879                 ctrl |= IXGBE_CTRL_GIO_DIS;
3880                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3881
3882                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3883         } else {
3884                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3885                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3886         }
3887
3888         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3889                 pci_wake_from_d3(pdev, true);
3890         else
3891                 pci_wake_from_d3(pdev, false);
3892
3893         *enable_wake = !!wufc;
3894
3895         ixgbe_release_hw_control(adapter);
3896
3897         pci_disable_device(pdev);
3898
3899         return 0;
3900 }
3901
3902 #ifdef CONFIG_PM
3903 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3904 {
3905         int retval;
3906         bool wake;
3907
3908         retval = __ixgbe_shutdown(pdev, &wake);
3909         if (retval)
3910                 return retval;
3911
3912         if (wake) {
3913                 pci_prepare_to_sleep(pdev);
3914         } else {
3915                 pci_wake_from_d3(pdev, false);
3916                 pci_set_power_state(pdev, PCI_D3hot);
3917         }
3918
3919         return 0;
3920 }
3921 #endif /* CONFIG_PM */
3922
3923 static void ixgbe_shutdown(struct pci_dev *pdev)
3924 {
3925         bool wake;
3926
3927         __ixgbe_shutdown(pdev, &wake);
3928
3929         if (system_state == SYSTEM_POWER_OFF) {
3930                 pci_wake_from_d3(pdev, wake);
3931                 pci_set_power_state(pdev, PCI_D3hot);
3932         }
3933 }
3934
3935 /**
3936  * ixgbe_update_stats - Update the board statistics counters.
3937  * @adapter: board private structure
3938  **/
3939 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3940 {
3941         struct ixgbe_hw *hw = &adapter->hw;
3942         u64 total_mpc = 0;
3943         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3944
3945         if (hw->mac.type == ixgbe_mac_82599EB) {
3946                 u64 rsc_count = 0;
3947                 for (i = 0; i < 16; i++)
3948                         adapter->hw_rx_no_dma_resources +=
3949                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3950                 for (i = 0; i < adapter->num_rx_queues; i++)
3951                         rsc_count += adapter->rx_ring[i].rsc_count;
3952                 adapter->rsc_count = rsc_count;
3953         }
3954
3955         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3956         for (i = 0; i < 8; i++) {
3957                 /* for packet buffers not used, the register should read 0 */
3958                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3959                 missed_rx += mpc;
3960                 adapter->stats.mpc[i] += mpc;
3961                 total_mpc += adapter->stats.mpc[i];
3962                 if (hw->mac.type == ixgbe_mac_82598EB)
3963                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3964                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3965                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3966                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3967                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3968                 if (hw->mac.type == ixgbe_mac_82599EB) {
3969                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3970                                                             IXGBE_PXONRXCNT(i));
3971                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3972                                                            IXGBE_PXOFFRXCNT(i));
3973                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3974                 } else {
3975                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3976                                                               IXGBE_PXONRXC(i));
3977                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3978                                                              IXGBE_PXOFFRXC(i));
3979                 }
3980                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3981                                                             IXGBE_PXONTXC(i));
3982                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3983                                                              IXGBE_PXOFFTXC(i));
3984         }
3985         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3986         /* work around hardware counting issue */
3987         adapter->stats.gprc -= missed_rx;
3988
3989         /* 82598 hardware only has a 32 bit counter in the high register */
3990         if (hw->mac.type == ixgbe_mac_82599EB) {
3991                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3992                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3993                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3994                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3995                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3996                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3997                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3998                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3999         } else {
4000                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4001                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4002                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4003                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4004                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4005         }
4006         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4007         adapter->stats.bprc += bprc;
4008         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4009         if (hw->mac.type == ixgbe_mac_82598EB)
4010                 adapter->stats.mprc -= bprc;
4011         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4012         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4013         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4014         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4015         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4016         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4017         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4018         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4019         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4020         adapter->stats.lxontxc += lxon;
4021         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4022         adapter->stats.lxofftxc += lxoff;
4023         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4024         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4025         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4026         /*
4027          * 82598 errata - tx of flow control packets is included in tx counters
4028          */
4029         xon_off_tot = lxon + lxoff;
4030         adapter->stats.gptc -= xon_off_tot;
4031         adapter->stats.mptc -= xon_off_tot;
4032         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4033         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4034         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4035         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4036         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4037         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4038         adapter->stats.ptc64 -= xon_off_tot;
4039         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4040         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4041         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4042         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4043         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4044         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4045
4046         /* Fill out the OS statistics structure */
4047         adapter->net_stats.multicast = adapter->stats.mprc;
4048
4049         /* Rx Errors */
4050         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4051                                        adapter->stats.rlec;
4052         adapter->net_stats.rx_dropped = 0;
4053         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4054         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4055         adapter->net_stats.rx_missed_errors = total_mpc;
4056 }
4057
4058 /**
4059  * ixgbe_watchdog - Timer Call-back
4060  * @data: pointer to adapter cast into an unsigned long
4061  **/
4062 static void ixgbe_watchdog(unsigned long data)
4063 {
4064         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4065         struct ixgbe_hw *hw = &adapter->hw;
4066
4067         /* Do the watchdog outside of interrupt context due to the lovely
4068          * delays that some of the newer hardware requires */
4069         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
4070                 u64 eics = 0;
4071                 int i;
4072
4073                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4074                         eics |= ((u64)1 << i);
4075
4076                 /* Cause software interrupt to ensure rx rings are cleaned */
4077                 switch (hw->mac.type) {
4078                 case ixgbe_mac_82598EB:
4079                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4080                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4081                         } else {
4082                                 /*
4083                                  * for legacy and MSI interrupts don't set any
4084                                  * bits that are enabled for EIAM, because this
4085                                  * operation would set *both* EIMS and EICS for
4086                                  * any bit in EIAM
4087                                  */
4088                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4089                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4090                         }
4091                         break;
4092                 case ixgbe_mac_82599EB:
4093                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4094                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4095                                                 (u32)(eics & 0xFFFFFFFF));
4096                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4097                                                 (u32)(eics >> 32));
4098                         } else {
4099                                 /*
4100                                  * for legacy and MSI interrupts don't set any
4101                                  * bits that are enabled for EIAM, because this
4102                                  * operation would set *both* EIMS and EICS for
4103                                  * any bit in EIAM
4104                                  */
4105                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4106                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4107                         }
4108                         break;
4109                 default:
4110                         break;
4111                 }
4112                 /* Reset the timer */
4113                 mod_timer(&adapter->watchdog_timer,
4114                           round_jiffies(jiffies + 2 * HZ));
4115         }
4116
4117         schedule_work(&adapter->watchdog_task);
4118 }
4119
4120 /**
4121  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4122  * @work: pointer to work_struct containing our data
4123  **/
4124 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4125 {
4126         struct ixgbe_adapter *adapter = container_of(work,
4127                                                      struct ixgbe_adapter,
4128                                                      multispeed_fiber_task);
4129         struct ixgbe_hw *hw = &adapter->hw;
4130         u32 autoneg;
4131
4132         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4133         if (hw->mac.ops.get_link_capabilities)
4134                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4135                                                   &hw->mac.autoneg);
4136         if (hw->mac.ops.setup_link_speed)
4137                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4138         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4139         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4140 }
4141
4142 /**
4143  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4144  * @work: pointer to work_struct containing our data
4145  **/
4146 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4147 {
4148         struct ixgbe_adapter *adapter = container_of(work,
4149                                                      struct ixgbe_adapter,
4150                                                      sfp_config_module_task);
4151         struct ixgbe_hw *hw = &adapter->hw;
4152         u32 err;
4153
4154         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4155         err = hw->phy.ops.identify_sfp(hw);
4156         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4157                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4158                 ixgbe_down(adapter);
4159                 return;
4160         }
4161         hw->mac.ops.setup_sfp(hw);
4162
4163         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4164                 /* This will also work for DA Twinax connections */
4165                 schedule_work(&adapter->multispeed_fiber_task);
4166         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4167 }
4168
4169 /**
4170  * ixgbe_watchdog_task - worker thread to bring link up
4171  * @work: pointer to work_struct containing our data
4172  **/
4173 static void ixgbe_watchdog_task(struct work_struct *work)
4174 {
4175         struct ixgbe_adapter *adapter = container_of(work,
4176                                                      struct ixgbe_adapter,
4177                                                      watchdog_task);
4178         struct net_device *netdev = adapter->netdev;
4179         struct ixgbe_hw *hw = &adapter->hw;
4180         u32 link_speed = adapter->link_speed;
4181         bool link_up = adapter->link_up;
4182         int i;
4183         struct ixgbe_ring *tx_ring;
4184         int some_tx_pending = 0;
4185
4186         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4187
4188         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4189                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4190                 if (link_up ||
4191                     time_after(jiffies, (adapter->link_check_timeout +
4192                                          IXGBE_TRY_LINK_TIMEOUT))) {
4193                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4194                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4195                 }
4196                 adapter->link_up = link_up;
4197                 adapter->link_speed = link_speed;
4198         }
4199
4200         if (link_up) {
4201                 if (!netif_carrier_ok(netdev)) {
4202                         bool flow_rx, flow_tx;
4203
4204                         if (hw->mac.type == ixgbe_mac_82599EB) {
4205                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4206                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4207                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4208                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4209                         } else {
4210                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4211                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4212                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4213                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4214                         }
4215
4216                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4217                                "Flow Control: %s\n",
4218                                netdev->name,
4219                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4220                                 "10 Gbps" :
4221                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4222                                  "1 Gbps" : "unknown speed")),
4223                                ((flow_rx && flow_tx) ? "RX/TX" :
4224                                 (flow_rx ? "RX" :
4225                                 (flow_tx ? "TX" : "None"))));
4226
4227                         netif_carrier_on(netdev);
4228                 } else {
4229                         /* Force detection of hung controller */
4230                         adapter->detect_tx_hung = true;
4231                 }
4232         } else {
4233                 adapter->link_up = false;
4234                 adapter->link_speed = 0;
4235                 if (netif_carrier_ok(netdev)) {
4236                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4237                                netdev->name);
4238                         netif_carrier_off(netdev);
4239                 }
4240         }
4241
4242         if (!netif_carrier_ok(netdev)) {
4243                 for (i = 0; i < adapter->num_tx_queues; i++) {
4244                         tx_ring = &adapter->tx_ring[i];
4245                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4246                                 some_tx_pending = 1;
4247                                 break;
4248                         }
4249                 }
4250
4251                 if (some_tx_pending) {
4252                         /* We've lost link, so the controller stops DMA,
4253                          * but we've got queued Tx work that's never going
4254                          * to get done, so reset controller to flush Tx.
4255                          * (Do the reset outside of interrupt context).
4256                          */
4257                          schedule_work(&adapter->reset_task);
4258                 }
4259         }
4260
4261         ixgbe_update_stats(adapter);
4262         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4263 }
4264
4265 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4266                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4267                      u32 tx_flags, u8 *hdr_len)
4268 {
4269         struct ixgbe_adv_tx_context_desc *context_desc;
4270         unsigned int i;
4271         int err;
4272         struct ixgbe_tx_buffer *tx_buffer_info;
4273         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4274         u32 mss_l4len_idx, l4len;
4275
4276         if (skb_is_gso(skb)) {
4277                 if (skb_header_cloned(skb)) {
4278                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4279                         if (err)
4280                                 return err;
4281                 }
4282                 l4len = tcp_hdrlen(skb);
4283                 *hdr_len += l4len;
4284
4285                 if (skb->protocol == htons(ETH_P_IP)) {
4286                         struct iphdr *iph = ip_hdr(skb);
4287                         iph->tot_len = 0;
4288                         iph->check = 0;
4289                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4290                                                                  iph->daddr, 0,
4291                                                                  IPPROTO_TCP,
4292                                                                  0);
4293                         adapter->hw_tso_ctxt++;
4294                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4295                         ipv6_hdr(skb)->payload_len = 0;
4296                         tcp_hdr(skb)->check =
4297                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4298                                              &ipv6_hdr(skb)->daddr,
4299                                              0, IPPROTO_TCP, 0);
4300                         adapter->hw_tso6_ctxt++;
4301                 }
4302
4303                 i = tx_ring->next_to_use;
4304
4305                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4306                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4307
4308                 /* VLAN MACLEN IPLEN */
4309                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4310                         vlan_macip_lens |=
4311                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4312                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4313                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4314                 *hdr_len += skb_network_offset(skb);
4315                 vlan_macip_lens |=
4316                     (skb_transport_header(skb) - skb_network_header(skb));
4317                 *hdr_len +=
4318                     (skb_transport_header(skb) - skb_network_header(skb));
4319                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4320                 context_desc->seqnum_seed = 0;
4321
4322                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4323                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4324                                    IXGBE_ADVTXD_DTYP_CTXT);
4325
4326                 if (skb->protocol == htons(ETH_P_IP))
4327                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4328                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4329                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4330
4331                 /* MSS L4LEN IDX */
4332                 mss_l4len_idx =
4333                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4334                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4335                 /* use index 1 for TSO */
4336                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4337                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4338
4339                 tx_buffer_info->time_stamp = jiffies;
4340                 tx_buffer_info->next_to_watch = i;
4341
4342                 i++;
4343                 if (i == tx_ring->count)
4344                         i = 0;
4345                 tx_ring->next_to_use = i;
4346
4347                 return true;
4348         }
4349         return false;
4350 }
4351
4352 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4353                           struct ixgbe_ring *tx_ring,
4354                           struct sk_buff *skb, u32 tx_flags)
4355 {
4356         struct ixgbe_adv_tx_context_desc *context_desc;
4357         unsigned int i;
4358         struct ixgbe_tx_buffer *tx_buffer_info;
4359         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4360
4361         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4362             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4363                 i = tx_ring->next_to_use;
4364                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4365                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4366
4367                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4368                         vlan_macip_lens |=
4369                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4370                 vlan_macip_lens |= (skb_network_offset(skb) <<
4371                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4372                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4373                         vlan_macip_lens |= (skb_transport_header(skb) -
4374                                             skb_network_header(skb));
4375
4376                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4377                 context_desc->seqnum_seed = 0;
4378
4379                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4380                                     IXGBE_ADVTXD_DTYP_CTXT);
4381
4382                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4383                         switch (skb->protocol) {
4384                         case cpu_to_be16(ETH_P_IP):
4385                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4386                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4387                                         type_tucmd_mlhl |=
4388                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4389                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4390                                         type_tucmd_mlhl |=
4391                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4392                                 break;
4393                         case cpu_to_be16(ETH_P_IPV6):
4394                                 /* XXX what about other V6 headers?? */
4395                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4396                                         type_tucmd_mlhl |=
4397                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4398                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4399                                         type_tucmd_mlhl |=
4400                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4401                                 break;
4402                         default:
4403                                 if (unlikely(net_ratelimit())) {
4404                                         DPRINTK(PROBE, WARNING,
4405                                          "partial checksum but proto=%x!\n",
4406                                          skb->protocol);
4407                                 }
4408                                 break;
4409                         }
4410                 }
4411
4412                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4413                 /* use index zero for tx checksum offload */
4414                 context_desc->mss_l4len_idx = 0;
4415
4416                 tx_buffer_info->time_stamp = jiffies;
4417                 tx_buffer_info->next_to_watch = i;
4418
4419                 adapter->hw_csum_tx_good++;
4420                 i++;
4421                 if (i == tx_ring->count)
4422                         i = 0;
4423                 tx_ring->next_to_use = i;
4424
4425                 return true;
4426         }
4427
4428         return false;
4429 }
4430
4431 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4432                         struct ixgbe_ring *tx_ring,
4433                         struct sk_buff *skb, u32 tx_flags,
4434                         unsigned int first)
4435 {
4436         struct ixgbe_tx_buffer *tx_buffer_info;
4437         unsigned int len;
4438         unsigned int total = skb->len;
4439         unsigned int offset = 0, size, count = 0, i;
4440         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4441         unsigned int f;
4442         dma_addr_t *map;
4443
4444         i = tx_ring->next_to_use;
4445
4446         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4447                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4448                 return 0;
4449         }
4450
4451         map = skb_shinfo(skb)->dma_maps;
4452
4453         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4454                 /* excluding fcoe_crc_eof for FCoE */
4455                 total -= sizeof(struct fcoe_crc_eof);
4456
4457         len = min(skb_headlen(skb), total);
4458         while (len) {
4459                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4460                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4461
4462                 tx_buffer_info->length = size;
4463                 tx_buffer_info->dma = map[0] + offset;
4464                 tx_buffer_info->time_stamp = jiffies;
4465                 tx_buffer_info->next_to_watch = i;
4466
4467                 len -= size;
4468                 total -= size;
4469                 offset += size;
4470                 count++;
4471
4472                 if (len) {
4473                         i++;
4474                         if (i == tx_ring->count)
4475                                 i = 0;
4476                 }
4477         }
4478
4479         for (f = 0; f < nr_frags; f++) {
4480                 struct skb_frag_struct *frag;
4481
4482                 frag = &skb_shinfo(skb)->frags[f];
4483                 len = min((unsigned int)frag->size, total);
4484                 offset = 0;
4485
4486                 while (len) {
4487                         i++;
4488                         if (i == tx_ring->count)
4489                                 i = 0;
4490
4491                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4492                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4493
4494                         tx_buffer_info->length = size;
4495                         tx_buffer_info->dma = map[f + 1] + offset;
4496                         tx_buffer_info->time_stamp = jiffies;
4497                         tx_buffer_info->next_to_watch = i;
4498
4499                         len -= size;
4500                         total -= size;
4501                         offset += size;
4502                         count++;
4503                 }
4504                 if (total == 0)
4505                         break;
4506         }
4507
4508         tx_ring->tx_buffer_info[i].skb = skb;
4509         tx_ring->tx_buffer_info[first].next_to_watch = i;
4510
4511         return count;
4512 }
4513
4514 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4515                            struct ixgbe_ring *tx_ring,
4516                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4517 {
4518         union ixgbe_adv_tx_desc *tx_desc = NULL;
4519         struct ixgbe_tx_buffer *tx_buffer_info;
4520         u32 olinfo_status = 0, cmd_type_len = 0;
4521         unsigned int i;
4522         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4523
4524         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4525
4526         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4527
4528         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4529                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4530
4531         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4532                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4533
4534                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4535                                  IXGBE_ADVTXD_POPTS_SHIFT;
4536
4537                 /* use index 1 context for tso */
4538                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4539                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4540                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4541                                          IXGBE_ADVTXD_POPTS_SHIFT;
4542
4543         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4544                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4545                                  IXGBE_ADVTXD_POPTS_SHIFT;
4546
4547         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4548                 olinfo_status |= IXGBE_ADVTXD_CC;
4549                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4550                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4551                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4552         }
4553
4554         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4555
4556         i = tx_ring->next_to_use;
4557         while (count--) {
4558                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4559                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4560                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4561                 tx_desc->read.cmd_type_len =
4562                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4563                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4564                 i++;
4565                 if (i == tx_ring->count)
4566                         i = 0;
4567         }
4568
4569         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4570
4571         /*
4572          * Force memory writes to complete before letting h/w
4573          * know there are new descriptors to fetch.  (Only
4574          * applicable for weak-ordered memory model archs,
4575          * such as IA-64).
4576          */
4577         wmb();
4578
4579         tx_ring->next_to_use = i;
4580         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4581 }
4582
4583 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4584                                  struct ixgbe_ring *tx_ring, int size)
4585 {
4586         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4587
4588         netif_stop_subqueue(netdev, tx_ring->queue_index);
4589         /* Herbert's original patch had:
4590          *  smp_mb__after_netif_stop_queue();
4591          * but since that doesn't exist yet, just open code it. */
4592         smp_mb();
4593
4594         /* We need to check again in a case another CPU has just
4595          * made room available. */
4596         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4597                 return -EBUSY;
4598
4599         /* A reprieve! - use start_queue because it doesn't call schedule */
4600         netif_start_subqueue(netdev, tx_ring->queue_index);
4601         ++adapter->restart_queue;
4602         return 0;
4603 }
4604
4605 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4606                               struct ixgbe_ring *tx_ring, int size)
4607 {
4608         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4609                 return 0;
4610         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4611 }
4612
4613 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4614 {
4615         struct ixgbe_adapter *adapter = netdev_priv(dev);
4616
4617         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4618                 return 0;  /* All traffic should default to class 0 */
4619
4620         return skb_tx_hash(dev, skb);
4621 }
4622
4623 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4624 {
4625         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4626         struct ixgbe_ring *tx_ring;
4627         unsigned int first;
4628         unsigned int tx_flags = 0;
4629         u8 hdr_len = 0;
4630         int r_idx = 0, tso;
4631         int count = 0;
4632         unsigned int f;
4633
4634         r_idx = skb->queue_mapping;
4635         tx_ring = &adapter->tx_ring[r_idx];
4636
4637         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4638                 tx_flags |= vlan_tx_tag_get(skb);
4639                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4640                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4641                         tx_flags |= (skb->queue_mapping << 13);
4642                 }
4643                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4644                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4645         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4646                 tx_flags |= (skb->queue_mapping << 13);
4647                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4648                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4649         }
4650
4651         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4652             (skb->protocol == htons(ETH_P_FCOE)))
4653                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4654
4655         /* four things can cause us to need a context descriptor */
4656         if (skb_is_gso(skb) ||
4657             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4658             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4659             (tx_flags & IXGBE_TX_FLAGS_FCOE))
4660                 count++;
4661
4662         count += TXD_USE_COUNT(skb_headlen(skb));
4663         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4664                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4665
4666         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4667                 adapter->tx_busy++;
4668                 return NETDEV_TX_BUSY;
4669         }
4670
4671         first = tx_ring->next_to_use;
4672         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4673 #ifdef IXGBE_FCOE
4674                 /* setup tx offload for FCoE */
4675                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4676                 if (tso < 0) {
4677                         dev_kfree_skb_any(skb);
4678                         return NETDEV_TX_OK;
4679                 }
4680                 if (tso)
4681                         tx_flags |= IXGBE_TX_FLAGS_FSO;
4682 #endif /* IXGBE_FCOE */
4683         } else {
4684                 if (skb->protocol == htons(ETH_P_IP))
4685                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
4686                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4687                 if (tso < 0) {
4688                         dev_kfree_skb_any(skb);
4689                         return NETDEV_TX_OK;
4690                 }
4691
4692                 if (tso)
4693                         tx_flags |= IXGBE_TX_FLAGS_TSO;
4694                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4695                          (skb->ip_summed == CHECKSUM_PARTIAL))
4696                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
4697         }
4698
4699         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
4700         if (count) {
4701                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4702                                hdr_len);
4703                 netdev->trans_start = jiffies;
4704                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4705
4706         } else {
4707                 dev_kfree_skb_any(skb);
4708                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4709                 tx_ring->next_to_use = first;
4710         }
4711
4712         return NETDEV_TX_OK;
4713 }
4714
4715 /**
4716  * ixgbe_get_stats - Get System Network Statistics
4717  * @netdev: network interface device structure
4718  *
4719  * Returns the address of the device statistics structure.
4720  * The statistics are actually updated from the timer callback.
4721  **/
4722 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4723 {
4724         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4725
4726         /* only return the current stats */
4727         return &adapter->net_stats;
4728 }
4729
4730 /**
4731  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4732  * @netdev: network interface device structure
4733  * @p: pointer to an address structure
4734  *
4735  * Returns 0 on success, negative on failure
4736  **/
4737 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4738 {
4739         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4740         struct ixgbe_hw *hw = &adapter->hw;
4741         struct sockaddr *addr = p;
4742
4743         if (!is_valid_ether_addr(addr->sa_data))
4744                 return -EADDRNOTAVAIL;
4745
4746         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4747         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4748
4749         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4750
4751         return 0;
4752 }
4753
4754 static int
4755 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4756 {
4757         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4758         struct ixgbe_hw *hw = &adapter->hw;
4759         u16 value;
4760         int rc;
4761
4762         if (prtad != hw->phy.mdio.prtad)
4763                 return -EINVAL;
4764         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4765         if (!rc)
4766                 rc = value;
4767         return rc;
4768 }
4769
4770 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4771                             u16 addr, u16 value)
4772 {
4773         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4774         struct ixgbe_hw *hw = &adapter->hw;
4775
4776         if (prtad != hw->phy.mdio.prtad)
4777                 return -EINVAL;
4778         return hw->phy.ops.write_reg(hw, addr, devad, value);
4779 }
4780
4781 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4782 {
4783         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4784
4785         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4786 }
4787
4788 #ifdef CONFIG_NET_POLL_CONTROLLER
4789 /*
4790  * Polling 'interrupt' - used by things like netconsole to send skbs
4791  * without having to re-enable interrupts. It's not called while
4792  * the interrupt routine is executing.
4793  */
4794 static void ixgbe_netpoll(struct net_device *netdev)
4795 {
4796         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4797
4798         disable_irq(adapter->pdev->irq);
4799         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4800         ixgbe_intr(adapter->pdev->irq, netdev);
4801         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4802         enable_irq(adapter->pdev->irq);
4803 }
4804 #endif
4805
4806 static const struct net_device_ops ixgbe_netdev_ops = {
4807         .ndo_open               = ixgbe_open,
4808         .ndo_stop               = ixgbe_close,
4809         .ndo_start_xmit         = ixgbe_xmit_frame,
4810         .ndo_select_queue       = ixgbe_select_queue,
4811         .ndo_get_stats          = ixgbe_get_stats,
4812         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
4813         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4814         .ndo_validate_addr      = eth_validate_addr,
4815         .ndo_set_mac_address    = ixgbe_set_mac,
4816         .ndo_change_mtu         = ixgbe_change_mtu,
4817         .ndo_tx_timeout         = ixgbe_tx_timeout,
4818         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4819         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4820         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4821         .ndo_do_ioctl           = ixgbe_ioctl,
4822 #ifdef CONFIG_NET_POLL_CONTROLLER
4823         .ndo_poll_controller    = ixgbe_netpoll,
4824 #endif
4825 };
4826
4827 /**
4828  * ixgbe_probe - Device Initialization Routine
4829  * @pdev: PCI device information struct
4830  * @ent: entry in ixgbe_pci_tbl
4831  *
4832  * Returns 0 on success, negative on failure
4833  *
4834  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4835  * The OS initialization, configuring of the adapter private structure,
4836  * and a hardware reset occur.
4837  **/
4838 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4839                                  const struct pci_device_id *ent)
4840 {
4841         struct net_device *netdev;
4842         struct ixgbe_adapter *adapter = NULL;
4843         struct ixgbe_hw *hw;
4844         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4845         static int cards_found;
4846         int i, err, pci_using_dac;
4847 #ifdef IXGBE_FCOE
4848         u16 device_caps;
4849 #endif
4850         u32 part_num, eec;
4851
4852         err = pci_enable_device_mem(pdev);
4853         if (err)
4854                 return err;
4855
4856         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4857             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
4858                 pci_using_dac = 1;
4859         } else {
4860                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4861                 if (err) {
4862                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4863                         if (err) {
4864                                 dev_err(&pdev->dev, "No usable DMA "
4865                                         "configuration, aborting\n");
4866                                 goto err_dma;
4867                         }
4868                 }
4869                 pci_using_dac = 0;
4870         }
4871
4872         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
4873                                            IORESOURCE_MEM), ixgbe_driver_name);
4874         if (err) {
4875                 dev_err(&pdev->dev,
4876                         "pci_request_selected_regions failed 0x%x\n", err);
4877                 goto err_pci_reg;
4878         }
4879
4880         err = pci_enable_pcie_error_reporting(pdev);
4881         if (err) {
4882                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4883                                     "0x%x\n", err);
4884                 /* non-fatal, continue */
4885         }
4886
4887         pci_set_master(pdev);
4888         pci_save_state(pdev);
4889
4890         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4891         if (!netdev) {
4892                 err = -ENOMEM;
4893                 goto err_alloc_etherdev;
4894         }
4895
4896         SET_NETDEV_DEV(netdev, &pdev->dev);
4897
4898         pci_set_drvdata(pdev, netdev);
4899         adapter = netdev_priv(netdev);
4900
4901         adapter->netdev = netdev;
4902         adapter->pdev = pdev;
4903         hw = &adapter->hw;
4904         hw->back = adapter;
4905         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4906
4907         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4908                               pci_resource_len(pdev, 0));
4909         if (!hw->hw_addr) {
4910                 err = -EIO;
4911                 goto err_ioremap;
4912         }
4913
4914         for (i = 1; i <= 5; i++) {
4915                 if (pci_resource_len(pdev, i) == 0)
4916                         continue;
4917         }
4918
4919         netdev->netdev_ops = &ixgbe_netdev_ops;
4920         ixgbe_set_ethtool_ops(netdev);
4921         netdev->watchdog_timeo = 5 * HZ;
4922         strcpy(netdev->name, pci_name(pdev));
4923
4924         adapter->bd_number = cards_found;
4925
4926         /* Setup hw api */
4927         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4928         hw->mac.type  = ii->mac;
4929
4930         /* EEPROM */
4931         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4932         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4933         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4934         if (!(eec & (1 << 8)))
4935                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4936
4937         /* PHY */
4938         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4939         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4940         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
4941         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
4942         hw->phy.mdio.mmds = 0;
4943         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
4944         hw->phy.mdio.dev = netdev;
4945         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
4946         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
4947
4948         /* set up this timer and work struct before calling get_invariants
4949          * which might start the timer
4950          */
4951         init_timer(&adapter->sfp_timer);
4952         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4953         adapter->sfp_timer.data = (unsigned long) adapter;
4954
4955         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4956
4957         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4958         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4959
4960         /* a new SFP+ module arrival, called from GPI SDP2 context */
4961         INIT_WORK(&adapter->sfp_config_module_task,
4962                   ixgbe_sfp_config_module_task);
4963
4964         err = ii->get_invariants(hw);
4965         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4966                 /* start a kernel thread to watch for a module to arrive */
4967                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4968                 mod_timer(&adapter->sfp_timer,
4969                           round_jiffies(jiffies + (2 * HZ)));
4970                 err = 0;
4971         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4972                 DPRINTK(PROBE, ERR, "failed to load because an "
4973                         "unsupported SFP+ module type was detected.\n");
4974                 goto err_hw_init;
4975         } else if (err) {
4976                 goto err_hw_init;
4977         }
4978
4979         /* setup the private structure */
4980         err = ixgbe_sw_init(adapter);
4981         if (err)
4982                 goto err_sw_init;
4983
4984         /*
4985          * If there is a fan on this device and it has failed log the
4986          * failure.
4987          */
4988         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4989                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4990                 if (esdp & IXGBE_ESDP_SDP1)
4991                         DPRINTK(PROBE, CRIT,
4992                                 "Fan has stopped, replace the adapter\n");
4993         }
4994
4995         /* reset_hw fills in the perm_addr as well */
4996         err = hw->mac.ops.reset_hw(hw);
4997         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4998                 dev_err(&adapter->pdev->dev, "failed to load because an "
4999                         "unsupported SFP+ module type was detected.\n");
5000                 goto err_sw_init;
5001         } else if (err) {
5002                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5003                 goto err_sw_init;
5004         }
5005
5006         netdev->features = NETIF_F_SG |
5007                            NETIF_F_IP_CSUM |
5008                            NETIF_F_HW_VLAN_TX |
5009                            NETIF_F_HW_VLAN_RX |
5010                            NETIF_F_HW_VLAN_FILTER;
5011
5012         netdev->features |= NETIF_F_IPV6_CSUM;
5013         netdev->features |= NETIF_F_TSO;
5014         netdev->features |= NETIF_F_TSO6;
5015         netdev->features |= NETIF_F_GRO;
5016
5017         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5018                 netdev->features |= NETIF_F_SCTP_CSUM;
5019
5020         netdev->vlan_features |= NETIF_F_TSO;
5021         netdev->vlan_features |= NETIF_F_TSO6;
5022         netdev->vlan_features |= NETIF_F_IP_CSUM;
5023         netdev->vlan_features |= NETIF_F_SG;
5024
5025         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5026                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5027
5028 #ifdef CONFIG_IXGBE_DCB
5029         netdev->dcbnl_ops = &dcbnl_ops;
5030 #endif
5031
5032 #ifdef IXGBE_FCOE
5033         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5034                 if (hw->mac.ops.get_device_caps) {
5035                         hw->mac.ops.get_device_caps(hw, &device_caps);
5036                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5037                                 netdev->features |= NETIF_F_FCOE_CRC;
5038                                 netdev->features |= NETIF_F_FSO;
5039                         } else {
5040                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5041                         }
5042                 }
5043         }
5044 #endif /* IXGBE_FCOE */
5045         if (pci_using_dac)
5046                 netdev->features |= NETIF_F_HIGHDMA;
5047
5048         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5049                 netdev->features |= NETIF_F_LRO;
5050
5051         /* make sure the EEPROM is good */
5052         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5053                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5054                 err = -EIO;
5055                 goto err_eeprom;
5056         }
5057
5058         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5059         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5060
5061         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5062                 dev_err(&pdev->dev, "invalid MAC address\n");
5063                 err = -EIO;
5064                 goto err_eeprom;
5065         }
5066
5067         init_timer(&adapter->watchdog_timer);
5068         adapter->watchdog_timer.function = &ixgbe_watchdog;
5069         adapter->watchdog_timer.data = (unsigned long)adapter;
5070
5071         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5072         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5073
5074         err = ixgbe_init_interrupt_scheme(adapter);
5075         if (err)
5076                 goto err_sw_init;
5077
5078         switch (pdev->device) {
5079         case IXGBE_DEV_ID_82599_KX4:
5080                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5081                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5082                 break;
5083         default:
5084                 adapter->wol = 0;
5085                 break;
5086         }
5087         device_init_wakeup(&adapter->pdev->dev, true);
5088         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5089
5090         /* pick up the PCI bus settings for reporting later */
5091         hw->mac.ops.get_bus_info(hw);
5092
5093         /* print bus type/speed/width info */
5094         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5095                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5096                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5097                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5098                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5099                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5100                  "Unknown"),
5101                 netdev->dev_addr);
5102         ixgbe_read_pba_num_generic(hw, &part_num);
5103         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5104                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5105                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5106                          (part_num >> 8), (part_num & 0xff));
5107         else
5108                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5109                          hw->mac.type, hw->phy.type,
5110                          (part_num >> 8), (part_num & 0xff));
5111
5112         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5113                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5114                          "this card is not sufficient for optimal "
5115                          "performance.\n");
5116                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5117                          "PCI-Express slot is required.\n");
5118         }
5119
5120         /* save off EEPROM version number */
5121         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5122
5123         /* reset the hardware with the new settings */
5124         hw->mac.ops.start_hw(hw);
5125
5126         strcpy(netdev->name, "eth%d");
5127         err = register_netdev(netdev);
5128         if (err)
5129                 goto err_register;
5130
5131         /* carrier off reporting is important to ethtool even BEFORE open */
5132         netif_carrier_off(netdev);
5133
5134 #ifdef CONFIG_IXGBE_DCA
5135         if (dca_add_requester(&pdev->dev) == 0) {
5136                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5137                 /* always use CB2 mode, difference is masked
5138                  * in the CB driver */
5139                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5140                 ixgbe_setup_dca(adapter);
5141         }
5142 #endif
5143
5144         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5145         cards_found++;
5146         return 0;
5147
5148 err_register:
5149         ixgbe_release_hw_control(adapter);
5150 err_hw_init:
5151         ixgbe_clear_interrupt_scheme(adapter);
5152 err_sw_init:
5153 err_eeprom:
5154         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5155         del_timer_sync(&adapter->sfp_timer);
5156         cancel_work_sync(&adapter->sfp_task);
5157         cancel_work_sync(&adapter->multispeed_fiber_task);
5158         cancel_work_sync(&adapter->sfp_config_module_task);
5159         iounmap(hw->hw_addr);
5160 err_ioremap:
5161         free_netdev(netdev);
5162 err_alloc_etherdev:
5163         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5164                                      IORESOURCE_MEM));
5165 err_pci_reg:
5166 err_dma:
5167         pci_disable_device(pdev);
5168         return err;
5169 }
5170
5171 /**
5172  * ixgbe_remove - Device Removal Routine
5173  * @pdev: PCI device information struct
5174  *
5175  * ixgbe_remove is called by the PCI subsystem to alert the driver
5176  * that it should release a PCI device.  The could be caused by a
5177  * Hot-Plug event, or because the driver is going to be removed from
5178  * memory.
5179  **/
5180 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5181 {
5182         struct net_device *netdev = pci_get_drvdata(pdev);
5183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5184         int err;
5185
5186         set_bit(__IXGBE_DOWN, &adapter->state);
5187         /* clear the module not found bit to make sure the worker won't
5188          * reschedule
5189          */
5190         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5191         del_timer_sync(&adapter->watchdog_timer);
5192
5193         del_timer_sync(&adapter->sfp_timer);
5194         cancel_work_sync(&adapter->watchdog_task);
5195         cancel_work_sync(&adapter->sfp_task);
5196         cancel_work_sync(&adapter->multispeed_fiber_task);
5197         cancel_work_sync(&adapter->sfp_config_module_task);
5198         flush_scheduled_work();
5199
5200 #ifdef CONFIG_IXGBE_DCA
5201         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5202                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5203                 dca_remove_requester(&pdev->dev);
5204                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5205         }
5206
5207 #endif
5208         if (netdev->reg_state == NETREG_REGISTERED)
5209                 unregister_netdev(netdev);
5210
5211         ixgbe_clear_interrupt_scheme(adapter);
5212
5213         ixgbe_release_hw_control(adapter);
5214
5215         iounmap(adapter->hw.hw_addr);
5216         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5217                                      IORESOURCE_MEM));
5218
5219         DPRINTK(PROBE, INFO, "complete\n");
5220
5221         free_netdev(netdev);
5222
5223         err = pci_disable_pcie_error_reporting(pdev);
5224         if (err)
5225                 dev_err(&pdev->dev,
5226                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5227
5228         pci_disable_device(pdev);
5229 }
5230
5231 /**
5232  * ixgbe_io_error_detected - called when PCI error is detected
5233  * @pdev: Pointer to PCI device
5234  * @state: The current pci connection state
5235  *
5236  * This function is called after a PCI bus error affecting
5237  * this device has been detected.
5238  */
5239 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5240                                                 pci_channel_state_t state)
5241 {
5242         struct net_device *netdev = pci_get_drvdata(pdev);
5243         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5244
5245         netif_device_detach(netdev);
5246
5247         if (state == pci_channel_io_perm_failure)
5248                 return PCI_ERS_RESULT_DISCONNECT;
5249
5250         if (netif_running(netdev))
5251                 ixgbe_down(adapter);
5252         pci_disable_device(pdev);
5253
5254         /* Request a slot reset. */
5255         return PCI_ERS_RESULT_NEED_RESET;
5256 }
5257
5258 /**
5259  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5260  * @pdev: Pointer to PCI device
5261  *
5262  * Restart the card from scratch, as if from a cold-boot.
5263  */
5264 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5265 {
5266         struct net_device *netdev = pci_get_drvdata(pdev);
5267         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5268         pci_ers_result_t result;
5269         int err;
5270
5271         if (pci_enable_device_mem(pdev)) {
5272                 DPRINTK(PROBE, ERR,
5273                         "Cannot re-enable PCI device after reset.\n");
5274                 result = PCI_ERS_RESULT_DISCONNECT;
5275         } else {
5276                 pci_set_master(pdev);
5277                 pci_restore_state(pdev);
5278
5279                 pci_wake_from_d3(pdev, false);
5280
5281                 ixgbe_reset(adapter);
5282                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5283                 result = PCI_ERS_RESULT_RECOVERED;
5284         }
5285
5286         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5287         if (err) {
5288                 dev_err(&pdev->dev,
5289                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5290                 /* non-fatal, continue */
5291         }
5292
5293         return result;
5294 }
5295
5296 /**
5297  * ixgbe_io_resume - called when traffic can start flowing again.
5298  * @pdev: Pointer to PCI device
5299  *
5300  * This callback is called when the error recovery driver tells us that
5301  * its OK to resume normal operation.
5302  */
5303 static void ixgbe_io_resume(struct pci_dev *pdev)
5304 {
5305         struct net_device *netdev = pci_get_drvdata(pdev);
5306         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5307
5308         if (netif_running(netdev)) {
5309                 if (ixgbe_up(adapter)) {
5310                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5311                         return;
5312                 }
5313         }
5314
5315         netif_device_attach(netdev);
5316 }
5317
5318 static struct pci_error_handlers ixgbe_err_handler = {
5319         .error_detected = ixgbe_io_error_detected,
5320         .slot_reset = ixgbe_io_slot_reset,
5321         .resume = ixgbe_io_resume,
5322 };
5323
5324 static struct pci_driver ixgbe_driver = {
5325         .name     = ixgbe_driver_name,
5326         .id_table = ixgbe_pci_tbl,
5327         .probe    = ixgbe_probe,
5328         .remove   = __devexit_p(ixgbe_remove),
5329 #ifdef CONFIG_PM
5330         .suspend  = ixgbe_suspend,
5331         .resume   = ixgbe_resume,
5332 #endif
5333         .shutdown = ixgbe_shutdown,
5334         .err_handler = &ixgbe_err_handler
5335 };
5336
5337 /**
5338  * ixgbe_init_module - Driver Registration Routine
5339  *
5340  * ixgbe_init_module is the first routine called when the driver is
5341  * loaded. All it does is register with the PCI subsystem.
5342  **/
5343 static int __init ixgbe_init_module(void)
5344 {
5345         int ret;
5346         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5347                ixgbe_driver_string, ixgbe_driver_version);
5348
5349         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5350
5351 #ifdef CONFIG_IXGBE_DCA
5352         dca_register_notify(&dca_notifier);
5353 #endif
5354
5355         ret = pci_register_driver(&ixgbe_driver);
5356         return ret;
5357 }
5358
5359 module_init(ixgbe_init_module);
5360
5361 /**
5362  * ixgbe_exit_module - Driver Exit Cleanup Routine
5363  *
5364  * ixgbe_exit_module is called just before the driver is removed
5365  * from memory.
5366  **/
5367 static void __exit ixgbe_exit_module(void)
5368 {
5369 #ifdef CONFIG_IXGBE_DCA
5370         dca_unregister_notify(&dca_notifier);
5371 #endif
5372         pci_unregister_driver(&ixgbe_driver);
5373 }
5374
5375 #ifdef CONFIG_IXGBE_DCA
5376 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5377                             void *p)
5378 {
5379         int ret_val;
5380
5381         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5382                                          __ixgbe_notify_dca);
5383
5384         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5385 }
5386
5387 #endif /* CONFIG_IXGBE_DCA */
5388 #ifdef DEBUG
5389 /**
5390  * ixgbe_get_hw_dev_name - return device name string
5391  * used by hardware layer to print debugging information
5392  **/
5393 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5394 {
5395         struct ixgbe_adapter *adapter = hw->back;
5396         return adapter->netdev->name;
5397 }
5398
5399 #endif
5400 module_exit(ixgbe_exit_module);
5401
5402 /* ixgbe_main.c */