drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
  36 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  37 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  38
  39 /**
  40  *  ixgbe_identify_phy_generic - Get physical layer module
  41  *  @hw: pointer to hardware structure
  42  *
  43  *  Determines the physical layer module found on the current adapter.
  44  **/
  45 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  46 {
  47         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  48         u32 phy_addr;
  49
  50         if (hw->phy.type == ixgbe_phy_unknown) {
  51                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  52                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  53                                 hw->phy.addr = phy_addr;
  54                                 ixgbe_get_phy_id(hw);
  55                                 hw->phy.type =
  56                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  57                                 status = 0;
  58                                 break;
  59                         }
  60                 }
  61         } else {
  62                 status = 0;
  63         }
  64
  65         return status;
  66 }
  67
  68 /**
  69  *  ixgbe_validate_phy_addr - Determines phy address is valid
  70  *  @hw: pointer to hardware structure
  71  *
  72  **/
  73 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
  74 {
  75         u16 phy_id = 0;
  76         bool valid = false;
  77
  78         hw->phy.addr = phy_addr;
  79         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
  80                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
  81
  82         if (phy_id != 0xFFFF && phy_id != 0x0)
  83                 valid = true;
  84
  85         return valid;
  86 }
  87
  88 /**
  89  *  ixgbe_get_phy_id - Get the phy type
  90  *  @hw: pointer to hardware structure
  91  *
  92  **/
  93 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  94 {
  95         u32 status;
  96         u16 phy_id_high = 0;
  97         u16 phy_id_low = 0;
  98
  99         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 100                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 101                                       &phy_id_high);
 102
 103         if (status == 0) {
 104                 hw->phy.id = (u32)(phy_id_high << 16);
 105                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 106                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 107                                               &phy_id_low);
 108                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 109                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 110         }
 111         return status;
 112 }
 113
 114 /**
 115  *  ixgbe_get_phy_type_from_id - Get the phy type
 116  *  @hw: pointer to hardware structure
 117  *
 118  **/
 119 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 120 {
 121         enum ixgbe_phy_type phy_type;
 122
 123         switch (phy_id) {
 124         case TN1010_PHY_ID:
 125                 phy_type = ixgbe_phy_tn;
 126                 break;
 127         case QT2022_PHY_ID:
 128                 phy_type = ixgbe_phy_qt;
 129                 break;
 130         default:
 131                 phy_type = ixgbe_phy_unknown;
 132                 break;
 133         }
 134
 135         return phy_type;
 136 }
 137
 138 /**
 139  *  ixgbe_reset_phy_generic - Performs a PHY reset
 140  *  @hw: pointer to hardware structure
 141  **/
 142 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 143 {
 144         /*
 145          * Perform soft PHY reset to the PHY_XS.
 146          * This will cause a soft reset to the PHY
 147          */
 148         return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 149                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 150                                      IXGBE_MDIO_PHY_XS_RESET);
 151 }
 152
 153 /**
 154  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 155  *  @hw: pointer to hardware structure
 156  *  @reg_addr: 32 bit address of PHY register to read
 157  *  @phy_data: Pointer to read data from PHY register
 158  **/
 159 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 160                                u32 device_type, u16 *phy_data)
 161 {
 162         u32 command;
 163         u32 i;
 164         u32 data;
 165         s32 status = 0;
 166         u16 gssr;
 167
 168         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 169                 gssr = IXGBE_GSSR_PHY1_SM;
 170         else
 171                 gssr = IXGBE_GSSR_PHY0_SM;
 172
 173         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 174                 status = IXGBE_ERR_SWFW_SYNC;
 175
 176         if (status == 0) {
 177                 /* Setup and write the address cycle command */
 178                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 179                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 180                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 181                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 182
 183                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 184
 185                 /*
 186                  * Check every 10 usec to see if the address cycle completed.
 187                  * The MDI Command bit will clear when the operation is
 188                  * complete
 189                  */
 190                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 191                         udelay(10);
 192
 193                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 194
 195                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 196                                 break;
 197                 }
 198
 199                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 200                         hw_dbg(hw, "PHY address command did not complete.\n");
 201                         status = IXGBE_ERR_PHY;
 202                 }
 203
 204                 if (status == 0) {
 205                         /*
 206                          * Address cycle complete, setup and write the read
 207                          * command
 208                          */
 209                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 210                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 211                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 212                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 213
 214                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 215
 216                         /*
 217                          * Check every 10 usec to see if the address cycle
 218                          * completed. The MDI Command bit will clear when the
 219                          * operation is complete
 220                          */
 221                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 222                                 udelay(10);
 223
 224                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 225
 226                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 227                                         break;
 228                         }
 229
 230                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 231                                 hw_dbg(hw, "PHY read command didn't complete\n");
 232                                 status = IXGBE_ERR_PHY;
 233                         } else {
 234                                 /*
 235                                  * Read operation is complete.  Get the data
 236                                  * from MSRWD
 237                                  */
 238                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 239                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 240                                 *phy_data = (u16)(data);
 241                         }
 242                 }
 243
 244                 ixgbe_release_swfw_sync(hw, gssr);
 245         }
 246
 247         return status;
 248 }
 249
 250 /**
 251  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 252  *  @hw: pointer to hardware structure
 253  *  @reg_addr: 32 bit PHY register to write
 254  *  @device_type: 5 bit device type
 255  *  @phy_data: Data to write to the PHY register
 256  **/
 257 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 258                                 u32 device_type, u16 phy_data)
 259 {
 260         u32 command;
 261         u32 i;
 262         s32 status = 0;
 263         u16 gssr;
 264
 265         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 266                 gssr = IXGBE_GSSR_PHY1_SM;
 267         else
 268                 gssr = IXGBE_GSSR_PHY0_SM;
 269
 270         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 271                 status = IXGBE_ERR_SWFW_SYNC;
 272
 273         if (status == 0) {
 274                 /* Put the data in the MDI single read and write data register*/
 275                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 276
 277                 /* Setup and write the address cycle command */
 278                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 279                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 280                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 281                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 282
 283                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 284
 285                 /*
 286                  * Check every 10 usec to see if the address cycle completed.
 287                  * The MDI Command bit will clear when the operation is
 288                  * complete
 289                  */
 290                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 291                         udelay(10);
 292
 293                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 294
 295                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 296                                 break;
 297                 }
 298
 299                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 300                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 301                         status = IXGBE_ERR_PHY;
 302                 }
 303
 304                 if (status == 0) {
 305                         /*
 306                          * Address cycle complete, setup and write the write
 307                          * command
 308                          */
 309                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 310                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 311                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 312                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 313
 314                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 315
 316                         /*
 317                          * Check every 10 usec to see if the address cycle
 318                          * completed. The MDI Command bit will clear when the
 319                          * operation is complete
 320                          */
 321                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 322                                 udelay(10);
 323
 324                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 325
 326                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 327                                         break;
 328                         }
 329
 330                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 331                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 332                                 status = IXGBE_ERR_PHY;
 333                         }
 334                 }
 335
 336                 ixgbe_release_swfw_sync(hw, gssr);
 337         }
 338
 339         return status;
 340 }
 341
 342 /**
 343  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 344  *  @hw: pointer to hardware structure
 345  *
 346  *  Restart autonegotiation and PHY and waits for completion.
 347  **/
 348 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 349 {
 350         s32 status = IXGBE_NOT_IMPLEMENTED;
 351         u32 time_out;
 352         u32 max_time_out = 10;
 353         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 354
 355         /*
 356          * Set advertisement settings in PHY based on autoneg_advertised
 357          * settings. If autoneg_advertised = 0, then advertise default values
 358          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 359          * for a 1G.
 360          */
 361         hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 362                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 363
 364         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 365                 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
 366         else
 367                 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
 368
 369         hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 370                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 371
 372         /* Restart PHY autonegotiation and wait for completion */
 373         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 374                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 375
 376         autoneg_reg |= IXGBE_MII_RESTART;
 377
 378         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 379                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 380
 381         /* Wait for autonegotiation to finish */
 382         for (time_out = 0; time_out < max_time_out; time_out++) {
 383                 udelay(10);
 384                 /* Restart PHY autonegotiation and wait for completion */
 385                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 386                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 387                                               &autoneg_reg);
 388
 389                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 390                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
 391                         status = 0;
 392                         break;
 393                 }
 394         }
 395
 396         if (time_out == max_time_out)
 397                 status = IXGBE_ERR_LINK_SETUP;
 398
 399         return status;
 400 }
 401
 402 /**
 403  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 404  *  @hw: pointer to hardware structure
 405  *  @speed: new link speed
 406  *  @autoneg: true if autonegotiation enabled
 407  **/
 408 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 409                                        ixgbe_link_speed speed,
 410                                        bool autoneg,
 411                                        bool autoneg_wait_to_complete)
 412 {
 413
 414         /*
 415          * Clear autoneg_advertised and set new values based on input link
 416          * speed.
 417          */
 418         hw->phy.autoneg_advertised = 0;
 419
 420         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 421                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 422
 423         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 424                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 425
 426         /* Setup link based on the new speed settings */
 427         hw->phy.ops.setup_link(hw);
 428
 429         return 0;
 430 }
 431
 432 /**
 433  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 434  *  @hw: pointer to hardware structure
 435  *
 436  *  Reads the VS1 register to determine if link is up and the current speed for
 437  *  the PHY.
 438  **/
 439 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 440                              bool *link_up)
 441 {
 442         s32 status = 0;
 443         u32 time_out;
 444         u32 max_time_out = 10;
 445         u16 phy_link = 0;
 446         u16 phy_speed = 0;
 447         u16 phy_data = 0;
 448
 449         /* Initialize speed and link to default case */
 450         *link_up = false;
 451         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 452
 453         /*
 454          * Check current speed and link status of the PHY register.
 455          * This is a vendor specific register and may have to
 456          * be changed for other copper PHYs.
 457          */
 458         for (time_out = 0; time_out < max_time_out; time_out++) {
 459                 udelay(10);
 460                 status = hw->phy.ops.read_reg(hw,
 461                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 462                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 463                                         &phy_data);
 464                 phy_link = phy_data &
 465                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 466                 phy_speed = phy_data &
 467                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 468                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 469                         *link_up = true;
 470                         if (phy_speed ==
 471                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 472                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 473                         break;
 474                 }
 475         }
 476
 477         return status;
 478 }
 479
 480 /**
 481  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 482  *  @hw: pointer to hardware structure
 483  *  @firmware_version: pointer to the PHY Firmware Version
 484  **/
 485 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 486                                        u16 *firmware_version)
 487 {
 488         s32 status = 0;
 489
 490         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 491                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 492                                       firmware_version);
 493
 494         return status;
 495 }
 496