1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
54 * Determines the physical layer module found on the current adapter.
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63 hw->phy.mdio.prtad = phy_addr;
64 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
67 ixgbe_get_phy_type_from_id(hw->phy.id);
72 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0;
82 * ixgbe_get_phy_id - Get the phy type
83 * @hw: pointer to hardware structure
86 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
92 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
96 hw->phy.id = (u32)(phy_id_high << 16);
97 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
99 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
100 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
106 * ixgbe_get_phy_type_from_id - Get the phy type
107 * @hw: pointer to hardware structure
110 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
112 enum ixgbe_phy_type phy_type;
116 phy_type = ixgbe_phy_tn;
119 phy_type = ixgbe_phy_qt;
122 phy_type = ixgbe_phy_nl;
125 phy_type = ixgbe_phy_unknown;
133 * ixgbe_reset_phy_generic - Performs a PHY reset
134 * @hw: pointer to hardware structure
136 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
138 /* Don't reset PHY if it's shut down due to overtemp. */
139 if (!hw->phy.reset_if_overtemp &&
140 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
144 * Perform soft PHY reset to the PHY_XS.
145 * This will cause a soft reset to the PHY
147 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
152 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
153 * @hw: pointer to hardware structure
154 * @reg_addr: 32 bit address of PHY register to read
155 * @phy_data: Pointer to read data from PHY register
157 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
158 u32 device_type, u16 *phy_data)
166 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
167 gssr = IXGBE_GSSR_PHY1_SM;
169 gssr = IXGBE_GSSR_PHY0_SM;
171 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
172 status = IXGBE_ERR_SWFW_SYNC;
175 /* Setup and write the address cycle command */
176 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
177 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
178 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
179 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
181 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
184 * Check every 10 usec to see if the address cycle completed.
185 * The MDI Command bit will clear when the operation is
188 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
191 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
193 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
197 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
198 hw_dbg(hw, "PHY address command did not complete.\n");
199 status = IXGBE_ERR_PHY;
204 * Address cycle complete, setup and write the read
207 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
208 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
209 (hw->phy.mdio.prtad <<
210 IXGBE_MSCA_PHY_ADDR_SHIFT) |
211 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
213 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
216 * Check every 10 usec to see if the address cycle
217 * completed. The MDI Command bit will clear when the
218 * operation is complete
220 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
223 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
225 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
229 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
230 hw_dbg(hw, "PHY read command didn't complete\n");
231 status = IXGBE_ERR_PHY;
234 * Read operation is complete. Get the data
237 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
238 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
239 *phy_data = (u16)(data);
243 ixgbe_release_swfw_sync(hw, gssr);
250 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
251 * @hw: pointer to hardware structure
252 * @reg_addr: 32 bit PHY register to write
253 * @device_type: 5 bit device type
254 * @phy_data: Data to write to the PHY register
256 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
257 u32 device_type, u16 phy_data)
264 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
265 gssr = IXGBE_GSSR_PHY1_SM;
267 gssr = IXGBE_GSSR_PHY0_SM;
269 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
270 status = IXGBE_ERR_SWFW_SYNC;
273 /* Put the data in the MDI single read and write data register*/
274 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
276 /* Setup and write the address cycle command */
277 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
278 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
279 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
280 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
282 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
285 * Check every 10 usec to see if the address cycle completed.
286 * The MDI Command bit will clear when the operation is
289 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
292 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
294 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
298 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
299 hw_dbg(hw, "PHY address cmd didn't complete\n");
300 status = IXGBE_ERR_PHY;
305 * Address cycle complete, setup and write the write
308 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
309 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
310 (hw->phy.mdio.prtad <<
311 IXGBE_MSCA_PHY_ADDR_SHIFT) |
312 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
314 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
317 * Check every 10 usec to see if the address cycle
318 * completed. The MDI Command bit will clear when the
319 * operation is complete
321 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
324 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
326 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
330 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
331 hw_dbg(hw, "PHY address cmd didn't complete\n");
332 status = IXGBE_ERR_PHY;
336 ixgbe_release_swfw_sync(hw, gssr);
343 * ixgbe_setup_phy_link_generic - Set and restart autoneg
344 * @hw: pointer to hardware structure
346 * Restart autonegotiation and PHY and waits for completion.
348 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
350 s32 status = IXGBE_NOT_IMPLEMENTED;
352 u32 max_time_out = 10;
356 * Set advertisement settings in PHY based on autoneg_advertised
357 * settings. If autoneg_advertised = 0, then advertise default values
358 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
361 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
363 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
364 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
366 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
368 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
370 /* Restart PHY autonegotiation and wait for completion */
371 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
373 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
375 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
377 /* Wait for autonegotiation to finish */
378 for (time_out = 0; time_out < max_time_out; time_out++) {
380 /* Restart PHY autonegotiation and wait for completion */
381 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
384 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
385 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
391 if (time_out == max_time_out)
392 status = IXGBE_ERR_LINK_SETUP;
398 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
399 * @hw: pointer to hardware structure
400 * @speed: new link speed
401 * @autoneg: true if autonegotiation enabled
403 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
404 ixgbe_link_speed speed,
406 bool autoneg_wait_to_complete)
410 * Clear autoneg_advertised and set new values based on input link
413 hw->phy.autoneg_advertised = 0;
415 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
416 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
418 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
419 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
421 /* Setup link based on the new speed settings */
422 hw->phy.ops.setup_link(hw);
428 * ixgbe_reset_phy_nl - Performs a PHY reset
429 * @hw: pointer to hardware structure
431 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
433 u16 phy_offset, control, eword, edata, block_crc;
434 bool end_data = false;
435 u16 list_offset, data_offset;
440 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
442 /* reset the PHY and poll for completion */
443 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
444 (phy_data | MDIO_CTRL1_RESET));
446 for (i = 0; i < 100; i++) {
447 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
449 if ((phy_data & MDIO_CTRL1_RESET) == 0)
454 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
455 hw_dbg(hw, "PHY reset did not complete.\n");
456 ret_val = IXGBE_ERR_PHY;
460 /* Get init offsets */
461 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
466 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
470 * Read control word from PHY init contents offset
472 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
473 control = (eword & IXGBE_CONTROL_MASK_NL) >>
474 IXGBE_CONTROL_SHIFT_NL;
475 edata = eword & IXGBE_DATA_MASK_NL;
479 hw_dbg(hw, "DELAY: %d MS\n", edata);
483 hw_dbg(hw, "DATA:\n");
485 hw->eeprom.ops.read(hw, data_offset++,
487 for (i = 0; i < edata; i++) {
488 hw->eeprom.ops.read(hw, data_offset, &eword);
489 hw->phy.ops.write_reg(hw, phy_offset,
490 MDIO_MMD_PMAPMD, eword);
491 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
497 case IXGBE_CONTROL_NL:
499 hw_dbg(hw, "CONTROL:\n");
500 if (edata == IXGBE_CONTROL_EOL_NL) {
503 } else if (edata == IXGBE_CONTROL_SOL_NL) {
506 hw_dbg(hw, "Bad control value\n");
507 ret_val = IXGBE_ERR_PHY;
512 hw_dbg(hw, "Bad control type\n");
513 ret_val = IXGBE_ERR_PHY;
523 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
525 * @hw: pointer to hardware structure
527 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
529 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
531 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
533 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
535 u8 comp_codes_1g = 0;
536 u8 comp_codes_10g = 0;
537 u8 oui_bytes[3] = {0, 0, 0};
542 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
543 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
544 status = IXGBE_ERR_SFP_NOT_PRESENT;
548 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
551 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
552 status = IXGBE_ERR_SFP_NOT_PRESENT;
553 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
554 if (hw->phy.type != ixgbe_phy_nl) {
556 hw->phy.type = ixgbe_phy_unknown;
561 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
562 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
564 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
566 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
574 * 3 SFP_DA_CORE0 - 82599-specific
575 * 4 SFP_DA_CORE1 - 82599-specific
576 * 5 SFP_SR/LR_CORE0 - 82599-specific
577 * 6 SFP_SR/LR_CORE1 - 82599-specific
579 if (hw->mac.type == ixgbe_mac_82598EB) {
580 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
581 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
582 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
583 hw->phy.sfp_type = ixgbe_sfp_type_sr;
584 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
585 hw->phy.sfp_type = ixgbe_sfp_type_lr;
587 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
588 } else if (hw->mac.type == ixgbe_mac_82599EB) {
589 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
590 if (hw->bus.lan_id == 0)
592 ixgbe_sfp_type_da_cu_core0;
595 ixgbe_sfp_type_da_cu_core1;
596 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
597 hw->phy.ops.read_i2c_eeprom(
598 hw, IXGBE_SFF_CABLE_SPEC_COMP,
601 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
602 if (hw->bus.lan_id == 0)
604 ixgbe_sfp_type_da_act_lmt_core0;
607 ixgbe_sfp_type_da_act_lmt_core1;
610 ixgbe_sfp_type_unknown;
612 } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
613 if (hw->bus.lan_id == 0)
615 ixgbe_sfp_type_srlr_core0;
618 ixgbe_sfp_type_srlr_core1;
619 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
620 if (hw->bus.lan_id == 0)
622 ixgbe_sfp_type_srlr_core0;
625 ixgbe_sfp_type_srlr_core1;
627 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
630 if (hw->phy.sfp_type != stored_sfp_type)
631 hw->phy.sfp_setup_needed = true;
633 /* Determine if the SFP+ PHY is dual speed or not. */
634 hw->phy.multispeed_fiber = false;
635 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
636 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
637 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
638 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
639 hw->phy.multispeed_fiber = true;
641 /* Determine PHY vendor */
642 if (hw->phy.type != ixgbe_phy_nl) {
643 hw->phy.id = identifier;
644 hw->phy.ops.read_i2c_eeprom(hw,
645 IXGBE_SFF_VENDOR_OUI_BYTE0,
647 hw->phy.ops.read_i2c_eeprom(hw,
648 IXGBE_SFF_VENDOR_OUI_BYTE1,
650 hw->phy.ops.read_i2c_eeprom(hw,
651 IXGBE_SFF_VENDOR_OUI_BYTE2,
655 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
656 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
657 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
659 switch (vendor_oui) {
660 case IXGBE_SFF_VENDOR_OUI_TYCO:
661 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
663 ixgbe_phy_sfp_passive_tyco;
665 case IXGBE_SFF_VENDOR_OUI_FTL:
666 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
667 hw->phy.type = ixgbe_phy_sfp_ftl_active;
669 hw->phy.type = ixgbe_phy_sfp_ftl;
671 case IXGBE_SFF_VENDOR_OUI_AVAGO:
672 hw->phy.type = ixgbe_phy_sfp_avago;
674 case IXGBE_SFF_VENDOR_OUI_INTEL:
675 hw->phy.type = ixgbe_phy_sfp_intel;
678 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
680 ixgbe_phy_sfp_passive_unknown;
681 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
683 ixgbe_phy_sfp_active_unknown;
685 hw->phy.type = ixgbe_phy_sfp_unknown;
690 /* All passive DA cables are supported */
691 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
692 IXGBE_SFF_DA_ACTIVE_CABLE)) {
697 /* 1G SFP modules are not supported */
698 if (comp_codes_10g == 0) {
699 hw->phy.type = ixgbe_phy_sfp_unsupported;
700 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
704 /* Anything else 82598-based is supported */
705 if (hw->mac.type == ixgbe_mac_82598EB) {
710 /* This is guaranteed to be 82599, no need to check for NULL */
711 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
712 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
713 /* Make sure we're a supported PHY type */
714 if (hw->phy.type == ixgbe_phy_sfp_intel) {
717 hw_dbg(hw, "SFP+ module not supported\n");
718 hw->phy.type = ixgbe_phy_sfp_unsupported;
719 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
731 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
732 * if it supports a given SFP+ module type, if so it returns the offsets to the
733 * phy init sequence block.
734 * @hw: pointer to hardware structure
735 * @list_offset: offset to the SFP ID list
736 * @data_offset: offset to the SFP data block
738 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
744 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
745 return IXGBE_ERR_SFP_NOT_SUPPORTED;
747 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
748 return IXGBE_ERR_SFP_NOT_PRESENT;
750 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
751 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
752 return IXGBE_ERR_SFP_NOT_SUPPORTED;
754 /* Read offset to PHY init contents */
755 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
757 if ((!*list_offset) || (*list_offset == 0xFFFF))
758 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
760 /* Shift offset to first ID word */
764 * Find the matching SFP ID in the EEPROM
765 * and program the init sequence
767 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
769 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
770 if (sfp_id == hw->phy.sfp_type) {
772 hw->eeprom.ops.read(hw, *list_offset, data_offset);
773 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
774 hw_dbg(hw, "SFP+ module not supported\n");
775 return IXGBE_ERR_SFP_NOT_SUPPORTED;
781 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
782 return IXGBE_ERR_PHY;
786 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
787 hw_dbg(hw, "No matching SFP+ module found\n");
788 return IXGBE_ERR_SFP_NOT_SUPPORTED;
795 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
796 * @hw: pointer to hardware structure
797 * @byte_offset: EEPROM byte offset to read
798 * @eeprom_data: value read
800 * Performs byte read operation to SFP module's EEPROM over I2C interface.
802 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
805 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
806 IXGBE_I2C_EEPROM_DEV_ADDR,
811 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
812 * @hw: pointer to hardware structure
813 * @byte_offset: EEPROM byte offset to write
814 * @eeprom_data: value to write
816 * Performs byte write operation to SFP module's EEPROM over I2C interface.
818 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
821 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
822 IXGBE_I2C_EEPROM_DEV_ADDR,
827 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
828 * @hw: pointer to hardware structure
829 * @byte_offset: byte offset to read
832 * Performs byte read operation to SFP module's EEPROM over I2C interface at
833 * a specified deivce address.
835 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
836 u8 dev_addr, u8 *data)
846 /* Device Address and write indication */
847 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
851 status = ixgbe_get_i2c_ack(hw);
855 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
859 status = ixgbe_get_i2c_ack(hw);
865 /* Device Address and read indication */
866 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
870 status = ixgbe_get_i2c_ack(hw);
874 status = ixgbe_clock_in_i2c_byte(hw, data);
878 status = ixgbe_clock_out_i2c_bit(hw, nack);
886 ixgbe_i2c_bus_clear(hw);
888 if (retry < max_retry)
889 hw_dbg(hw, "I2C byte read error - Retrying.\n");
891 hw_dbg(hw, "I2C byte read error.\n");
893 } while (retry < max_retry);
899 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
900 * @hw: pointer to hardware structure
901 * @byte_offset: byte offset to write
902 * @data: value to write
904 * Performs byte write operation to SFP module's EEPROM over I2C interface at
905 * a specified device address.
907 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
908 u8 dev_addr, u8 data)
917 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
921 status = ixgbe_get_i2c_ack(hw);
925 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
929 status = ixgbe_get_i2c_ack(hw);
933 status = ixgbe_clock_out_i2c_byte(hw, data);
937 status = ixgbe_get_i2c_ack(hw);
945 ixgbe_i2c_bus_clear(hw);
947 if (retry < max_retry)
948 hw_dbg(hw, "I2C byte write error - Retrying.\n");
950 hw_dbg(hw, "I2C byte write error.\n");
951 } while (retry < max_retry);
957 * ixgbe_i2c_start - Sets I2C start condition
958 * @hw: pointer to hardware structure
960 * Sets I2C start condition (High -> Low on SDA while SCL is High)
962 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
964 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
966 /* Start condition must begin with data and clock high */
967 ixgbe_set_i2c_data(hw, &i2cctl, 1);
968 ixgbe_raise_i2c_clk(hw, &i2cctl);
970 /* Setup time for start condition (4.7us) */
971 udelay(IXGBE_I2C_T_SU_STA);
973 ixgbe_set_i2c_data(hw, &i2cctl, 0);
975 /* Hold time for start condition (4us) */
976 udelay(IXGBE_I2C_T_HD_STA);
978 ixgbe_lower_i2c_clk(hw, &i2cctl);
980 /* Minimum low period of clock is 4.7 us */
981 udelay(IXGBE_I2C_T_LOW);
986 * ixgbe_i2c_stop - Sets I2C stop condition
987 * @hw: pointer to hardware structure
989 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
991 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
993 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
995 /* Stop condition must begin with data low and clock high */
996 ixgbe_set_i2c_data(hw, &i2cctl, 0);
997 ixgbe_raise_i2c_clk(hw, &i2cctl);
999 /* Setup time for stop condition (4us) */
1000 udelay(IXGBE_I2C_T_SU_STO);
1002 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1004 /* bus free time between stop and start (4.7us)*/
1005 udelay(IXGBE_I2C_T_BUF);
1009 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1010 * @hw: pointer to hardware structure
1011 * @data: data byte to clock in
1013 * Clocks in one byte data via I2C data/clock
1015 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1021 for (i = 7; i >= 0; i--) {
1022 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1033 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1034 * @hw: pointer to hardware structure
1035 * @data: data byte clocked out
1037 * Clocks out one byte data via I2C data/clock
1039 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1046 for (i = 7; i >= 0; i--) {
1047 bit = (data >> i) & 0x1;
1048 status = ixgbe_clock_out_i2c_bit(hw, bit);
1054 /* Release SDA line (set high) */
1055 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1056 i2cctl |= IXGBE_I2C_DATA_OUT;
1057 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1063 * ixgbe_get_i2c_ack - Polls for I2C ACK
1064 * @hw: pointer to hardware structure
1066 * Clocks in/out one bit via I2C data/clock
1068 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1072 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1076 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1081 /* Minimum high period of clock is 4us */
1082 udelay(IXGBE_I2C_T_HIGH);
1084 /* Poll for ACK. Note that ACK in I2C spec is
1085 * transition from 1 to 0 */
1086 for (i = 0; i < timeout; i++) {
1087 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1088 ack = ixgbe_get_i2c_data(&i2cctl);
1096 hw_dbg(hw, "I2C ack was not received.\n");
1097 status = IXGBE_ERR_I2C;
1100 ixgbe_lower_i2c_clk(hw, &i2cctl);
1102 /* Minimum low period of clock is 4.7 us */
1103 udelay(IXGBE_I2C_T_LOW);
1110 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1111 * @hw: pointer to hardware structure
1112 * @data: read data value
1114 * Clocks in one bit via I2C data/clock
1116 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1119 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1121 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1123 /* Minimum high period of clock is 4us */
1124 udelay(IXGBE_I2C_T_HIGH);
1126 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1127 *data = ixgbe_get_i2c_data(&i2cctl);
1129 ixgbe_lower_i2c_clk(hw, &i2cctl);
1131 /* Minimum low period of clock is 4.7 us */
1132 udelay(IXGBE_I2C_T_LOW);
1138 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1139 * @hw: pointer to hardware structure
1140 * @data: data value to write
1142 * Clocks out one bit via I2C data/clock
1144 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1147 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1149 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1151 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1153 /* Minimum high period of clock is 4us */
1154 udelay(IXGBE_I2C_T_HIGH);
1156 ixgbe_lower_i2c_clk(hw, &i2cctl);
1158 /* Minimum low period of clock is 4.7 us.
1159 * This also takes care of the data hold time.
1161 udelay(IXGBE_I2C_T_LOW);
1163 status = IXGBE_ERR_I2C;
1164 hw_dbg(hw, "I2C data was not set to %X\n", data);
1170 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1171 * @hw: pointer to hardware structure
1172 * @i2cctl: Current value of I2CCTL register
1174 * Raises the I2C clock line '0'->'1'
1176 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1180 *i2cctl |= IXGBE_I2C_CLK_OUT;
1182 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1184 /* SCL rise time (1000ns) */
1185 udelay(IXGBE_I2C_T_RISE);
1191 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1192 * @hw: pointer to hardware structure
1193 * @i2cctl: Current value of I2CCTL register
1195 * Lowers the I2C clock line '1'->'0'
1197 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1200 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1202 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1204 /* SCL fall time (300ns) */
1205 udelay(IXGBE_I2C_T_FALL);
1209 * ixgbe_set_i2c_data - Sets the I2C data bit
1210 * @hw: pointer to hardware structure
1211 * @i2cctl: Current value of I2CCTL register
1212 * @data: I2C data value (0 or 1) to set
1214 * Sets the I2C data bit
1216 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1221 *i2cctl |= IXGBE_I2C_DATA_OUT;
1223 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1225 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1227 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1228 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1230 /* Verify data was set correctly */
1231 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1232 if (data != ixgbe_get_i2c_data(i2cctl)) {
1233 status = IXGBE_ERR_I2C;
1234 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1241 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1242 * @hw: pointer to hardware structure
1243 * @i2cctl: Current value of I2CCTL register
1245 * Returns the I2C data bit value
1247 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1251 if (*i2cctl & IXGBE_I2C_DATA_IN)
1260 * ixgbe_i2c_bus_clear - Clears the I2C bus
1261 * @hw: pointer to hardware structure
1263 * Clears the I2C bus by sending nine clock pulses.
1264 * Used when data line is stuck low.
1266 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1268 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1271 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1273 for (i = 0; i < 9; i++) {
1274 ixgbe_raise_i2c_clk(hw, &i2cctl);
1276 /* Min high period of clock is 4us */
1277 udelay(IXGBE_I2C_T_HIGH);
1279 ixgbe_lower_i2c_clk(hw, &i2cctl);
1281 /* Min low period of clock is 4.7us*/
1282 udelay(IXGBE_I2C_T_LOW);
1285 /* Put the i2c bus back to default state */
1290 * ixgbe_check_phy_link_tnx - Determine link and speed status
1291 * @hw: pointer to hardware structure
1293 * Reads the VS1 register to determine if link is up and the current speed for
1296 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1301 u32 max_time_out = 10;
1306 /* Initialize speed and link to default case */
1308 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1311 * Check current speed and link status of the PHY register.
1312 * This is a vendor specific register and may have to
1313 * be changed for other copper PHYs.
1315 for (time_out = 0; time_out < max_time_out; time_out++) {
1317 status = hw->phy.ops.read_reg(hw,
1318 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1321 phy_link = phy_data &
1322 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1323 phy_speed = phy_data &
1324 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1325 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1328 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1329 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1338 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1339 * @hw: pointer to hardware structure
1340 * @firmware_version: pointer to the PHY Firmware Version
1342 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1343 u16 *firmware_version)
1347 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1354 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1355 * @hw: pointer to hardware structure
1357 * Checks if the LASI temp alarm status was triggered due to overtemp
1359 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1364 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1367 /* Check that the LASI temp alarm status was triggered */
1368 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1369 MDIO_MMD_PMAPMD, &phy_data);
1371 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1374 status = IXGBE_ERR_OVERTEMP;