2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_reset_phy_processor(struct jme_adapter *jme)
114 jme_mdio_write(jme->dev,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125 val = jme_mdio_read(jme->dev,
129 jme_mdio_write(jme->dev,
131 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
204 jme_clear_pm(struct jme_adapter *jme)
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
212 jme_reload_eeprom(struct jme_adapter *jme)
217 val = jread32(jme, JME_SMBCSR);
219 if (val & SMBCSR_EEPROMD) {
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device *netdev)
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
295 jme_start_irq(struct jme_adapter *jme)
297 register struct dynpcc_info *dpi = &(jme->dpi);
299 jme_set_rx_pcc(jme, PCC_P1);
301 dpi->attempt = PCC_P1;
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
317 jme_stop_irq(struct jme_adapter *jme)
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326 jme_linkstat_from_phy(struct jme_adapter *jme)
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
339 jme_set_phyfifoa(struct jme_adapter *jme)
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345 jme_set_phyfifob(struct jme_adapter *jme)
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351 jme_check_link(struct net_device *netdev, int testonly)
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
361 phylink = jme_linkstat_from_phy(jme);
363 phylink = jread32(jme, JME_PHY_LINK);
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
371 phylink = PHY_LINK_UP;
373 bmcr = jme_mdio_read(jme->dev,
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
387 strcat(linkmsg, "Forced: ");
390 * Keep polling for speed/duplex resolve complete
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
398 phylink = jme_linkstat_from_phy(jme);
400 phylink = jread32(jme, JME_PHY_LINK);
404 "Waiting speed resolve timeout.\n");
406 strcat(linkmsg, "ANed: ");
409 if (jme->phylink == phylink) {
416 jme->phylink = phylink;
418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
425 strcat(linkmsg, "10 Mbps, ");
427 case PHY_LINK_SPEED_100M:
428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
430 strcat(linkmsg, "100 Mbps, ");
432 case PHY_LINK_SPEED_1000M:
433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
435 strcat(linkmsg, "1000 Mbps, ");
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
492 netif_info(jme, link, jme->dev, "Link is down.\n");
494 netif_carrier_off(netdev);
502 jme_setup_tx_resources(struct jme_adapter *jme)
504 struct jme_ring *txring = &(jme->txring[0]);
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
530 * Initialize Transmit Descriptors
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
546 txring->dmaalloc = 0;
548 txring->bufinf = NULL;
554 jme_free_tx_resources(struct jme_adapter *jme)
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
565 dev_kfree_skb(txbi->skb);
571 txbi->start_xmit = 0;
573 kfree(txring->bufinf);
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
581 txring->alloc = NULL;
583 txring->dmaalloc = 0;
585 txring->bufinf = NULL;
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
593 jme_enable_tx_engine(struct jme_adapter *jme)
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
602 * Setup TX Queue 0 DMA Bass Address
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
609 * Setup TX Descptor Count
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
624 jme_restart_tx_engine(struct jme_adapter *jme)
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
635 jme_disable_tx_engine(struct jme_adapter *jme)
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
649 val = jread32(jme, JME_TXCS);
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
658 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
679 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
691 rxbi->len = skb_tailroom(skb);
692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
702 jme_free_rx_buf(struct jme_adapter *jme, int i)
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
709 pci_unmap_page(jme->pdev,
713 dev_kfree_skb(rxbi->skb);
721 jme_free_rx_resources(struct jme_adapter *jme)
724 struct jme_ring *rxring = &(jme->rxring[0]);
727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
733 dma_free_coherent(&(jme->pdev->dev),
734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
737 rxring->alloc = NULL;
739 rxring->dmaalloc = 0;
741 rxring->bufinf = NULL;
743 rxring->next_to_use = 0;
744 atomic_set(&rxring->next_to_clean, 0);
748 jme_setup_rx_resources(struct jme_adapter *jme)
751 struct jme_ring *rxring = &(jme->rxring[0]);
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
766 rxring->next_to_use = 0;
767 atomic_set(&rxring->next_to_clean, 0);
769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
775 * Initiallize Receive Descriptors
777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
781 jme_free_rx_resources(jme);
785 jme_set_clean_rxdesc(jme, i);
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
797 rxring->dmaalloc = 0;
799 rxring->bufinf = NULL;
805 jme_enable_rx_engine(struct jme_adapter *jme)
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
815 * Setup RX DMA Bass Address
817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
822 * Setup RX Descriptor Count
824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
827 * Setup Unicast Filter
829 jme_set_multi(jme->dev);
835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
842 jme_restart_rx_engine(struct jme_adapter *jme)
847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
854 jme_disable_rx_engine(struct jme_adapter *jme)
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
865 val = jread32(jme, JME_RXCS);
866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
868 val = jread32(jme, JME_RXCS);
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
878 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
886 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
893 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
899 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
907 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
909 struct jme_ring *rxring = &(jme->rxring[0]);
910 struct rxdesc *rxdesc = rxring->desc;
911 struct jme_buffer_info *rxbi = rxring->bufinf;
919 pci_dma_sync_single_for_cpu(jme->pdev,
924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
925 pci_dma_sync_single_for_device(jme->pdev,
930 ++(NET_STAT(jme).rx_dropped);
932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
940 skb->ip_summed = CHECKSUM_UNNECESSARY;
942 skb->ip_summed = CHECKSUM_NONE;
944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
946 jme->jme_vlan_rx(skb, jme->vlgrp,
947 le16_to_cpu(rxdesc->descwb.vlan));
948 NET_STAT(jme).rx_bytes += 4;
956 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
957 cpu_to_le16(RXWBFLAG_DEST_MUL))
958 ++(NET_STAT(jme).multicast);
960 NET_STAT(jme).rx_bytes += framesize;
961 ++(NET_STAT(jme).rx_packets);
964 jme_set_clean_rxdesc(jme, idx);
969 jme_process_receive(struct jme_adapter *jme, int limit)
971 struct jme_ring *rxring = &(jme->rxring[0]);
972 struct rxdesc *rxdesc = rxring->desc;
973 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
975 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
978 if (unlikely(atomic_read(&jme->link_changing) != 1))
981 if (unlikely(!netif_carrier_ok(jme->dev)))
984 i = atomic_read(&rxring->next_to_clean);
986 rxdesc = rxring->desc;
989 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
990 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
996 if (unlikely(desccnt > 1 ||
997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000 ++(NET_STAT(jme).rx_crc_errors);
1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002 ++(NET_STAT(jme).rx_fifo_errors);
1004 ++(NET_STAT(jme).rx_errors);
1007 limit -= desccnt - 1;
1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010 jme_set_clean_rxdesc(jme, j);
1011 j = (j + 1) & (mask);
1015 jme_alloc_and_feed_skb(jme, i);
1018 i = (i + desccnt) & (mask);
1022 atomic_set(&rxring->next_to_clean, i);
1025 atomic_inc(&jme->rx_cleaning);
1027 return limit > 0 ? limit : 0;
1032 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1034 if (likely(atmp == dpi->cur)) {
1039 if (dpi->attempt == atmp) {
1042 dpi->attempt = atmp;
1049 jme_dynamic_pcc(struct jme_adapter *jme)
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P3);
1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1057 jme_attempt_pcc(dpi, PCC_P2);
1059 jme_attempt_pcc(dpi, PCC_P1);
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1071 jme_start_pcc_timer(struct jme_adapter *jme)
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1082 jme_stop_pcc_timer(struct jme_adapter *jme)
1084 jwrite32(jme, JME_TMCSR, 0);
1088 jme_shutdown_nic(struct jme_adapter *jme)
1092 phylink = jme_linkstat_from_phy(jme);
1094 if (!(phylink & PHY_LINK_UP)) {
1096 * Disable all interrupt before issue timer
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1104 jme_pcc_tasklet(unsigned long arg)
1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
1107 struct net_device *netdev = jme->dev;
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1114 if (unlikely(!netif_carrier_ok(netdev) ||
1115 (atomic_read(&jme->link_changing) != 1)
1117 jme_stop_pcc_timer(jme);
1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122 jme_dynamic_pcc(jme);
1124 jme_start_pcc_timer(jme);
1128 jme_polling_mode(struct jme_adapter *jme)
1130 jme_set_rx_pcc(jme, PCC_OFF);
1134 jme_interrupt_mode(struct jme_adapter *jme)
1136 jme_set_rx_pcc(jme, PCC_P1);
1140 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1148 jme_start_shutdown_timer(struct jme_adapter *jme)
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1158 jwrite32f(jme, JME_APMC, apmc);
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1167 jme_stop_shutdown_timer(struct jme_adapter *jme)
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1179 jwrite32f(jme, JME_APMC, apmc);
1183 jme_link_change_tasklet(unsigned long arg)
1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
1186 struct net_device *netdev = jme->dev;
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
1191 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1192 while (atomic_read(&jme->link_changing) != 1)
1193 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1199 jme->old_mtu = netdev->mtu;
1200 netif_stop_queue(netdev);
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_polling_mode(jme);
1220 netif_carrier_off(netdev);
1223 jme_check_link(netdev, 0);
1224 if (netif_carrier_ok(netdev)) {
1225 rc = jme_setup_rx_resources(jme);
1227 jeprintk(jme->pdev, "Allocating resources for RX error"
1228 ", Device STOPPED!\n");
1229 goto out_enable_tasklet;
1232 rc = jme_setup_tx_resources(jme);
1234 jeprintk(jme->pdev, "Allocating resources for TX error"
1235 ", Device STOPPED!\n");
1236 goto err_out_free_rx_resources;
1239 jme_enable_rx_engine(jme);
1240 jme_enable_tx_engine(jme);
1242 netif_start_queue(netdev);
1244 if (test_bit(JME_FLAG_POLL, &jme->flags))
1245 jme_interrupt_mode(jme);
1247 jme_start_pcc_timer(jme);
1248 } else if (jme_pseudo_hotplug_enabled(jme)) {
1249 jme_start_shutdown_timer(jme);
1252 goto out_enable_tasklet;
1254 err_out_free_rx_resources:
1255 jme_free_rx_resources(jme);
1257 tasklet_enable(&jme->txclean_task);
1258 tasklet_hi_enable(&jme->rxclean_task);
1259 tasklet_hi_enable(&jme->rxempty_task);
1261 atomic_inc(&jme->link_changing);
1265 jme_rx_clean_tasklet(unsigned long arg)
1267 struct jme_adapter *jme = (struct jme_adapter *)arg;
1268 struct dynpcc_info *dpi = &(jme->dpi);
1270 jme_process_receive(jme, jme->rx_ring_size);
1276 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1278 struct jme_adapter *jme = jme_napi_priv(holder);
1281 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1283 while (atomic_read(&jme->rx_empty) > 0) {
1284 atomic_dec(&jme->rx_empty);
1285 ++(NET_STAT(jme).rx_dropped);
1286 jme_restart_rx_engine(jme);
1288 atomic_inc(&jme->rx_empty);
1291 JME_RX_COMPLETE(netdev, holder);
1292 jme_interrupt_mode(jme);
1295 JME_NAPI_WEIGHT_SET(budget, rest);
1296 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1300 jme_rx_empty_tasklet(unsigned long arg)
1302 struct jme_adapter *jme = (struct jme_adapter *)arg;
1304 if (unlikely(atomic_read(&jme->link_changing) != 1))
1307 if (unlikely(!netif_carrier_ok(jme->dev)))
1310 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1312 jme_rx_clean_tasklet(arg);
1314 while (atomic_read(&jme->rx_empty) > 0) {
1315 atomic_dec(&jme->rx_empty);
1316 ++(NET_STAT(jme).rx_dropped);
1317 jme_restart_rx_engine(jme);
1319 atomic_inc(&jme->rx_empty);
1323 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1325 struct jme_ring *txring = &(jme->txring[0]);
1328 if (unlikely(netif_queue_stopped(jme->dev) &&
1329 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1330 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1331 netif_wake_queue(jme->dev);
1337 jme_tx_clean_tasklet(unsigned long arg)
1339 struct jme_adapter *jme = (struct jme_adapter *)arg;
1340 struct jme_ring *txring = &(jme->txring[0]);
1341 struct txdesc *txdesc = txring->desc;
1342 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1343 int i, j, cnt = 0, max, err, mask;
1345 tx_dbg(jme, "Into txclean.\n");
1347 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1350 if (unlikely(atomic_read(&jme->link_changing) != 1))
1353 if (unlikely(!netif_carrier_ok(jme->dev)))
1356 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1357 mask = jme->tx_ring_mask;
1359 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1363 if (likely(ctxbi->skb &&
1364 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1366 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1367 i, ctxbi->nr_desc, jiffies);
1369 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1371 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1372 ttxbi = txbi + ((i + j) & (mask));
1373 txdesc[(i + j) & (mask)].dw[0] = 0;
1375 pci_unmap_page(jme->pdev,
1384 dev_kfree_skb(ctxbi->skb);
1386 cnt += ctxbi->nr_desc;
1388 if (unlikely(err)) {
1389 ++(NET_STAT(jme).tx_carrier_errors);
1391 ++(NET_STAT(jme).tx_packets);
1392 NET_STAT(jme).tx_bytes += ctxbi->len;
1397 ctxbi->start_xmit = 0;
1403 i = (i + ctxbi->nr_desc) & mask;
1408 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1409 atomic_set(&txring->next_to_clean, i);
1410 atomic_add(cnt, &txring->nr_free);
1412 jme_wake_queue_if_stopped(jme);
1415 atomic_inc(&jme->tx_cleaning);
1419 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1424 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1426 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1428 * Link change event is critical
1429 * all other events are ignored
1431 jwrite32(jme, JME_IEVE, intrstat);
1432 tasklet_schedule(&jme->linkch_task);
1436 if (intrstat & INTR_TMINTR) {
1437 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1438 tasklet_schedule(&jme->pcc_task);
1441 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1442 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1443 tasklet_schedule(&jme->txclean_task);
1446 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1447 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1453 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1454 if (intrstat & INTR_RX0EMP)
1455 atomic_inc(&jme->rx_empty);
1457 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1458 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1459 jme_polling_mode(jme);
1460 JME_RX_SCHEDULE(jme);
1464 if (intrstat & INTR_RX0EMP) {
1465 atomic_inc(&jme->rx_empty);
1466 tasklet_hi_schedule(&jme->rxempty_task);
1467 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1468 tasklet_hi_schedule(&jme->rxclean_task);
1474 * Re-enable interrupt
1476 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1480 jme_intr(int irq, void *dev_id)
1482 struct net_device *netdev = dev_id;
1483 struct jme_adapter *jme = netdev_priv(netdev);
1486 intrstat = jread32(jme, JME_IEVE);
1489 * Check if it's really an interrupt for us
1491 if (unlikely((intrstat & INTR_ENABLE) == 0))
1495 * Check if the device still exist
1497 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1500 jme_intr_msi(jme, intrstat);
1506 jme_msi(int irq, void *dev_id)
1508 struct net_device *netdev = dev_id;
1509 struct jme_adapter *jme = netdev_priv(netdev);
1512 intrstat = jread32(jme, JME_IEVE);
1514 jme_intr_msi(jme, intrstat);
1520 jme_reset_link(struct jme_adapter *jme)
1522 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1526 jme_restart_an(struct jme_adapter *jme)
1530 spin_lock_bh(&jme->phy_lock);
1531 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1532 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1533 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1534 spin_unlock_bh(&jme->phy_lock);
1538 jme_request_irq(struct jme_adapter *jme)
1541 struct net_device *netdev = jme->dev;
1542 irq_handler_t handler = jme_intr;
1543 int irq_flags = IRQF_SHARED;
1545 if (!pci_enable_msi(jme->pdev)) {
1546 set_bit(JME_FLAG_MSI, &jme->flags);
1551 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1555 "Unable to request %s interrupt (return: %d)\n",
1556 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1559 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1560 pci_disable_msi(jme->pdev);
1561 clear_bit(JME_FLAG_MSI, &jme->flags);
1564 netdev->irq = jme->pdev->irq;
1571 jme_free_irq(struct jme_adapter *jme)
1573 free_irq(jme->pdev->irq, jme->dev);
1574 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1575 pci_disable_msi(jme->pdev);
1576 clear_bit(JME_FLAG_MSI, &jme->flags);
1577 jme->dev->irq = jme->pdev->irq;
1582 jme_open(struct net_device *netdev)
1584 struct jme_adapter *jme = netdev_priv(netdev);
1588 JME_NAPI_ENABLE(jme);
1590 tasklet_enable(&jme->linkch_task);
1591 tasklet_enable(&jme->txclean_task);
1592 tasklet_hi_enable(&jme->rxclean_task);
1593 tasklet_hi_enable(&jme->rxempty_task);
1595 rc = jme_request_irq(jme);
1601 if (test_bit(JME_FLAG_SSET, &jme->flags))
1602 jme_set_settings(netdev, &jme->old_ecmd);
1604 jme_reset_phy_processor(jme);
1606 jme_reset_link(jme);
1611 netif_stop_queue(netdev);
1612 netif_carrier_off(netdev);
1618 jme_set_100m_half(struct jme_adapter *jme)
1622 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1623 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1624 BMCR_SPEED1000 | BMCR_FULLDPLX);
1625 tmp |= BMCR_SPEED100;
1628 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1631 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1633 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1636 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1638 jme_wait_link(struct jme_adapter *jme)
1640 u32 phylink, to = JME_WAIT_LINK_TIME;
1643 phylink = jme_linkstat_from_phy(jme);
1644 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1646 phylink = jme_linkstat_from_phy(jme);
1652 jme_phy_off(struct jme_adapter *jme)
1654 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1658 jme_close(struct net_device *netdev)
1660 struct jme_adapter *jme = netdev_priv(netdev);
1662 netif_stop_queue(netdev);
1663 netif_carrier_off(netdev);
1668 JME_NAPI_DISABLE(jme);
1670 tasklet_disable(&jme->linkch_task);
1671 tasklet_disable(&jme->txclean_task);
1672 tasklet_disable(&jme->rxclean_task);
1673 tasklet_disable(&jme->rxempty_task);
1675 jme_reset_ghc_speed(jme);
1676 jme_disable_rx_engine(jme);
1677 jme_disable_tx_engine(jme);
1678 jme_reset_mac_processor(jme);
1679 jme_free_rx_resources(jme);
1680 jme_free_tx_resources(jme);
1688 jme_alloc_txdesc(struct jme_adapter *jme,
1689 struct sk_buff *skb)
1691 struct jme_ring *txring = &(jme->txring[0]);
1692 int idx, nr_alloc, mask = jme->tx_ring_mask;
1694 idx = txring->next_to_use;
1695 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1697 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1700 atomic_sub(nr_alloc, &txring->nr_free);
1702 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1708 jme_fill_tx_map(struct pci_dev *pdev,
1709 struct txdesc *txdesc,
1710 struct jme_buffer_info *txbi,
1718 dmaaddr = pci_map_page(pdev,
1724 pci_dma_sync_single_for_device(pdev,
1731 txdesc->desc2.flags = TXFLAG_OWN;
1732 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1733 txdesc->desc2.datalen = cpu_to_le16(len);
1734 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1735 txdesc->desc2.bufaddrl = cpu_to_le32(
1736 (__u64)dmaaddr & 0xFFFFFFFFUL);
1738 txbi->mapping = dmaaddr;
1743 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1745 struct jme_ring *txring = &(jme->txring[0]);
1746 struct txdesc *txdesc = txring->desc, *ctxdesc;
1747 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1748 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1749 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1750 int mask = jme->tx_ring_mask;
1751 struct skb_frag_struct *frag;
1754 for (i = 0 ; i < nr_frags ; ++i) {
1755 frag = &skb_shinfo(skb)->frags[i];
1756 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1757 ctxbi = txbi + ((idx + i + 2) & (mask));
1759 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1760 frag->page_offset, frag->size, hidma);
1763 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1764 ctxdesc = txdesc + ((idx + 1) & (mask));
1765 ctxbi = txbi + ((idx + 1) & (mask));
1766 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1767 offset_in_page(skb->data), len, hidma);
1772 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1774 if (unlikely(skb_shinfo(skb)->gso_size &&
1775 skb_header_cloned(skb) &&
1776 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1785 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1787 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1789 *flags |= TXFLAG_LSEN;
1791 if (skb->protocol == htons(ETH_P_IP)) {
1792 struct iphdr *iph = ip_hdr(skb);
1795 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1800 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1802 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1815 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1817 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1820 switch (skb->protocol) {
1821 case htons(ETH_P_IP):
1822 ip_proto = ip_hdr(skb)->protocol;
1824 case htons(ETH_P_IPV6):
1825 ip_proto = ipv6_hdr(skb)->nexthdr;
1834 *flags |= TXFLAG_TCPCS;
1837 *flags |= TXFLAG_UDPCS;
1840 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1847 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1849 if (vlan_tx_tag_present(skb)) {
1850 *flags |= TXFLAG_TAGON;
1851 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1856 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1858 struct jme_ring *txring = &(jme->txring[0]);
1859 struct txdesc *txdesc;
1860 struct jme_buffer_info *txbi;
1863 txdesc = (struct txdesc *)txring->desc + idx;
1864 txbi = txring->bufinf + idx;
1870 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1872 * Set OWN bit at final.
1873 * When kernel transmit faster than NIC.
1874 * And NIC trying to send this descriptor before we tell
1875 * it to start sending this TX queue.
1876 * Other fields are already filled correctly.
1879 flags = TXFLAG_OWN | TXFLAG_INT;
1881 * Set checksum flags while not tso
1883 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1884 jme_tx_csum(jme, skb, &flags);
1885 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1886 jme_map_tx_skb(jme, skb, idx);
1887 txdesc->desc1.flags = flags;
1889 * Set tx buffer info after telling NIC to send
1890 * For better tx_clean timing
1893 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1895 txbi->len = skb->len;
1896 txbi->start_xmit = jiffies;
1897 if (!txbi->start_xmit)
1898 txbi->start_xmit = (0UL-1);
1904 jme_stop_queue_if_full(struct jme_adapter *jme)
1906 struct jme_ring *txring = &(jme->txring[0]);
1907 struct jme_buffer_info *txbi = txring->bufinf;
1908 int idx = atomic_read(&txring->next_to_clean);
1913 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1914 netif_stop_queue(jme->dev);
1915 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1917 if (atomic_read(&txring->nr_free)
1918 >= (jme->tx_wake_threshold)) {
1919 netif_wake_queue(jme->dev);
1920 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1924 if (unlikely(txbi->start_xmit &&
1925 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1927 netif_stop_queue(jme->dev);
1928 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1933 * This function is already protected by netif_tx_lock()
1937 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1939 struct jme_adapter *jme = netdev_priv(netdev);
1942 if (unlikely(jme_expand_header(jme, skb))) {
1943 ++(NET_STAT(jme).tx_dropped);
1944 return NETDEV_TX_OK;
1947 idx = jme_alloc_txdesc(jme, skb);
1949 if (unlikely(idx < 0)) {
1950 netif_stop_queue(netdev);
1951 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1953 return NETDEV_TX_BUSY;
1956 jme_fill_tx_desc(jme, skb, idx);
1958 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1959 TXCS_SELECT_QUEUE0 |
1963 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1964 skb_shinfo(skb)->nr_frags + 2,
1966 jme_stop_queue_if_full(jme);
1968 return NETDEV_TX_OK;
1972 jme_set_macaddr(struct net_device *netdev, void *p)
1974 struct jme_adapter *jme = netdev_priv(netdev);
1975 struct sockaddr *addr = p;
1978 if (netif_running(netdev))
1981 spin_lock_bh(&jme->macaddr_lock);
1982 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1984 val = (addr->sa_data[3] & 0xff) << 24 |
1985 (addr->sa_data[2] & 0xff) << 16 |
1986 (addr->sa_data[1] & 0xff) << 8 |
1987 (addr->sa_data[0] & 0xff);
1988 jwrite32(jme, JME_RXUMA_LO, val);
1989 val = (addr->sa_data[5] & 0xff) << 8 |
1990 (addr->sa_data[4] & 0xff);
1991 jwrite32(jme, JME_RXUMA_HI, val);
1992 spin_unlock_bh(&jme->macaddr_lock);
1998 jme_set_multi(struct net_device *netdev)
2000 struct jme_adapter *jme = netdev_priv(netdev);
2001 u32 mc_hash[2] = {};
2003 spin_lock_bh(&jme->rxmcs_lock);
2005 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2007 if (netdev->flags & IFF_PROMISC) {
2008 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2009 } else if (netdev->flags & IFF_ALLMULTI) {
2010 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2011 } else if (netdev->flags & IFF_MULTICAST) {
2012 struct dev_mc_list *mclist;
2015 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2016 netdev_for_each_mc_addr(mclist, netdev) {
2017 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2018 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2021 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2022 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2026 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2028 spin_unlock_bh(&jme->rxmcs_lock);
2032 jme_change_mtu(struct net_device *netdev, int new_mtu)
2034 struct jme_adapter *jme = netdev_priv(netdev);
2036 if (new_mtu == jme->old_mtu)
2039 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2040 ((new_mtu) < IPV6_MIN_MTU))
2043 if (new_mtu > 4000) {
2044 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2045 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2046 jme_restart_rx_engine(jme);
2048 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2049 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2050 jme_restart_rx_engine(jme);
2053 if (new_mtu > 1900) {
2054 netdev->features &= ~(NETIF_F_HW_CSUM |
2058 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2059 netdev->features |= NETIF_F_HW_CSUM;
2060 if (test_bit(JME_FLAG_TSO, &jme->flags))
2061 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2064 netdev->mtu = new_mtu;
2065 jme_reset_link(jme);
2071 jme_tx_timeout(struct net_device *netdev)
2073 struct jme_adapter *jme = netdev_priv(netdev);
2076 jme_reset_phy_processor(jme);
2077 if (test_bit(JME_FLAG_SSET, &jme->flags))
2078 jme_set_settings(netdev, &jme->old_ecmd);
2081 * Force to Reset the link again
2083 jme_reset_link(jme);
2086 static inline void jme_pause_rx(struct jme_adapter *jme)
2088 atomic_dec(&jme->link_changing);
2090 jme_set_rx_pcc(jme, PCC_OFF);
2091 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2092 JME_NAPI_DISABLE(jme);
2094 tasklet_disable(&jme->rxclean_task);
2095 tasklet_disable(&jme->rxempty_task);
2099 static inline void jme_resume_rx(struct jme_adapter *jme)
2101 struct dynpcc_info *dpi = &(jme->dpi);
2103 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2104 JME_NAPI_ENABLE(jme);
2106 tasklet_hi_enable(&jme->rxclean_task);
2107 tasklet_hi_enable(&jme->rxempty_task);
2110 dpi->attempt = PCC_P1;
2112 jme_set_rx_pcc(jme, PCC_P1);
2114 atomic_inc(&jme->link_changing);
2118 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2120 struct jme_adapter *jme = netdev_priv(netdev);
2128 jme_get_drvinfo(struct net_device *netdev,
2129 struct ethtool_drvinfo *info)
2131 struct jme_adapter *jme = netdev_priv(netdev);
2133 strcpy(info->driver, DRV_NAME);
2134 strcpy(info->version, DRV_VERSION);
2135 strcpy(info->bus_info, pci_name(jme->pdev));
2139 jme_get_regs_len(struct net_device *netdev)
2145 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2149 for (i = 0 ; i < len ; i += 4)
2150 p[i >> 2] = jread32(jme, reg + i);
2154 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2157 u16 *p16 = (u16 *)p;
2159 for (i = 0 ; i < reg_nr ; ++i)
2160 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2164 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2166 struct jme_adapter *jme = netdev_priv(netdev);
2167 u32 *p32 = (u32 *)p;
2169 memset(p, 0xFF, JME_REG_LEN);
2172 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2175 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2178 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2181 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2184 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2188 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2190 struct jme_adapter *jme = netdev_priv(netdev);
2192 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2193 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2195 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2196 ecmd->use_adaptive_rx_coalesce = false;
2197 ecmd->rx_coalesce_usecs = 0;
2198 ecmd->rx_max_coalesced_frames = 0;
2202 ecmd->use_adaptive_rx_coalesce = true;
2204 switch (jme->dpi.cur) {
2206 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2207 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2210 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2211 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2214 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2215 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2225 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2227 struct jme_adapter *jme = netdev_priv(netdev);
2228 struct dynpcc_info *dpi = &(jme->dpi);
2230 if (netif_running(netdev))
2233 if (ecmd->use_adaptive_rx_coalesce &&
2234 test_bit(JME_FLAG_POLL, &jme->flags)) {
2235 clear_bit(JME_FLAG_POLL, &jme->flags);
2236 jme->jme_rx = netif_rx;
2237 jme->jme_vlan_rx = vlan_hwaccel_rx;
2239 dpi->attempt = PCC_P1;
2241 jme_set_rx_pcc(jme, PCC_P1);
2242 jme_interrupt_mode(jme);
2243 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2244 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2245 set_bit(JME_FLAG_POLL, &jme->flags);
2246 jme->jme_rx = netif_receive_skb;
2247 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2248 jme_interrupt_mode(jme);
2255 jme_get_pauseparam(struct net_device *netdev,
2256 struct ethtool_pauseparam *ecmd)
2258 struct jme_adapter *jme = netdev_priv(netdev);
2261 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2262 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2264 spin_lock_bh(&jme->phy_lock);
2265 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2266 spin_unlock_bh(&jme->phy_lock);
2269 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2273 jme_set_pauseparam(struct net_device *netdev,
2274 struct ethtool_pauseparam *ecmd)
2276 struct jme_adapter *jme = netdev_priv(netdev);
2279 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2280 (ecmd->tx_pause != 0)) {
2283 jme->reg_txpfc |= TXPFC_PF_EN;
2285 jme->reg_txpfc &= ~TXPFC_PF_EN;
2287 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2290 spin_lock_bh(&jme->rxmcs_lock);
2291 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2292 (ecmd->rx_pause != 0)) {
2295 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2297 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2299 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2301 spin_unlock_bh(&jme->rxmcs_lock);
2303 spin_lock_bh(&jme->phy_lock);
2304 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2305 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2306 (ecmd->autoneg != 0)) {
2309 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2311 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2313 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2314 MII_ADVERTISE, val);
2316 spin_unlock_bh(&jme->phy_lock);
2322 jme_get_wol(struct net_device *netdev,
2323 struct ethtool_wolinfo *wol)
2325 struct jme_adapter *jme = netdev_priv(netdev);
2327 wol->supported = WAKE_MAGIC | WAKE_PHY;
2331 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2332 wol->wolopts |= WAKE_PHY;
2334 if (jme->reg_pmcs & PMCS_MFEN)
2335 wol->wolopts |= WAKE_MAGIC;
2340 jme_set_wol(struct net_device *netdev,
2341 struct ethtool_wolinfo *wol)
2343 struct jme_adapter *jme = netdev_priv(netdev);
2345 if (wol->wolopts & (WAKE_MAGICSECURE |
2354 if (wol->wolopts & WAKE_PHY)
2355 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2357 if (wol->wolopts & WAKE_MAGIC)
2358 jme->reg_pmcs |= PMCS_MFEN;
2360 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2366 jme_get_settings(struct net_device *netdev,
2367 struct ethtool_cmd *ecmd)
2369 struct jme_adapter *jme = netdev_priv(netdev);
2372 spin_lock_bh(&jme->phy_lock);
2373 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2374 spin_unlock_bh(&jme->phy_lock);
2379 jme_set_settings(struct net_device *netdev,
2380 struct ethtool_cmd *ecmd)
2382 struct jme_adapter *jme = netdev_priv(netdev);
2385 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2388 if (jme->mii_if.force_media &&
2389 ecmd->autoneg != AUTONEG_ENABLE &&
2390 (jme->mii_if.full_duplex != ecmd->duplex))
2393 spin_lock_bh(&jme->phy_lock);
2394 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2395 spin_unlock_bh(&jme->phy_lock);
2398 jme_reset_link(jme);
2401 set_bit(JME_FLAG_SSET, &jme->flags);
2402 jme->old_ecmd = *ecmd;
2409 jme_get_link(struct net_device *netdev)
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2416 jme_get_msglevel(struct net_device *netdev)
2418 struct jme_adapter *jme = netdev_priv(netdev);
2419 return jme->msg_enable;
2423 jme_set_msglevel(struct net_device *netdev, u32 value)
2425 struct jme_adapter *jme = netdev_priv(netdev);
2426 jme->msg_enable = value;
2430 jme_get_rx_csum(struct net_device *netdev)
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2437 jme_set_rx_csum(struct net_device *netdev, u32 on)
2439 struct jme_adapter *jme = netdev_priv(netdev);
2441 spin_lock_bh(&jme->rxmcs_lock);
2443 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2445 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2446 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2447 spin_unlock_bh(&jme->rxmcs_lock);
2453 jme_set_tx_csum(struct net_device *netdev, u32 on)
2455 struct jme_adapter *jme = netdev_priv(netdev);
2458 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2459 if (netdev->mtu <= 1900)
2460 netdev->features |= NETIF_F_HW_CSUM;
2462 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2463 netdev->features &= ~NETIF_F_HW_CSUM;
2470 jme_set_tso(struct net_device *netdev, u32 on)
2472 struct jme_adapter *jme = netdev_priv(netdev);
2475 set_bit(JME_FLAG_TSO, &jme->flags);
2476 if (netdev->mtu <= 1900)
2477 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2479 clear_bit(JME_FLAG_TSO, &jme->flags);
2480 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2487 jme_nway_reset(struct net_device *netdev)
2489 struct jme_adapter *jme = netdev_priv(netdev);
2490 jme_restart_an(jme);
2495 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2500 val = jread32(jme, JME_SMBCSR);
2501 to = JME_SMB_BUSY_TIMEOUT;
2502 while ((val & SMBCSR_BUSY) && --to) {
2504 val = jread32(jme, JME_SMBCSR);
2507 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2511 jwrite32(jme, JME_SMBINTF,
2512 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2513 SMBINTF_HWRWN_READ |
2516 val = jread32(jme, JME_SMBINTF);
2517 to = JME_SMB_BUSY_TIMEOUT;
2518 while ((val & SMBINTF_HWCMD) && --to) {
2520 val = jread32(jme, JME_SMBINTF);
2523 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2527 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2531 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2536 val = jread32(jme, JME_SMBCSR);
2537 to = JME_SMB_BUSY_TIMEOUT;
2538 while ((val & SMBCSR_BUSY) && --to) {
2540 val = jread32(jme, JME_SMBCSR);
2543 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2547 jwrite32(jme, JME_SMBINTF,
2548 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2549 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2550 SMBINTF_HWRWN_WRITE |
2553 val = jread32(jme, JME_SMBINTF);
2554 to = JME_SMB_BUSY_TIMEOUT;
2555 while ((val & SMBINTF_HWCMD) && --to) {
2557 val = jread32(jme, JME_SMBINTF);
2560 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2568 jme_get_eeprom_len(struct net_device *netdev)
2570 struct jme_adapter *jme = netdev_priv(netdev);
2572 val = jread32(jme, JME_SMBCSR);
2573 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2577 jme_get_eeprom(struct net_device *netdev,
2578 struct ethtool_eeprom *eeprom, u8 *data)
2580 struct jme_adapter *jme = netdev_priv(netdev);
2581 int i, offset = eeprom->offset, len = eeprom->len;
2584 * ethtool will check the boundary for us
2586 eeprom->magic = JME_EEPROM_MAGIC;
2587 for (i = 0 ; i < len ; ++i)
2588 data[i] = jme_smb_read(jme, i + offset);
2594 jme_set_eeprom(struct net_device *netdev,
2595 struct ethtool_eeprom *eeprom, u8 *data)
2597 struct jme_adapter *jme = netdev_priv(netdev);
2598 int i, offset = eeprom->offset, len = eeprom->len;
2600 if (eeprom->magic != JME_EEPROM_MAGIC)
2604 * ethtool will check the boundary for us
2606 for (i = 0 ; i < len ; ++i)
2607 jme_smb_write(jme, i + offset, data[i]);
2612 static const struct ethtool_ops jme_ethtool_ops = {
2613 .get_drvinfo = jme_get_drvinfo,
2614 .get_regs_len = jme_get_regs_len,
2615 .get_regs = jme_get_regs,
2616 .get_coalesce = jme_get_coalesce,
2617 .set_coalesce = jme_set_coalesce,
2618 .get_pauseparam = jme_get_pauseparam,
2619 .set_pauseparam = jme_set_pauseparam,
2620 .get_wol = jme_get_wol,
2621 .set_wol = jme_set_wol,
2622 .get_settings = jme_get_settings,
2623 .set_settings = jme_set_settings,
2624 .get_link = jme_get_link,
2625 .get_msglevel = jme_get_msglevel,
2626 .set_msglevel = jme_set_msglevel,
2627 .get_rx_csum = jme_get_rx_csum,
2628 .set_rx_csum = jme_set_rx_csum,
2629 .set_tx_csum = jme_set_tx_csum,
2630 .set_tso = jme_set_tso,
2631 .set_sg = ethtool_op_set_sg,
2632 .nway_reset = jme_nway_reset,
2633 .get_eeprom_len = jme_get_eeprom_len,
2634 .get_eeprom = jme_get_eeprom,
2635 .set_eeprom = jme_set_eeprom,
2639 jme_pci_dma64(struct pci_dev *pdev)
2641 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2642 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2643 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2646 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2647 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2648 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2651 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2652 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2659 jme_phy_init(struct jme_adapter *jme)
2663 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2664 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2668 jme_check_hw_ver(struct jme_adapter *jme)
2672 chipmode = jread32(jme, JME_CHIPMODE);
2674 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2675 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2678 static const struct net_device_ops jme_netdev_ops = {
2679 .ndo_open = jme_open,
2680 .ndo_stop = jme_close,
2681 .ndo_validate_addr = eth_validate_addr,
2682 .ndo_start_xmit = jme_start_xmit,
2683 .ndo_set_mac_address = jme_set_macaddr,
2684 .ndo_set_multicast_list = jme_set_multi,
2685 .ndo_change_mtu = jme_change_mtu,
2686 .ndo_tx_timeout = jme_tx_timeout,
2687 .ndo_vlan_rx_register = jme_vlan_rx_register,
2690 static int __devinit
2691 jme_init_one(struct pci_dev *pdev,
2692 const struct pci_device_id *ent)
2694 int rc = 0, using_dac, i;
2695 struct net_device *netdev;
2696 struct jme_adapter *jme;
2701 * set up PCI device basics
2703 rc = pci_enable_device(pdev);
2705 jeprintk(pdev, "Cannot enable PCI device.\n");
2709 using_dac = jme_pci_dma64(pdev);
2710 if (using_dac < 0) {
2711 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2713 goto err_out_disable_pdev;
2716 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2717 jeprintk(pdev, "No PCI resource region found.\n");
2719 goto err_out_disable_pdev;
2722 rc = pci_request_regions(pdev, DRV_NAME);
2724 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2725 goto err_out_disable_pdev;
2728 pci_set_master(pdev);
2731 * alloc and init net device
2733 netdev = alloc_etherdev(sizeof(*jme));
2735 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2737 goto err_out_release_regions;
2739 netdev->netdev_ops = &jme_netdev_ops;
2740 netdev->ethtool_ops = &jme_ethtool_ops;
2741 netdev->watchdog_timeo = TX_TIMEOUT;
2742 netdev->features = NETIF_F_HW_CSUM |
2746 NETIF_F_HW_VLAN_TX |
2749 netdev->features |= NETIF_F_HIGHDMA;
2751 SET_NETDEV_DEV(netdev, &pdev->dev);
2752 pci_set_drvdata(pdev, netdev);
2757 jme = netdev_priv(netdev);
2760 jme->jme_rx = netif_rx;
2761 jme->jme_vlan_rx = vlan_hwaccel_rx;
2762 jme->old_mtu = netdev->mtu = 1500;
2764 jme->tx_ring_size = 1 << 10;
2765 jme->tx_ring_mask = jme->tx_ring_size - 1;
2766 jme->tx_wake_threshold = 1 << 9;
2767 jme->rx_ring_size = 1 << 9;
2768 jme->rx_ring_mask = jme->rx_ring_size - 1;
2769 jme->msg_enable = JME_DEF_MSG_ENABLE;
2770 jme->regs = ioremap(pci_resource_start(pdev, 0),
2771 pci_resource_len(pdev, 0));
2773 jeprintk(pdev, "Mapping PCI resource region error.\n");
2775 goto err_out_free_netdev;
2779 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2780 jwrite32(jme, JME_APMC, apmc);
2781 } else if (force_pseudohp) {
2782 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2783 jwrite32(jme, JME_APMC, apmc);
2786 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2788 spin_lock_init(&jme->phy_lock);
2789 spin_lock_init(&jme->macaddr_lock);
2790 spin_lock_init(&jme->rxmcs_lock);
2792 atomic_set(&jme->link_changing, 1);
2793 atomic_set(&jme->rx_cleaning, 1);
2794 atomic_set(&jme->tx_cleaning, 1);
2795 atomic_set(&jme->rx_empty, 1);
2797 tasklet_init(&jme->pcc_task,
2799 (unsigned long) jme);
2800 tasklet_init(&jme->linkch_task,
2801 jme_link_change_tasklet,
2802 (unsigned long) jme);
2803 tasklet_init(&jme->txclean_task,
2804 jme_tx_clean_tasklet,
2805 (unsigned long) jme);
2806 tasklet_init(&jme->rxclean_task,
2807 jme_rx_clean_tasklet,
2808 (unsigned long) jme);
2809 tasklet_init(&jme->rxempty_task,
2810 jme_rx_empty_tasklet,
2811 (unsigned long) jme);
2812 tasklet_disable_nosync(&jme->linkch_task);
2813 tasklet_disable_nosync(&jme->txclean_task);
2814 tasklet_disable_nosync(&jme->rxclean_task);
2815 tasklet_disable_nosync(&jme->rxempty_task);
2816 jme->dpi.cur = PCC_P1;
2819 jme->reg_rxcs = RXCS_DEFAULT;
2820 jme->reg_rxmcs = RXMCS_DEFAULT;
2822 jme->reg_pmcs = PMCS_MFEN;
2823 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2824 set_bit(JME_FLAG_TSO, &jme->flags);
2827 * Get Max Read Req Size from PCI Config Space
2829 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2830 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2831 switch (jme->mrrs) {
2833 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2836 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2839 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2844 * Must check before reset_mac_processor
2846 jme_check_hw_ver(jme);
2847 jme->mii_if.dev = netdev;
2849 jme->mii_if.phy_id = 0;
2850 for (i = 1 ; i < 32 ; ++i) {
2851 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2852 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2853 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2854 jme->mii_if.phy_id = i;
2859 if (!jme->mii_if.phy_id) {
2861 jeprintk(pdev, "Can not find phy_id.\n");
2865 jme->reg_ghc |= GHC_LINK_POLL;
2867 jme->mii_if.phy_id = 1;
2869 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2870 jme->mii_if.supports_gmii = true;
2872 jme->mii_if.supports_gmii = false;
2873 jme->mii_if.mdio_read = jme_mdio_read;
2874 jme->mii_if.mdio_write = jme_mdio_write;
2877 jme_set_phyfifoa(jme);
2878 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2884 * Reset MAC processor and reload EEPROM for MAC Address
2886 jme_reset_mac_processor(jme);
2887 rc = jme_reload_eeprom(jme);
2890 "Reload eeprom for reading MAC Address error.\n");
2893 jme_load_macaddr(netdev);
2896 * Tell stack that we are not ready to work until open()
2898 netif_carrier_off(netdev);
2899 netif_stop_queue(netdev);
2904 rc = register_netdev(netdev);
2906 jeprintk(pdev, "Cannot register net device.\n");
2910 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2911 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2912 "JMC250 Gigabit Ethernet" :
2913 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2914 "JMC260 Fast Ethernet" : "Unknown",
2915 (jme->fpgaver != 0) ? " (FPGA)" : "",
2916 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2917 jme->rev, netdev->dev_addr);
2923 err_out_free_netdev:
2924 pci_set_drvdata(pdev, NULL);
2925 free_netdev(netdev);
2926 err_out_release_regions:
2927 pci_release_regions(pdev);
2928 err_out_disable_pdev:
2929 pci_disable_device(pdev);
2934 static void __devexit
2935 jme_remove_one(struct pci_dev *pdev)
2937 struct net_device *netdev = pci_get_drvdata(pdev);
2938 struct jme_adapter *jme = netdev_priv(netdev);
2940 unregister_netdev(netdev);
2942 pci_set_drvdata(pdev, NULL);
2943 free_netdev(netdev);
2944 pci_release_regions(pdev);
2945 pci_disable_device(pdev);
2951 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2953 struct net_device *netdev = pci_get_drvdata(pdev);
2954 struct jme_adapter *jme = netdev_priv(netdev);
2956 atomic_dec(&jme->link_changing);
2958 netif_device_detach(netdev);
2959 netif_stop_queue(netdev);
2962 tasklet_disable(&jme->txclean_task);
2963 tasklet_disable(&jme->rxclean_task);
2964 tasklet_disable(&jme->rxempty_task);
2966 if (netif_carrier_ok(netdev)) {
2967 if (test_bit(JME_FLAG_POLL, &jme->flags))
2968 jme_polling_mode(jme);
2970 jme_stop_pcc_timer(jme);
2971 jme_reset_ghc_speed(jme);
2972 jme_disable_rx_engine(jme);
2973 jme_disable_tx_engine(jme);
2974 jme_reset_mac_processor(jme);
2975 jme_free_rx_resources(jme);
2976 jme_free_tx_resources(jme);
2977 netif_carrier_off(netdev);
2981 tasklet_enable(&jme->txclean_task);
2982 tasklet_hi_enable(&jme->rxclean_task);
2983 tasklet_hi_enable(&jme->rxempty_task);
2985 pci_save_state(pdev);
2986 if (jme->reg_pmcs) {
2987 jme_set_100m_half(jme);
2989 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2992 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2994 pci_enable_wake(pdev, PCI_D3cold, true);
2998 pci_set_power_state(pdev, PCI_D3cold);
3004 jme_resume(struct pci_dev *pdev)
3006 struct net_device *netdev = pci_get_drvdata(pdev);
3007 struct jme_adapter *jme = netdev_priv(netdev);
3010 pci_restore_state(pdev);
3012 if (test_bit(JME_FLAG_SSET, &jme->flags))
3013 jme_set_settings(netdev, &jme->old_ecmd);
3015 jme_reset_phy_processor(jme);
3018 netif_device_attach(netdev);
3020 atomic_inc(&jme->link_changing);
3022 jme_reset_link(jme);
3028 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3029 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3030 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3034 static struct pci_driver jme_driver = {
3036 .id_table = jme_pci_tbl,
3037 .probe = jme_init_one,
3038 .remove = __devexit_p(jme_remove_one),
3040 .suspend = jme_suspend,
3041 .resume = jme_resume,
3042 #endif /* CONFIG_PM */
3046 jme_init_module(void)
3048 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3049 "driver version %s\n", DRV_VERSION);
3050 return pci_register_driver(&jme_driver);
3054 jme_cleanup_module(void)
3056 pci_unregister_driver(&jme_driver);
3059 module_init(jme_init_module);
3060 module_exit(jme_cleanup_module);
3062 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3063 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3064 MODULE_LICENSE("GPL");
3065 MODULE_VERSION(DRV_VERSION);
3066 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);