2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_reset_phy_processor(struct jme_adapter *jme)
114 jme_mdio_write(jme->dev,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125 val = jme_mdio_read(jme->dev,
129 jme_mdio_write(jme->dev,
131 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
204 jme_clear_pm(struct jme_adapter *jme)
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
212 jme_reload_eeprom(struct jme_adapter *jme)
217 val = jread32(jme, JME_SMBCSR);
219 if (val & SMBCSR_EEPROMD) {
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device *netdev)
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
295 jme_start_irq(struct jme_adapter *jme)
297 register struct dynpcc_info *dpi = &(jme->dpi);
299 jme_set_rx_pcc(jme, PCC_P1);
301 dpi->attempt = PCC_P1;
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
317 jme_stop_irq(struct jme_adapter *jme)
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326 jme_enable_shadow(struct jme_adapter *jme)
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
334 jme_disable_shadow(struct jme_adapter *jme)
336 jwrite32(jme, JME_SHBA_LO, 0x0);
340 jme_linkstat_from_phy(struct jme_adapter *jme)
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
353 jme_set_phyfifoa(struct jme_adapter *jme)
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
359 jme_set_phyfifob(struct jme_adapter *jme)
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
365 jme_check_link(struct net_device *netdev, int testonly)
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
375 phylink = jme_linkstat_from_phy(jme);
377 phylink = jread32(jme, JME_PHY_LINK);
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
385 phylink = PHY_LINK_UP;
387 bmcr = jme_mdio_read(jme->dev,
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
401 strcat(linkmsg, "Forced: ");
404 * Keep polling for speed/duplex resolve complete
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
412 phylink = jme_linkstat_from_phy(jme);
414 phylink = jread32(jme, JME_PHY_LINK);
418 "Waiting speed resolve timeout.\n");
420 strcat(linkmsg, "ANed: ");
423 if (jme->phylink == phylink) {
430 jme->phylink = phylink;
432 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
433 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
435 switch (phylink & PHY_LINK_SPEED_MASK) {
436 case PHY_LINK_SPEED_10M:
437 ghc |= GHC_SPEED_10M |
438 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
439 strcat(linkmsg, "10 Mbps, ");
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M |
443 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
444 strcat(linkmsg, "100 Mbps, ");
446 case PHY_LINK_SPEED_1000M:
447 ghc |= GHC_SPEED_1000M |
448 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
449 strcat(linkmsg, "1000 Mbps, ");
455 if (phylink & PHY_LINK_DUPLEX) {
456 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
459 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
463 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
464 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
466 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
469 gpreg1 = GPREG1_DEFAULT;
470 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
471 if (!(phylink & PHY_LINK_DUPLEX))
472 gpreg1 |= GPREG1_HALFMODEPATCH;
473 switch (phylink & PHY_LINK_SPEED_MASK) {
474 case PHY_LINK_SPEED_10M:
475 jme_set_phyfifoa(jme);
476 gpreg1 |= GPREG1_RSSPATCH;
478 case PHY_LINK_SPEED_100M:
479 jme_set_phyfifob(jme);
480 gpreg1 |= GPREG1_RSSPATCH;
482 case PHY_LINK_SPEED_1000M:
483 jme_set_phyfifoa(jme);
490 jwrite32(jme, JME_GPREG1, gpreg1);
491 jwrite32(jme, JME_GHC, ghc);
494 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
497 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
506 msg_link(jme, "Link is down.\n");
508 netif_carrier_off(netdev);
516 jme_setup_tx_resources(struct jme_adapter *jme)
518 struct jme_ring *txring = &(jme->txring[0]);
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
525 if (!txring->alloc) {
527 txring->dmaalloc = 0;
535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, jme->tx_ring_size);
543 * Initialize Transmit Descriptors
545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
546 memset(txring->bufinf, 0,
547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
553 jme_free_tx_resources(struct jme_adapter *jme)
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi = txring->bufinf;
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
563 dev_kfree_skb(txbi->skb);
569 txbi->start_xmit = 0;
572 dma_free_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577 txring->alloc = NULL;
579 txring->dmaalloc = 0;
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, 0);
589 jme_enable_tx_engine(struct jme_adapter *jme)
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
598 * Setup TX Queue 0 DMA Bass Address
600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 * Setup TX Descptor Count
607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
620 jme_restart_tx_engine(struct jme_adapter *jme)
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
631 jme_disable_tx_engine(struct jme_adapter *jme)
639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
642 val = jread32(jme, JME_TXCS);
643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
645 val = jread32(jme, JME_TXCS);
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
654 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
656 struct jme_ring *rxring = jme->rxring;
657 register struct rxdesc *rxdesc = rxring->desc;
658 struct jme_buffer_info *rxbi = rxring->bufinf;
664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
668 if (jme->dev->features & NETIF_F_HIGHDMA)
669 rxdesc->desc1.flags = RXFLAG_64BIT;
671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
675 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
677 struct jme_ring *rxring = &(jme->rxring[0]);
678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
687 rxbi->len = skb_tailroom(skb);
688 rxbi->mapping = pci_map_page(jme->pdev,
689 virt_to_page(skb->data),
690 offset_in_page(skb->data),
698 jme_free_rx_buf(struct jme_adapter *jme, int i)
700 struct jme_ring *rxring = &(jme->rxring[0]);
701 struct jme_buffer_info *rxbi = rxring->bufinf;
705 pci_unmap_page(jme->pdev,
709 dev_kfree_skb(rxbi->skb);
717 jme_free_rx_resources(struct jme_adapter *jme)
720 struct jme_ring *rxring = &(jme->rxring[0]);
723 for (i = 0 ; i < jme->rx_ring_size ; ++i)
724 jme_free_rx_buf(jme, i);
726 dma_free_coherent(&(jme->pdev->dev),
727 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
730 rxring->alloc = NULL;
732 rxring->dmaalloc = 0;
735 rxring->next_to_use = 0;
736 atomic_set(&rxring->next_to_clean, 0);
740 jme_setup_rx_resources(struct jme_adapter *jme)
743 struct jme_ring *rxring = &(jme->rxring[0]);
745 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
746 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
749 if (!rxring->alloc) {
751 rxring->dmaalloc = 0;
759 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
761 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
762 rxring->next_to_use = 0;
763 atomic_set(&rxring->next_to_clean, 0);
766 * Initiallize Receive Descriptors
768 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
769 if (unlikely(jme_make_new_rx_buf(jme, i))) {
770 jme_free_rx_resources(jme);
774 jme_set_clean_rxdesc(jme, i);
781 jme_enable_rx_engine(struct jme_adapter *jme)
786 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
791 * Setup RX DMA Bass Address
793 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
794 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
795 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
798 * Setup RX Descriptor Count
800 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
803 * Setup Unicast Filter
805 jme_set_multi(jme->dev);
811 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
818 jme_restart_rx_engine(struct jme_adapter *jme)
823 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
830 jme_disable_rx_engine(struct jme_adapter *jme)
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
841 val = jread32(jme, JME_RXCS);
842 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
844 val = jread32(jme, JME_RXCS);
849 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
854 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
856 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
859 if (unlikely(!(flags & RXWBFLAG_MF) &&
860 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
861 msg_rx_err(jme, "TCP Checksum error.\n");
865 if (unlikely(!(flags & RXWBFLAG_MF) &&
866 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
867 msg_rx_err(jme, "UDP Checksum error.\n");
871 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
872 msg_rx_err(jme, "IPv4 Checksum error.\n");
883 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
885 struct jme_ring *rxring = &(jme->rxring[0]);
886 struct rxdesc *rxdesc = rxring->desc;
887 struct jme_buffer_info *rxbi = rxring->bufinf;
895 pci_dma_sync_single_for_cpu(jme->pdev,
900 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
901 pci_dma_sync_single_for_device(jme->pdev,
906 ++(NET_STAT(jme).rx_dropped);
908 framesize = le16_to_cpu(rxdesc->descwb.framesize)
911 skb_reserve(skb, RX_PREPAD_SIZE);
912 skb_put(skb, framesize);
913 skb->protocol = eth_type_trans(skb, jme->dev);
915 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
916 skb->ip_summed = CHECKSUM_UNNECESSARY;
918 skb->ip_summed = CHECKSUM_NONE;
920 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
922 jme->jme_vlan_rx(skb, jme->vlgrp,
923 le16_to_cpu(rxdesc->descwb.vlan));
924 NET_STAT(jme).rx_bytes += 4;
930 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
931 cpu_to_le16(RXWBFLAG_DEST_MUL))
932 ++(NET_STAT(jme).multicast);
934 NET_STAT(jme).rx_bytes += framesize;
935 ++(NET_STAT(jme).rx_packets);
938 jme_set_clean_rxdesc(jme, idx);
943 jme_process_receive(struct jme_adapter *jme, int limit)
945 struct jme_ring *rxring = &(jme->rxring[0]);
946 struct rxdesc *rxdesc = rxring->desc;
947 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
949 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
952 if (unlikely(atomic_read(&jme->link_changing) != 1))
955 if (unlikely(!netif_carrier_ok(jme->dev)))
958 i = atomic_read(&rxring->next_to_clean);
959 while (limit-- > 0) {
960 rxdesc = rxring->desc;
963 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
964 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
967 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
969 if (unlikely(desccnt > 1 ||
970 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
972 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
973 ++(NET_STAT(jme).rx_crc_errors);
974 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
975 ++(NET_STAT(jme).rx_fifo_errors);
977 ++(NET_STAT(jme).rx_errors);
980 limit -= desccnt - 1;
982 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
983 jme_set_clean_rxdesc(jme, j);
984 j = (j + 1) & (mask);
988 jme_alloc_and_feed_skb(jme, i);
991 i = (i + desccnt) & (mask);
995 atomic_set(&rxring->next_to_clean, i);
998 atomic_inc(&jme->rx_cleaning);
1000 return limit > 0 ? limit : 0;
1005 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1007 if (likely(atmp == dpi->cur)) {
1012 if (dpi->attempt == atmp) {
1015 dpi->attempt = atmp;
1022 jme_dynamic_pcc(struct jme_adapter *jme)
1024 register struct dynpcc_info *dpi = &(jme->dpi);
1026 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1027 jme_attempt_pcc(dpi, PCC_P3);
1028 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1029 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1030 jme_attempt_pcc(dpi, PCC_P2);
1032 jme_attempt_pcc(dpi, PCC_P1);
1034 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1035 if (dpi->attempt < dpi->cur)
1036 tasklet_schedule(&jme->rxclean_task);
1037 jme_set_rx_pcc(jme, dpi->attempt);
1038 dpi->cur = dpi->attempt;
1044 jme_start_pcc_timer(struct jme_adapter *jme)
1046 struct dynpcc_info *dpi = &(jme->dpi);
1047 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1048 dpi->last_pkts = NET_STAT(jme).rx_packets;
1050 jwrite32(jme, JME_TMCSR,
1051 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1055 jme_stop_pcc_timer(struct jme_adapter *jme)
1057 jwrite32(jme, JME_TMCSR, 0);
1061 jme_shutdown_nic(struct jme_adapter *jme)
1065 phylink = jme_linkstat_from_phy(jme);
1067 if (!(phylink & PHY_LINK_UP)) {
1069 * Disable all interrupt before issue timer
1072 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1077 jme_pcc_tasklet(unsigned long arg)
1079 struct jme_adapter *jme = (struct jme_adapter *)arg;
1080 struct net_device *netdev = jme->dev;
1082 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1083 jme_shutdown_nic(jme);
1087 if (unlikely(!netif_carrier_ok(netdev) ||
1088 (atomic_read(&jme->link_changing) != 1)
1090 jme_stop_pcc_timer(jme);
1094 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1095 jme_dynamic_pcc(jme);
1097 jme_start_pcc_timer(jme);
1101 jme_polling_mode(struct jme_adapter *jme)
1103 jme_set_rx_pcc(jme, PCC_OFF);
1107 jme_interrupt_mode(struct jme_adapter *jme)
1109 jme_set_rx_pcc(jme, PCC_P1);
1113 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1116 apmc = jread32(jme, JME_APMC);
1117 return apmc & JME_APMC_PSEUDO_HP_EN;
1121 jme_start_shutdown_timer(struct jme_adapter *jme)
1125 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1126 apmc &= ~JME_APMC_EPIEN_CTRL;
1128 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1131 jwrite32f(jme, JME_APMC, apmc);
1133 jwrite32f(jme, JME_TIMER2, 0);
1134 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1135 jwrite32(jme, JME_TMCSR,
1136 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1140 jme_stop_shutdown_timer(struct jme_adapter *jme)
1144 jwrite32f(jme, JME_TMCSR, 0);
1145 jwrite32f(jme, JME_TIMER2, 0);
1146 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1148 apmc = jread32(jme, JME_APMC);
1149 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1150 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1152 jwrite32f(jme, JME_APMC, apmc);
1156 jme_link_change_tasklet(unsigned long arg)
1158 struct jme_adapter *jme = (struct jme_adapter *)arg;
1159 struct net_device *netdev = jme->dev;
1162 while (!atomic_dec_and_test(&jme->link_changing)) {
1163 atomic_inc(&jme->link_changing);
1164 msg_intr(jme, "Get link change lock failed.\n");
1165 while (atomic_read(&jme->link_changing) != 1)
1166 msg_intr(jme, "Waiting link change lock.\n");
1169 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1172 jme->old_mtu = netdev->mtu;
1173 netif_stop_queue(netdev);
1174 if (jme_pseudo_hotplug_enabled(jme))
1175 jme_stop_shutdown_timer(jme);
1177 jme_stop_pcc_timer(jme);
1178 tasklet_disable(&jme->txclean_task);
1179 tasklet_disable(&jme->rxclean_task);
1180 tasklet_disable(&jme->rxempty_task);
1182 if (netif_carrier_ok(netdev)) {
1183 jme_reset_ghc_speed(jme);
1184 jme_disable_rx_engine(jme);
1185 jme_disable_tx_engine(jme);
1186 jme_reset_mac_processor(jme);
1187 jme_free_rx_resources(jme);
1188 jme_free_tx_resources(jme);
1190 if (test_bit(JME_FLAG_POLL, &jme->flags))
1191 jme_polling_mode(jme);
1193 netif_carrier_off(netdev);
1196 jme_check_link(netdev, 0);
1197 if (netif_carrier_ok(netdev)) {
1198 rc = jme_setup_rx_resources(jme);
1200 jeprintk(jme->pdev, "Allocating resources for RX error"
1201 ", Device STOPPED!\n");
1202 goto out_enable_tasklet;
1205 rc = jme_setup_tx_resources(jme);
1207 jeprintk(jme->pdev, "Allocating resources for TX error"
1208 ", Device STOPPED!\n");
1209 goto err_out_free_rx_resources;
1212 jme_enable_rx_engine(jme);
1213 jme_enable_tx_engine(jme);
1215 netif_start_queue(netdev);
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_interrupt_mode(jme);
1220 jme_start_pcc_timer(jme);
1221 } else if (jme_pseudo_hotplug_enabled(jme)) {
1222 jme_start_shutdown_timer(jme);
1225 goto out_enable_tasklet;
1227 err_out_free_rx_resources:
1228 jme_free_rx_resources(jme);
1230 tasklet_enable(&jme->txclean_task);
1231 tasklet_hi_enable(&jme->rxclean_task);
1232 tasklet_hi_enable(&jme->rxempty_task);
1234 atomic_inc(&jme->link_changing);
1238 jme_rx_clean_tasklet(unsigned long arg)
1240 struct jme_adapter *jme = (struct jme_adapter *)arg;
1241 struct dynpcc_info *dpi = &(jme->dpi);
1243 jme_process_receive(jme, jme->rx_ring_size);
1249 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1251 struct jme_adapter *jme = jme_napi_priv(holder);
1254 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1256 while (atomic_read(&jme->rx_empty) > 0) {
1257 atomic_dec(&jme->rx_empty);
1258 ++(NET_STAT(jme).rx_dropped);
1259 jme_restart_rx_engine(jme);
1261 atomic_inc(&jme->rx_empty);
1264 JME_RX_COMPLETE(netdev, holder);
1265 jme_interrupt_mode(jme);
1268 JME_NAPI_WEIGHT_SET(budget, rest);
1269 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1273 jme_rx_empty_tasklet(unsigned long arg)
1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
1277 if (unlikely(atomic_read(&jme->link_changing) != 1))
1280 if (unlikely(!netif_carrier_ok(jme->dev)))
1283 msg_rx_status(jme, "RX Queue Full!\n");
1285 jme_rx_clean_tasklet(arg);
1287 while (atomic_read(&jme->rx_empty) > 0) {
1288 atomic_dec(&jme->rx_empty);
1289 ++(NET_STAT(jme).rx_dropped);
1290 jme_restart_rx_engine(jme);
1292 atomic_inc(&jme->rx_empty);
1296 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1298 struct jme_ring *txring = jme->txring;
1301 if (unlikely(netif_queue_stopped(jme->dev) &&
1302 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1303 msg_tx_done(jme, "TX Queue Waked.\n");
1304 netif_wake_queue(jme->dev);
1310 jme_tx_clean_tasklet(unsigned long arg)
1312 struct jme_adapter *jme = (struct jme_adapter *)arg;
1313 struct jme_ring *txring = &(jme->txring[0]);
1314 struct txdesc *txdesc = txring->desc;
1315 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1316 int i, j, cnt = 0, max, err, mask;
1318 tx_dbg(jme, "Into txclean.\n");
1320 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1323 if (unlikely(atomic_read(&jme->link_changing) != 1))
1326 if (unlikely(!netif_carrier_ok(jme->dev)))
1329 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1330 mask = jme->tx_ring_mask;
1332 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1336 if (likely(ctxbi->skb &&
1337 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1339 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1340 i, ctxbi->nr_desc, jiffies);
1342 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1344 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1345 ttxbi = txbi + ((i + j) & (mask));
1346 txdesc[(i + j) & (mask)].dw[0] = 0;
1348 pci_unmap_page(jme->pdev,
1357 dev_kfree_skb(ctxbi->skb);
1359 cnt += ctxbi->nr_desc;
1361 if (unlikely(err)) {
1362 ++(NET_STAT(jme).tx_carrier_errors);
1364 ++(NET_STAT(jme).tx_packets);
1365 NET_STAT(jme).tx_bytes += ctxbi->len;
1370 ctxbi->start_xmit = 0;
1376 i = (i + ctxbi->nr_desc) & mask;
1381 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1382 atomic_set(&txring->next_to_clean, i);
1383 atomic_add(cnt, &txring->nr_free);
1385 jme_wake_queue_if_stopped(jme);
1388 atomic_inc(&jme->tx_cleaning);
1392 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1397 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1399 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1401 * Link change event is critical
1402 * all other events are ignored
1404 jwrite32(jme, JME_IEVE, intrstat);
1405 tasklet_schedule(&jme->linkch_task);
1409 if (intrstat & INTR_TMINTR) {
1410 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1411 tasklet_schedule(&jme->pcc_task);
1414 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1415 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1416 tasklet_schedule(&jme->txclean_task);
1419 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1420 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1426 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1427 if (intrstat & INTR_RX0EMP)
1428 atomic_inc(&jme->rx_empty);
1430 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1431 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1432 jme_polling_mode(jme);
1433 JME_RX_SCHEDULE(jme);
1437 if (intrstat & INTR_RX0EMP) {
1438 atomic_inc(&jme->rx_empty);
1439 tasklet_hi_schedule(&jme->rxempty_task);
1440 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1441 tasklet_hi_schedule(&jme->rxclean_task);
1447 * Re-enable interrupt
1449 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1453 jme_intr(int irq, void *dev_id)
1455 struct net_device *netdev = dev_id;
1456 struct jme_adapter *jme = netdev_priv(netdev);
1459 intrstat = jread32(jme, JME_IEVE);
1462 * Check if it's really an interrupt for us
1464 if (unlikely((intrstat & INTR_ENABLE) == 0))
1468 * Check if the device still exist
1470 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1473 jme_intr_msi(jme, intrstat);
1479 jme_msi(int irq, void *dev_id)
1481 struct net_device *netdev = dev_id;
1482 struct jme_adapter *jme = netdev_priv(netdev);
1485 pci_dma_sync_single_for_cpu(jme->pdev,
1487 sizeof(u32) * SHADOW_REG_NR,
1488 PCI_DMA_FROMDEVICE);
1489 intrstat = jme->shadow_regs[SHADOW_IEVE];
1490 jme->shadow_regs[SHADOW_IEVE] = 0;
1492 jme_intr_msi(jme, intrstat);
1498 jme_reset_link(struct jme_adapter *jme)
1500 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1504 jme_restart_an(struct jme_adapter *jme)
1508 spin_lock_bh(&jme->phy_lock);
1509 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1510 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1511 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1512 spin_unlock_bh(&jme->phy_lock);
1516 jme_request_irq(struct jme_adapter *jme)
1519 struct net_device *netdev = jme->dev;
1520 irq_handler_t handler = jme_intr;
1521 int irq_flags = IRQF_SHARED;
1523 if (!pci_enable_msi(jme->pdev)) {
1524 set_bit(JME_FLAG_MSI, &jme->flags);
1529 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1533 "Unable to request %s interrupt (return: %d)\n",
1534 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1537 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1538 pci_disable_msi(jme->pdev);
1539 clear_bit(JME_FLAG_MSI, &jme->flags);
1542 netdev->irq = jme->pdev->irq;
1549 jme_free_irq(struct jme_adapter *jme)
1551 free_irq(jme->pdev->irq, jme->dev);
1552 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1553 pci_disable_msi(jme->pdev);
1554 clear_bit(JME_FLAG_MSI, &jme->flags);
1555 jme->dev->irq = jme->pdev->irq;
1560 jme_open(struct net_device *netdev)
1562 struct jme_adapter *jme = netdev_priv(netdev);
1566 JME_NAPI_ENABLE(jme);
1568 tasklet_enable(&jme->txclean_task);
1569 tasklet_hi_enable(&jme->rxclean_task);
1570 tasklet_hi_enable(&jme->rxempty_task);
1572 rc = jme_request_irq(jme);
1576 jme_enable_shadow(jme);
1579 if (test_bit(JME_FLAG_SSET, &jme->flags))
1580 jme_set_settings(netdev, &jme->old_ecmd);
1582 jme_reset_phy_processor(jme);
1584 jme_reset_link(jme);
1589 netif_stop_queue(netdev);
1590 netif_carrier_off(netdev);
1596 jme_set_100m_half(struct jme_adapter *jme)
1600 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1601 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1602 BMCR_SPEED1000 | BMCR_FULLDPLX);
1603 tmp |= BMCR_SPEED100;
1606 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1609 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1611 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1614 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1616 jme_wait_link(struct jme_adapter *jme)
1618 u32 phylink, to = JME_WAIT_LINK_TIME;
1621 phylink = jme_linkstat_from_phy(jme);
1622 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1624 phylink = jme_linkstat_from_phy(jme);
1630 jme_phy_off(struct jme_adapter *jme)
1632 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1636 jme_close(struct net_device *netdev)
1638 struct jme_adapter *jme = netdev_priv(netdev);
1640 netif_stop_queue(netdev);
1641 netif_carrier_off(netdev);
1644 jme_disable_shadow(jme);
1647 JME_NAPI_DISABLE(jme);
1649 tasklet_kill(&jme->linkch_task);
1650 tasklet_kill(&jme->txclean_task);
1651 tasklet_kill(&jme->rxclean_task);
1652 tasklet_kill(&jme->rxempty_task);
1654 jme_reset_ghc_speed(jme);
1655 jme_disable_rx_engine(jme);
1656 jme_disable_tx_engine(jme);
1657 jme_reset_mac_processor(jme);
1658 jme_free_rx_resources(jme);
1659 jme_free_tx_resources(jme);
1667 jme_alloc_txdesc(struct jme_adapter *jme,
1668 struct sk_buff *skb)
1670 struct jme_ring *txring = jme->txring;
1671 int idx, nr_alloc, mask = jme->tx_ring_mask;
1673 idx = txring->next_to_use;
1674 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1676 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1679 atomic_sub(nr_alloc, &txring->nr_free);
1681 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1687 jme_fill_tx_map(struct pci_dev *pdev,
1688 struct txdesc *txdesc,
1689 struct jme_buffer_info *txbi,
1697 dmaaddr = pci_map_page(pdev,
1703 pci_dma_sync_single_for_device(pdev,
1710 txdesc->desc2.flags = TXFLAG_OWN;
1711 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1712 txdesc->desc2.datalen = cpu_to_le16(len);
1713 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1714 txdesc->desc2.bufaddrl = cpu_to_le32(
1715 (__u64)dmaaddr & 0xFFFFFFFFUL);
1717 txbi->mapping = dmaaddr;
1722 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1724 struct jme_ring *txring = jme->txring;
1725 struct txdesc *txdesc = txring->desc, *ctxdesc;
1726 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1727 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1728 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1729 int mask = jme->tx_ring_mask;
1730 struct skb_frag_struct *frag;
1733 for (i = 0 ; i < nr_frags ; ++i) {
1734 frag = &skb_shinfo(skb)->frags[i];
1735 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1736 ctxbi = txbi + ((idx + i + 2) & (mask));
1738 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1739 frag->page_offset, frag->size, hidma);
1742 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1743 ctxdesc = txdesc + ((idx + 1) & (mask));
1744 ctxbi = txbi + ((idx + 1) & (mask));
1745 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1746 offset_in_page(skb->data), len, hidma);
1751 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1753 if (unlikely(skb_shinfo(skb)->gso_size &&
1754 skb_header_cloned(skb) &&
1755 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1764 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1766 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1768 *flags |= TXFLAG_LSEN;
1770 if (skb->protocol == htons(ETH_P_IP)) {
1771 struct iphdr *iph = ip_hdr(skb);
1774 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1779 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1781 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1794 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1796 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1799 switch (skb->protocol) {
1800 case htons(ETH_P_IP):
1801 ip_proto = ip_hdr(skb)->protocol;
1803 case htons(ETH_P_IPV6):
1804 ip_proto = ipv6_hdr(skb)->nexthdr;
1813 *flags |= TXFLAG_TCPCS;
1816 *flags |= TXFLAG_UDPCS;
1819 msg_tx_err(jme, "Error upper layer protocol.\n");
1826 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1828 if (vlan_tx_tag_present(skb)) {
1829 *flags |= TXFLAG_TAGON;
1830 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1835 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1837 struct jme_ring *txring = jme->txring;
1838 struct txdesc *txdesc;
1839 struct jme_buffer_info *txbi;
1842 txdesc = (struct txdesc *)txring->desc + idx;
1843 txbi = txring->bufinf + idx;
1849 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1851 * Set OWN bit at final.
1852 * When kernel transmit faster than NIC.
1853 * And NIC trying to send this descriptor before we tell
1854 * it to start sending this TX queue.
1855 * Other fields are already filled correctly.
1858 flags = TXFLAG_OWN | TXFLAG_INT;
1860 * Set checksum flags while not tso
1862 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1863 jme_tx_csum(jme, skb, &flags);
1864 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1865 jme_map_tx_skb(jme, skb, idx);
1866 txdesc->desc1.flags = flags;
1868 * Set tx buffer info after telling NIC to send
1869 * For better tx_clean timing
1872 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1874 txbi->len = skb->len;
1875 txbi->start_xmit = jiffies;
1876 if (!txbi->start_xmit)
1877 txbi->start_xmit = (0UL-1);
1883 jme_stop_queue_if_full(struct jme_adapter *jme)
1885 struct jme_ring *txring = jme->txring;
1886 struct jme_buffer_info *txbi = txring->bufinf;
1887 int idx = atomic_read(&txring->next_to_clean);
1892 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1893 netif_stop_queue(jme->dev);
1894 msg_tx_queued(jme, "TX Queue Paused.\n");
1896 if (atomic_read(&txring->nr_free)
1897 >= (jme->tx_wake_threshold)) {
1898 netif_wake_queue(jme->dev);
1899 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1903 if (unlikely(txbi->start_xmit &&
1904 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1906 netif_stop_queue(jme->dev);
1907 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1912 * This function is already protected by netif_tx_lock()
1916 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1918 struct jme_adapter *jme = netdev_priv(netdev);
1921 if (unlikely(jme_expand_header(jme, skb))) {
1922 ++(NET_STAT(jme).tx_dropped);
1923 return NETDEV_TX_OK;
1926 idx = jme_alloc_txdesc(jme, skb);
1928 if (unlikely(idx < 0)) {
1929 netif_stop_queue(netdev);
1930 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1932 return NETDEV_TX_BUSY;
1935 jme_fill_tx_desc(jme, skb, idx);
1937 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1938 TXCS_SELECT_QUEUE0 |
1941 netdev->trans_start = jiffies;
1943 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1944 skb_shinfo(skb)->nr_frags + 2,
1946 jme_stop_queue_if_full(jme);
1948 return NETDEV_TX_OK;
1952 jme_set_macaddr(struct net_device *netdev, void *p)
1954 struct jme_adapter *jme = netdev_priv(netdev);
1955 struct sockaddr *addr = p;
1958 if (netif_running(netdev))
1961 spin_lock_bh(&jme->macaddr_lock);
1962 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1964 val = (addr->sa_data[3] & 0xff) << 24 |
1965 (addr->sa_data[2] & 0xff) << 16 |
1966 (addr->sa_data[1] & 0xff) << 8 |
1967 (addr->sa_data[0] & 0xff);
1968 jwrite32(jme, JME_RXUMA_LO, val);
1969 val = (addr->sa_data[5] & 0xff) << 8 |
1970 (addr->sa_data[4] & 0xff);
1971 jwrite32(jme, JME_RXUMA_HI, val);
1972 spin_unlock_bh(&jme->macaddr_lock);
1978 jme_set_multi(struct net_device *netdev)
1980 struct jme_adapter *jme = netdev_priv(netdev);
1981 u32 mc_hash[2] = {};
1984 spin_lock_bh(&jme->rxmcs_lock);
1986 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1988 if (netdev->flags & IFF_PROMISC) {
1989 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1990 } else if (netdev->flags & IFF_ALLMULTI) {
1991 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1992 } else if (netdev->flags & IFF_MULTICAST) {
1993 struct dev_mc_list *mclist;
1996 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1997 for (i = 0, mclist = netdev->mc_list;
1998 mclist && i < netdev->mc_count;
1999 ++i, mclist = mclist->next) {
2001 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2002 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2005 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2006 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2010 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2012 spin_unlock_bh(&jme->rxmcs_lock);
2016 jme_change_mtu(struct net_device *netdev, int new_mtu)
2018 struct jme_adapter *jme = netdev_priv(netdev);
2020 if (new_mtu == jme->old_mtu)
2023 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2024 ((new_mtu) < IPV6_MIN_MTU))
2027 if (new_mtu > 4000) {
2028 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2029 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2030 jme_restart_rx_engine(jme);
2032 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2033 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2034 jme_restart_rx_engine(jme);
2037 if (new_mtu > 1900) {
2038 netdev->features &= ~(NETIF_F_HW_CSUM |
2042 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2043 netdev->features |= NETIF_F_HW_CSUM;
2044 if (test_bit(JME_FLAG_TSO, &jme->flags))
2045 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2048 netdev->mtu = new_mtu;
2049 jme_reset_link(jme);
2055 jme_tx_timeout(struct net_device *netdev)
2057 struct jme_adapter *jme = netdev_priv(netdev);
2060 jme_reset_phy_processor(jme);
2061 if (test_bit(JME_FLAG_SSET, &jme->flags))
2062 jme_set_settings(netdev, &jme->old_ecmd);
2065 * Force to Reset the link again
2067 jme_reset_link(jme);
2071 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2073 struct jme_adapter *jme = netdev_priv(netdev);
2079 jme_get_drvinfo(struct net_device *netdev,
2080 struct ethtool_drvinfo *info)
2082 struct jme_adapter *jme = netdev_priv(netdev);
2084 strcpy(info->driver, DRV_NAME);
2085 strcpy(info->version, DRV_VERSION);
2086 strcpy(info->bus_info, pci_name(jme->pdev));
2090 jme_get_regs_len(struct net_device *netdev)
2096 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2100 for (i = 0 ; i < len ; i += 4)
2101 p[i >> 2] = jread32(jme, reg + i);
2105 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2108 u16 *p16 = (u16 *)p;
2110 for (i = 0 ; i < reg_nr ; ++i)
2111 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2115 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2117 struct jme_adapter *jme = netdev_priv(netdev);
2118 u32 *p32 = (u32 *)p;
2120 memset(p, 0xFF, JME_REG_LEN);
2123 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2126 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2129 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2132 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2135 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2139 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2141 struct jme_adapter *jme = netdev_priv(netdev);
2143 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2144 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2146 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2147 ecmd->use_adaptive_rx_coalesce = false;
2148 ecmd->rx_coalesce_usecs = 0;
2149 ecmd->rx_max_coalesced_frames = 0;
2153 ecmd->use_adaptive_rx_coalesce = true;
2155 switch (jme->dpi.cur) {
2157 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2158 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2161 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2162 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2165 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2166 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2176 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2178 struct jme_adapter *jme = netdev_priv(netdev);
2179 struct dynpcc_info *dpi = &(jme->dpi);
2181 if (netif_running(netdev))
2184 if (ecmd->use_adaptive_rx_coalesce
2185 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2186 clear_bit(JME_FLAG_POLL, &jme->flags);
2187 jme->jme_rx = netif_rx;
2188 jme->jme_vlan_rx = vlan_hwaccel_rx;
2190 dpi->attempt = PCC_P1;
2192 jme_set_rx_pcc(jme, PCC_P1);
2193 jme_interrupt_mode(jme);
2194 } else if (!(ecmd->use_adaptive_rx_coalesce)
2195 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2196 set_bit(JME_FLAG_POLL, &jme->flags);
2197 jme->jme_rx = netif_receive_skb;
2198 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2199 jme_interrupt_mode(jme);
2206 jme_get_pauseparam(struct net_device *netdev,
2207 struct ethtool_pauseparam *ecmd)
2209 struct jme_adapter *jme = netdev_priv(netdev);
2212 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2213 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2215 spin_lock_bh(&jme->phy_lock);
2216 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2217 spin_unlock_bh(&jme->phy_lock);
2220 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2224 jme_set_pauseparam(struct net_device *netdev,
2225 struct ethtool_pauseparam *ecmd)
2227 struct jme_adapter *jme = netdev_priv(netdev);
2230 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2231 (ecmd->tx_pause != 0)) {
2234 jme->reg_txpfc |= TXPFC_PF_EN;
2236 jme->reg_txpfc &= ~TXPFC_PF_EN;
2238 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2241 spin_lock_bh(&jme->rxmcs_lock);
2242 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2243 (ecmd->rx_pause != 0)) {
2246 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2248 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2250 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2252 spin_unlock_bh(&jme->rxmcs_lock);
2254 spin_lock_bh(&jme->phy_lock);
2255 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2256 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2257 (ecmd->autoneg != 0)) {
2260 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2262 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2264 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2265 MII_ADVERTISE, val);
2267 spin_unlock_bh(&jme->phy_lock);
2273 jme_get_wol(struct net_device *netdev,
2274 struct ethtool_wolinfo *wol)
2276 struct jme_adapter *jme = netdev_priv(netdev);
2278 wol->supported = WAKE_MAGIC | WAKE_PHY;
2282 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2283 wol->wolopts |= WAKE_PHY;
2285 if (jme->reg_pmcs & PMCS_MFEN)
2286 wol->wolopts |= WAKE_MAGIC;
2291 jme_set_wol(struct net_device *netdev,
2292 struct ethtool_wolinfo *wol)
2294 struct jme_adapter *jme = netdev_priv(netdev);
2296 if (wol->wolopts & (WAKE_MAGICSECURE |
2305 if (wol->wolopts & WAKE_PHY)
2306 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2308 if (wol->wolopts & WAKE_MAGIC)
2309 jme->reg_pmcs |= PMCS_MFEN;
2311 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2317 jme_get_settings(struct net_device *netdev,
2318 struct ethtool_cmd *ecmd)
2320 struct jme_adapter *jme = netdev_priv(netdev);
2323 spin_lock_bh(&jme->phy_lock);
2324 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2325 spin_unlock_bh(&jme->phy_lock);
2330 jme_set_settings(struct net_device *netdev,
2331 struct ethtool_cmd *ecmd)
2333 struct jme_adapter *jme = netdev_priv(netdev);
2336 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2339 if (jme->mii_if.force_media &&
2340 ecmd->autoneg != AUTONEG_ENABLE &&
2341 (jme->mii_if.full_duplex != ecmd->duplex))
2344 spin_lock_bh(&jme->phy_lock);
2345 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2346 spin_unlock_bh(&jme->phy_lock);
2349 jme_reset_link(jme);
2352 set_bit(JME_FLAG_SSET, &jme->flags);
2353 jme->old_ecmd = *ecmd;
2360 jme_get_link(struct net_device *netdev)
2362 struct jme_adapter *jme = netdev_priv(netdev);
2363 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2367 jme_get_msglevel(struct net_device *netdev)
2369 struct jme_adapter *jme = netdev_priv(netdev);
2370 return jme->msg_enable;
2374 jme_set_msglevel(struct net_device *netdev, u32 value)
2376 struct jme_adapter *jme = netdev_priv(netdev);
2377 jme->msg_enable = value;
2381 jme_get_rx_csum(struct net_device *netdev)
2383 struct jme_adapter *jme = netdev_priv(netdev);
2384 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2388 jme_set_rx_csum(struct net_device *netdev, u32 on)
2390 struct jme_adapter *jme = netdev_priv(netdev);
2392 spin_lock_bh(&jme->rxmcs_lock);
2394 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2396 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2397 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2398 spin_unlock_bh(&jme->rxmcs_lock);
2404 jme_set_tx_csum(struct net_device *netdev, u32 on)
2406 struct jme_adapter *jme = netdev_priv(netdev);
2409 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2410 if (netdev->mtu <= 1900)
2411 netdev->features |= NETIF_F_HW_CSUM;
2413 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2414 netdev->features &= ~NETIF_F_HW_CSUM;
2421 jme_set_tso(struct net_device *netdev, u32 on)
2423 struct jme_adapter *jme = netdev_priv(netdev);
2426 set_bit(JME_FLAG_TSO, &jme->flags);
2427 if (netdev->mtu <= 1900)
2428 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2430 clear_bit(JME_FLAG_TSO, &jme->flags);
2431 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2438 jme_nway_reset(struct net_device *netdev)
2440 struct jme_adapter *jme = netdev_priv(netdev);
2441 jme_restart_an(jme);
2446 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2451 val = jread32(jme, JME_SMBCSR);
2452 to = JME_SMB_BUSY_TIMEOUT;
2453 while ((val & SMBCSR_BUSY) && --to) {
2455 val = jread32(jme, JME_SMBCSR);
2458 msg_hw(jme, "SMB Bus Busy.\n");
2462 jwrite32(jme, JME_SMBINTF,
2463 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2464 SMBINTF_HWRWN_READ |
2467 val = jread32(jme, JME_SMBINTF);
2468 to = JME_SMB_BUSY_TIMEOUT;
2469 while ((val & SMBINTF_HWCMD) && --to) {
2471 val = jread32(jme, JME_SMBINTF);
2474 msg_hw(jme, "SMB Bus Busy.\n");
2478 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2482 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2487 val = jread32(jme, JME_SMBCSR);
2488 to = JME_SMB_BUSY_TIMEOUT;
2489 while ((val & SMBCSR_BUSY) && --to) {
2491 val = jread32(jme, JME_SMBCSR);
2494 msg_hw(jme, "SMB Bus Busy.\n");
2498 jwrite32(jme, JME_SMBINTF,
2499 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2500 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2501 SMBINTF_HWRWN_WRITE |
2504 val = jread32(jme, JME_SMBINTF);
2505 to = JME_SMB_BUSY_TIMEOUT;
2506 while ((val & SMBINTF_HWCMD) && --to) {
2508 val = jread32(jme, JME_SMBINTF);
2511 msg_hw(jme, "SMB Bus Busy.\n");
2519 jme_get_eeprom_len(struct net_device *netdev)
2521 struct jme_adapter *jme = netdev_priv(netdev);
2523 val = jread32(jme, JME_SMBCSR);
2524 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2528 jme_get_eeprom(struct net_device *netdev,
2529 struct ethtool_eeprom *eeprom, u8 *data)
2531 struct jme_adapter *jme = netdev_priv(netdev);
2532 int i, offset = eeprom->offset, len = eeprom->len;
2535 * ethtool will check the boundary for us
2537 eeprom->magic = JME_EEPROM_MAGIC;
2538 for (i = 0 ; i < len ; ++i)
2539 data[i] = jme_smb_read(jme, i + offset);
2545 jme_set_eeprom(struct net_device *netdev,
2546 struct ethtool_eeprom *eeprom, u8 *data)
2548 struct jme_adapter *jme = netdev_priv(netdev);
2549 int i, offset = eeprom->offset, len = eeprom->len;
2551 if (eeprom->magic != JME_EEPROM_MAGIC)
2555 * ethtool will check the boundary for us
2557 for (i = 0 ; i < len ; ++i)
2558 jme_smb_write(jme, i + offset, data[i]);
2563 static const struct ethtool_ops jme_ethtool_ops = {
2564 .get_drvinfo = jme_get_drvinfo,
2565 .get_regs_len = jme_get_regs_len,
2566 .get_regs = jme_get_regs,
2567 .get_coalesce = jme_get_coalesce,
2568 .set_coalesce = jme_set_coalesce,
2569 .get_pauseparam = jme_get_pauseparam,
2570 .set_pauseparam = jme_set_pauseparam,
2571 .get_wol = jme_get_wol,
2572 .set_wol = jme_set_wol,
2573 .get_settings = jme_get_settings,
2574 .set_settings = jme_set_settings,
2575 .get_link = jme_get_link,
2576 .get_msglevel = jme_get_msglevel,
2577 .set_msglevel = jme_set_msglevel,
2578 .get_rx_csum = jme_get_rx_csum,
2579 .set_rx_csum = jme_set_rx_csum,
2580 .set_tx_csum = jme_set_tx_csum,
2581 .set_tso = jme_set_tso,
2582 .set_sg = ethtool_op_set_sg,
2583 .nway_reset = jme_nway_reset,
2584 .get_eeprom_len = jme_get_eeprom_len,
2585 .get_eeprom = jme_get_eeprom,
2586 .set_eeprom = jme_set_eeprom,
2590 jme_pci_dma64(struct pci_dev *pdev)
2592 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2593 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2600 jme_phy_init(struct jme_adapter *jme)
2604 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2605 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2609 jme_check_hw_ver(struct jme_adapter *jme)
2613 chipmode = jread32(jme, JME_CHIPMODE);
2615 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2616 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2619 static const struct net_device_ops jme_netdev_ops = {
2620 .ndo_open = jme_open,
2621 .ndo_stop = jme_close,
2622 .ndo_validate_addr = eth_validate_addr,
2623 .ndo_start_xmit = jme_start_xmit,
2624 .ndo_set_mac_address = jme_set_macaddr,
2625 .ndo_set_multicast_list = jme_set_multi,
2626 .ndo_change_mtu = jme_change_mtu,
2627 .ndo_tx_timeout = jme_tx_timeout,
2628 .ndo_vlan_rx_register = jme_vlan_rx_register,
2631 static int __devinit
2632 jme_init_one(struct pci_dev *pdev,
2633 const struct pci_device_id *ent)
2635 int rc = 0, using_dac, i;
2636 struct net_device *netdev;
2637 struct jme_adapter *jme;
2642 * set up PCI device basics
2644 rc = pci_enable_device(pdev);
2646 jeprintk(pdev, "Cannot enable PCI device.\n");
2650 using_dac = jme_pci_dma64(pdev);
2651 if (using_dac < 0) {
2652 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2654 goto err_out_disable_pdev;
2657 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2658 jeprintk(pdev, "No PCI resource region found.\n");
2660 goto err_out_disable_pdev;
2663 rc = pci_request_regions(pdev, DRV_NAME);
2665 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2666 goto err_out_disable_pdev;
2669 pci_set_master(pdev);
2672 * alloc and init net device
2674 netdev = alloc_etherdev(sizeof(*jme));
2676 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2678 goto err_out_release_regions;
2680 netdev->netdev_ops = &jme_netdev_ops;
2681 netdev->ethtool_ops = &jme_ethtool_ops;
2682 netdev->watchdog_timeo = TX_TIMEOUT;
2683 netdev->features = NETIF_F_HW_CSUM |
2687 NETIF_F_HW_VLAN_TX |
2690 netdev->features |= NETIF_F_HIGHDMA;
2692 SET_NETDEV_DEV(netdev, &pdev->dev);
2693 pci_set_drvdata(pdev, netdev);
2698 jme = netdev_priv(netdev);
2701 jme->jme_rx = netif_rx;
2702 jme->jme_vlan_rx = vlan_hwaccel_rx;
2703 jme->old_mtu = netdev->mtu = 1500;
2705 jme->tx_ring_size = 1 << 10;
2706 jme->tx_ring_mask = jme->tx_ring_size - 1;
2707 jme->tx_wake_threshold = 1 << 9;
2708 jme->rx_ring_size = 1 << 9;
2709 jme->rx_ring_mask = jme->rx_ring_size - 1;
2710 jme->msg_enable = JME_DEF_MSG_ENABLE;
2711 jme->regs = ioremap(pci_resource_start(pdev, 0),
2712 pci_resource_len(pdev, 0));
2714 jeprintk(pdev, "Mapping PCI resource region error.\n");
2716 goto err_out_free_netdev;
2718 jme->shadow_regs = pci_alloc_consistent(pdev,
2719 sizeof(u32) * SHADOW_REG_NR,
2720 &(jme->shadow_dma));
2721 if (!(jme->shadow_regs)) {
2722 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2728 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2729 jwrite32(jme, JME_APMC, apmc);
2730 } else if (force_pseudohp) {
2731 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2732 jwrite32(jme, JME_APMC, apmc);
2735 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2737 spin_lock_init(&jme->phy_lock);
2738 spin_lock_init(&jme->macaddr_lock);
2739 spin_lock_init(&jme->rxmcs_lock);
2741 atomic_set(&jme->link_changing, 1);
2742 atomic_set(&jme->rx_cleaning, 1);
2743 atomic_set(&jme->tx_cleaning, 1);
2744 atomic_set(&jme->rx_empty, 1);
2746 tasklet_init(&jme->pcc_task,
2748 (unsigned long) jme);
2749 tasklet_init(&jme->linkch_task,
2750 &jme_link_change_tasklet,
2751 (unsigned long) jme);
2752 tasklet_init(&jme->txclean_task,
2753 &jme_tx_clean_tasklet,
2754 (unsigned long) jme);
2755 tasklet_init(&jme->rxclean_task,
2756 &jme_rx_clean_tasklet,
2757 (unsigned long) jme);
2758 tasklet_init(&jme->rxempty_task,
2759 &jme_rx_empty_tasklet,
2760 (unsigned long) jme);
2761 tasklet_disable_nosync(&jme->txclean_task);
2762 tasklet_disable_nosync(&jme->rxclean_task);
2763 tasklet_disable_nosync(&jme->rxempty_task);
2764 jme->dpi.cur = PCC_P1;
2767 jme->reg_rxcs = RXCS_DEFAULT;
2768 jme->reg_rxmcs = RXMCS_DEFAULT;
2770 jme->reg_pmcs = PMCS_MFEN;
2771 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2772 set_bit(JME_FLAG_TSO, &jme->flags);
2775 * Get Max Read Req Size from PCI Config Space
2777 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2778 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2779 switch (jme->mrrs) {
2781 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2784 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2787 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2792 * Must check before reset_mac_processor
2794 jme_check_hw_ver(jme);
2795 jme->mii_if.dev = netdev;
2797 jme->mii_if.phy_id = 0;
2798 for (i = 1 ; i < 32 ; ++i) {
2799 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2800 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2801 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2802 jme->mii_if.phy_id = i;
2807 if (!jme->mii_if.phy_id) {
2809 jeprintk(pdev, "Can not find phy_id.\n");
2810 goto err_out_free_shadow;
2813 jme->reg_ghc |= GHC_LINK_POLL;
2815 jme->mii_if.phy_id = 1;
2817 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2818 jme->mii_if.supports_gmii = true;
2820 jme->mii_if.supports_gmii = false;
2821 jme->mii_if.mdio_read = jme_mdio_read;
2822 jme->mii_if.mdio_write = jme_mdio_write;
2825 jme_set_phyfifoa(jme);
2826 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2832 * Reset MAC processor and reload EEPROM for MAC Address
2834 jme_reset_mac_processor(jme);
2835 rc = jme_reload_eeprom(jme);
2838 "Reload eeprom for reading MAC Address error.\n");
2839 goto err_out_free_shadow;
2841 jme_load_macaddr(netdev);
2844 * Tell stack that we are not ready to work until open()
2846 netif_carrier_off(netdev);
2847 netif_stop_queue(netdev);
2852 rc = register_netdev(netdev);
2854 jeprintk(pdev, "Cannot register net device.\n");
2855 goto err_out_free_shadow;
2858 msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2859 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2860 "JMC250 Gigabit Ethernet" :
2861 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2862 "JMC260 Fast Ethernet" : "Unknown",
2863 (jme->fpgaver != 0) ? " (FPGA)" : "",
2864 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2865 jme->rev, netdev->dev_addr);
2869 err_out_free_shadow:
2870 pci_free_consistent(pdev,
2871 sizeof(u32) * SHADOW_REG_NR,
2876 err_out_free_netdev:
2877 pci_set_drvdata(pdev, NULL);
2878 free_netdev(netdev);
2879 err_out_release_regions:
2880 pci_release_regions(pdev);
2881 err_out_disable_pdev:
2882 pci_disable_device(pdev);
2887 static void __devexit
2888 jme_remove_one(struct pci_dev *pdev)
2890 struct net_device *netdev = pci_get_drvdata(pdev);
2891 struct jme_adapter *jme = netdev_priv(netdev);
2893 unregister_netdev(netdev);
2894 pci_free_consistent(pdev,
2895 sizeof(u32) * SHADOW_REG_NR,
2899 pci_set_drvdata(pdev, NULL);
2900 free_netdev(netdev);
2901 pci_release_regions(pdev);
2902 pci_disable_device(pdev);
2908 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2910 struct net_device *netdev = pci_get_drvdata(pdev);
2911 struct jme_adapter *jme = netdev_priv(netdev);
2913 atomic_dec(&jme->link_changing);
2915 netif_device_detach(netdev);
2916 netif_stop_queue(netdev);
2919 tasklet_disable(&jme->txclean_task);
2920 tasklet_disable(&jme->rxclean_task);
2921 tasklet_disable(&jme->rxempty_task);
2923 jme_disable_shadow(jme);
2925 if (netif_carrier_ok(netdev)) {
2926 if (test_bit(JME_FLAG_POLL, &jme->flags))
2927 jme_polling_mode(jme);
2929 jme_stop_pcc_timer(jme);
2930 jme_reset_ghc_speed(jme);
2931 jme_disable_rx_engine(jme);
2932 jme_disable_tx_engine(jme);
2933 jme_reset_mac_processor(jme);
2934 jme_free_rx_resources(jme);
2935 jme_free_tx_resources(jme);
2936 netif_carrier_off(netdev);
2940 tasklet_enable(&jme->txclean_task);
2941 tasklet_hi_enable(&jme->rxclean_task);
2942 tasklet_hi_enable(&jme->rxempty_task);
2944 pci_save_state(pdev);
2945 if (jme->reg_pmcs) {
2946 jme_set_100m_half(jme);
2948 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2951 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2953 pci_enable_wake(pdev, PCI_D3cold, true);
2957 pci_set_power_state(pdev, PCI_D3cold);
2963 jme_resume(struct pci_dev *pdev)
2965 struct net_device *netdev = pci_get_drvdata(pdev);
2966 struct jme_adapter *jme = netdev_priv(netdev);
2969 pci_restore_state(pdev);
2971 if (test_bit(JME_FLAG_SSET, &jme->flags))
2972 jme_set_settings(netdev, &jme->old_ecmd);
2974 jme_reset_phy_processor(jme);
2976 jme_enable_shadow(jme);
2978 netif_device_attach(netdev);
2980 atomic_inc(&jme->link_changing);
2982 jme_reset_link(jme);
2988 static struct pci_device_id jme_pci_tbl[] = {
2989 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2990 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
2994 static struct pci_driver jme_driver = {
2996 .id_table = jme_pci_tbl,
2997 .probe = jme_init_one,
2998 .remove = __devexit_p(jme_remove_one),
3000 .suspend = jme_suspend,
3001 .resume = jme_resume,
3002 #endif /* CONFIG_PM */
3006 jme_init_module(void)
3008 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3009 "driver version %s\n", DRV_VERSION);
3010 return pci_register_driver(&jme_driver);
3014 jme_cleanup_module(void)
3016 pci_unregister_driver(&jme_driver);
3019 module_init(jme_init_module);
3020 module_exit(jme_cleanup_module);
3022 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3023 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3024 MODULE_LICENSE("GPL");
3025 MODULE_VERSION(DRV_VERSION);
3026 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);