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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[mv-sheeva.git] / drivers / net / ll_temac_main.c
1 /*
2  * Driver for Xilinx TEMAC Ethernet device
3  *
4  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
5  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
6  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7  *
8  * This is a driver for the Xilinx ll_temac ipcore which is often used
9  * in the Virtex and Spartan series of chips.
10  *
11  * Notes:
12  * - The ll_temac hardware uses indirect access for many of the TEMAC
13  *   registers, include the MDIO bus.  However, indirect access to MDIO
14  *   registers take considerably more clock cycles than to TEMAC registers.
15  *   MDIO accesses are long, so threads doing them should probably sleep
16  *   rather than busywait.  However, since only one indirect access can be
17  *   in progress at any given time, that means that *all* indirect accesses
18  *   could end up sleeping (to wait for an MDIO access to complete).
19  *   Fortunately none of the indirect accesses are on the 'hot' path for tx
20  *   or rx, so this should be okay.
21  *
22  * TODO:
23  * - Factor out locallink DMA code into separate driver
24  * - Fix multicast assignment.
25  * - Fix support for hardware checksumming.
26  * - Testing.  Lots and lots of testing.
27  *
28  */
29
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/tcp.h>      /* needed for sizeof(tcphdr) */
44 #include <linux/udp.h>      /* needed for sizeof(udphdr) */
45 #include <linux/phy.h>
46 #include <linux/in.h>
47 #include <linux/io.h>
48 #include <linux/ip.h>
49 #include <linux/slab.h>
50
51 #include "ll_temac.h"
52
53 #define TX_BD_NUM   64
54 #define RX_BD_NUM   128
55
56 /* ---------------------------------------------------------------------
57  * Low level register access functions
58  */
59
60 u32 temac_ior(struct temac_local *lp, int offset)
61 {
62         return in_be32((u32 *)(lp->regs + offset));
63 }
64
65 void temac_iow(struct temac_local *lp, int offset, u32 value)
66 {
67         out_be32((u32 *) (lp->regs + offset), value);
68 }
69
70 int temac_indirect_busywait(struct temac_local *lp)
71 {
72         long end = jiffies + 2;
73
74         while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
75                 if (end - jiffies <= 0) {
76                         WARN_ON(1);
77                         return -ETIMEDOUT;
78                 }
79                 msleep(1);
80         }
81         return 0;
82 }
83
84 /**
85  * temac_indirect_in32
86  *
87  * lp->indirect_mutex must be held when calling this function
88  */
89 u32 temac_indirect_in32(struct temac_local *lp, int reg)
90 {
91         u32 val;
92
93         if (temac_indirect_busywait(lp))
94                 return -ETIMEDOUT;
95         temac_iow(lp, XTE_CTL0_OFFSET, reg);
96         if (temac_indirect_busywait(lp))
97                 return -ETIMEDOUT;
98         val = temac_ior(lp, XTE_LSW0_OFFSET);
99
100         return val;
101 }
102
103 /**
104  * temac_indirect_out32
105  *
106  * lp->indirect_mutex must be held when calling this function
107  */
108 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
109 {
110         if (temac_indirect_busywait(lp))
111                 return;
112         temac_iow(lp, XTE_LSW0_OFFSET, value);
113         temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
114 }
115
116 /**
117  * temac_dma_in32 - Memory mapped DMA read, this function expects a
118  * register input that is based on DCR word addresses which
119  * are then converted to memory mapped byte addresses
120  */
121 static u32 temac_dma_in32(struct temac_local *lp, int reg)
122 {
123         return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
124 }
125
126 /**
127  * temac_dma_out32 - Memory mapped DMA read, this function expects a
128  * register input that is based on DCR word addresses which
129  * are then converted to memory mapped byte addresses
130  */
131 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
132 {
133         out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
134 }
135
136 /* DMA register access functions can be DCR based or memory mapped.
137  * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
138  * memory mapped.
139  */
140 #ifdef CONFIG_PPC_DCR
141
142 /**
143  * temac_dma_dcr_in32 - DCR based DMA read
144  */
145 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
146 {
147         return dcr_read(lp->sdma_dcrs, reg);
148 }
149
150 /**
151  * temac_dma_dcr_out32 - DCR based DMA write
152  */
153 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
154 {
155         dcr_write(lp->sdma_dcrs, reg, value);
156 }
157
158 /**
159  * temac_dcr_setup - If the DMA is DCR based, then setup the address and
160  * I/O  functions
161  */
162 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
163                                 struct device_node *np)
164 {
165         unsigned int dcrs;
166
167         /* setup the dcr address mapping if it's in the device tree */
168
169         dcrs = dcr_resource_start(np, 0);
170         if (dcrs != 0) {
171                 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
172                 lp->dma_in = temac_dma_dcr_in;
173                 lp->dma_out = temac_dma_dcr_out;
174                 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
175                 return 0;
176         }
177         /* no DCR in the device tree, indicate a failure */
178         return -1;
179 }
180
181 #else
182
183 /*
184  * temac_dcr_setup - This is a stub for when DCR is not supported,
185  * such as with MicroBlaze
186  */
187 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
188                                 struct device_node *np)
189 {
190         return -1;
191 }
192
193 #endif
194
195 /**
196  *  * temac_dma_bd_release - Release buffer descriptor rings
197  */
198 static void temac_dma_bd_release(struct net_device *ndev)
199 {
200         struct temac_local *lp = netdev_priv(ndev);
201         int i;
202
203         for (i = 0; i < RX_BD_NUM; i++) {
204                 if (!lp->rx_skb[i])
205                         break;
206                 else {
207                         dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
208                                         XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
209                         dev_kfree_skb(lp->rx_skb[i]);
210                 }
211         }
212         if (lp->rx_bd_v)
213                 dma_free_coherent(ndev->dev.parent,
214                                 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
215                                 lp->rx_bd_v, lp->rx_bd_p);
216         if (lp->tx_bd_v)
217                 dma_free_coherent(ndev->dev.parent,
218                                 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
219                                 lp->tx_bd_v, lp->tx_bd_p);
220         if (lp->rx_skb)
221                 kfree(lp->rx_skb);
222 }
223
224 /**
225  * temac_dma_bd_init - Setup buffer descriptor rings
226  */
227 static int temac_dma_bd_init(struct net_device *ndev)
228 {
229         struct temac_local *lp = netdev_priv(ndev);
230         struct sk_buff *skb;
231         int i;
232
233         lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
234         if (!lp->rx_skb) {
235                 dev_err(&ndev->dev,
236                                 "can't allocate memory for DMA RX buffer\n");
237                 goto out;
238         }
239         /* allocate the tx and rx ring buffer descriptors. */
240         /* returns a virtual addres and a physical address. */
241         lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
242                                          sizeof(*lp->tx_bd_v) * TX_BD_NUM,
243                                          &lp->tx_bd_p, GFP_KERNEL);
244         if (!lp->tx_bd_v) {
245                 dev_err(&ndev->dev,
246                                 "unable to allocate DMA TX buffer descriptors");
247                 goto out;
248         }
249         lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
250                                          sizeof(*lp->rx_bd_v) * RX_BD_NUM,
251                                          &lp->rx_bd_p, GFP_KERNEL);
252         if (!lp->rx_bd_v) {
253                 dev_err(&ndev->dev,
254                                 "unable to allocate DMA RX buffer descriptors");
255                 goto out;
256         }
257
258         memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
259         for (i = 0; i < TX_BD_NUM; i++) {
260                 lp->tx_bd_v[i].next = lp->tx_bd_p +
261                                 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
262         }
263
264         memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
265         for (i = 0; i < RX_BD_NUM; i++) {
266                 lp->rx_bd_v[i].next = lp->rx_bd_p +
267                                 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
268
269                 skb = netdev_alloc_skb_ip_align(ndev,
270                                                 XTE_MAX_JUMBO_FRAME_SIZE);
271
272                 if (skb == 0) {
273                         dev_err(&ndev->dev, "alloc_skb error %d\n", i);
274                         goto out;
275                 }
276                 lp->rx_skb[i] = skb;
277                 /* returns physical address of skb->data */
278                 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
279                                                      skb->data,
280                                                      XTE_MAX_JUMBO_FRAME_SIZE,
281                                                      DMA_FROM_DEVICE);
282                 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
283                 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
284         }
285
286         lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
287                                           CHNL_CTRL_IRQ_EN |
288                                           CHNL_CTRL_IRQ_DLY_EN |
289                                           CHNL_CTRL_IRQ_COAL_EN);
290         /* 0x10220483 */
291         /* 0x00100483 */
292         lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
293                                           CHNL_CTRL_IRQ_EN |
294                                           CHNL_CTRL_IRQ_DLY_EN |
295                                           CHNL_CTRL_IRQ_COAL_EN |
296                                           CHNL_CTRL_IRQ_IOE);
297         /* 0xff010283 */
298
299         lp->dma_out(lp, RX_CURDESC_PTR,  lp->rx_bd_p);
300         lp->dma_out(lp, RX_TAILDESC_PTR,
301                        lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
302         lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
303
304         return 0;
305
306 out:
307         temac_dma_bd_release(ndev);
308         return -ENOMEM;
309 }
310
311 /* ---------------------------------------------------------------------
312  * net_device_ops
313  */
314
315 static int temac_set_mac_address(struct net_device *ndev, void *address)
316 {
317         struct temac_local *lp = netdev_priv(ndev);
318
319         if (address)
320                 memcpy(ndev->dev_addr, address, ETH_ALEN);
321
322         if (!is_valid_ether_addr(ndev->dev_addr))
323                 random_ether_addr(ndev->dev_addr);
324
325         /* set up unicast MAC address filter set its mac address */
326         mutex_lock(&lp->indirect_mutex);
327         temac_indirect_out32(lp, XTE_UAW0_OFFSET,
328                              (ndev->dev_addr[0]) |
329                              (ndev->dev_addr[1] << 8) |
330                              (ndev->dev_addr[2] << 16) |
331                              (ndev->dev_addr[3] << 24));
332         /* There are reserved bits in EUAW1
333          * so don't affect them Set MAC bits [47:32] in EUAW1 */
334         temac_indirect_out32(lp, XTE_UAW1_OFFSET,
335                              (ndev->dev_addr[4] & 0x000000ff) |
336                              (ndev->dev_addr[5] << 8));
337         mutex_unlock(&lp->indirect_mutex);
338
339         return 0;
340 }
341
342 static int netdev_set_mac_address(struct net_device *ndev, void *p)
343 {
344         struct sockaddr *addr = p;
345
346         return temac_set_mac_address(ndev, addr->sa_data);
347 }
348
349 static void temac_set_multicast_list(struct net_device *ndev)
350 {
351         struct temac_local *lp = netdev_priv(ndev);
352         u32 multi_addr_msw, multi_addr_lsw, val;
353         int i;
354
355         mutex_lock(&lp->indirect_mutex);
356         if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
357             netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
358                 /*
359                  *      We must make the kernel realise we had to move
360                  *      into promisc mode or we start all out war on
361                  *      the cable. If it was a promisc request the
362                  *      flag is already set. If not we assert it.
363                  */
364                 ndev->flags |= IFF_PROMISC;
365                 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
366                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
367         } else if (!netdev_mc_empty(ndev)) {
368                 struct netdev_hw_addr *ha;
369
370                 i = 0;
371                 netdev_for_each_mc_addr(ha, ndev) {
372                         if (i >= MULTICAST_CAM_TABLE_NUM)
373                                 break;
374                         multi_addr_msw = ((ha->addr[3] << 24) |
375                                           (ha->addr[2] << 16) |
376                                           (ha->addr[1] << 8) |
377                                           (ha->addr[0]));
378                         temac_indirect_out32(lp, XTE_MAW0_OFFSET,
379                                              multi_addr_msw);
380                         multi_addr_lsw = ((ha->addr[5] << 8) |
381                                           (ha->addr[4]) | (i << 16));
382                         temac_indirect_out32(lp, XTE_MAW1_OFFSET,
383                                              multi_addr_lsw);
384                         i++;
385                 }
386         } else {
387                 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
388                 temac_indirect_out32(lp, XTE_AFM_OFFSET,
389                                      val & ~XTE_AFM_EPPRM_MASK);
390                 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
391                 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
392                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
393         }
394         mutex_unlock(&lp->indirect_mutex);
395 }
396
397 struct temac_option {
398         int flg;
399         u32 opt;
400         u32 reg;
401         u32 m_or;
402         u32 m_and;
403 } temac_options[] = {
404         /* Turn on jumbo packet support for both Rx and Tx */
405         {
406                 .opt = XTE_OPTION_JUMBO,
407                 .reg = XTE_TXC_OFFSET,
408                 .m_or = XTE_TXC_TXJMBO_MASK,
409         },
410         {
411                 .opt = XTE_OPTION_JUMBO,
412                 .reg = XTE_RXC1_OFFSET,
413                 .m_or =XTE_RXC1_RXJMBO_MASK,
414         },
415         /* Turn on VLAN packet support for both Rx and Tx */
416         {
417                 .opt = XTE_OPTION_VLAN,
418                 .reg = XTE_TXC_OFFSET,
419                 .m_or =XTE_TXC_TXVLAN_MASK,
420         },
421         {
422                 .opt = XTE_OPTION_VLAN,
423                 .reg = XTE_RXC1_OFFSET,
424                 .m_or =XTE_RXC1_RXVLAN_MASK,
425         },
426         /* Turn on FCS stripping on receive packets */
427         {
428                 .opt = XTE_OPTION_FCS_STRIP,
429                 .reg = XTE_RXC1_OFFSET,
430                 .m_or =XTE_RXC1_RXFCS_MASK,
431         },
432         /* Turn on FCS insertion on transmit packets */
433         {
434                 .opt = XTE_OPTION_FCS_INSERT,
435                 .reg = XTE_TXC_OFFSET,
436                 .m_or =XTE_TXC_TXFCS_MASK,
437         },
438         /* Turn on length/type field checking on receive packets */
439         {
440                 .opt = XTE_OPTION_LENTYPE_ERR,
441                 .reg = XTE_RXC1_OFFSET,
442                 .m_or =XTE_RXC1_RXLT_MASK,
443         },
444         /* Turn on flow control */
445         {
446                 .opt = XTE_OPTION_FLOW_CONTROL,
447                 .reg = XTE_FCC_OFFSET,
448                 .m_or =XTE_FCC_RXFLO_MASK,
449         },
450         /* Turn on flow control */
451         {
452                 .opt = XTE_OPTION_FLOW_CONTROL,
453                 .reg = XTE_FCC_OFFSET,
454                 .m_or =XTE_FCC_TXFLO_MASK,
455         },
456         /* Turn on promiscuous frame filtering (all frames are received ) */
457         {
458                 .opt = XTE_OPTION_PROMISC,
459                 .reg = XTE_AFM_OFFSET,
460                 .m_or =XTE_AFM_EPPRM_MASK,
461         },
462         /* Enable transmitter if not already enabled */
463         {
464                 .opt = XTE_OPTION_TXEN,
465                 .reg = XTE_TXC_OFFSET,
466                 .m_or =XTE_TXC_TXEN_MASK,
467         },
468         /* Enable receiver? */
469         {
470                 .opt = XTE_OPTION_RXEN,
471                 .reg = XTE_RXC1_OFFSET,
472                 .m_or =XTE_RXC1_RXEN_MASK,
473         },
474         {}
475 };
476
477 /**
478  * temac_setoptions
479  */
480 static u32 temac_setoptions(struct net_device *ndev, u32 options)
481 {
482         struct temac_local *lp = netdev_priv(ndev);
483         struct temac_option *tp = &temac_options[0];
484         int reg;
485
486         mutex_lock(&lp->indirect_mutex);
487         while (tp->opt) {
488                 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
489                 if (options & tp->opt)
490                         reg |= tp->m_or;
491                 temac_indirect_out32(lp, tp->reg, reg);
492                 tp++;
493         }
494         lp->options |= options;
495         mutex_unlock(&lp->indirect_mutex);
496
497         return (0);
498 }
499
500 /* Initialize temac */
501 static void temac_device_reset(struct net_device *ndev)
502 {
503         struct temac_local *lp = netdev_priv(ndev);
504         u32 timeout;
505         u32 val;
506
507         /* Perform a software reset */
508
509         /* 0x300 host enable bit ? */
510         /* reset PHY through control register ?:1 */
511
512         dev_dbg(&ndev->dev, "%s()\n", __func__);
513
514         mutex_lock(&lp->indirect_mutex);
515         /* Reset the receiver and wait for it to finish reset */
516         temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
517         timeout = 1000;
518         while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
519                 udelay(1);
520                 if (--timeout == 0) {
521                         dev_err(&ndev->dev,
522                                 "temac_device_reset RX reset timeout!!\n");
523                         break;
524                 }
525         }
526
527         /* Reset the transmitter and wait for it to finish reset */
528         temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
529         timeout = 1000;
530         while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
531                 udelay(1);
532                 if (--timeout == 0) {
533                         dev_err(&ndev->dev,
534                                 "temac_device_reset TX reset timeout!!\n");
535                         break;
536                 }
537         }
538
539         /* Disable the receiver */
540         val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
541         temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
542
543         /* Reset Local Link (DMA) */
544         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
545         timeout = 1000;
546         while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
547                 udelay(1);
548                 if (--timeout == 0) {
549                         dev_err(&ndev->dev,
550                                 "temac_device_reset DMA reset timeout!!\n");
551                         break;
552                 }
553         }
554         lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
555
556         if (temac_dma_bd_init(ndev)) {
557                 dev_err(&ndev->dev,
558                                 "temac_device_reset descriptor allocation failed\n");
559         }
560
561         temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
562         temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
563         temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
564         temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
565
566         mutex_unlock(&lp->indirect_mutex);
567
568         /* Sync default options with HW
569          * but leave receiver and transmitter disabled.  */
570         temac_setoptions(ndev,
571                          lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
572
573         temac_set_mac_address(ndev, NULL);
574
575         /* Set address filter table */
576         temac_set_multicast_list(ndev);
577         if (temac_setoptions(ndev, lp->options))
578                 dev_err(&ndev->dev, "Error setting TEMAC options\n");
579
580         /* Init Driver variable */
581         ndev->trans_start = jiffies; /* prevent tx timeout */
582 }
583
584 void temac_adjust_link(struct net_device *ndev)
585 {
586         struct temac_local *lp = netdev_priv(ndev);
587         struct phy_device *phy = lp->phy_dev;
588         u32 mii_speed;
589         int link_state;
590
591         /* hash together the state values to decide if something has changed */
592         link_state = phy->speed | (phy->duplex << 1) | phy->link;
593
594         mutex_lock(&lp->indirect_mutex);
595         if (lp->last_link != link_state) {
596                 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
597                 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
598
599                 switch (phy->speed) {
600                 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
601                 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
602                 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
603                 }
604
605                 /* Write new speed setting out to TEMAC */
606                 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
607                 lp->last_link = link_state;
608                 phy_print_status(phy);
609         }
610         mutex_unlock(&lp->indirect_mutex);
611 }
612
613 static void temac_start_xmit_done(struct net_device *ndev)
614 {
615         struct temac_local *lp = netdev_priv(ndev);
616         struct cdmac_bd *cur_p;
617         unsigned int stat = 0;
618
619         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
620         stat = cur_p->app0;
621
622         while (stat & STS_CTRL_APP0_CMPLT) {
623                 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
624                                  DMA_TO_DEVICE);
625                 if (cur_p->app4)
626                         dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
627                 cur_p->app0 = 0;
628                 cur_p->app1 = 0;
629                 cur_p->app2 = 0;
630                 cur_p->app3 = 0;
631                 cur_p->app4 = 0;
632
633                 ndev->stats.tx_packets++;
634                 ndev->stats.tx_bytes += cur_p->len;
635
636                 lp->tx_bd_ci++;
637                 if (lp->tx_bd_ci >= TX_BD_NUM)
638                         lp->tx_bd_ci = 0;
639
640                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
641                 stat = cur_p->app0;
642         }
643
644         netif_wake_queue(ndev);
645 }
646
647 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
648 {
649         struct cdmac_bd *cur_p;
650         int tail;
651
652         tail = lp->tx_bd_tail;
653         cur_p = &lp->tx_bd_v[tail];
654
655         do {
656                 if (cur_p->app0)
657                         return NETDEV_TX_BUSY;
658
659                 tail++;
660                 if (tail >= TX_BD_NUM)
661                         tail = 0;
662
663                 cur_p = &lp->tx_bd_v[tail];
664                 num_frag--;
665         } while (num_frag >= 0);
666
667         return 0;
668 }
669
670 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
671 {
672         struct temac_local *lp = netdev_priv(ndev);
673         struct cdmac_bd *cur_p;
674         dma_addr_t start_p, tail_p;
675         int ii;
676         unsigned long num_frag;
677         skb_frag_t *frag;
678
679         num_frag = skb_shinfo(skb)->nr_frags;
680         frag = &skb_shinfo(skb)->frags[0];
681         start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
682         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
683
684         if (temac_check_tx_bd_space(lp, num_frag)) {
685                 if (!netif_queue_stopped(ndev)) {
686                         netif_stop_queue(ndev);
687                         return NETDEV_TX_BUSY;
688                 }
689                 return NETDEV_TX_BUSY;
690         }
691
692         cur_p->app0 = 0;
693         if (skb->ip_summed == CHECKSUM_PARTIAL) {
694                 unsigned int csum_start_off = skb_transport_offset(skb);
695                 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
696
697                 cur_p->app0 |= 1; /* TX Checksum Enabled */
698                 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
699                 cur_p->app2 = 0;  /* initial checksum seed */
700         }
701
702         cur_p->app0 |= STS_CTRL_APP0_SOP;
703         cur_p->len = skb_headlen(skb);
704         cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
705                                      DMA_TO_DEVICE);
706         cur_p->app4 = (unsigned long)skb;
707
708         for (ii = 0; ii < num_frag; ii++) {
709                 lp->tx_bd_tail++;
710                 if (lp->tx_bd_tail >= TX_BD_NUM)
711                         lp->tx_bd_tail = 0;
712
713                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
714                 cur_p->phys = dma_map_single(ndev->dev.parent,
715                                              (void *)page_address(frag->page) +
716                                                   frag->page_offset,
717                                              frag->size, DMA_TO_DEVICE);
718                 cur_p->len = frag->size;
719                 cur_p->app0 = 0;
720                 frag++;
721         }
722         cur_p->app0 |= STS_CTRL_APP0_EOP;
723
724         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
725         lp->tx_bd_tail++;
726         if (lp->tx_bd_tail >= TX_BD_NUM)
727                 lp->tx_bd_tail = 0;
728
729         /* Kick off the transfer */
730         lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
731
732         return NETDEV_TX_OK;
733 }
734
735
736 static void ll_temac_recv(struct net_device *ndev)
737 {
738         struct temac_local *lp = netdev_priv(ndev);
739         struct sk_buff *skb, *new_skb;
740         unsigned int bdstat;
741         struct cdmac_bd *cur_p;
742         dma_addr_t tail_p;
743         int length;
744         unsigned long flags;
745
746         spin_lock_irqsave(&lp->rx_lock, flags);
747
748         tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
749         cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
750
751         bdstat = cur_p->app0;
752         while ((bdstat & STS_CTRL_APP0_CMPLT)) {
753
754                 skb = lp->rx_skb[lp->rx_bd_ci];
755                 length = cur_p->app4 & 0x3FFF;
756
757                 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
758                                  DMA_FROM_DEVICE);
759
760                 skb_put(skb, length);
761                 skb->dev = ndev;
762                 skb->protocol = eth_type_trans(skb, ndev);
763                 skb->ip_summed = CHECKSUM_NONE;
764
765                 /* if we're doing rx csum offload, set it up */
766                 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
767                         (skb->protocol == __constant_htons(ETH_P_IP)) &&
768                         (skb->len > 64)) {
769
770                         skb->csum = cur_p->app3 & 0xFFFF;
771                         skb->ip_summed = CHECKSUM_COMPLETE;
772                 }
773
774                 netif_rx(skb);
775
776                 ndev->stats.rx_packets++;
777                 ndev->stats.rx_bytes += length;
778
779                 new_skb = netdev_alloc_skb_ip_align(ndev,
780                                                 XTE_MAX_JUMBO_FRAME_SIZE);
781
782                 if (new_skb == 0) {
783                         dev_err(&ndev->dev, "no memory for new sk_buff\n");
784                         spin_unlock_irqrestore(&lp->rx_lock, flags);
785                         return;
786                 }
787
788                 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
789                 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
790                                              XTE_MAX_JUMBO_FRAME_SIZE,
791                                              DMA_FROM_DEVICE);
792                 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
793                 lp->rx_skb[lp->rx_bd_ci] = new_skb;
794
795                 lp->rx_bd_ci++;
796                 if (lp->rx_bd_ci >= RX_BD_NUM)
797                         lp->rx_bd_ci = 0;
798
799                 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
800                 bdstat = cur_p->app0;
801         }
802         lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
803
804         spin_unlock_irqrestore(&lp->rx_lock, flags);
805 }
806
807 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
808 {
809         struct net_device *ndev = _ndev;
810         struct temac_local *lp = netdev_priv(ndev);
811         unsigned int status;
812
813         status = lp->dma_in(lp, TX_IRQ_REG);
814         lp->dma_out(lp, TX_IRQ_REG, status);
815
816         if (status & (IRQ_COAL | IRQ_DLY))
817                 temac_start_xmit_done(lp->ndev);
818         if (status & 0x080)
819                 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
820
821         return IRQ_HANDLED;
822 }
823
824 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
825 {
826         struct net_device *ndev = _ndev;
827         struct temac_local *lp = netdev_priv(ndev);
828         unsigned int status;
829
830         /* Read and clear the status registers */
831         status = lp->dma_in(lp, RX_IRQ_REG);
832         lp->dma_out(lp, RX_IRQ_REG, status);
833
834         if (status & (IRQ_COAL | IRQ_DLY))
835                 ll_temac_recv(lp->ndev);
836
837         return IRQ_HANDLED;
838 }
839
840 static int temac_open(struct net_device *ndev)
841 {
842         struct temac_local *lp = netdev_priv(ndev);
843         int rc;
844
845         dev_dbg(&ndev->dev, "temac_open()\n");
846
847         if (lp->phy_node) {
848                 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
849                                              temac_adjust_link, 0, 0);
850                 if (!lp->phy_dev) {
851                         dev_err(lp->dev, "of_phy_connect() failed\n");
852                         return -ENODEV;
853                 }
854
855                 phy_start(lp->phy_dev);
856         }
857
858         rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
859         if (rc)
860                 goto err_tx_irq;
861         rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
862         if (rc)
863                 goto err_rx_irq;
864
865         temac_device_reset(ndev);
866         return 0;
867
868  err_rx_irq:
869         free_irq(lp->tx_irq, ndev);
870  err_tx_irq:
871         if (lp->phy_dev)
872                 phy_disconnect(lp->phy_dev);
873         lp->phy_dev = NULL;
874         dev_err(lp->dev, "request_irq() failed\n");
875         return rc;
876 }
877
878 static int temac_stop(struct net_device *ndev)
879 {
880         struct temac_local *lp = netdev_priv(ndev);
881
882         dev_dbg(&ndev->dev, "temac_close()\n");
883
884         free_irq(lp->tx_irq, ndev);
885         free_irq(lp->rx_irq, ndev);
886
887         if (lp->phy_dev)
888                 phy_disconnect(lp->phy_dev);
889         lp->phy_dev = NULL;
890
891         temac_dma_bd_release(ndev);
892
893         return 0;
894 }
895
896 #ifdef CONFIG_NET_POLL_CONTROLLER
897 static void
898 temac_poll_controller(struct net_device *ndev)
899 {
900         struct temac_local *lp = netdev_priv(ndev);
901
902         disable_irq(lp->tx_irq);
903         disable_irq(lp->rx_irq);
904
905         ll_temac_rx_irq(lp->tx_irq, ndev);
906         ll_temac_tx_irq(lp->rx_irq, ndev);
907
908         enable_irq(lp->tx_irq);
909         enable_irq(lp->rx_irq);
910 }
911 #endif
912
913 static const struct net_device_ops temac_netdev_ops = {
914         .ndo_open = temac_open,
915         .ndo_stop = temac_stop,
916         .ndo_start_xmit = temac_start_xmit,
917         .ndo_set_mac_address = netdev_set_mac_address,
918         .ndo_validate_addr = eth_validate_addr,
919         //.ndo_set_multicast_list = temac_set_multicast_list,
920 #ifdef CONFIG_NET_POLL_CONTROLLER
921         .ndo_poll_controller = temac_poll_controller,
922 #endif
923 };
924
925 /* ---------------------------------------------------------------------
926  * SYSFS device attributes
927  */
928 static ssize_t temac_show_llink_regs(struct device *dev,
929                                      struct device_attribute *attr, char *buf)
930 {
931         struct net_device *ndev = dev_get_drvdata(dev);
932         struct temac_local *lp = netdev_priv(ndev);
933         int i, len = 0;
934
935         for (i = 0; i < 0x11; i++)
936                 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
937                                (i % 8) == 7 ? "\n" : " ");
938         len += sprintf(buf + len, "\n");
939
940         return len;
941 }
942
943 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
944
945 static struct attribute *temac_device_attrs[] = {
946         &dev_attr_llink_regs.attr,
947         NULL,
948 };
949
950 static const struct attribute_group temac_attr_group = {
951         .attrs = temac_device_attrs,
952 };
953
954 static int __init
955 temac_of_probe(struct platform_device *op, const struct of_device_id *match)
956 {
957         struct device_node *np;
958         struct temac_local *lp;
959         struct net_device *ndev;
960         const void *addr;
961         __be32 *p;
962         int size, rc = 0;
963
964         /* Init network device structure */
965         ndev = alloc_etherdev(sizeof(*lp));
966         if (!ndev) {
967                 dev_err(&op->dev, "could not allocate device.\n");
968                 return -ENOMEM;
969         }
970         ether_setup(ndev);
971         dev_set_drvdata(&op->dev, ndev);
972         SET_NETDEV_DEV(ndev, &op->dev);
973         ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
974         ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
975         ndev->netdev_ops = &temac_netdev_ops;
976 #if 0
977         ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
978         ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
979         ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
980         ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
981         ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
982         ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
983         ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
984         ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
985         ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
986         ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
987         ndev->features |= NETIF_F_LRO; /* large receive offload */
988 #endif
989
990         /* setup temac private info structure */
991         lp = netdev_priv(ndev);
992         lp->ndev = ndev;
993         lp->dev = &op->dev;
994         lp->options = XTE_OPTION_DEFAULTS;
995         spin_lock_init(&lp->rx_lock);
996         mutex_init(&lp->indirect_mutex);
997
998         /* map device registers */
999         lp->regs = of_iomap(op->dev.of_node, 0);
1000         if (!lp->regs) {
1001                 dev_err(&op->dev, "could not map temac regs.\n");
1002                 goto nodev;
1003         }
1004
1005         /* Setup checksum offload, but default to off if not specified */
1006         lp->temac_features = 0;
1007         p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1008         if (p && be32_to_cpu(*p)) {
1009                 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1010                 /* Can checksum TCP/UDP over IPv4. */
1011                 ndev->features |= NETIF_F_IP_CSUM;
1012         }
1013         p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1014         if (p && be32_to_cpu(*p))
1015                 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1016
1017         /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1018         np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1019         if (!np) {
1020                 dev_err(&op->dev, "could not find DMA node\n");
1021                 goto err_iounmap;
1022         }
1023
1024         /* Setup the DMA register accesses, could be DCR or memory mapped */
1025         if (temac_dcr_setup(lp, op, np)) {
1026
1027                 /* no DCR in the device tree, try non-DCR */
1028                 lp->sdma_regs = of_iomap(np, 0);
1029                 if (lp->sdma_regs) {
1030                         lp->dma_in = temac_dma_in32;
1031                         lp->dma_out = temac_dma_out32;
1032                         dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1033                 } else {
1034                         dev_err(&op->dev, "unable to map DMA registers\n");
1035                         of_node_put(np);
1036                         goto err_iounmap;
1037                 }
1038         }
1039
1040         lp->rx_irq = irq_of_parse_and_map(np, 0);
1041         lp->tx_irq = irq_of_parse_and_map(np, 1);
1042
1043         of_node_put(np); /* Finished with the DMA node; drop the reference */
1044
1045         if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
1046                 dev_err(&op->dev, "could not determine irqs\n");
1047                 rc = -ENOMEM;
1048                 goto err_iounmap_2;
1049         }
1050
1051
1052         /* Retrieve the MAC address */
1053         addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1054         if ((!addr) || (size != 6)) {
1055                 dev_err(&op->dev, "could not find MAC address\n");
1056                 rc = -ENODEV;
1057                 goto err_iounmap_2;
1058         }
1059         temac_set_mac_address(ndev, (void *)addr);
1060
1061         rc = temac_mdio_setup(lp, op->dev.of_node);
1062         if (rc)
1063                 dev_warn(&op->dev, "error registering MDIO bus\n");
1064
1065         lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1066         if (lp->phy_node)
1067                 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1068
1069         /* Add the device attributes */
1070         rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1071         if (rc) {
1072                 dev_err(lp->dev, "Error creating sysfs files\n");
1073                 goto err_iounmap_2;
1074         }
1075
1076         rc = register_netdev(lp->ndev);
1077         if (rc) {
1078                 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1079                 goto err_register_ndev;
1080         }
1081
1082         return 0;
1083
1084  err_register_ndev:
1085         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1086  err_iounmap_2:
1087         if (lp->sdma_regs)
1088                 iounmap(lp->sdma_regs);
1089  err_iounmap:
1090         iounmap(lp->regs);
1091  nodev:
1092         free_netdev(ndev);
1093         ndev = NULL;
1094         return rc;
1095 }
1096
1097 static int __devexit temac_of_remove(struct platform_device *op)
1098 {
1099         struct net_device *ndev = dev_get_drvdata(&op->dev);
1100         struct temac_local *lp = netdev_priv(ndev);
1101
1102         temac_mdio_teardown(lp);
1103         unregister_netdev(ndev);
1104         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1105         if (lp->phy_node)
1106                 of_node_put(lp->phy_node);
1107         lp->phy_node = NULL;
1108         dev_set_drvdata(&op->dev, NULL);
1109         iounmap(lp->regs);
1110         if (lp->sdma_regs)
1111                 iounmap(lp->sdma_regs);
1112         free_netdev(ndev);
1113         return 0;
1114 }
1115
1116 static struct of_device_id temac_of_match[] __devinitdata = {
1117         { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1118         { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1119         { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1120         { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1121         {},
1122 };
1123 MODULE_DEVICE_TABLE(of, temac_of_match);
1124
1125 static struct of_platform_driver temac_of_driver = {
1126         .probe = temac_of_probe,
1127         .remove = __devexit_p(temac_of_remove),
1128         .driver = {
1129                 .owner = THIS_MODULE,
1130                 .name = "xilinx_temac",
1131                 .of_match_table = temac_of_match,
1132         },
1133 };
1134
1135 static int __init temac_init(void)
1136 {
1137         return of_register_platform_driver(&temac_of_driver);
1138 }
1139 module_init(temac_init);
1140
1141 static void __exit temac_exit(void)
1142 {
1143         of_unregister_platform_driver(&temac_of_driver);
1144 }
1145 module_exit(temac_exit);
1146
1147 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1148 MODULE_AUTHOR("Yoshio Kashiwagi");
1149 MODULE_LICENSE("GPL");