2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <asm-generic/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 #define MACB_RX_BUFFER_SIZE 4096
49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50 #define MACB_TX_RING_SIZE 16
51 #define MACB_TX_TIMEOUT 1000
52 #define MACB_AUTONEG_TIMEOUT 5000000
54 struct macb_dma_desc {
59 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
60 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
61 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
62 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
64 #define RXADDR_USED 0x00000001
65 #define RXADDR_WRAP 0x00000002
67 #define RXBUF_FRMLEN_MASK 0x00000fff
68 #define RXBUF_FRAME_START 0x00004000
69 #define RXBUF_FRAME_END 0x00008000
70 #define RXBUF_TYPEID_MATCH 0x00400000
71 #define RXBUF_ADDR4_MATCH 0x00800000
72 #define RXBUF_ADDR3_MATCH 0x01000000
73 #define RXBUF_ADDR2_MATCH 0x02000000
74 #define RXBUF_ADDR1_MATCH 0x04000000
75 #define RXBUF_BROADCAST 0x80000000
77 #define TXBUF_FRMLEN_MASK 0x000007ff
78 #define TXBUF_FRAME_END 0x00008000
79 #define TXBUF_NOCRC 0x00010000
80 #define TXBUF_EXHAUSTED 0x08000000
81 #define TXBUF_UNDERRUN 0x10000000
82 #define TXBUF_MAXRETRY 0x20000000
83 #define TXBUF_WRAP 0x40000000
84 #define TXBUF_USED 0x80000000
92 unsigned int next_rx_tail;
97 struct macb_dma_desc *rx_ring;
98 struct macb_dma_desc *tx_ring;
100 unsigned long rx_buffer_dma;
101 unsigned long rx_ring_dma;
102 unsigned long tx_ring_dma;
104 struct macb_dma_desc *dummy_desc;
105 unsigned long dummy_desc_dma;
107 const struct device *dev;
108 #ifndef CONFIG_DM_ETH
109 struct eth_device netdev;
111 unsigned short phy_addr;
115 phy_interface_t phy_interface;
118 #ifndef CONFIG_DM_ETH
119 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
122 static int macb_is_gem(struct macb_device *macb)
124 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
127 #ifndef cpu_is_sama5d2
128 #define cpu_is_sama5d2() 0
131 #ifndef cpu_is_sama5d4
132 #define cpu_is_sama5d4() 0
135 static int gem_is_gigabit_capable(struct macb_device *macb)
138 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
139 * configured to support only 10/100.
141 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
144 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
146 unsigned long netctl;
147 unsigned long netstat;
150 netctl = macb_readl(macb, NCR);
151 netctl |= MACB_BIT(MPE);
152 macb_writel(macb, NCR, netctl);
154 frame = (MACB_BF(SOF, 1)
156 | MACB_BF(PHYA, macb->phy_addr)
159 | MACB_BF(DATA, value));
160 macb_writel(macb, MAN, frame);
163 netstat = macb_readl(macb, NSR);
164 } while (!(netstat & MACB_BIT(IDLE)));
166 netctl = macb_readl(macb, NCR);
167 netctl &= ~MACB_BIT(MPE);
168 macb_writel(macb, NCR, netctl);
171 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
173 unsigned long netctl;
174 unsigned long netstat;
177 netctl = macb_readl(macb, NCR);
178 netctl |= MACB_BIT(MPE);
179 macb_writel(macb, NCR, netctl);
181 frame = (MACB_BF(SOF, 1)
183 | MACB_BF(PHYA, macb->phy_addr)
186 macb_writel(macb, MAN, frame);
189 netstat = macb_readl(macb, NSR);
190 } while (!(netstat & MACB_BIT(IDLE)));
192 frame = macb_readl(macb, MAN);
194 netctl = macb_readl(macb, NCR);
195 netctl &= ~MACB_BIT(MPE);
196 macb_writel(macb, NCR, netctl);
198 return MACB_BFEXT(DATA, frame);
201 void __weak arch_get_mdio_control(const char *name)
206 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
208 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
211 struct udevice *dev = eth_get_dev_by_name(devname);
212 struct macb_device *macb = dev_get_priv(dev);
214 struct eth_device *dev = eth_get_dev_by_name(devname);
215 struct macb_device *macb = to_macb(dev);
218 if (macb->phy_addr != phy_adr)
221 arch_get_mdio_control(devname);
222 *value = macb_mdio_read(macb, reg);
227 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
230 struct udevice *dev = eth_get_dev_by_name(devname);
231 struct macb_device *macb = dev_get_priv(dev);
233 struct eth_device *dev = eth_get_dev_by_name(devname);
234 struct macb_device *macb = to_macb(dev);
237 if (macb->phy_addr != phy_adr)
240 arch_get_mdio_control(devname);
241 macb_mdio_write(macb, reg, value);
249 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
252 invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
253 MACB_RX_DMA_DESC_SIZE);
255 invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
256 MACB_TX_DMA_DESC_SIZE);
259 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
262 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
263 MACB_RX_DMA_DESC_SIZE);
265 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
266 MACB_TX_DMA_DESC_SIZE);
269 static inline void macb_flush_rx_buffer(struct macb_device *macb)
271 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
272 MACB_RX_BUFFER_SIZE);
275 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
277 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
278 MACB_RX_BUFFER_SIZE);
281 #if defined(CONFIG_CMD_NET)
283 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
286 unsigned long paddr, ctrl;
287 unsigned int tx_head = macb->tx_head;
290 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
292 ctrl = length & TXBUF_FRMLEN_MASK;
293 ctrl |= TXBUF_FRAME_END;
294 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
301 macb->tx_ring[tx_head].ctrl = ctrl;
302 macb->tx_ring[tx_head].addr = paddr;
304 macb_flush_ring_desc(macb, TX);
305 /* Do we need check paddr and length is dcache line aligned? */
306 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
307 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
310 * I guess this is necessary because the networking core may
311 * re-use the transmit buffer as soon as we return...
313 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
315 macb_invalidate_ring_desc(macb, TX);
316 ctrl = macb->tx_ring[tx_head].ctrl;
317 if (ctrl & TXBUF_USED)
322 dma_unmap_single(packet, length, paddr);
324 if (i <= MACB_TX_TIMEOUT) {
325 if (ctrl & TXBUF_UNDERRUN)
326 printf("%s: TX underrun\n", name);
327 if (ctrl & TXBUF_EXHAUSTED)
328 printf("%s: TX buffers exhausted in mid frame\n", name);
330 printf("%s: TX timeout\n", name);
333 /* No one cares anyway */
337 static void reclaim_rx_buffers(struct macb_device *macb,
338 unsigned int new_tail)
344 macb_invalidate_ring_desc(macb, RX);
345 while (i > new_tail) {
346 macb->rx_ring[i].addr &= ~RXADDR_USED;
348 if (i > MACB_RX_RING_SIZE)
352 while (i < new_tail) {
353 macb->rx_ring[i].addr &= ~RXADDR_USED;
358 macb_flush_ring_desc(macb, RX);
359 macb->rx_tail = new_tail;
362 static int _macb_recv(struct macb_device *macb, uchar **packetp)
364 unsigned int next_rx_tail = macb->next_rx_tail;
369 macb->wrapped = false;
371 macb_invalidate_ring_desc(macb, RX);
373 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
376 status = macb->rx_ring[next_rx_tail].ctrl;
377 if (status & RXBUF_FRAME_START) {
378 if (next_rx_tail != macb->rx_tail)
379 reclaim_rx_buffers(macb, next_rx_tail);
380 macb->wrapped = false;
383 if (status & RXBUF_FRAME_END) {
384 buffer = macb->rx_buffer + 128 * macb->rx_tail;
385 length = status & RXBUF_FRMLEN_MASK;
387 macb_invalidate_rx_buffer(macb);
389 unsigned int headlen, taillen;
391 headlen = 128 * (MACB_RX_RING_SIZE
393 taillen = length - headlen;
394 memcpy((void *)net_rx_packets[0],
396 memcpy((void *)net_rx_packets[0] + headlen,
397 macb->rx_buffer, taillen);
398 *packetp = (void *)net_rx_packets[0];
403 if (++next_rx_tail >= MACB_RX_RING_SIZE)
405 macb->next_rx_tail = next_rx_tail;
408 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
409 macb->wrapped = true;
417 static void macb_phy_reset(struct macb_device *macb, const char *name)
422 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
423 macb_mdio_write(macb, MII_ADVERTISE, adv);
424 printf("%s: Starting autonegotiation...\n", name);
425 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
428 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
429 status = macb_mdio_read(macb, MII_BMSR);
430 if (status & BMSR_ANEGCOMPLETE)
435 if (status & BMSR_ANEGCOMPLETE)
436 printf("%s: Autonegotiation complete\n", name);
438 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
442 #ifdef CONFIG_MACB_SEARCH_PHY
443 static int macb_phy_find(struct macb_device *macb, const char *name)
448 /* Search for PHY... */
449 for (i = 0; i < 32; i++) {
451 phy_id = macb_mdio_read(macb, MII_PHYSID1);
452 if (phy_id != 0xffff) {
453 printf("%s: PHY present at %d\n", name, i);
458 /* PHY isn't up to snuff */
459 printf("%s: PHY not found\n", name);
463 #endif /* CONFIG_MACB_SEARCH_PHY */
466 static int macb_phy_init(struct udevice *dev, const char *name)
468 static int macb_phy_init(struct macb_device *macb, const char *name)
472 struct macb_device *macb = dev_get_priv(dev);
475 struct phy_device *phydev;
478 u16 phy_id, status, adv, lpa;
479 int media, speed, duplex;
482 arch_get_mdio_control(name);
483 #ifdef CONFIG_MACB_SEARCH_PHY
484 /* Auto-detect phy_addr */
485 if (!macb_phy_find(macb, name))
487 #endif /* CONFIG_MACB_SEARCH_PHY */
489 /* Check if the PHY is up to snuff... */
490 phy_id = macb_mdio_read(macb, MII_PHYSID1);
491 if (phy_id == 0xffff) {
492 printf("%s: No PHY present\n", name);
498 phydev = phy_connect(macb->bus, macb->phy_addr, dev,
499 macb->phy_interface);
501 /* need to consider other phy interface mode */
502 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
503 PHY_INTERFACE_MODE_RGMII);
506 printf("phy_connect failed\n");
513 status = macb_mdio_read(macb, MII_BMSR);
514 if (!(status & BMSR_LSTATUS)) {
515 /* Try to re-negotiate if we don't have link already. */
516 macb_phy_reset(macb, name);
518 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
519 status = macb_mdio_read(macb, MII_BMSR);
520 if (status & BMSR_LSTATUS)
526 if (!(status & BMSR_LSTATUS)) {
527 printf("%s: link down (status: 0x%04x)\n",
532 /* First check for GMAC and that it is GiB capable */
533 if (gem_is_gigabit_capable(macb)) {
534 lpa = macb_mdio_read(macb, MII_STAT1000);
536 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
537 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
539 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
541 duplex ? "full" : "half",
544 ncfgr = macb_readl(macb, NCFGR);
545 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
546 ncfgr |= GEM_BIT(GBE);
549 ncfgr |= MACB_BIT(FD);
551 macb_writel(macb, NCFGR, ncfgr);
557 /* fall back for EMAC checking */
558 adv = macb_mdio_read(macb, MII_ADVERTISE);
559 lpa = macb_mdio_read(macb, MII_LPA);
560 media = mii_nway_result(lpa & adv);
561 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
563 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
564 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
566 speed ? "100" : "10",
567 duplex ? "full" : "half",
570 ncfgr = macb_readl(macb, NCFGR);
571 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
573 ncfgr |= MACB_BIT(SPD);
575 ncfgr |= MACB_BIT(FD);
576 macb_writel(macb, NCFGR, ncfgr);
581 static int gmac_init_multi_queues(struct macb_device *macb)
583 int i, num_queues = 1;
586 /* bit 0 is never set but queue 0 always exists */
587 queue_mask = gem_readl(macb, DCFG6) & 0xff;
590 for (i = 1; i < MACB_MAX_QUEUES; i++)
591 if (queue_mask & (1 << i))
594 macb->dummy_desc->ctrl = TXBUF_USED;
595 macb->dummy_desc->addr = 0;
596 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
597 MACB_TX_DUMMY_DMA_DESC_SIZE);
599 for (i = 1; i < num_queues; i++)
600 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
606 static int _macb_init(struct udevice *dev, const char *name)
608 static int _macb_init(struct macb_device *macb, const char *name)
612 struct macb_device *macb = dev_get_priv(dev);
618 * macb_halt should have been called at some point before now,
619 * so we'll assume the controller is idle.
622 /* initialize DMA descriptors */
623 paddr = macb->rx_buffer_dma;
624 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
625 if (i == (MACB_RX_RING_SIZE - 1))
626 paddr |= RXADDR_WRAP;
627 macb->rx_ring[i].addr = paddr;
628 macb->rx_ring[i].ctrl = 0;
631 macb_flush_ring_desc(macb, RX);
632 macb_flush_rx_buffer(macb);
634 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
635 macb->tx_ring[i].addr = 0;
636 if (i == (MACB_TX_RING_SIZE - 1))
637 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
639 macb->tx_ring[i].ctrl = TXBUF_USED;
641 macb_flush_ring_desc(macb, TX);
646 macb->next_rx_tail = 0;
648 macb_writel(macb, RBQP, macb->rx_ring_dma);
649 macb_writel(macb, TBQP, macb->tx_ring_dma);
651 if (macb_is_gem(macb)) {
652 /* Check the multi queue and initialize the queue for tx */
653 gmac_init_multi_queues(macb);
656 * When the GMAC IP with GE feature, this bit is used to
657 * select interface between RGMII and GMII.
658 * When the GMAC IP without GE feature, this bit is used
659 * to select interface between RMII and MII.
662 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
663 gem_writel(macb, UR, GEM_BIT(RGMII));
665 gem_writel(macb, UR, 0);
667 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
668 gem_writel(macb, UR, GEM_BIT(RGMII));
670 gem_writel(macb, UR, 0);
674 /* choose RMII or MII mode. This depends on the board */
676 #ifdef CONFIG_AT91FAMILY
677 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
678 macb_writel(macb, USRIO,
679 MACB_BIT(RMII) | MACB_BIT(CLKEN));
681 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
684 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
685 macb_writel(macb, USRIO, 0);
687 macb_writel(macb, USRIO, MACB_BIT(MII));
691 #ifdef CONFIG_AT91FAMILY
692 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
694 macb_writel(macb, USRIO, 0);
697 #ifdef CONFIG_AT91FAMILY
698 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
700 macb_writel(macb, USRIO, MACB_BIT(MII));
702 #endif /* CONFIG_RMII */
707 if (!macb_phy_init(dev, name))
709 if (!macb_phy_init(macb, name))
713 /* Enable TX and RX */
714 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
719 static void _macb_halt(struct macb_device *macb)
723 /* Halt the controller and wait for any ongoing transmission to end. */
724 ncr = macb_readl(macb, NCR);
725 ncr |= MACB_BIT(THALT);
726 macb_writel(macb, NCR, ncr);
729 tsr = macb_readl(macb, TSR);
730 } while (tsr & MACB_BIT(TGO));
732 /* Disable TX and RX, and clear statistics */
733 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
736 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
741 /* set hardware address */
742 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
743 enetaddr[2] << 16 | enetaddr[3] << 24;
744 macb_writel(macb, SA1B, hwaddr_bottom);
745 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
746 macb_writel(macb, SA1T, hwaddr_top);
750 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
753 unsigned long macb_hz = get_macb_pclk_rate(id);
755 if (macb_hz < 20000000)
756 config = MACB_BF(CLK, MACB_CLK_DIV8);
757 else if (macb_hz < 40000000)
758 config = MACB_BF(CLK, MACB_CLK_DIV16);
759 else if (macb_hz < 80000000)
760 config = MACB_BF(CLK, MACB_CLK_DIV32);
762 config = MACB_BF(CLK, MACB_CLK_DIV64);
767 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
770 unsigned long macb_hz = get_macb_pclk_rate(id);
772 if (macb_hz < 20000000)
773 config = GEM_BF(CLK, GEM_CLK_DIV8);
774 else if (macb_hz < 40000000)
775 config = GEM_BF(CLK, GEM_CLK_DIV16);
776 else if (macb_hz < 80000000)
777 config = GEM_BF(CLK, GEM_CLK_DIV32);
778 else if (macb_hz < 120000000)
779 config = GEM_BF(CLK, GEM_CLK_DIV48);
780 else if (macb_hz < 160000000)
781 config = GEM_BF(CLK, GEM_CLK_DIV64);
783 config = GEM_BF(CLK, GEM_CLK_DIV96);
789 * Get the DMA bus width field of the network configuration register that we
790 * should program. We find the width from decoding the design configuration
791 * register to find the maximum supported data bus width.
793 static u32 macb_dbw(struct macb_device *macb)
795 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
797 return GEM_BF(DBW, GEM_DBW128);
799 return GEM_BF(DBW, GEM_DBW64);
802 return GEM_BF(DBW, GEM_DBW32);
806 static void _macb_eth_initialize(struct macb_device *macb)
808 int id = 0; /* This is not used by functions we call */
811 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
812 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
813 &macb->rx_buffer_dma);
814 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
816 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
818 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
819 &macb->dummy_desc_dma);
822 * Do some basic initialization so that we at least can talk
825 if (macb_is_gem(macb)) {
826 ncfgr = gem_mdc_clk_div(id, macb);
827 ncfgr |= macb_dbw(macb);
829 ncfgr = macb_mdc_clk_div(id, macb);
832 macb_writel(macb, NCFGR, ncfgr);
835 #ifndef CONFIG_DM_ETH
836 static int macb_send(struct eth_device *netdev, void *packet, int length)
838 struct macb_device *macb = to_macb(netdev);
840 return _macb_send(macb, netdev->name, packet, length);
843 static int macb_recv(struct eth_device *netdev)
845 struct macb_device *macb = to_macb(netdev);
849 macb->wrapped = false;
851 macb->next_rx_tail = macb->rx_tail;
852 length = _macb_recv(macb, &packet);
854 net_process_received_packet(packet, length);
855 reclaim_rx_buffers(macb, macb->next_rx_tail);
856 } else if (length < 0) {
862 static int macb_init(struct eth_device *netdev, bd_t *bd)
864 struct macb_device *macb = to_macb(netdev);
866 return _macb_init(macb, netdev->name);
869 static void macb_halt(struct eth_device *netdev)
871 struct macb_device *macb = to_macb(netdev);
873 return _macb_halt(macb);
876 static int macb_write_hwaddr(struct eth_device *netdev)
878 struct macb_device *macb = to_macb(netdev);
880 return _macb_write_hwaddr(macb, netdev->enetaddr);
883 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
885 struct macb_device *macb;
886 struct eth_device *netdev;
888 macb = malloc(sizeof(struct macb_device));
890 printf("Error: Failed to allocate memory for MACB%d\n", id);
893 memset(macb, 0, sizeof(struct macb_device));
895 netdev = &macb->netdev;
898 macb->phy_addr = phy_addr;
900 if (macb_is_gem(macb))
901 sprintf(netdev->name, "gmac%d", id);
903 sprintf(netdev->name, "macb%d", id);
905 netdev->init = macb_init;
906 netdev->halt = macb_halt;
907 netdev->send = macb_send;
908 netdev->recv = macb_recv;
909 netdev->write_hwaddr = macb_write_hwaddr;
911 _macb_eth_initialize(macb);
913 eth_register(netdev);
915 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
916 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
917 macb->bus = miiphy_get_dev_by_name(netdev->name);
921 #endif /* !CONFIG_DM_ETH */
925 static int macb_start(struct udevice *dev)
927 return _macb_init(dev, dev->name);
930 static int macb_send(struct udevice *dev, void *packet, int length)
932 struct macb_device *macb = dev_get_priv(dev);
934 return _macb_send(macb, dev->name, packet, length);
937 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
939 struct macb_device *macb = dev_get_priv(dev);
941 macb->next_rx_tail = macb->rx_tail;
942 macb->wrapped = false;
944 return _macb_recv(macb, packetp);
947 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
949 struct macb_device *macb = dev_get_priv(dev);
951 reclaim_rx_buffers(macb, macb->next_rx_tail);
956 static void macb_stop(struct udevice *dev)
958 struct macb_device *macb = dev_get_priv(dev);
963 static int macb_write_hwaddr(struct udevice *dev)
965 struct eth_pdata *plat = dev_get_platdata(dev);
966 struct macb_device *macb = dev_get_priv(dev);
968 return _macb_write_hwaddr(macb, plat->enetaddr);
971 static const struct eth_ops macb_eth_ops = {
976 .free_pkt = macb_free_pkt,
977 .write_hwaddr = macb_write_hwaddr,
980 static int macb_eth_probe(struct udevice *dev)
982 struct eth_pdata *pdata = dev_get_platdata(dev);
983 struct macb_device *macb = dev_get_priv(dev);
986 const char *phy_mode;
988 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
990 macb->phy_interface = phy_get_interface_by_name(phy_mode);
991 if (macb->phy_interface == -1) {
992 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
997 macb->regs = (void *)pdata->iobase;
999 _macb_eth_initialize(macb);
1000 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1001 miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
1002 macb->bus = miiphy_get_dev_by_name(dev->name);
1008 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1010 struct eth_pdata *pdata = dev_get_platdata(dev);
1012 pdata->iobase = dev_get_addr(dev);
1016 static const struct udevice_id macb_eth_ids[] = {
1017 { .compatible = "cdns,macb" },
1021 U_BOOT_DRIVER(eth_macb) = {
1024 .of_match = macb_eth_ids,
1025 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1026 .probe = macb_eth_probe,
1027 .ops = &macb_eth_ops,
1028 .priv_auto_alloc_size = sizeof(struct macb_device),
1029 .platdata_auto_alloc_size = sizeof(struct eth_pdata),