2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
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15 * without modification, are permitted provided that the following
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22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
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25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/hardirq.h>
39 #include <linux/mlx4/cmd.h>
40 #include <linux/mlx4/cq.h>
45 struct mlx4_cq_context {
49 __be32 logsize_usrpage;
57 __be32 mtt_base_addr_l;
58 __be32 last_notified_index;
59 __be32 solicit_producer_index;
60 __be32 consumer_index;
61 __be32 producer_index;
66 #define MLX4_CQ_STATUS_OK ( 0 << 28)
67 #define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
68 #define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
69 #define MLX4_CQ_FLAG_CC ( 1 << 18)
70 #define MLX4_CQ_FLAG_OI ( 1 << 17)
71 #define MLX4_CQ_STATE_ARMED ( 9 << 8)
72 #define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
73 #define MLX4_EQ_STATE_FIRED (10 << 8)
75 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
79 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
80 cqn & (dev->caps.num_cqs - 1));
82 mlx4_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
91 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
93 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
96 spin_lock(&cq_table->lock);
98 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
100 atomic_inc(&cq->refcount);
102 spin_unlock(&cq_table->lock);
105 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
109 cq->event(cq, event_type);
111 if (atomic_dec_and_test(&cq->refcount))
115 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
118 return mlx4_cmd(dev, mailbox->dma, cq_num, 0, MLX4_CMD_SW2HW_CQ,
119 MLX4_CMD_TIME_CLASS_A);
122 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
123 int cq_num, u32 opmod)
125 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
126 MLX4_CMD_TIME_CLASS_A);
129 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
132 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
133 mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
134 MLX4_CMD_TIME_CLASS_A);
137 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
138 u16 count, u16 period)
140 struct mlx4_cmd_mailbox *mailbox;
141 struct mlx4_cq_context *cq_context;
144 mailbox = mlx4_alloc_cmd_mailbox(dev);
146 return PTR_ERR(mailbox);
148 cq_context = mailbox->buf;
149 memset(cq_context, 0, sizeof *cq_context);
151 cq_context->cq_max_count = cpu_to_be16(count);
152 cq_context->cq_period = cpu_to_be16(period);
154 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
156 mlx4_free_cmd_mailbox(dev, mailbox);
159 EXPORT_SYMBOL_GPL(mlx4_cq_modify);
161 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
162 int entries, struct mlx4_mtt *mtt)
164 struct mlx4_cmd_mailbox *mailbox;
165 struct mlx4_cq_context *cq_context;
169 mailbox = mlx4_alloc_cmd_mailbox(dev);
171 return PTR_ERR(mailbox);
173 cq_context = mailbox->buf;
174 memset(cq_context, 0, sizeof *cq_context);
176 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
177 cq_context->log_page_size = mtt->page_shift - 12;
178 mtt_addr = mlx4_mtt_addr(dev, mtt);
179 cq_context->mtt_base_addr_h = mtt_addr >> 32;
180 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
182 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
184 mlx4_free_cmd_mailbox(dev, mailbox);
187 EXPORT_SYMBOL_GPL(mlx4_cq_resize);
189 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
190 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
191 unsigned vector, int collapsed)
193 struct mlx4_priv *priv = mlx4_priv(dev);
194 struct mlx4_cq_table *cq_table = &priv->cq_table;
195 struct mlx4_cmd_mailbox *mailbox;
196 struct mlx4_cq_context *cq_context;
200 if (vector >= dev->caps.num_comp_vectors)
205 cq->cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
209 err = mlx4_table_get(dev, &cq_table->table, cq->cqn);
213 err = mlx4_table_get(dev, &cq_table->cmpt_table, cq->cqn);
217 spin_lock_irq(&cq_table->lock);
218 err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
219 spin_unlock_irq(&cq_table->lock);
223 mailbox = mlx4_alloc_cmd_mailbox(dev);
224 if (IS_ERR(mailbox)) {
225 err = PTR_ERR(mailbox);
229 cq_context = mailbox->buf;
230 memset(cq_context, 0, sizeof *cq_context);
232 cq_context->flags = cpu_to_be32(!!collapsed << 18);
233 cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
234 cq_context->comp_eqn = priv->eq_table.eq[vector].eqn;
235 cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
237 mtt_addr = mlx4_mtt_addr(dev, mtt);
238 cq_context->mtt_base_addr_h = mtt_addr >> 32;
239 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
240 cq_context->db_rec_addr = cpu_to_be64(db_rec);
242 err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
243 mlx4_free_cmd_mailbox(dev, mailbox);
250 atomic_set(&cq->refcount, 1);
251 init_completion(&cq->free);
256 spin_lock_irq(&cq_table->lock);
257 radix_tree_delete(&cq_table->tree, cq->cqn);
258 spin_unlock_irq(&cq_table->lock);
261 mlx4_table_put(dev, &cq_table->cmpt_table, cq->cqn);
264 mlx4_table_put(dev, &cq_table->table, cq->cqn);
267 mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
271 EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
273 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
275 struct mlx4_priv *priv = mlx4_priv(dev);
276 struct mlx4_cq_table *cq_table = &priv->cq_table;
279 err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
281 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
283 synchronize_irq(priv->eq_table.eq[cq->vector].irq);
285 spin_lock_irq(&cq_table->lock);
286 radix_tree_delete(&cq_table->tree, cq->cqn);
287 spin_unlock_irq(&cq_table->lock);
289 if (atomic_dec_and_test(&cq->refcount))
291 wait_for_completion(&cq->free);
293 mlx4_table_put(dev, &cq_table->table, cq->cqn);
294 mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
296 EXPORT_SYMBOL_GPL(mlx4_cq_free);
298 int mlx4_init_cq_table(struct mlx4_dev *dev)
300 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
303 spin_lock_init(&cq_table->lock);
304 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
306 err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
307 dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
314 void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
316 /* Nothing to do to clean up radix_tree */
317 mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);