2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/cmd.h>
44 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
45 u64 mac, u64 clear, u8 mode)
47 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
48 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
51 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
53 struct mlx4_cmd_mailbox *mailbox;
54 struct mlx4_set_vlan_fltr_mbox *filter;
61 mailbox = mlx4_alloc_cmd_mailbox(dev);
63 return PTR_ERR(mailbox);
65 filter = mailbox->buf;
66 memset(filter, 0, sizeof(*filter));
67 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
69 for (j = 0; j < 32; j++)
70 if (test_bit(index++, priv->active_vlans))
72 filter->entry[i] = cpu_to_be32(entry);
74 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
75 MLX4_CMD_TIME_CLASS_B);
76 mlx4_free_cmd_mailbox(dev, mailbox);
81 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
82 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
84 struct mlx4_cmd_mailbox *mailbox;
85 struct mlx4_set_port_general_context *context;
89 mailbox = mlx4_alloc_cmd_mailbox(dev);
91 return PTR_ERR(mailbox);
92 context = mailbox->buf;
93 memset(context, 0, sizeof *context);
95 context->flags = SET_PORT_GEN_ALL_VALID;
96 context->mtu = cpu_to_be16(mtu);
97 context->pptx = (pptx * (!pfctx)) << 7;
98 context->pfctx = pfctx;
99 context->pprx = (pprx * (!pfcrx)) << 7;
100 context->pfcrx = pfcrx;
102 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
104 MLX4_CMD_TIME_CLASS_B);
106 mlx4_free_cmd_mailbox(dev, mailbox);
110 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
113 struct mlx4_cmd_mailbox *mailbox;
114 struct mlx4_set_port_rqp_calc_context *context;
117 u32 m_promisc = (dev->caps.vep_mc_steering) ? MCAST_DIRECT : MCAST_DEFAULT;
119 if (dev->caps.vep_mc_steering && dev->caps.vep_uc_steering)
122 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 return PTR_ERR(mailbox);
125 context = mailbox->buf;
126 memset(context, 0, sizeof *context);
128 context->base_qpn = cpu_to_be32(base_qpn);
129 context->n_mac = 0x7;
130 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
132 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
134 context->intra_no_vlan = 0;
135 context->no_vlan = MLX4_NO_VLAN_IDX;
136 context->intra_vlan_miss = 0;
137 context->vlan_miss = MLX4_VLAN_MISS_IDX;
139 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
140 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
141 MLX4_CMD_TIME_CLASS_B);
143 mlx4_free_cmd_mailbox(dev, mailbox);
147 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
149 struct mlx4_en_query_port_context *qport_context;
150 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
151 struct mlx4_en_port_state *state = &priv->port_state;
152 struct mlx4_cmd_mailbox *mailbox;
155 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
157 return PTR_ERR(mailbox);
158 memset(mailbox->buf, 0, sizeof(*qport_context));
159 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
160 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
163 qport_context = mailbox->buf;
165 /* This command is always accessed from Ethtool context
166 * already synchronized, no need in locking */
167 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
168 if ((qport_context->link_speed & MLX4_EN_SPEED_MASK) ==
170 state->link_speed = 1000;
172 state->link_speed = 10000;
173 state->transciver = qport_context->transceiver;
176 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
180 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
182 struct mlx4_en_stat_out_mbox *mlx4_en_stats;
183 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
184 struct net_device_stats *stats = &priv->stats;
185 struct mlx4_cmd_mailbox *mailbox;
186 u64 in_mod = reset << 8 | port;
190 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
192 return PTR_ERR(mailbox);
193 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
194 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
195 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
199 mlx4_en_stats = mailbox->buf;
201 spin_lock_bh(&priv->stats_lock);
203 stats->rx_packets = 0;
205 for (i = 0; i < priv->rx_ring_num; i++) {
206 stats->rx_packets += priv->rx_ring[i].packets;
207 stats->rx_bytes += priv->rx_ring[i].bytes;
209 stats->tx_packets = 0;
211 for (i = 0; i < priv->tx_ring_num; i++) {
212 stats->tx_packets += priv->tx_ring[i].packets;
213 stats->tx_bytes += priv->tx_ring[i].bytes;
216 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
217 be32_to_cpu(mlx4_en_stats->RdropLength) +
218 be32_to_cpu(mlx4_en_stats->RJBBR) +
219 be32_to_cpu(mlx4_en_stats->RCRC) +
220 be32_to_cpu(mlx4_en_stats->RRUNT);
221 stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
222 stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
223 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
224 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
225 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
226 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
227 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
228 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
229 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
230 be64_to_cpu(mlx4_en_stats->MCAST_novlan);
231 stats->collisions = 0;
232 stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
233 stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
234 stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
235 stats->rx_frame_errors = 0;
236 stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
237 stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
238 stats->tx_aborted_errors = 0;
239 stats->tx_carrier_errors = 0;
240 stats->tx_fifo_errors = 0;
241 stats->tx_heartbeat_errors = 0;
242 stats->tx_window_errors = 0;
244 priv->pkstats.broadcast =
245 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
246 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
247 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
248 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
249 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
250 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
251 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
252 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
253 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
254 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
255 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
256 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
257 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
258 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
259 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
260 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
261 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
262 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
263 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
264 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
265 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
266 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
267 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
268 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
269 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
270 spin_unlock_bh(&priv->stats_lock);
273 mlx4_free_cmd_mailbox(mdev->dev, mailbox);