2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/compiler.h>
38 #include <linux/list.h>
39 #include <linux/mutex.h>
40 #include <linux/netdevice.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/mlx4/qp.h>
44 #include <linux/mlx4/cq.h>
45 #include <linux/mlx4/srq.h>
46 #include <linux/mlx4/doorbell.h>
47 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_en"
52 #define DRV_VERSION "1.5.1.6"
53 #define DRV_RELDATE "August 2010"
55 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
62 #define MLX4_EN_PAGE_SHIFT 12
63 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
64 #define MAX_RX_RINGS 16
66 #define HEADROOM (2048 / TXBB_SIZE + 1)
67 #define STAMP_STRIDE 64
68 #define STAMP_DWORDS (STAMP_STRIDE / 4)
69 #define STAMP_SHIFT 31
70 #define STAMP_VAL 0x7fffffff
71 #define STATS_DELAY (HZ / 4)
73 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
74 #define MAX_DESC_SIZE 512
75 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
78 * OS related constants and tunables
81 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
83 #define MLX4_EN_ALLOC_ORDER 2
84 #define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
86 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
88 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
89 * and 4K allocations) */
91 FRAG_SZ0 = 512 - NET_IP_ALIGN,
94 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
96 #define MLX4_EN_MAX_RX_FRAGS 4
98 /* Maximum ring sizes */
99 #define MLX4_EN_MAX_TX_SIZE 8192
100 #define MLX4_EN_MAX_RX_SIZE 8192
102 /* Minimum ring size for our page-allocation sceme to work */
103 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
104 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
106 #define MLX4_EN_SMALL_PKT_SIZE 64
107 #define MLX4_EN_NUM_TX_RINGS 8
108 #define MLX4_EN_NUM_PPP_RINGS 8
109 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
110 #define MLX4_EN_DEF_TX_RING_SIZE 512
111 #define MLX4_EN_DEF_RX_RING_SIZE 1024
113 /* Target number of packets to coalesce with interrupt moderation */
114 #define MLX4_EN_RX_COAL_TARGET 44
115 #define MLX4_EN_RX_COAL_TIME 0x10
117 #define MLX4_EN_TX_COAL_PKTS 5
118 #define MLX4_EN_TX_COAL_TIME 0x80
120 #define MLX4_EN_RX_RATE_LOW 400000
121 #define MLX4_EN_RX_COAL_TIME_LOW 0
122 #define MLX4_EN_RX_RATE_HIGH 450000
123 #define MLX4_EN_RX_COAL_TIME_HIGH 128
124 #define MLX4_EN_RX_SIZE_THRESH 1024
125 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
126 #define MLX4_EN_SAMPLE_INTERVAL 0
128 #define MLX4_EN_AUTO_CONF 0xffff
130 #define MLX4_EN_DEF_RX_PAUSE 1
131 #define MLX4_EN_DEF_TX_PAUSE 1
133 /* Interval between successive polls in the Tx routine when polling is used
134 instead of interrupts (in per-core Tx rings) - should be power of 2 */
135 #define MLX4_EN_TX_POLL_MODER 16
136 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
138 #define ETH_LLC_SNAP_SIZE 8
140 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
141 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
142 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
144 #define MLX4_EN_MIN_MTU 46
145 #define ETH_BCAST 0xffffffffffffULL
147 #define MLX4_EN_LOOPBACK_RETRIES 5
148 #define MLX4_EN_LOOPBACK_TIMEOUT 100
150 #ifdef MLX4_EN_PERF_STAT
151 /* Number of samples to 'average' */
153 #define AVG_FACTOR 1024
154 #define NUM_PERF_STATS NUM_PERF_COUNTERS
156 #define INC_PERF_COUNTER(cnt) (++(cnt))
157 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
158 #define AVG_PERF_COUNTER(cnt, sample) \
159 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
160 #define GET_PERF_COUNTER(cnt) (cnt)
161 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
165 #define NUM_PERF_STATS 0
166 #define INC_PERF_COUNTER(cnt) do {} while (0)
167 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
168 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
169 #define GET_PERF_COUNTER(cnt) (0)
170 #define GET_AVG_PERF_COUNTER(cnt) (0)
171 #endif /* MLX4_EN_PERF_STAT */
186 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
187 #define XNOR(x, y) (!(x) == !(y))
188 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
191 struct mlx4_en_tx_info {
200 #define MLX4_EN_BIT_DESC_OWN 0x80000000
201 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
202 #define MLX4_EN_MEMTYPE_PAD 0x100
203 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
206 struct mlx4_en_tx_desc {
207 struct mlx4_wqe_ctrl_seg ctrl;
209 struct mlx4_wqe_data_seg data; /* at least one data segment */
210 struct mlx4_wqe_lso_seg lso;
211 struct mlx4_wqe_inline_seg inl;
215 #define MLX4_EN_USE_SRQ 0x01000000
217 struct mlx4_en_rx_alloc {
222 struct mlx4_en_tx_ring {
223 struct mlx4_hwq_resources wqres;
224 u32 size ; /* number of TXBBs */
227 u16 cqn; /* index of port CQ associated with this ring */
235 struct mlx4_en_tx_info *tx_info;
239 struct mlx4_qp_context context;
241 enum mlx4_qp_state qp_state;
242 struct mlx4_srq dummy;
244 unsigned long packets;
245 spinlock_t comp_lock;
248 struct mlx4_en_rx_desc {
249 /* actual number of entries depends on rx ring stride */
250 struct mlx4_wqe_data_seg data[0];
253 struct mlx4_en_rx_ring {
254 struct mlx4_hwq_resources wqres;
255 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
256 u32 size ; /* number of Rx descs*/
261 u16 cqn; /* index of port CQ associated with this ring */
268 unsigned long packets;
272 static inline int mlx4_en_can_lro(__be16 status)
274 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
275 MLX4_CQE_STATUS_IPV4F |
276 MLX4_CQE_STATUS_IPV6 |
277 MLX4_CQE_STATUS_IPV4OPT |
278 MLX4_CQE_STATUS_TCP |
279 MLX4_CQE_STATUS_UDP |
280 MLX4_CQE_STATUS_IPOK)) ==
281 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
282 MLX4_CQE_STATUS_IPOK |
283 MLX4_CQE_STATUS_TCP);
288 struct mlx4_hwq_resources wqres;
291 struct net_device *dev;
292 struct napi_struct napi;
293 /* Per-core Tx cq processing support */
294 struct timer_list timer;
301 struct mlx4_cqe *buf;
302 #define MLX4_EN_OPCODE_ERROR 0x1e
305 struct mlx4_en_port_profile {
317 struct mlx4_en_profile {
325 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
329 struct mlx4_dev *dev;
330 struct pci_dev *pdev;
331 struct mutex state_lock;
332 struct net_device *pndev[MLX4_MAX_PORTS + 1];
335 struct mlx4_en_profile profile;
337 struct workqueue_struct *workqueue;
338 struct device *dma_device;
339 void __iomem *uar_map;
340 struct mlx4_uar priv_uar;
344 u8 mac_removed[MLX4_MAX_PORTS + 1];
348 struct mlx4_en_rss_map {
350 struct mlx4_qp qps[MAX_RX_RINGS];
351 enum mlx4_qp_state state[MAX_RX_RINGS];
352 struct mlx4_qp indir_qp;
353 enum mlx4_qp_state indir_state;
356 struct mlx4_en_rss_context {
366 struct mlx4_en_port_state {
372 struct mlx4_en_pkt_stats {
373 unsigned long broadcast;
374 unsigned long rx_prio[8];
375 unsigned long tx_prio[8];
376 #define NUM_PKT_STATS 17
379 struct mlx4_en_port_stats {
380 unsigned long tso_packets;
381 unsigned long queue_stopped;
382 unsigned long wake_queue;
383 unsigned long tx_timeout;
384 unsigned long rx_alloc_failed;
385 unsigned long rx_chksum_good;
386 unsigned long rx_chksum_none;
387 unsigned long tx_chksum_offload;
388 #define NUM_PORT_STATS 8
391 struct mlx4_en_perf_stats {
398 #define NUM_PERF_COUNTERS 6
401 struct mlx4_en_frag_info {
403 u16 frag_prefix_size;
410 struct mlx4_en_priv {
411 struct mlx4_en_dev *mdev;
412 struct mlx4_en_port_profile *prof;
413 struct net_device *dev;
414 struct vlan_group *vlgrp;
415 struct net_device_stats stats;
416 struct net_device_stats ret_stats;
417 struct mlx4_en_port_state port_state;
418 spinlock_t stats_lock;
420 unsigned long last_moder_packets;
421 unsigned long last_moder_tx_packets;
422 unsigned long last_moder_bytes;
423 unsigned long last_moder_jiffies;
434 u16 adaptive_rx_coal;
437 u32 validate_loopback;
439 struct mlx4_hwq_resources res;
453 struct mlx4_en_rss_map rss_map;
455 #define MLX4_EN_FLAG_PROMISC 0x1
459 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
463 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
464 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
465 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
466 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
467 struct work_struct mcast_task;
468 struct work_struct mac_task;
469 struct work_struct watchdog_task;
470 struct work_struct linkstate_task;
471 struct delayed_work stats_task;
472 struct mlx4_en_perf_stats pstats;
473 struct mlx4_en_pkt_stats pkstats;
474 struct mlx4_en_port_stats port_stats;
477 struct mlx4_en_stat_out_mbox hw_stats;
481 void mlx4_en_destroy_netdev(struct net_device *dev);
482 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
483 struct mlx4_en_port_profile *prof);
485 int mlx4_en_start_port(struct net_device *dev);
486 void mlx4_en_stop_port(struct net_device *dev);
488 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
489 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
491 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
492 int entries, int ring, enum cq_type mode);
493 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
494 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
495 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
496 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
497 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
499 void mlx4_en_poll_tx_cq(unsigned long data);
500 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
501 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
502 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
504 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
505 u32 size, u16 stride);
506 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
507 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
508 struct mlx4_en_tx_ring *ring,
510 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
511 struct mlx4_en_tx_ring *ring);
513 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
514 struct mlx4_en_rx_ring *ring,
515 u32 size, u16 stride);
516 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
517 struct mlx4_en_rx_ring *ring);
518 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
519 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
520 struct mlx4_en_rx_ring *ring);
521 int mlx4_en_process_rx_cq(struct net_device *dev,
522 struct mlx4_en_cq *cq,
524 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
525 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
526 int is_tx, int rss, int qpn, int cqn,
527 struct mlx4_qp_context *context);
528 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
529 int mlx4_en_map_buffer(struct mlx4_buf *buf);
530 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
532 void mlx4_en_calc_rx_buf(struct net_device *dev);
533 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
534 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
535 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
536 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
538 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
539 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
540 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
541 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
542 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
545 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
546 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
548 #define MLX4_EN_NUM_SELF_TEST 5
549 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
550 u64 mlx4_en_mac_to_u64(u8 *addr);
555 extern const struct ethtool_ops mlx4_en_ethtool_ops;
560 * printk / logging functions
563 int en_print(const char *level, const struct mlx4_en_priv *priv,
564 const char *format, ...) __attribute__ ((format (printf, 3, 4)));
566 #define en_dbg(mlevel, priv, format, arg...) \
568 if (NETIF_MSG_##mlevel & priv->msg_enable) \
569 en_print(KERN_DEBUG, priv, format, ##arg); \
571 #define en_warn(priv, format, arg...) \
572 en_print(KERN_WARNING, priv, format, ##arg)
573 #define en_err(priv, format, arg...) \
574 en_print(KERN_ERR, priv, format, ##arg)
575 #define en_info(priv, format, arg...) \
576 en_print(KERN_INFO, priv, format, ## arg)
578 #define mlx4_err(mdev, format, arg...) \
579 pr_err("%s %s: " format, DRV_NAME, \
580 dev_name(&mdev->pdev->dev), ##arg)
581 #define mlx4_info(mdev, format, arg...) \
582 pr_info("%s %s: " format, DRV_NAME, \
583 dev_name(&mdev->pdev->dev), ##arg)
584 #define mlx4_warn(mdev, format, arg...) \
585 pr_warning("%s %s: " format, DRV_NAME, \
586 dev_name(&mdev->pdev->dev), ##arg)