drivers/net/myri10ge/myri10ge.c

   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2009 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42
  43 #include <linux/tcp.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/string.h>
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/if_ether.h>
  52 #include <linux/if_vlan.h>
  53 #include <linux/inet_lro.h>
  54 #include <linux/dca.h>
  55 #include <linux/ip.h>
  56 #include <linux/inet.h>
  57 #include <linux/in.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/firmware.h>
  60 #include <linux/delay.h>
  61 #include <linux/timer.h>
  62 #include <linux/vmalloc.h>
  63 #include <linux/crc32.h>
  64 #include <linux/moduleparam.h>
  65 #include <linux/io.h>
  66 #include <linux/log2.h>
  67 #include <linux/slab.h>
  68 #include <net/checksum.h>
  69 #include <net/ip.h>
  70 #include <net/tcp.h>
  71 #include <asm/byteorder.h>
  72 #include <asm/io.h>
  73 #include <asm/processor.h>
  74 #ifdef CONFIG_MTRR
  75 #include <asm/mtrr.h>
  76 #endif
  77
  78 #include "myri10ge_mcp.h"
  79 #include "myri10ge_mcp_gen_header.h"
  80
  81 #define MYRI10GE_VERSION_STR "1.5.2-1.459"
  82
  83 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  84 MODULE_AUTHOR("Maintainer: help@myri.com");
  85 MODULE_VERSION(MYRI10GE_VERSION_STR);
  86 MODULE_LICENSE("Dual BSD/GPL");
  87
  88 #define MYRI10GE_MAX_ETHER_MTU 9014
  89
  90 #define MYRI10GE_ETH_STOPPED 0
  91 #define MYRI10GE_ETH_STOPPING 1
  92 #define MYRI10GE_ETH_STARTING 2
  93 #define MYRI10GE_ETH_RUNNING 3
  94 #define MYRI10GE_ETH_OPEN_FAILED 4
  95
  96 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  97 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  98 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  99 #define MYRI10GE_LRO_MAX_PKTS 64
 100
 101 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 102 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 103
 104 #define MYRI10GE_ALLOC_ORDER 0
 105 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 106 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 107
 108 #define MYRI10GE_MAX_SLICES 32
 109
 110 struct myri10ge_rx_buffer_state {
 111         struct page *page;
 112         int page_offset;
 113         DEFINE_DMA_UNMAP_ADDR(bus);
 114         DEFINE_DMA_UNMAP_LEN(len);
 115 };
 116
 117 struct myri10ge_tx_buffer_state {
 118         struct sk_buff *skb;
 119         int last;
 120         DEFINE_DMA_UNMAP_ADDR(bus);
 121         DEFINE_DMA_UNMAP_LEN(len);
 122 };
 123
 124 struct myri10ge_cmd {
 125         u32 data0;
 126         u32 data1;
 127         u32 data2;
 128 };
 129
 130 struct myri10ge_rx_buf {
 131         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 132         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 133         struct myri10ge_rx_buffer_state *info;
 134         struct page *page;
 135         dma_addr_t bus;
 136         int page_offset;
 137         int cnt;
 138         int fill_cnt;
 139         int alloc_fail;
 140         int mask;               /* number of rx slots -1 */
 141         int watchdog_needed;
 142 };
 143
 144 struct myri10ge_tx_buf {
 145         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 146         __be32 __iomem *send_go;        /* "go" doorbell ptr */
 147         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
 148         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 149         char *req_bytes;
 150         struct myri10ge_tx_buffer_state *info;
 151         int mask;               /* number of transmit slots -1  */
 152         int req ____cacheline_aligned;  /* transmit slots submitted     */
 153         int pkt_start;          /* packets started */
 154         int stop_queue;
 155         int linearized;
 156         int done ____cacheline_aligned; /* transmit slots completed     */
 157         int pkt_done;           /* packets completed */
 158         int wake_queue;
 159         int queue_active;
 160 };
 161
 162 struct myri10ge_rx_done {
 163         struct mcp_slot *entry;
 164         dma_addr_t bus;
 165         int cnt;
 166         int idx;
 167         struct net_lro_mgr lro_mgr;
 168         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 169 };
 170
 171 struct myri10ge_slice_netstats {
 172         unsigned long rx_packets;
 173         unsigned long tx_packets;
 174         unsigned long rx_bytes;
 175         unsigned long tx_bytes;
 176         unsigned long rx_dropped;
 177         unsigned long tx_dropped;
 178 };
 179
 180 struct myri10ge_slice_state {
 181         struct myri10ge_tx_buf tx;      /* transmit ring        */
 182         struct myri10ge_rx_buf rx_small;
 183         struct myri10ge_rx_buf rx_big;
 184         struct myri10ge_rx_done rx_done;
 185         struct net_device *dev;
 186         struct napi_struct napi;
 187         struct myri10ge_priv *mgp;
 188         struct myri10ge_slice_netstats stats;
 189         __be32 __iomem *irq_claim;
 190         struct mcp_irq_data *fw_stats;
 191         dma_addr_t fw_stats_bus;
 192         int watchdog_tx_done;
 193         int watchdog_tx_req;
 194         int watchdog_rx_done;
 195 #ifdef CONFIG_MYRI10GE_DCA
 196         int cached_dca_tag;
 197         int cpu;
 198         __be32 __iomem *dca_tag;
 199 #endif
 200         char irq_desc[32];
 201 };
 202
 203 struct myri10ge_priv {
 204         struct myri10ge_slice_state *ss;
 205         int tx_boundary;        /* boundary transmits cannot cross */
 206         int num_slices;
 207         int running;            /* running?             */
 208         int csum_flag;          /* rx_csums?            */
 209         int small_bytes;
 210         int big_bytes;
 211         int max_intr_slots;
 212         struct net_device *dev;
 213         spinlock_t stats_lock;
 214         u8 __iomem *sram;
 215         int sram_size;
 216         unsigned long board_span;
 217         unsigned long iomem_base;
 218         __be32 __iomem *irq_deassert;
 219         char *mac_addr_string;
 220         struct mcp_cmd_response *cmd;
 221         dma_addr_t cmd_bus;
 222         struct pci_dev *pdev;
 223         int msi_enabled;
 224         int msix_enabled;
 225         struct msix_entry *msix_vectors;
 226 #ifdef CONFIG_MYRI10GE_DCA
 227         int dca_enabled;
 228 #endif
 229         u32 link_state;
 230         unsigned int rdma_tags_available;
 231         int intr_coal_delay;
 232         __be32 __iomem *intr_coal_delay_ptr;
 233         int mtrr;
 234         int wc_enabled;
 235         int down_cnt;
 236         wait_queue_head_t down_wq;
 237         struct work_struct watchdog_work;
 238         struct timer_list watchdog_timer;
 239         int watchdog_resets;
 240         int watchdog_pause;
 241         int pause;
 242         char *fw_name;
 243         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 244         char *product_code_string;
 245         char fw_version[128];
 246         int fw_ver_major;
 247         int fw_ver_minor;
 248         int fw_ver_tiny;
 249         int adopted_rx_filter_bug;
 250         u8 mac_addr[6];         /* eeprom mac address */
 251         unsigned long serial_number;
 252         int vendor_specific_offset;
 253         int fw_multicast_support;
 254         unsigned long features;
 255         u32 max_tso6;
 256         u32 read_dma;
 257         u32 write_dma;
 258         u32 read_write_dma;
 259         u32 link_changes;
 260         u32 msg_enable;
 261         unsigned int board_number;
 262         int rebooted;
 263 };
 264
 265 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 266 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 267 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 268 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 269 MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
 270 MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
 271 MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
 272 MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
 273
 274 static char *myri10ge_fw_name = NULL;
 275 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 276 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 277
 278 #define MYRI10GE_MAX_BOARDS 8
 279 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
 280     {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
 281 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
 282                          0444);
 283 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
 284
 285 static int myri10ge_ecrc_enable = 1;
 286 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 287 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 288
 289 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 290 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 291 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 292
 293 static int myri10ge_msi = 1;    /* enable msi by default */
 294 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 295 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 296
 297 static int myri10ge_intr_coal_delay = 75;
 298 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 299 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 300
 301 static int myri10ge_flow_control = 1;
 302 module_param(myri10ge_flow_control, int, S_IRUGO);
 303 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 304
 305 static int myri10ge_deassert_wait = 1;
 306 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 307 MODULE_PARM_DESC(myri10ge_deassert_wait,
 308                  "Wait when deasserting legacy interrupts");
 309
 310 static int myri10ge_force_firmware = 0;
 311 module_param(myri10ge_force_firmware, int, S_IRUGO);
 312 MODULE_PARM_DESC(myri10ge_force_firmware,
 313                  "Force firmware to assume aligned completions");
 314
 315 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 316 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 317 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 318
 319 static int myri10ge_napi_weight = 64;
 320 module_param(myri10ge_napi_weight, int, S_IRUGO);
 321 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 322
 323 static int myri10ge_watchdog_timeout = 1;
 324 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 325 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 326
 327 static int myri10ge_max_irq_loops = 1048576;
 328 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 329 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 330                  "Set stuck legacy IRQ detection threshold");
 331
 332 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 333
 334 static int myri10ge_debug = -1; /* defaults above */
 335 module_param(myri10ge_debug, int, 0);
 336 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 337
 338 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 339 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 340 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 341                  "Number of LRO packets to be aggregated");
 342
 343 static int myri10ge_fill_thresh = 256;
 344 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 345 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 346
 347 static int myri10ge_reset_recover = 1;
 348
 349 static int myri10ge_max_slices = 1;
 350 module_param(myri10ge_max_slices, int, S_IRUGO);
 351 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 352
 353 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
 354 module_param(myri10ge_rss_hash, int, S_IRUGO);
 355 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 356
 357 static int myri10ge_dca = 1;
 358 module_param(myri10ge_dca, int, S_IRUGO);
 359 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 360
 361 #define MYRI10GE_FW_OFFSET 1024*1024
 362 #define MYRI10GE_HIGHPART_TO_U32(X) \
 363 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 364 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 365
 366 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 367
 368 static void myri10ge_set_multicast_list(struct net_device *dev);
 369 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
 370                                          struct net_device *dev);
 371
 372 static inline void put_be32(__be32 val, __be32 __iomem * p)
 373 {
 374         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 375 }
 376
 377 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
 378
 379 static int
 380 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 381                   struct myri10ge_cmd *data, int atomic)
 382 {
 383         struct mcp_cmd *buf;
 384         char buf_bytes[sizeof(*buf) + 8];
 385         struct mcp_cmd_response *response = mgp->cmd;
 386         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 387         u32 dma_low, dma_high, result, value;
 388         int sleep_total = 0;
 389
 390         /* ensure buf is aligned to 8 bytes */
 391         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 392
 393         buf->data0 = htonl(data->data0);
 394         buf->data1 = htonl(data->data1);
 395         buf->data2 = htonl(data->data2);
 396         buf->cmd = htonl(cmd);
 397         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 398         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 399
 400         buf->response_addr.low = htonl(dma_low);
 401         buf->response_addr.high = htonl(dma_high);
 402         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 403         mb();
 404         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 405
 406         /* wait up to 15ms. Longest command is the DMA benchmark,
 407          * which is capped at 5ms, but runs from a timeout handler
 408          * that runs every 7.8ms. So a 15ms timeout leaves us with
 409          * a 2.2ms margin
 410          */
 411         if (atomic) {
 412                 /* if atomic is set, do not sleep,
 413                  * and try to get the completion quickly
 414                  * (1ms will be enough for those commands) */
 415                 for (sleep_total = 0;
 416                      sleep_total < 1000 &&
 417                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 418                      sleep_total += 10) {
 419                         udelay(10);
 420                         mb();
 421                 }
 422         } else {
 423                 /* use msleep for most command */
 424                 for (sleep_total = 0;
 425                      sleep_total < 15 &&
 426                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 427                      sleep_total++)
 428                         msleep(1);
 429         }
 430
 431         result = ntohl(response->result);
 432         value = ntohl(response->data);
 433         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 434                 if (result == 0) {
 435                         data->data0 = value;
 436                         return 0;
 437                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 438                         return -ENOSYS;
 439                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 440                         return -E2BIG;
 441                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
 442                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
 443                            (data->
 444                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
 445                            0) {
 446                         return -ERANGE;
 447                 } else {
 448                         dev_err(&mgp->pdev->dev,
 449                                 "command %d failed, result = %d\n",
 450                                 cmd, result);
 451                         return -ENXIO;
 452                 }
 453         }
 454
 455         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 456                 cmd, result);
 457         return -EAGAIN;
 458 }
 459
 460 /*
 461  * The eeprom strings on the lanaiX have the format
 462  * SN=x\0
 463  * MAC=x:x:x:x:x:x\0
 464  * PT:ddd mmm xx xx:xx:xx xx\0
 465  * PV:ddd mmm xx xx:xx:xx xx\0
 466  */
 467 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 468 {
 469         char *ptr, *limit;
 470         int i;
 471
 472         ptr = mgp->eeprom_strings;
 473         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 474
 475         while (*ptr != '\0' && ptr < limit) {
 476                 if (memcmp(ptr, "MAC=", 4) == 0) {
 477                         ptr += 4;
 478                         mgp->mac_addr_string = ptr;
 479                         for (i = 0; i < 6; i++) {
 480                                 if ((ptr + 2) > limit)
 481                                         goto abort;
 482                                 mgp->mac_addr[i] =
 483                                     simple_strtoul(ptr, &ptr, 16);
 484                                 ptr += 1;
 485                         }
 486                 }
 487                 if (memcmp(ptr, "PC=", 3) == 0) {
 488                         ptr += 3;
 489                         mgp->product_code_string = ptr;
 490                 }
 491                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 492                         ptr += 3;
 493                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 494                 }
 495                 while (ptr < limit && *ptr++) ;
 496         }
 497
 498         return 0;
 499
 500 abort:
 501         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 502         return -ENXIO;
 503 }
 504
 505 /*
 506  * Enable or disable periodic RDMAs from the host to make certain
 507  * chipsets resend dropped PCIe messages
 508  */
 509
 510 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 511 {
 512         char __iomem *submit;
 513         __be32 buf[16] __attribute__ ((__aligned__(8)));
 514         u32 dma_low, dma_high;
 515         int i;
 516
 517         /* clear confirmation addr */
 518         mgp->cmd->data = 0;
 519         mb();
 520
 521         /* send a rdma command to the PCIe engine, and wait for the
 522          * response in the confirmation address.  The firmware should
 523          * write a -1 there to indicate it is alive and well
 524          */
 525         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 526         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 527
 528         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 529         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 530         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 531         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 532         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 533         buf[5] = htonl(enable); /* enable? */
 534
 535         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 536
 537         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 538         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 539                 msleep(1);
 540         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 541                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 542                         (enable ? "enable" : "disable"));
 543 }
 544
 545 static int
 546 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 547                            struct mcp_gen_header *hdr)
 548 {
 549         struct device *dev = &mgp->pdev->dev;
 550
 551         /* check firmware type */
 552         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 553                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 554                 return -EINVAL;
 555         }
 556
 557         /* save firmware version for ethtool */
 558         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 559
 560         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 561                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 562
 563         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
 564               mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 565                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 566                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 567                         MXGEFW_VERSION_MINOR);
 568                 return -EINVAL;
 569         }
 570         return 0;
 571 }
 572
 573 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 574 {
 575         unsigned crc, reread_crc;
 576         const struct firmware *fw;
 577         struct device *dev = &mgp->pdev->dev;
 578         unsigned char *fw_readback;
 579         struct mcp_gen_header *hdr;
 580         size_t hdr_offset;
 581         int status;
 582         unsigned i;
 583
 584         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 585                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 586                         mgp->fw_name);
 587                 status = -EINVAL;
 588                 goto abort_with_nothing;
 589         }
 590
 591         /* check size */
 592
 593         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 594             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 595                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 596                 status = -EINVAL;
 597                 goto abort_with_fw;
 598         }
 599
 600         /* check id */
 601         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 602         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 603                 dev_err(dev, "Bad firmware file\n");
 604                 status = -EINVAL;
 605                 goto abort_with_fw;
 606         }
 607         hdr = (void *)(fw->data + hdr_offset);
 608
 609         status = myri10ge_validate_firmware(mgp, hdr);
 610         if (status != 0)
 611                 goto abort_with_fw;
 612
 613         crc = crc32(~0, fw->data, fw->size);
 614         for (i = 0; i < fw->size; i += 256) {
 615                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 616                                   fw->data + i,
 617                                   min(256U, (unsigned)(fw->size - i)));
 618                 mb();
 619                 readb(mgp->sram);
 620         }
 621         fw_readback = vmalloc(fw->size);
 622         if (!fw_readback) {
 623                 status = -ENOMEM;
 624                 goto abort_with_fw;
 625         }
 626         /* corruption checking is good for parity recovery and buggy chipset */
 627         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 628         reread_crc = crc32(~0, fw_readback, fw->size);
 629         vfree(fw_readback);
 630         if (crc != reread_crc) {
 631                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 632                         (unsigned)fw->size, reread_crc, crc);
 633                 status = -EIO;
 634                 goto abort_with_fw;
 635         }
 636         *size = (u32) fw->size;
 637
 638 abort_with_fw:
 639         release_firmware(fw);
 640
 641 abort_with_nothing:
 642         return status;
 643 }
 644
 645 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 646 {
 647         struct mcp_gen_header *hdr;
 648         struct device *dev = &mgp->pdev->dev;
 649         const size_t bytes = sizeof(struct mcp_gen_header);
 650         size_t hdr_offset;
 651         int status;
 652
 653         /* find running firmware header */
 654         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 655
 656         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 657                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 658                         (int)hdr_offset);
 659                 return -EIO;
 660         }
 661
 662         /* copy header of running firmware from SRAM to host memory to
 663          * validate firmware */
 664         hdr = kmalloc(bytes, GFP_KERNEL);
 665         if (hdr == NULL) {
 666                 dev_err(dev, "could not malloc firmware hdr\n");
 667                 return -ENOMEM;
 668         }
 669         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 670         status = myri10ge_validate_firmware(mgp, hdr);
 671         kfree(hdr);
 672
 673         /* check to see if adopted firmware has bug where adopting
 674          * it will cause broadcasts to be filtered unless the NIC
 675          * is kept in ALLMULTI mode */
 676         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 677             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 678                 mgp->adopted_rx_filter_bug = 1;
 679                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 680                          "working around rx filter bug\n",
 681                          mgp->fw_ver_major, mgp->fw_ver_minor,
 682                          mgp->fw_ver_tiny);
 683         }
 684         return status;
 685 }
 686
 687 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 688 {
 689         struct myri10ge_cmd cmd;
 690         int status;
 691
 692         /* probe for IPv6 TSO support */
 693         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 694         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 695                                    &cmd, 0);
 696         if (status == 0) {
 697                 mgp->max_tso6 = cmd.data0;
 698                 mgp->features |= NETIF_F_TSO6;
 699         }
 700
 701         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 702         if (status != 0) {
 703                 dev_err(&mgp->pdev->dev,
 704                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 705                 return -ENXIO;
 706         }
 707
 708         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 709
 710         return 0;
 711 }
 712
 713 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 714 {
 715         char __iomem *submit;
 716         __be32 buf[16] __attribute__ ((__aligned__(8)));
 717         u32 dma_low, dma_high, size;
 718         int status, i;
 719
 720         size = 0;
 721         status = myri10ge_load_hotplug_firmware(mgp, &size);
 722         if (status) {
 723                 if (!adopt)
 724                         return status;
 725                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 726
 727                 /* Do not attempt to adopt firmware if there
 728                  * was a bad crc */
 729                 if (status == -EIO)
 730                         return status;
 731
 732                 status = myri10ge_adopt_running_firmware(mgp);
 733                 if (status != 0) {
 734                         dev_err(&mgp->pdev->dev,
 735                                 "failed to adopt running firmware\n");
 736                         return status;
 737                 }
 738                 dev_info(&mgp->pdev->dev,
 739                          "Successfully adopted running firmware\n");
 740                 if (mgp->tx_boundary == 4096) {
 741                         dev_warn(&mgp->pdev->dev,
 742                                  "Using firmware currently running on NIC"
 743                                  ".  For optimal\n");
 744                         dev_warn(&mgp->pdev->dev,
 745                                  "performance consider loading optimized "
 746                                  "firmware\n");
 747                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 748                 }
 749
 750                 mgp->fw_name = "adopted";
 751                 mgp->tx_boundary = 2048;
 752                 myri10ge_dummy_rdma(mgp, 1);
 753                 status = myri10ge_get_firmware_capabilities(mgp);
 754                 return status;
 755         }
 756
 757         /* clear confirmation addr */
 758         mgp->cmd->data = 0;
 759         mb();
 760
 761         /* send a reload command to the bootstrap MCP, and wait for the
 762          *  response in the confirmation address.  The firmware should
 763          * write a -1 there to indicate it is alive and well
 764          */
 765         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 766         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 767
 768         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 769         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 770         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 771
 772         /* FIX: All newest firmware should un-protect the bottom of
 773          * the sram before handoff. However, the very first interfaces
 774          * do not. Therefore the handoff copy must skip the first 8 bytes
 775          */
 776         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 777         buf[4] = htonl(size - 8);       /* length of code */
 778         buf[5] = htonl(8);      /* where to copy to */
 779         buf[6] = htonl(0);      /* where to jump to */
 780
 781         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 782
 783         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 784         mb();
 785         msleep(1);
 786         mb();
 787         i = 0;
 788         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 789                 msleep(1 << i);
 790                 i++;
 791         }
 792         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 793                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 794                 return -ENXIO;
 795         }
 796         myri10ge_dummy_rdma(mgp, 1);
 797         status = myri10ge_get_firmware_capabilities(mgp);
 798
 799         return status;
 800 }
 801
 802 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 803 {
 804         struct myri10ge_cmd cmd;
 805         int status;
 806
 807         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 808                      | (addr[2] << 8) | addr[3]);
 809
 810         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 811
 812         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 813         return status;
 814 }
 815
 816 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 817 {
 818         struct myri10ge_cmd cmd;
 819         int status, ctl;
 820
 821         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 822         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 823
 824         if (status) {
 825                 netdev_err(mgp->dev, "Failed to set flow control mode\n");
 826                 return status;
 827         }
 828         mgp->pause = pause;
 829         return 0;
 830 }
 831
 832 static void
 833 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 834 {
 835         struct myri10ge_cmd cmd;
 836         int status, ctl;
 837
 838         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 839         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 840         if (status)
 841                 netdev_err(mgp->dev, "Failed to set promisc mode\n");
 842 }
 843
 844 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 845 {
 846         struct myri10ge_cmd cmd;
 847         int status;
 848         u32 len;
 849         struct page *dmatest_page;
 850         dma_addr_t dmatest_bus;
 851         char *test = " ";
 852
 853         dmatest_page = alloc_page(GFP_KERNEL);
 854         if (!dmatest_page)
 855                 return -ENOMEM;
 856         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 857                                    DMA_BIDIRECTIONAL);
 858
 859         /* Run a small DMA test.
 860          * The magic multipliers to the length tell the firmware
 861          * to do DMA read, write, or read+write tests.  The
 862          * results are returned in cmd.data0.  The upper 16
 863          * bits or the return is the number of transfers completed.
 864          * The lower 16 bits is the time in 0.5us ticks that the
 865          * transfers took to complete.
 866          */
 867
 868         len = mgp->tx_boundary;
 869
 870         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 871         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 872         cmd.data2 = len * 0x10000;
 873         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 874         if (status != 0) {
 875                 test = "read";
 876                 goto abort;
 877         }
 878         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 879         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 880         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 881         cmd.data2 = len * 0x1;
 882         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 883         if (status != 0) {
 884                 test = "write";
 885                 goto abort;
 886         }
 887         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 888
 889         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 890         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 891         cmd.data2 = len * 0x10001;
 892         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 893         if (status != 0) {
 894                 test = "read/write";
 895                 goto abort;
 896         }
 897         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 898             (cmd.data0 & 0xffff);
 899
 900 abort:
 901         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 902         put_page(dmatest_page);
 903
 904         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 905                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 906                          test, status);
 907
 908         return status;
 909 }
 910
 911 static int myri10ge_reset(struct myri10ge_priv *mgp)
 912 {
 913         struct myri10ge_cmd cmd;
 914         struct myri10ge_slice_state *ss;
 915         int i, status;
 916         size_t bytes;
 917 #ifdef CONFIG_MYRI10GE_DCA
 918         unsigned long dca_tag_off;
 919 #endif
 920
 921         /* try to send a reset command to the card to see if it
 922          * is alive */
 923         memset(&cmd, 0, sizeof(cmd));
 924         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 925         if (status != 0) {
 926                 dev_err(&mgp->pdev->dev, "failed reset\n");
 927                 return -ENXIO;
 928         }
 929
 930         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 931         /*
 932          * Use non-ndis mcp_slot (eg, 4 bytes total,
 933          * no toeplitz hash value returned.  Older firmware will
 934          * not understand this command, but will use the correct
 935          * sized mcp_slot, so we ignore error returns
 936          */
 937         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 938         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 939
 940         /* Now exchange information about interrupts  */
 941
 942         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 943         cmd.data0 = (u32) bytes;
 944         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 945
 946         /*
 947          * Even though we already know how many slices are supported
 948          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 949          * has magic side effects, and must be called after a reset.
 950          * It must be called prior to calling any RSS related cmds,
 951          * including assigning an interrupt queue for anything but
 952          * slice 0.  It must also be called *after*
 953          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 954          * the firmware to compute offsets.
 955          */
 956
 957         if (mgp->num_slices > 1) {
 958
 959                 /* ask the maximum number of slices it supports */
 960                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 961                                            &cmd, 0);
 962                 if (status != 0) {
 963                         dev_err(&mgp->pdev->dev,
 964                                 "failed to get number of slices\n");
 965                 }
 966
 967                 /*
 968                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 969                  * to setting up the interrupt queue DMA
 970                  */
 971
 972                 cmd.data0 = mgp->num_slices;
 973                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 974                 if (mgp->dev->real_num_tx_queues > 1)
 975                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
 976                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 977                                            &cmd, 0);
 978
 979                 /* Firmware older than 1.4.32 only supports multiple
 980                  * RX queues, so if we get an error, first retry using a
 981                  * single TX queue before giving up */
 982                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
 983                         mgp->dev->real_num_tx_queues = 1;
 984                         cmd.data0 = mgp->num_slices;
 985                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 986                         status = myri10ge_send_cmd(mgp,
 987                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
 988                                                    &cmd, 0);
 989                 }
 990
 991                 if (status != 0) {
 992                         dev_err(&mgp->pdev->dev,
 993                                 "failed to set number of slices\n");
 994
 995                         return status;
 996                 }
 997         }
 998         for (i = 0; i < mgp->num_slices; i++) {
 999                 ss = &mgp->ss[i];
1000                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1001                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1002                 cmd.data2 = i;
1003                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1004                                             &cmd, 0);
1005         };
1006
1007         status |=
1008             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1009         for (i = 0; i < mgp->num_slices; i++) {
1010                 ss = &mgp->ss[i];
1011                 ss->irq_claim =
1012                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1013         }
1014         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1015                                     &cmd, 0);
1016         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1017
1018         status |= myri10ge_send_cmd
1019             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1020         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1021         if (status != 0) {
1022                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1023                 return status;
1024         }
1025         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1026
1027 #ifdef CONFIG_MYRI10GE_DCA
1028         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1029         dca_tag_off = cmd.data0;
1030         for (i = 0; i < mgp->num_slices; i++) {
1031                 ss = &mgp->ss[i];
1032                 if (status == 0) {
1033                         ss->dca_tag = (__iomem __be32 *)
1034                             (mgp->sram + dca_tag_off + 4 * i);
1035                 } else {
1036                         ss->dca_tag = NULL;
1037                 }
1038         }
1039 #endif                          /* CONFIG_MYRI10GE_DCA */
1040
1041         /* reset mcp/driver shared state back to 0 */
1042
1043         mgp->link_changes = 0;
1044         for (i = 0; i < mgp->num_slices; i++) {
1045                 ss = &mgp->ss[i];
1046
1047                 memset(ss->rx_done.entry, 0, bytes);
1048                 ss->tx.req = 0;
1049                 ss->tx.done = 0;
1050                 ss->tx.pkt_start = 0;
1051                 ss->tx.pkt_done = 0;
1052                 ss->rx_big.cnt = 0;
1053                 ss->rx_small.cnt = 0;
1054                 ss->rx_done.idx = 0;
1055                 ss->rx_done.cnt = 0;
1056                 ss->tx.wake_queue = 0;
1057                 ss->tx.stop_queue = 0;
1058         }
1059
1060         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1061         myri10ge_change_pause(mgp, mgp->pause);
1062         myri10ge_set_multicast_list(mgp->dev);
1063         return status;
1064 }
1065
1066 #ifdef CONFIG_MYRI10GE_DCA
1067 static void
1068 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1069 {
1070         ss->cpu = cpu;
1071         ss->cached_dca_tag = tag;
1072         put_be32(htonl(tag), ss->dca_tag);
1073 }
1074
1075 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1076 {
1077         int cpu = get_cpu();
1078         int tag;
1079
1080         if (cpu != ss->cpu) {
1081                 tag = dca_get_tag(cpu);
1082                 if (ss->cached_dca_tag != tag)
1083                         myri10ge_write_dca(ss, cpu, tag);
1084         }
1085         put_cpu();
1086 }
1087
1088 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1089 {
1090         int err, i;
1091         struct pci_dev *pdev = mgp->pdev;
1092
1093         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1094                 return;
1095         if (!myri10ge_dca) {
1096                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1097                 return;
1098         }
1099         err = dca_add_requester(&pdev->dev);
1100         if (err) {
1101                 if (err != -ENODEV)
1102                         dev_err(&pdev->dev,
1103                                 "dca_add_requester() failed, err=%d\n", err);
1104                 return;
1105         }
1106         mgp->dca_enabled = 1;
1107         for (i = 0; i < mgp->num_slices; i++)
1108                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1109 }
1110
1111 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1112 {
1113         struct pci_dev *pdev = mgp->pdev;
1114         int err;
1115
1116         if (!mgp->dca_enabled)
1117                 return;
1118         mgp->dca_enabled = 0;
1119         err = dca_remove_requester(&pdev->dev);
1120 }
1121
1122 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1123 {
1124         struct myri10ge_priv *mgp;
1125         unsigned long event;
1126
1127         mgp = dev_get_drvdata(dev);
1128         event = *(unsigned long *)data;
1129
1130         if (event == DCA_PROVIDER_ADD)
1131                 myri10ge_setup_dca(mgp);
1132         else if (event == DCA_PROVIDER_REMOVE)
1133                 myri10ge_teardown_dca(mgp);
1134         return 0;
1135 }
1136 #endif                          /* CONFIG_MYRI10GE_DCA */
1137
1138 static inline void
1139 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1140                     struct mcp_kreq_ether_recv *src)
1141 {
1142         __be32 low;
1143
1144         low = src->addr_low;
1145         src->addr_low = htonl(DMA_BIT_MASK(32));
1146         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1147         mb();
1148         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1149         mb();
1150         src->addr_low = low;
1151         put_be32(low, &dst->addr_low);
1152         mb();
1153 }
1154
1155 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1156 {
1157         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1158
1159         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1160             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1161              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1162                 skb->csum = hw_csum;
1163                 skb->ip_summed = CHECKSUM_COMPLETE;
1164         }
1165 }
1166
1167 static inline void
1168 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1169                       struct skb_frag_struct *rx_frags, int len, int hlen)
1170 {
1171         struct skb_frag_struct *skb_frags;
1172
1173         skb->len = skb->data_len = len;
1174         skb->truesize = len + sizeof(struct sk_buff);
1175         /* attach the page(s) */
1176
1177         skb_frags = skb_shinfo(skb)->frags;
1178         while (len > 0) {
1179                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1180                 len -= rx_frags->size;
1181                 skb_frags++;
1182                 rx_frags++;
1183                 skb_shinfo(skb)->nr_frags++;
1184         }
1185
1186         /* pskb_may_pull is not available in irq context, but
1187          * skb_pull() (for ether_pad and eth_type_trans()) requires
1188          * the beginning of the packet in skb_headlen(), move it
1189          * manually */
1190         skb_copy_to_linear_data(skb, va, hlen);
1191         skb_shinfo(skb)->frags[0].page_offset += hlen;
1192         skb_shinfo(skb)->frags[0].size -= hlen;
1193         skb->data_len -= hlen;
1194         skb->tail += hlen;
1195         skb_pull(skb, MXGEFW_PAD);
1196 }
1197
1198 static void
1199 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1200                         int bytes, int watchdog)
1201 {
1202         struct page *page;
1203         int idx;
1204 #if MYRI10GE_ALLOC_SIZE > 4096
1205         int end_offset;
1206 #endif
1207
1208         if (unlikely(rx->watchdog_needed && !watchdog))
1209                 return;
1210
1211         /* try to refill entire ring */
1212         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1213                 idx = rx->fill_cnt & rx->mask;
1214                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1215                         /* we can use part of previous page */
1216                         get_page(rx->page);
1217                 } else {
1218                         /* we need a new page */
1219                         page =
1220                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1221                                         MYRI10GE_ALLOC_ORDER);
1222                         if (unlikely(page == NULL)) {
1223                                 if (rx->fill_cnt - rx->cnt < 16)
1224                                         rx->watchdog_needed = 1;
1225                                 return;
1226                         }
1227                         rx->page = page;
1228                         rx->page_offset = 0;
1229                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1230                                                MYRI10GE_ALLOC_SIZE,
1231                                                PCI_DMA_FROMDEVICE);
1232                 }
1233                 rx->info[idx].page = rx->page;
1234                 rx->info[idx].page_offset = rx->page_offset;
1235                 /* note that this is the address of the start of the
1236                  * page */
1237                 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1238                 rx->shadow[idx].addr_low =
1239                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1240                 rx->shadow[idx].addr_high =
1241                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1242
1243                 /* start next packet on a cacheline boundary */
1244                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1245
1246 #if MYRI10GE_ALLOC_SIZE > 4096
1247                 /* don't cross a 4KB boundary */
1248                 end_offset = rx->page_offset + bytes - 1;
1249                 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1250                         rx->page_offset = end_offset & ~4095;
1251 #endif
1252                 rx->fill_cnt++;
1253
1254                 /* copy 8 descriptors to the firmware at a time */
1255                 if ((idx & 7) == 7) {
1256                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1257                                             &rx->shadow[idx - 7]);
1258                 }
1259         }
1260 }
1261
1262 static inline void
1263 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1264                        struct myri10ge_rx_buffer_state *info, int bytes)
1265 {
1266         /* unmap the recvd page if we're the only or last user of it */
1267         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1268             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1269                 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
1270                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1271                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1272         }
1273 }
1274
1275 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1276                                  * page into an skb */
1277
1278 static inline int
1279 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1280                  int bytes, int len, __wsum csum)
1281 {
1282         struct myri10ge_priv *mgp = ss->mgp;
1283         struct sk_buff *skb;
1284         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1285         int i, idx, hlen, remainder;
1286         struct pci_dev *pdev = mgp->pdev;
1287         struct net_device *dev = mgp->dev;
1288         u8 *va;
1289
1290         len += MXGEFW_PAD;
1291         idx = rx->cnt & rx->mask;
1292         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1293         prefetch(va);
1294         /* Fill skb_frag_struct(s) with data from our receive */
1295         for (i = 0, remainder = len; remainder > 0; i++) {
1296                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1297                 rx_frags[i].page = rx->info[idx].page;
1298                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1299                 if (remainder < MYRI10GE_ALLOC_SIZE)
1300                         rx_frags[i].size = remainder;
1301                 else
1302                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1303                 rx->cnt++;
1304                 idx = rx->cnt & rx->mask;
1305                 remainder -= MYRI10GE_ALLOC_SIZE;
1306         }
1307
1308         if (dev->features & NETIF_F_LRO) {
1309                 rx_frags[0].page_offset += MXGEFW_PAD;
1310                 rx_frags[0].size -= MXGEFW_PAD;
1311                 len -= MXGEFW_PAD;
1312                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1313                                   /* opaque, will come back in get_frag_header */
1314                                   len, len,
1315                                   (void *)(__force unsigned long)csum, csum);
1316
1317                 return 1;
1318         }
1319
1320         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1321
1322         /* allocate an skb to attach the page(s) to. This is done
1323          * after trying LRO, so as to avoid skb allocation overheads */
1324
1325         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1326         if (unlikely(skb == NULL)) {
1327                 ss->stats.rx_dropped++;
1328                 do {
1329                         i--;
1330                         put_page(rx_frags[i].page);
1331                 } while (i != 0);
1332                 return 0;
1333         }
1334
1335         /* Attach the pages to the skb, and trim off any padding */
1336         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1337         if (skb_shinfo(skb)->frags[0].size <= 0) {
1338                 put_page(skb_shinfo(skb)->frags[0].page);
1339                 skb_shinfo(skb)->nr_frags = 0;
1340         }
1341         skb->protocol = eth_type_trans(skb, dev);
1342         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1343
1344         if (mgp->csum_flag) {
1345                 if ((skb->protocol == htons(ETH_P_IP)) ||
1346                     (skb->protocol == htons(ETH_P_IPV6))) {
1347                         skb->csum = csum;
1348                         skb->ip_summed = CHECKSUM_COMPLETE;
1349                 } else
1350                         myri10ge_vlan_ip_csum(skb, csum);
1351         }
1352         netif_receive_skb(skb);
1353         return 1;
1354 }
1355
1356 static inline void
1357 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1358 {
1359         struct pci_dev *pdev = ss->mgp->pdev;
1360         struct myri10ge_tx_buf *tx = &ss->tx;
1361         struct netdev_queue *dev_queue;
1362         struct sk_buff *skb;
1363         int idx, len;
1364
1365         while (tx->pkt_done != mcp_index) {
1366                 idx = tx->done & tx->mask;
1367                 skb = tx->info[idx].skb;
1368
1369                 /* Mark as free */
1370                 tx->info[idx].skb = NULL;
1371                 if (tx->info[idx].last) {
1372                         tx->pkt_done++;
1373                         tx->info[idx].last = 0;
1374                 }
1375                 tx->done++;
1376                 len = dma_unmap_len(&tx->info[idx], len);
1377                 dma_unmap_len_set(&tx->info[idx], len, 0);
1378                 if (skb) {
1379                         ss->stats.tx_bytes += skb->len;
1380                         ss->stats.tx_packets++;
1381                         dev_kfree_skb_irq(skb);
1382                         if (len)
1383                                 pci_unmap_single(pdev,
1384                                                  dma_unmap_addr(&tx->info[idx],
1385                                                                 bus), len,
1386                                                  PCI_DMA_TODEVICE);
1387                 } else {
1388                         if (len)
1389                                 pci_unmap_page(pdev,
1390                                                dma_unmap_addr(&tx->info[idx],
1391                                                               bus), len,
1392                                                PCI_DMA_TODEVICE);
1393                 }
1394         }
1395
1396         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1397         /*
1398          * Make a minimal effort to prevent the NIC from polling an
1399          * idle tx queue.  If we can't get the lock we leave the queue
1400          * active. In this case, either a thread was about to start
1401          * using the queue anyway, or we lost a race and the NIC will
1402          * waste some of its resources polling an inactive queue for a
1403          * while.
1404          */
1405
1406         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1407             __netif_tx_trylock(dev_queue)) {
1408                 if (tx->req == tx->done) {
1409                         tx->queue_active = 0;
1410                         put_be32(htonl(1), tx->send_stop);
1411                         mb();
1412                         mmiowb();
1413                 }
1414                 __netif_tx_unlock(dev_queue);
1415         }
1416
1417         /* start the queue if we've stopped it */
1418         if (netif_tx_queue_stopped(dev_queue) &&
1419             tx->req - tx->done < (tx->mask >> 1)) {
1420                 tx->wake_queue++;
1421                 netif_tx_wake_queue(dev_queue);
1422         }
1423 }
1424
1425 static inline int
1426 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1427 {
1428         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1429         struct myri10ge_priv *mgp = ss->mgp;
1430         struct net_device *netdev = mgp->dev;
1431         unsigned long rx_bytes = 0;
1432         unsigned long rx_packets = 0;
1433         unsigned long rx_ok;
1434
1435         int idx = rx_done->idx;
1436         int cnt = rx_done->cnt;
1437         int work_done = 0;
1438         u16 length;
1439         __wsum checksum;
1440
1441         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1442                 length = ntohs(rx_done->entry[idx].length);
1443                 rx_done->entry[idx].length = 0;
1444                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1445                 if (length <= mgp->small_bytes)
1446                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1447                                                  mgp->small_bytes,
1448                                                  length, checksum);
1449                 else
1450                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1451                                                  mgp->big_bytes,
1452                                                  length, checksum);
1453                 rx_packets += rx_ok;
1454                 rx_bytes += rx_ok * (unsigned long)length;
1455                 cnt++;
1456                 idx = cnt & (mgp->max_intr_slots - 1);
1457                 work_done++;
1458         }
1459         rx_done->idx = idx;
1460         rx_done->cnt = cnt;
1461         ss->stats.rx_packets += rx_packets;
1462         ss->stats.rx_bytes += rx_bytes;
1463
1464         if (netdev->features & NETIF_F_LRO)
1465                 lro_flush_all(&rx_done->lro_mgr);
1466
1467         /* restock receive rings if needed */
1468         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1469                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1470                                         mgp->small_bytes + MXGEFW_PAD, 0);
1471         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1472                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1473
1474         return work_done;
1475 }
1476
1477 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1478 {
1479         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1480
1481         if (unlikely(stats->stats_updated)) {
1482                 unsigned link_up = ntohl(stats->link_up);
1483                 if (mgp->link_state != link_up) {
1484                         mgp->link_state = link_up;
1485
1486                         if (mgp->link_state == MXGEFW_LINK_UP) {
1487                                 if (netif_msg_link(mgp))
1488                                         netdev_info(mgp->dev, "link up\n");
1489                                 netif_carrier_on(mgp->dev);
1490                                 mgp->link_changes++;
1491                         } else {
1492                                 if (netif_msg_link(mgp))
1493                                         netdev_info(mgp->dev, "link %s\n",
1494                                             link_up == MXGEFW_LINK_MYRINET ?
1495                                             "mismatch (Myrinet detected)" :
1496                                             "down");
1497                                 netif_carrier_off(mgp->dev);
1498                                 mgp->link_changes++;
1499                         }
1500                 }
1501                 if (mgp->rdma_tags_available !=
1502                     ntohl(stats->rdma_tags_available)) {
1503                         mgp->rdma_tags_available =
1504                             ntohl(stats->rdma_tags_available);
1505                         netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1506                                     mgp->rdma_tags_available);
1507                 }
1508                 mgp->down_cnt += stats->link_down;
1509                 if (stats->link_down)
1510                         wake_up(&mgp->down_wq);
1511         }
1512 }
1513
1514 static int myri10ge_poll(struct napi_struct *napi, int budget)
1515 {
1516         struct myri10ge_slice_state *ss =
1517             container_of(napi, struct myri10ge_slice_state, napi);
1518         int work_done;
1519
1520 #ifdef CONFIG_MYRI10GE_DCA
1521         if (ss->mgp->dca_enabled)
1522                 myri10ge_update_dca(ss);
1523 #endif
1524
1525         /* process as many rx events as NAPI will allow */
1526         work_done = myri10ge_clean_rx_done(ss, budget);
1527
1528         if (work_done < budget) {
1529                 napi_complete(napi);
1530                 put_be32(htonl(3), ss->irq_claim);
1531         }
1532         return work_done;
1533 }
1534
1535 static irqreturn_t myri10ge_intr(int irq, void *arg)
1536 {
1537         struct myri10ge_slice_state *ss = arg;
1538         struct myri10ge_priv *mgp = ss->mgp;
1539         struct mcp_irq_data *stats = ss->fw_stats;
1540         struct myri10ge_tx_buf *tx = &ss->tx;
1541         u32 send_done_count;
1542         int i;
1543
1544         /* an interrupt on a non-zero receive-only slice is implicitly
1545          * valid  since MSI-X irqs are not shared */
1546         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1547                 napi_schedule(&ss->napi);
1548                 return (IRQ_HANDLED);
1549         }
1550
1551         /* make sure it is our IRQ, and that the DMA has finished */
1552         if (unlikely(!stats->valid))
1553                 return (IRQ_NONE);
1554
1555         /* low bit indicates receives are present, so schedule
1556          * napi poll handler */
1557         if (stats->valid & 1)
1558                 napi_schedule(&ss->napi);
1559
1560         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1561                 put_be32(0, mgp->irq_deassert);
1562                 if (!myri10ge_deassert_wait)
1563                         stats->valid = 0;
1564                 mb();
1565         } else
1566                 stats->valid = 0;
1567
1568         /* Wait for IRQ line to go low, if using INTx */
1569         i = 0;
1570         while (1) {
1571                 i++;
1572                 /* check for transmit completes and receives */
1573                 send_done_count = ntohl(stats->send_done_count);
1574                 if (send_done_count != tx->pkt_done)
1575                         myri10ge_tx_done(ss, (int)send_done_count);
1576                 if (unlikely(i > myri10ge_max_irq_loops)) {
1577                         netdev_err(mgp->dev, "irq stuck?\n");
1578                         stats->valid = 0;
1579                         schedule_work(&mgp->watchdog_work);
1580                 }
1581                 if (likely(stats->valid == 0))
1582                         break;
1583                 cpu_relax();
1584                 barrier();
1585         }
1586
1587         /* Only slice 0 updates stats */
1588         if (ss == mgp->ss)
1589                 myri10ge_check_statblock(mgp);
1590
1591         put_be32(htonl(3), ss->irq_claim + 1);
1592         return (IRQ_HANDLED);
1593 }
1594
1595 static int
1596 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1597 {
1598         struct myri10ge_priv *mgp = netdev_priv(netdev);
1599         char *ptr;
1600         int i;
1601
1602         cmd->autoneg = AUTONEG_DISABLE;
1603         cmd->speed = SPEED_10000;
1604         cmd->duplex = DUPLEX_FULL;
1605
1606         /*
1607          * parse the product code to deterimine the interface type
1608          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1609          * after the 3rd dash in the driver's cached copy of the
1610          * EEPROM's product code string.
1611          */
1612         ptr = mgp->product_code_string;
1613         if (ptr == NULL) {
1614                 netdev_err(netdev, "Missing product code\n");
1615                 return 0;
1616         }
1617         for (i = 0; i < 3; i++, ptr++) {
1618                 ptr = strchr(ptr, '-');
1619                 if (ptr == NULL) {
1620                         netdev_err(netdev, "Invalid product code %s\n",
1621                                    mgp->product_code_string);
1622                         return 0;
1623                 }
1624         }
1625         if (*ptr == '2')
1626                 ptr++;
1627         if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1628                 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
1629                 cmd->port = PORT_FIBRE;
1630                 cmd->supported |= SUPPORTED_FIBRE;
1631                 cmd->advertising |= ADVERTISED_FIBRE;
1632         } else {
1633                 cmd->port = PORT_OTHER;
1634         }
1635         if (*ptr == 'R' || *ptr == 'S')
1636                 cmd->transceiver = XCVR_EXTERNAL;
1637         else
1638                 cmd->transceiver = XCVR_INTERNAL;
1639
1640         return 0;
1641 }
1642
1643 static void
1644 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1645 {
1646         struct myri10ge_priv *mgp = netdev_priv(netdev);
1647
1648         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1649         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1650         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1651         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1652 }
1653
1654 static int
1655 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1656 {
1657         struct myri10ge_priv *mgp = netdev_priv(netdev);
1658
1659         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1660         return 0;
1661 }
1662
1663 static int
1664 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1665 {
1666         struct myri10ge_priv *mgp = netdev_priv(netdev);
1667
1668         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1669         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1670         return 0;
1671 }
1672
1673 static void
1674 myri10ge_get_pauseparam(struct net_device *netdev,
1675                         struct ethtool_pauseparam *pause)
1676 {
1677         struct myri10ge_priv *mgp = netdev_priv(netdev);
1678
1679         pause->autoneg = 0;
1680         pause->rx_pause = mgp->pause;
1681         pause->tx_pause = mgp->pause;
1682 }
1683
1684 static int
1685 myri10ge_set_pauseparam(struct net_device *netdev,
1686                         struct ethtool_pauseparam *pause)
1687 {
1688         struct myri10ge_priv *mgp = netdev_priv(netdev);
1689
1690         if (pause->tx_pause != mgp->pause)
1691                 return myri10ge_change_pause(mgp, pause->tx_pause);
1692         if (pause->rx_pause != mgp->pause)
1693                 return myri10ge_change_pause(mgp, pause->rx_pause);
1694         if (pause->autoneg != 0)
1695                 return -EINVAL;
1696         return 0;
1697 }
1698
1699 static void
1700 myri10ge_get_ringparam(struct net_device *netdev,
1701                        struct ethtool_ringparam *ring)
1702 {
1703         struct myri10ge_priv *mgp = netdev_priv(netdev);
1704
1705         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1706         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1707         ring->rx_jumbo_max_pending = 0;
1708         ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1709         ring->rx_mini_pending = ring->rx_mini_max_pending;
1710         ring->rx_pending = ring->rx_max_pending;
1711         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1712         ring->tx_pending = ring->tx_max_pending;
1713 }
1714
1715 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1716 {
1717         struct myri10ge_priv *mgp = netdev_priv(netdev);
1718
1719         if (mgp->csum_flag)
1720                 return 1;
1721         else
1722                 return 0;
1723 }
1724
1725 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1726 {
1727         struct myri10ge_priv *mgp = netdev_priv(netdev);
1728         int err = 0;
1729
1730         if (csum_enabled)
1731                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1732         else {
1733                 netdev->features &= ~NETIF_F_LRO;
1734                 mgp->csum_flag = 0;
1735
1736         }
1737         return err;
1738 }
1739
1740 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1741 {
1742         struct myri10ge_priv *mgp = netdev_priv(netdev);
1743         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1744
1745         if (tso_enabled)
1746                 netdev->features |= flags;
1747         else
1748                 netdev->features &= ~flags;
1749         return 0;
1750 }
1751
1752 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1753         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1754         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1755         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1756         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1757         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1758         "tx_heartbeat_errors", "tx_window_errors",
1759         /* device-specific stats */
1760         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1761         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1762         "serial_number", "watchdog_resets",
1763 #ifdef CONFIG_MYRI10GE_DCA
1764         "dca_capable_firmware", "dca_device_present",
1765 #endif
1766         "link_changes", "link_up", "dropped_link_overflow",
1767         "dropped_link_error_or_filtered",
1768         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1769         "dropped_unicast_filtered", "dropped_multicast_filtered",
1770         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1771         "dropped_no_big_buffer"
1772 };
1773
1774 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1775         "----------- slice ---------",
1776         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1777         "rx_small_cnt", "rx_big_cnt",
1778         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1779             "LRO flushed",
1780         "LRO avg aggr", "LRO no_desc"
1781 };
1782
1783 #define MYRI10GE_NET_STATS_LEN      21
1784 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1785 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1786
1787 static void
1788 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1789 {
1790         struct myri10ge_priv *mgp = netdev_priv(netdev);
1791         int i;
1792
1793         switch (stringset) {
1794         case ETH_SS_STATS:
1795                 memcpy(data, *myri10ge_gstrings_main_stats,
1796                        sizeof(myri10ge_gstrings_main_stats));
1797                 data += sizeof(myri10ge_gstrings_main_stats);
1798                 for (i = 0; i < mgp->num_slices; i++) {
1799                         memcpy(data, *myri10ge_gstrings_slice_stats,
1800                                sizeof(myri10ge_gstrings_slice_stats));
1801                         data += sizeof(myri10ge_gstrings_slice_stats);
1802                 }
1803                 break;
1804         }
1805 }
1806
1807 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1808 {
1809         struct myri10ge_priv *mgp = netdev_priv(netdev);
1810
1811         switch (sset) {
1812         case ETH_SS_STATS:
1813                 return MYRI10GE_MAIN_STATS_LEN +
1814                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1815         default:
1816                 return -EOPNOTSUPP;
1817         }
1818 }
1819
1820 static void
1821 myri10ge_get_ethtool_stats(struct net_device *netdev,
1822                            struct ethtool_stats *stats, u64 * data)
1823 {
1824         struct myri10ge_priv *mgp = netdev_priv(netdev);
1825         struct myri10ge_slice_state *ss;
1826         int slice;
1827         int i;
1828
1829         /* force stats update */
1830         (void)myri10ge_get_stats(netdev);
1831         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1832                 data[i] = ((unsigned long *)&netdev->stats)[i];
1833
1834         data[i++] = (unsigned int)mgp->tx_boundary;
1835         data[i++] = (unsigned int)mgp->wc_enabled;
1836         data[i++] = (unsigned int)mgp->pdev->irq;
1837         data[i++] = (unsigned int)mgp->msi_enabled;
1838         data[i++] = (unsigned int)mgp->msix_enabled;
1839         data[i++] = (unsigned int)mgp->read_dma;
1840         data[i++] = (unsigned int)mgp->write_dma;
1841         data[i++] = (unsigned int)mgp->read_write_dma;
1842         data[i++] = (unsigned int)mgp->serial_number;
1843         data[i++] = (unsigned int)mgp->watchdog_resets;
1844 #ifdef CONFIG_MYRI10GE_DCA
1845         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1846         data[i++] = (unsigned int)(mgp->dca_enabled);
1847 #endif
1848         data[i++] = (unsigned int)mgp->link_changes;
1849
1850         /* firmware stats are useful only in the first slice */
1851         ss = &mgp->ss[0];
1852         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1853         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1854         data[i++] =
1855             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1856         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1857         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1858         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1859         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1860         data[i++] =
1861             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1862         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1863         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1864         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1865         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1866
1867         for (slice = 0; slice < mgp->num_slices; slice++) {
1868                 ss = &mgp->ss[slice];
1869                 data[i++] = slice;
1870                 data[i++] = (unsigned int)ss->tx.pkt_start;
1871                 data[i++] = (unsigned int)ss->tx.pkt_done;
1872                 data[i++] = (unsigned int)ss->tx.req;
1873                 data[i++] = (unsigned int)ss->tx.done;
1874                 data[i++] = (unsigned int)ss->rx_small.cnt;
1875                 data[i++] = (unsigned int)ss->rx_big.cnt;
1876                 data[i++] = (unsigned int)ss->tx.wake_queue;
1877                 data[i++] = (unsigned int)ss->tx.stop_queue;
1878                 data[i++] = (unsigned int)ss->tx.linearized;
1879                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1880                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1881                 if (ss->rx_done.lro_mgr.stats.flushed)
1882                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1883                             ss->rx_done.lro_mgr.stats.flushed;
1884                 else
1885                         data[i++] = 0;
1886                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1887         }
1888 }
1889
1890 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1891 {
1892         struct myri10ge_priv *mgp = netdev_priv(netdev);
1893         mgp->msg_enable = value;
1894 }
1895
1896 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1897 {
1898         struct myri10ge_priv *mgp = netdev_priv(netdev);
1899         return mgp->msg_enable;
1900 }
1901
1902 static int myri10ge_set_flags(struct net_device *netdev, u32 value)
1903 {
1904         return ethtool_op_set_flags(netdev, value, ETH_FLAG_LRO);
1905 }
1906
1907 static const struct ethtool_ops myri10ge_ethtool_ops = {
1908         .get_settings = myri10ge_get_settings,
1909         .get_drvinfo = myri10ge_get_drvinfo,
1910         .get_coalesce = myri10ge_get_coalesce,
1911         .set_coalesce = myri10ge_set_coalesce,
1912         .get_pauseparam = myri10ge_get_pauseparam,
1913         .set_pauseparam = myri10ge_set_pauseparam,
1914         .get_ringparam = myri10ge_get_ringparam,
1915         .get_rx_csum = myri10ge_get_rx_csum,
1916         .set_rx_csum = myri10ge_set_rx_csum,
1917         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1918         .set_sg = ethtool_op_set_sg,
1919         .set_tso = myri10ge_set_tso,
1920         .get_link = ethtool_op_get_link,
1921         .get_strings = myri10ge_get_strings,
1922         .get_sset_count = myri10ge_get_sset_count,
1923         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1924         .set_msglevel = myri10ge_set_msglevel,
1925         .get_msglevel = myri10ge_get_msglevel,
1926         .get_flags = ethtool_op_get_flags,
1927         .set_flags = myri10ge_set_flags
1928 };
1929
1930 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1931 {
1932         struct myri10ge_priv *mgp = ss->mgp;
1933         struct myri10ge_cmd cmd;
1934         struct net_device *dev = mgp->dev;
1935         int tx_ring_size, rx_ring_size;
1936         int tx_ring_entries, rx_ring_entries;
1937         int i, slice, status;
1938         size_t bytes;
1939
1940         /* get ring sizes */
1941         slice = ss - mgp->ss;
1942         cmd.data0 = slice;
1943         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1944         tx_ring_size = cmd.data0;
1945         cmd.data0 = slice;
1946         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1947         if (status != 0)
1948                 return status;
1949         rx_ring_size = cmd.data0;
1950
1951         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1952         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1953         ss->tx.mask = tx_ring_entries - 1;
1954         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1955
1956         status = -ENOMEM;
1957
1958         /* allocate the host shadow rings */
1959
1960         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1961             * sizeof(*ss->tx.req_list);
1962         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1963         if (ss->tx.req_bytes == NULL)
1964                 goto abort_with_nothing;
1965
1966         /* ensure req_list entries are aligned to 8 bytes */
1967         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1968             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1969         ss->tx.queue_active = 0;
1970
1971         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1972         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1973         if (ss->rx_small.shadow == NULL)
1974                 goto abort_with_tx_req_bytes;
1975
1976         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1977         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1978         if (ss->rx_big.shadow == NULL)
1979                 goto abort_with_rx_small_shadow;
1980
1981         /* allocate the host info rings */
1982
1983         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1984         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1985         if (ss->tx.info == NULL)
1986                 goto abort_with_rx_big_shadow;
1987
1988         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1989         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1990         if (ss->rx_small.info == NULL)
1991                 goto abort_with_tx_info;
1992
1993         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1994         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1995         if (ss->rx_big.info == NULL)
1996                 goto abort_with_rx_small_info;
1997
1998         /* Fill the receive rings */
1999         ss->rx_big.cnt = 0;
2000         ss->rx_small.cnt = 0;
2001         ss->rx_big.fill_cnt = 0;
2002         ss->rx_small.fill_cnt = 0;
2003         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2004         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2005         ss->rx_small.watchdog_needed = 0;
2006         ss->rx_big.watchdog_needed = 0;
2007         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2008                                 mgp->small_bytes + MXGEFW_PAD, 0);
2009
2010         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
2011                 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2012                            slice, ss->rx_small.fill_cnt);
2013                 goto abort_with_rx_small_ring;
2014         }
2015
2016         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2017         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2018                 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2019                            slice, ss->rx_big.fill_cnt);
2020                 goto abort_with_rx_big_ring;
2021         }
2022
2023         return 0;
2024
2025 abort_with_rx_big_ring:
2026         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2027                 int idx = i & ss->rx_big.mask;
2028                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2029                                        mgp->big_bytes);
2030                 put_page(ss->rx_big.info[idx].page);
2031         }
2032
2033 abort_with_rx_small_ring:
2034         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2035                 int idx = i & ss->rx_small.mask;
2036                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2037                                        mgp->small_bytes + MXGEFW_PAD);
2038                 put_page(ss->rx_small.info[idx].page);
2039         }
2040
2041         kfree(ss->rx_big.info);
2042
2043 abort_with_rx_small_info:
2044         kfree(ss->rx_small.info);
2045
2046 abort_with_tx_info:
2047         kfree(ss->tx.info);
2048
2049 abort_with_rx_big_shadow:
2050         kfree(ss->rx_big.shadow);
2051
2052 abort_with_rx_small_shadow:
2053         kfree(ss->rx_small.shadow);
2054
2055 abort_with_tx_req_bytes:
2056         kfree(ss->tx.req_bytes);
2057         ss->tx.req_bytes = NULL;
2058         ss->tx.req_list = NULL;
2059
2060 abort_with_nothing:
2061         return status;
2062 }
2063
2064 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2065 {
2066         struct myri10ge_priv *mgp = ss->mgp;
2067         struct sk_buff *skb;
2068         struct myri10ge_tx_buf *tx;
2069         int i, len, idx;
2070
2071         /* If not allocated, skip it */
2072         if (ss->tx.req_list == NULL)
2073                 return;
2074
2075         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2076                 idx = i & ss->rx_big.mask;
2077                 if (i == ss->rx_big.fill_cnt - 1)
2078                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2079                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2080                                        mgp->big_bytes);
2081                 put_page(ss->rx_big.info[idx].page);
2082         }
2083
2084         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2085                 idx = i & ss->rx_small.mask;
2086                 if (i == ss->rx_small.fill_cnt - 1)
2087                         ss->rx_small.info[idx].page_offset =
2088                             MYRI10GE_ALLOC_SIZE;
2089                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2090                                        mgp->small_bytes + MXGEFW_PAD);
2091                 put_page(ss->rx_small.info[idx].page);
2092         }
2093         tx = &ss->tx;
2094         while (tx->done != tx->req) {
2095                 idx = tx->done & tx->mask;
2096                 skb = tx->info[idx].skb;
2097
2098                 /* Mark as free */
2099                 tx->info[idx].skb = NULL;
2100                 tx->done++;
2101                 len = dma_unmap_len(&tx->info[idx], len);
2102                 dma_unmap_len_set(&tx->info[idx], len, 0);
2103                 if (skb) {
2104                         ss->stats.tx_dropped++;
2105                         dev_kfree_skb_any(skb);
2106                         if (len)
2107                                 pci_unmap_single(mgp->pdev,
2108                                                  dma_unmap_addr(&tx->info[idx],
2109                                                                 bus), len,
2110                                                  PCI_DMA_TODEVICE);
2111                 } else {
2112                         if (len)
2113                                 pci_unmap_page(mgp->pdev,
2114                                                dma_unmap_addr(&tx->info[idx],
2115                                                               bus), len,
2116                                                PCI_DMA_TODEVICE);
2117                 }
2118         }
2119         kfree(ss->rx_big.info);
2120
2121         kfree(ss->rx_small.info);
2122
2123         kfree(ss->tx.info);
2124
2125         kfree(ss->rx_big.shadow);
2126
2127         kfree(ss->rx_small.shadow);
2128
2129         kfree(ss->tx.req_bytes);
2130         ss->tx.req_bytes = NULL;
2131         ss->tx.req_list = NULL;
2132 }
2133
2134 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2135 {
2136         struct pci_dev *pdev = mgp->pdev;
2137         struct myri10ge_slice_state *ss;
2138         struct net_device *netdev = mgp->dev;
2139         int i;
2140         int status;
2141
2142         mgp->msi_enabled = 0;
2143         mgp->msix_enabled = 0;
2144         status = 0;
2145         if (myri10ge_msi) {
2146                 if (mgp->num_slices > 1) {
2147                         status =
2148                             pci_enable_msix(pdev, mgp->msix_vectors,
2149                                             mgp->num_slices);
2150                         if (status == 0) {
2151                                 mgp->msix_enabled = 1;
2152                         } else {
2153                                 dev_err(&pdev->dev,
2154                                         "Error %d setting up MSI-X\n", status);
2155                                 return status;
2156                         }
2157                 }
2158                 if (mgp->msix_enabled == 0) {
2159                         status = pci_enable_msi(pdev);
2160                         if (status != 0) {
2161                                 dev_err(&pdev->dev,
2162                                         "Error %d setting up MSI; falling back to xPIC\n",
2163                                         status);
2164                         } else {
2165                                 mgp->msi_enabled = 1;
2166                         }
2167                 }
2168         }
2169         if (mgp->msix_enabled) {
2170                 for (i = 0; i < mgp->num_slices; i++) {
2171                         ss = &mgp->ss[i];
2172                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2173                                  "%s:slice-%d", netdev->name, i);
2174                         status = request_irq(mgp->msix_vectors[i].vector,
2175                                              myri10ge_intr, 0, ss->irq_desc,
2176                                              ss);
2177                         if (status != 0) {
2178                                 dev_err(&pdev->dev,
2179                                         "slice %d failed to allocate IRQ\n", i);
2180                                 i--;
2181                                 while (i >= 0) {
2182                                         free_irq(mgp->msix_vectors[i].vector,
2183                                                  &mgp->ss[i]);
2184                                         i--;
2185                                 }
2186                                 pci_disable_msix(pdev);
2187                                 return status;
2188                         }
2189                 }
2190         } else {
2191                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2192                                      mgp->dev->name, &mgp->ss[0]);
2193                 if (status != 0) {
2194                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2195                         if (mgp->msi_enabled)
2196                                 pci_disable_msi(pdev);
2197                 }
2198         }
2199         return status;
2200 }
2201
2202 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2203 {
2204         struct pci_dev *pdev = mgp->pdev;
2205         int i;
2206
2207         if (mgp->msix_enabled) {
2208                 for (i = 0; i < mgp->num_slices; i++)
2209                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2210         } else {
2211                 free_irq(pdev->irq, &mgp->ss[0]);
2212         }
2213         if (mgp->msi_enabled)
2214                 pci_disable_msi(pdev);
2215         if (mgp->msix_enabled)
2216                 pci_disable_msix(pdev);
2217 }
2218
2219 static int
2220 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2221                          void **ip_hdr, void **tcpudp_hdr,
2222                          u64 * hdr_flags, void *priv)
2223 {
2224         struct ethhdr *eh;
2225         struct vlan_ethhdr *veh;
2226         struct iphdr *iph;
2227         u8 *va = page_address(frag->page) + frag->page_offset;
2228         unsigned long ll_hlen;
2229         /* passed opaque through lro_receive_frags() */
2230         __wsum csum = (__force __wsum) (unsigned long)priv;
2231
2232         /* find the mac header, aborting if not IPv4 */
2233
2234         eh = (struct ethhdr *)va;
2235         *mac_hdr = eh;
2236         ll_hlen = ETH_HLEN;
2237         if (eh->h_proto != htons(ETH_P_IP)) {
2238                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2239                         veh = (struct vlan_ethhdr *)va;
2240                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2241                                 return -1;
2242
2243                         ll_hlen += VLAN_HLEN;
2244
2245                         /*
2246                          *  HW checksum starts ETH_HLEN bytes into
2247                          *  frame, so we must subtract off the VLAN
2248                          *  header's checksum before csum can be used
2249                          */
2250                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2251                                                            VLAN_HLEN, 0));
2252                 } else {
2253                         return -1;
2254                 }
2255         }
2256         *hdr_flags = LRO_IPV4;
2257
2258         iph = (struct iphdr *)(va + ll_hlen);
2259         *ip_hdr = iph;
2260         if (iph->protocol != IPPROTO_TCP)
2261                 return -1;
2262         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2263                 return -1;
2264         *hdr_flags |= LRO_TCP;
2265         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2266
2267         /* verify the IP checksum */
2268         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2269                 return -1;
2270
2271         /* verify the  checksum */
2272         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2273                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2274                                        IPPROTO_TCP, csum)))
2275                 return -1;
2276
2277         return 0;
2278 }
2279
2280 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2281 {
2282         struct myri10ge_cmd cmd;
2283         struct myri10ge_slice_state *ss;
2284         int status;
2285
2286         ss = &mgp->ss[slice];
2287         status = 0;
2288         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2289                 cmd.data0 = slice;
2290                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2291                                            &cmd, 0);
2292                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2293                     (mgp->sram + cmd.data0);
2294         }
2295         cmd.data0 = slice;
2296         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2297                                     &cmd, 0);
2298         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2299             (mgp->sram + cmd.data0);
2300
2301         cmd.data0 = slice;
2302         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2303         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2304             (mgp->sram + cmd.data0);
2305
2306         ss->tx.send_go = (__iomem __be32 *)
2307             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2308         ss->tx.send_stop = (__iomem __be32 *)
2309             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2310         return status;
2311
2312 }
2313
2314 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2315 {
2316         struct myri10ge_cmd cmd;
2317         struct myri10ge_slice_state *ss;
2318         int status;
2319
2320         ss = &mgp->ss[slice];
2321         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2322         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2323         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2324         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2325         if (status == -ENOSYS) {
2326                 dma_addr_t bus = ss->fw_stats_bus;
2327                 if (slice != 0)
2328                         return -EINVAL;
2329                 bus += offsetof(struct mcp_irq_data, send_done_count);
2330                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2331                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2332                 status = myri10ge_send_cmd(mgp,
2333                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2334                                            &cmd, 0);
2335                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2336                 mgp->fw_multicast_support = 0;
2337         } else {
2338                 mgp->fw_multicast_support = 1;
2339         }
2340         return 0;
2341 }
2342
2343 static int myri10ge_open(struct net_device *dev)
2344 {
2345         struct myri10ge_slice_state *ss;
2346         struct myri10ge_priv *mgp = netdev_priv(dev);
2347         struct myri10ge_cmd cmd;
2348         int i, status, big_pow2, slice;
2349         u8 *itable;
2350         struct net_lro_mgr *lro_mgr;
2351
2352         if (mgp->running != MYRI10GE_ETH_STOPPED)
2353                 return -EBUSY;
2354
2355         mgp->running = MYRI10GE_ETH_STARTING;
2356         status = myri10ge_reset(mgp);
2357         if (status != 0) {
2358                 netdev_err(dev, "failed reset\n");
2359                 goto abort_with_nothing;
2360         }
2361
2362         if (mgp->num_slices > 1) {
2363                 cmd.data0 = mgp->num_slices;
2364                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2365                 if (mgp->dev->real_num_tx_queues > 1)
2366                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2367                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2368                                            &cmd, 0);
2369                 if (status != 0) {
2370                         netdev_err(dev, "failed to set number of slices\n");
2371                         goto abort_with_nothing;
2372                 }
2373                 /* setup the indirection table */
2374                 cmd.data0 = mgp->num_slices;
2375                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2376                                            &cmd, 0);
2377
2378                 status |= myri10ge_send_cmd(mgp,
2379                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2380                                             &cmd, 0);
2381                 if (status != 0) {
2382                         netdev_err(dev, "failed to setup rss tables\n");
2383                         goto abort_with_nothing;
2384                 }
2385
2386                 /* just enable an identity mapping */
2387                 itable = mgp->sram + cmd.data0;
2388                 for (i = 0; i < mgp->num_slices; i++)
2389                         __raw_writeb(i, &itable[i]);
2390
2391                 cmd.data0 = 1;
2392                 cmd.data1 = myri10ge_rss_hash;
2393                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2394                                            &cmd, 0);
2395                 if (status != 0) {
2396                         netdev_err(dev, "failed to enable slices\n");
2397                         goto abort_with_nothing;
2398                 }
2399         }
2400
2401         status = myri10ge_request_irq(mgp);
2402         if (status != 0)
2403                 goto abort_with_nothing;
2404
2405         /* decide what small buffer size to use.  For good TCP rx
2406          * performance, it is important to not receive 1514 byte
2407          * frames into jumbo buffers, as it confuses the socket buffer
2408          * accounting code, leading to drops and erratic performance.
2409          */
2410
2411         if (dev->mtu <= ETH_DATA_LEN)
2412                 /* enough for a TCP header */
2413                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2414                     ? (128 - MXGEFW_PAD)
2415                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2416         else
2417                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2418                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2419
2420         /* Override the small buffer size? */
2421         if (myri10ge_small_bytes > 0)
2422                 mgp->small_bytes = myri10ge_small_bytes;
2423
2424         /* Firmware needs the big buff size as a power of 2.  Lie and
2425          * tell him the buffer is larger, because we only use 1
2426          * buffer/pkt, and the mtu will prevent overruns.
2427          */
2428         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2429         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2430                 while (!is_power_of_2(big_pow2))
2431                         big_pow2++;
2432                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2433         } else {
2434                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2435                 mgp->big_bytes = big_pow2;
2436         }
2437
2438         /* setup the per-slice data structures */
2439         for (slice = 0; slice < mgp->num_slices; slice++) {
2440                 ss = &mgp->ss[slice];
2441
2442                 status = myri10ge_get_txrx(mgp, slice);
2443                 if (status != 0) {
2444                         netdev_err(dev, "failed to get ring sizes or locations\n");
2445                         goto abort_with_rings;
2446                 }
2447                 status = myri10ge_allocate_rings(ss);
2448                 if (status != 0)
2449                         goto abort_with_rings;
2450
2451                 /* only firmware which supports multiple TX queues
2452                  * supports setting up the tx stats on non-zero
2453                  * slices */
2454                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2455                         status = myri10ge_set_stats(mgp, slice);
2456                 if (status) {
2457                         netdev_err(dev, "Couldn't set stats DMA\n");
2458                         goto abort_with_rings;
2459                 }
2460
2461                 lro_mgr = &ss->rx_done.lro_mgr;
2462                 lro_mgr->dev = dev;
2463                 lro_mgr->features = LRO_F_NAPI;
2464                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2465                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2466                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2467                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2468                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2469                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2470                 lro_mgr->frag_align_pad = 2;
2471                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2472                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2473
2474                 /* must happen prior to any irq */
2475                 napi_enable(&(ss)->napi);
2476         }
2477
2478         /* now give firmware buffers sizes, and MTU */
2479         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2480         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2481         cmd.data0 = mgp->small_bytes;
2482         status |=
2483             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2484         cmd.data0 = big_pow2;
2485         status |=
2486             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2487         if (status) {
2488                 netdev_err(dev, "Couldn't set buffer sizes\n");
2489                 goto abort_with_rings;
2490         }
2491
2492         /*
2493          * Set Linux style TSO mode; this is needed only on newer
2494          *  firmware versions.  Older versions default to Linux
2495          *  style TSO
2496          */
2497         cmd.data0 = 0;
2498         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2499         if (status && status != -ENOSYS) {
2500                 netdev_err(dev, "Couldn't set TSO mode\n");
2501                 goto abort_with_rings;
2502         }
2503
2504         mgp->link_state = ~0U;
2505         mgp->rdma_tags_available = 15;
2506
2507         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2508         if (status) {
2509                 netdev_err(dev, "Couldn't bring up link\n");
2510                 goto abort_with_rings;
2511         }
2512
2513         mgp->running = MYRI10GE_ETH_RUNNING;
2514         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2515         add_timer(&mgp->watchdog_timer);
2516         netif_tx_wake_all_queues(dev);
2517
2518         return 0;
2519
2520 abort_with_rings:
2521         while (slice) {
2522                 slice--;
2523                 napi_disable(&mgp->ss[slice].napi);
2524         }
2525         for (i = 0; i < mgp->num_slices; i++)
2526                 myri10ge_free_rings(&mgp->ss[i]);
2527
2528         myri10ge_free_irq(mgp);
2529
2530 abort_with_nothing:
2531         mgp->running = MYRI10GE_ETH_STOPPED;
2532         return -ENOMEM;
2533 }
2534
2535 static int myri10ge_close(struct net_device *dev)
2536 {
2537         struct myri10ge_priv *mgp = netdev_priv(dev);
2538         struct myri10ge_cmd cmd;
2539         int status, old_down_cnt;
2540         int i;
2541
2542         if (mgp->running != MYRI10GE_ETH_RUNNING)
2543                 return 0;
2544
2545         if (mgp->ss[0].tx.req_bytes == NULL)
2546                 return 0;
2547
2548         del_timer_sync(&mgp->watchdog_timer);
2549         mgp->running = MYRI10GE_ETH_STOPPING;
2550         for (i = 0; i < mgp->num_slices; i++) {
2551                 napi_disable(&mgp->ss[i].napi);
2552         }
2553         netif_carrier_off(dev);
2554
2555         netif_tx_stop_all_queues(dev);
2556         if (mgp->rebooted == 0) {
2557                 old_down_cnt = mgp->down_cnt;
2558                 mb();
2559                 status =
2560                     myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2561                 if (status)
2562                         netdev_err(dev, "Couldn't bring down link\n");
2563
2564                 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2565                                    HZ);
2566                 if (old_down_cnt == mgp->down_cnt)
2567                         netdev_err(dev, "never got down irq\n");
2568         }
2569         netif_tx_disable(dev);
2570         myri10ge_free_irq(mgp);
2571         for (i = 0; i < mgp->num_slices; i++)
2572                 myri10ge_free_rings(&mgp->ss[i]);
2573
2574         mgp->running = MYRI10GE_ETH_STOPPED;
2575         return 0;
2576 }
2577
2578 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2579  * backwards one at a time and handle ring wraps */
2580
2581 static inline void
2582 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2583                               struct mcp_kreq_ether_send *src, int cnt)
2584 {
2585         int idx, starting_slot;
2586         starting_slot = tx->req;
2587         while (cnt > 1) {
2588                 cnt--;
2589                 idx = (starting_slot + cnt) & tx->mask;
2590                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2591                 mb();
2592         }
2593 }
2594
2595 /*
2596  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2597  * at most 32 bytes at a time, so as to avoid involving the software
2598  * pio handler in the nic.   We re-write the first segment's flags
2599  * to mark them valid only after writing the entire chain.
2600  */
2601
2602 static inline void
2603 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2604                     int cnt)
2605 {
2606         int idx, i;
2607         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2608         struct mcp_kreq_ether_send *srcp;
2609         u8 last_flags;
2610
2611         idx = tx->req & tx->mask;
2612
2613         last_flags = src->flags;
2614         src->flags = 0;
2615         mb();
2616         dst = dstp = &tx->lanai[idx];
2617         srcp = src;
2618
2619         if ((idx + cnt) < tx->mask) {
2620                 for (i = 0; i < (cnt - 1); i += 2) {
2621                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2622                         mb();   /* force write every 32 bytes */
2623                         srcp += 2;
2624                         dstp += 2;
2625                 }
2626         } else {
2627                 /* submit all but the first request, and ensure
2628                  * that it is submitted below */
2629                 myri10ge_submit_req_backwards(tx, src, cnt);
2630                 i = 0;
2631         }
2632         if (i < cnt) {
2633                 /* submit the first request */
2634                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2635                 mb();           /* barrier before setting valid flag */
2636         }
2637
2638         /* re-write the last 32-bits with the valid flags */
2639         src->flags = last_flags;
2640         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2641         tx->req += cnt;
2642         mb();
2643 }
2644
2645 /*
2646  * Transmit a packet.  We need to split the packet so that a single
2647  * segment does not cross myri10ge->tx_boundary, so this makes segment
2648  * counting tricky.  So rather than try to count segments up front, we
2649  * just give up if there are too few segments to hold a reasonably
2650  * fragmented packet currently available.  If we run
2651  * out of segments while preparing a packet for DMA, we just linearize
2652  * it and try again.
2653  */
2654
2655 static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2656                                        struct net_device *dev)
2657 {
2658         struct myri10ge_priv *mgp = netdev_priv(dev);
2659         struct myri10ge_slice_state *ss;
2660         struct mcp_kreq_ether_send *req;
2661         struct myri10ge_tx_buf *tx;
2662         struct skb_frag_struct *frag;
2663         struct netdev_queue *netdev_queue;
2664         dma_addr_t bus;
2665         u32 low;
2666         __be32 high_swapped;
2667         unsigned int len;
2668         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2669         u16 pseudo_hdr_offset, cksum_offset, queue;
2670         int cum_len, seglen, boundary, rdma_count;
2671         u8 flags, odd_flag;
2672
2673         queue = skb_get_queue_mapping(skb);
2674         ss = &mgp->ss[queue];
2675         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2676         tx = &ss->tx;
2677
2678 again:
2679         req = tx->req_list;
2680         avail = tx->mask - 1 - (tx->req - tx->done);
2681
2682         mss = 0;
2683         max_segments = MXGEFW_MAX_SEND_DESC;
2684
2685         if (skb_is_gso(skb)) {
2686                 mss = skb_shinfo(skb)->gso_size;
2687                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2688         }
2689
2690         if ((unlikely(avail < max_segments))) {
2691                 /* we are out of transmit resources */
2692                 tx->stop_queue++;
2693                 netif_tx_stop_queue(netdev_queue);
2694                 return NETDEV_TX_BUSY;
2695         }
2696
2697         /* Setup checksum offloading, if needed */
2698         cksum_offset = 0;
2699         pseudo_hdr_offset = 0;
2700         odd_flag = 0;
2701         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2702         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2703                 cksum_offset = skb_transport_offset(skb);
2704                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2705                 /* If the headers are excessively large, then we must
2706                  * fall back to a software checksum */
2707                 if (unlikely(!mss && (cksum_offset > 255 ||
2708                                       pseudo_hdr_offset > 127))) {
2709                         if (skb_checksum_help(skb))
2710                                 goto drop;
2711                         cksum_offset = 0;
2712                         pseudo_hdr_offset = 0;
2713                 } else {
2714                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2715                         flags |= MXGEFW_FLAGS_CKSUM;
2716                 }
2717         }
2718
2719         cum_len = 0;
2720
2721         if (mss) {              /* TSO */
2722                 /* this removes any CKSUM flag from before */
2723                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2724
2725                 /* negative cum_len signifies to the
2726                  * send loop that we are still in the
2727                  * header portion of the TSO packet.
2728                  * TSO header can be at most 1KB long */
2729                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2730
2731                 /* for IPv6 TSO, the checksum offset stores the
2732                  * TCP header length, to save the firmware from
2733                  * the need to parse the headers */
2734                 if (skb_is_gso_v6(skb)) {
2735                         cksum_offset = tcp_hdrlen(skb);
2736                         /* Can only handle headers <= max_tso6 long */
2737                         if (unlikely(-cum_len > mgp->max_tso6))
2738                                 return myri10ge_sw_tso(skb, dev);
2739                 }
2740                 /* for TSO, pseudo_hdr_offset holds mss.
2741                  * The firmware figures out where to put
2742                  * the checksum by parsing the header. */
2743                 pseudo_hdr_offset = mss;
2744         } else
2745                 /* Mark small packets, and pad out tiny packets */
2746         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2747                 flags |= MXGEFW_FLAGS_SMALL;
2748
2749                 /* pad frames to at least ETH_ZLEN bytes */
2750                 if (unlikely(skb->len < ETH_ZLEN)) {
2751                         if (skb_padto(skb, ETH_ZLEN)) {
2752                                 /* The packet is gone, so we must
2753                                  * return 0 */
2754                                 ss->stats.tx_dropped += 1;
2755                                 return NETDEV_TX_OK;
2756                         }
2757                         /* adjust the len to account for the zero pad
2758                          * so that the nic can know how long it is */
2759                         skb->len = ETH_ZLEN;
2760                 }
2761         }
2762
2763         /* map the skb for DMA */
2764         len = skb_headlen(skb);
2765         idx = tx->req & tx->mask;
2766         tx->info[idx].skb = skb;
2767         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2768         dma_unmap_addr_set(&tx->info[idx], bus, bus);
2769         dma_unmap_len_set(&tx->info[idx], len, len);
2770
2771         frag_cnt = skb_shinfo(skb)->nr_frags;
2772         frag_idx = 0;
2773         count = 0;
2774         rdma_count = 0;
2775
2776         /* "rdma_count" is the number of RDMAs belonging to the
2777          * current packet BEFORE the current send request. For
2778          * non-TSO packets, this is equal to "count".
2779          * For TSO packets, rdma_count needs to be reset
2780          * to 0 after a segment cut.
2781          *
2782          * The rdma_count field of the send request is
2783          * the number of RDMAs of the packet starting at
2784          * that request. For TSO send requests with one ore more cuts
2785          * in the middle, this is the number of RDMAs starting
2786          * after the last cut in the request. All previous
2787          * segments before the last cut implicitly have 1 RDMA.
2788          *
2789          * Since the number of RDMAs is not known beforehand,
2790          * it must be filled-in retroactively - after each
2791          * segmentation cut or at the end of the entire packet.
2792          */
2793
2794         while (1) {
2795                 /* Break the SKB or Fragment up into pieces which
2796                  * do not cross mgp->tx_boundary */
2797                 low = MYRI10GE_LOWPART_TO_U32(bus);
2798                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2799                 while (len) {
2800                         u8 flags_next;
2801                         int cum_len_next;
2802
2803                         if (unlikely(count == max_segments))
2804                                 goto abort_linearize;
2805
2806                         boundary =
2807                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2808                         seglen = boundary - low;
2809                         if (seglen > len)
2810                                 seglen = len;
2811                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2812                         cum_len_next = cum_len + seglen;
2813                         if (mss) {      /* TSO */
2814                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2815
2816                                 if (likely(cum_len >= 0)) {     /* payload */
2817                                         int next_is_first, chop;
2818
2819                                         chop = (cum_len_next > mss);
2820                                         cum_len_next = cum_len_next % mss;
2821                                         next_is_first = (cum_len_next == 0);
2822                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2823                                         flags_next |= next_is_first *
2824                                             MXGEFW_FLAGS_FIRST;
2825                                         rdma_count |= -(chop | next_is_first);
2826                                         rdma_count += chop & !next_is_first;
2827                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2828                                         int small;
2829
2830                                         rdma_count = -1;
2831                                         cum_len_next = 0;
2832                                         seglen = -cum_len;
2833                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2834                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2835                                             MXGEFW_FLAGS_FIRST |
2836                                             (small * MXGEFW_FLAGS_SMALL);
2837                                 }
2838                         }
2839                         req->addr_high = high_swapped;
2840                         req->addr_low = htonl(low);
2841                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2842                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2843                         req->rdma_count = 1;
2844                         req->length = htons(seglen);
2845                         req->cksum_offset = cksum_offset;
2846                         req->flags = flags | ((cum_len & 1) * odd_flag);
2847
2848                         low += seglen;
2849                         len -= seglen;
2850                         cum_len = cum_len_next;
2851                         flags = flags_next;
2852                         req++;
2853                         count++;
2854                         rdma_count++;
2855                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2856                                 if (unlikely(cksum_offset > seglen))
2857                                         cksum_offset -= seglen;
2858                                 else
2859                                         cksum_offset = 0;
2860                         }
2861                 }
2862                 if (frag_idx == frag_cnt)
2863                         break;
2864
2865                 /* map next fragment for DMA */
2866                 idx = (count + tx->req) & tx->mask;
2867                 frag = &skb_shinfo(skb)->frags[frag_idx];
2868                 frag_idx++;
2869                 len = frag->size;
2870                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2871                                    len, PCI_DMA_TODEVICE);
2872                 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2873                 dma_unmap_len_set(&tx->info[idx], len, len);
2874         }
2875
2876         (req - rdma_count)->rdma_count = rdma_count;
2877         if (mss)
2878                 do {
2879                         req--;
2880                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2881                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2882                                          MXGEFW_FLAGS_FIRST)));
2883         idx = ((count - 1) + tx->req) & tx->mask;
2884         tx->info[idx].last = 1;
2885         myri10ge_submit_req(tx, tx->req_list, count);
2886         /* if using multiple tx queues, make sure NIC polls the
2887          * current slice */
2888         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2889                 tx->queue_active = 1;
2890                 put_be32(htonl(1), tx->send_go);
2891                 mb();
2892                 mmiowb();
2893         }
2894         tx->pkt_start++;
2895         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2896                 tx->stop_queue++;
2897                 netif_tx_stop_queue(netdev_queue);
2898         }
2899         return NETDEV_TX_OK;
2900
2901 abort_linearize:
2902         /* Free any DMA resources we've alloced and clear out the skb
2903          * slot so as to not trip up assertions, and to avoid a
2904          * double-free if linearizing fails */
2905
2906         last_idx = (idx + 1) & tx->mask;
2907         idx = tx->req & tx->mask;
2908         tx->info[idx].skb = NULL;
2909         do {
2910                 len = dma_unmap_len(&tx->info[idx], len);
2911                 if (len) {
2912                         if (tx->info[idx].skb != NULL)
2913                                 pci_unmap_single(mgp->pdev,
2914                                                  dma_unmap_addr(&tx->info[idx],
2915                                                                 bus), len,
2916                                                  PCI_DMA_TODEVICE);
2917                         else
2918                                 pci_unmap_page(mgp->pdev,
2919                                                dma_unmap_addr(&tx->info[idx],
2920                                                               bus), len,
2921                                                PCI_DMA_TODEVICE);
2922                         dma_unmap_len_set(&tx->info[idx], len, 0);
2923                         tx->info[idx].skb = NULL;
2924                 }
2925                 idx = (idx + 1) & tx->mask;
2926         } while (idx != last_idx);
2927         if (skb_is_gso(skb)) {
2928                 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2929                 goto drop;
2930         }
2931
2932         if (skb_linearize(skb))
2933                 goto drop;
2934
2935         tx->linearized++;
2936         goto again;
2937
2938 drop:
2939         dev_kfree_skb_any(skb);
2940         ss->stats.tx_dropped += 1;
2941         return NETDEV_TX_OK;
2942
2943 }
2944
2945 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2946                                          struct net_device *dev)
2947 {
2948         struct sk_buff *segs, *curr;
2949         struct myri10ge_priv *mgp = netdev_priv(dev);
2950         struct myri10ge_slice_state *ss;
2951         netdev_tx_t status;
2952
2953         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2954         if (IS_ERR(segs))
2955                 goto drop;
2956
2957         while (segs) {
2958                 curr = segs;
2959                 segs = segs->next;
2960                 curr->next = NULL;
2961                 status = myri10ge_xmit(curr, dev);
2962                 if (status != 0) {
2963                         dev_kfree_skb_any(curr);
2964                         if (segs != NULL) {
2965                                 curr = segs;
2966                                 segs = segs->next;
2967                                 curr->next = NULL;
2968                                 dev_kfree_skb_any(segs);
2969                         }
2970                         goto drop;
2971                 }
2972         }
2973         dev_kfree_skb_any(skb);
2974         return NETDEV_TX_OK;
2975
2976 drop:
2977         ss = &mgp->ss[skb_get_queue_mapping(skb)];
2978         dev_kfree_skb_any(skb);
2979         ss->stats.tx_dropped += 1;
2980         return NETDEV_TX_OK;
2981 }
2982
2983 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2984 {
2985         struct myri10ge_priv *mgp = netdev_priv(dev);
2986         struct myri10ge_slice_netstats *slice_stats;
2987         struct net_device_stats *stats = &dev->stats;
2988         int i;
2989
2990         spin_lock(&mgp->stats_lock);
2991         memset(stats, 0, sizeof(*stats));
2992         for (i = 0; i < mgp->num_slices; i++) {
2993                 slice_stats = &mgp->ss[i].stats;
2994                 stats->rx_packets += slice_stats->rx_packets;
2995                 stats->tx_packets += slice_stats->tx_packets;
2996                 stats->rx_bytes += slice_stats->rx_bytes;
2997                 stats->tx_bytes += slice_stats->tx_bytes;
2998                 stats->rx_dropped += slice_stats->rx_dropped;
2999                 stats->tx_dropped += slice_stats->tx_dropped;
3000         }
3001         spin_unlock(&mgp->stats_lock);
3002         return stats;
3003 }
3004
3005 static void myri10ge_set_multicast_list(struct net_device *dev)
3006 {
3007         struct myri10ge_priv *mgp = netdev_priv(dev);
3008         struct myri10ge_cmd cmd;
3009         struct netdev_hw_addr *ha;
3010         __be32 data[2] = { 0, 0 };
3011         int err;
3012
3013         /* can be called from atomic contexts,
3014          * pass 1 to force atomicity in myri10ge_send_cmd() */
3015         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3016
3017         /* This firmware is known to not support multicast */
3018         if (!mgp->fw_multicast_support)
3019                 return;
3020
3021         /* Disable multicast filtering */
3022
3023         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3024         if (err != 0) {
3025                 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3026                            err);
3027                 goto abort;
3028         }
3029
3030         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3031                 /* request to disable multicast filtering, so quit here */
3032                 return;
3033         }
3034
3035         /* Flush the filters */
3036
3037         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3038                                 &cmd, 1);
3039         if (err != 0) {
3040                 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3041                            err);
3042                 goto abort;
3043         }
3044
3045         /* Walk the multicast list, and add each address */
3046         netdev_for_each_mc_addr(ha, dev) {
3047                 memcpy(data, &ha->addr, 6);
3048                 cmd.data0 = ntohl(data[0]);
3049                 cmd.data1 = ntohl(data[1]);
3050                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3051                                         &cmd, 1);
3052
3053                 if (err != 0) {
3054                         netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
3055                                    err, ha->addr);
3056                         goto abort;
3057                 }
3058         }
3059         /* Enable multicast filtering */
3060         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3061         if (err != 0) {
3062                 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3063                            err);
3064                 goto abort;
3065         }
3066
3067         return;
3068
3069 abort:
3070         return;
3071 }
3072
3073 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3074 {
3075         struct sockaddr *sa = addr;
3076         struct myri10ge_priv *mgp = netdev_priv(dev);
3077         int status;
3078
3079         if (!is_valid_ether_addr(sa->sa_data))
3080                 return -EADDRNOTAVAIL;
3081
3082         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3083         if (status != 0) {
3084                 netdev_err(dev, "changing mac address failed with %d\n",
3085                            status);
3086                 return status;
3087         }
3088
3089         /* change the dev structure */
3090         memcpy(dev->dev_addr, sa->sa_data, 6);
3091         return 0;
3092 }
3093
3094 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3095 {
3096         struct myri10ge_priv *mgp = netdev_priv(dev);
3097         int error = 0;
3098
3099         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3100                 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
3101                 return -EINVAL;
3102         }
3103         netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
3104         if (mgp->running) {
3105                 /* if we change the mtu on an active device, we must
3106                  * reset the device so the firmware sees the change */
3107                 myri10ge_close(dev);
3108                 dev->mtu = new_mtu;
3109                 myri10ge_open(dev);
3110         } else
3111                 dev->mtu = new_mtu;
3112
3113         return error;
3114 }
3115
3116 /*
3117  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3118  * Only do it if the bridge is a root port since we don't want to disturb
3119  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3120  */
3121
3122 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3123 {
3124         struct pci_dev *bridge = mgp->pdev->bus->self;
3125         struct device *dev = &mgp->pdev->dev;
3126         unsigned cap;
3127         unsigned err_cap;
3128         u16 val;
3129         u8 ext_type;
3130         int ret;
3131
3132         if (!myri10ge_ecrc_enable || !bridge)
3133                 return;
3134
3135         /* check that the bridge is a root port */
3136         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3137         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3138         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3139         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3140                 if (myri10ge_ecrc_enable > 1) {
3141                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3142
3143                         /* Walk the hierarchy up to the root port
3144                          * where ECRC has to be enabled */
3145                         do {
3146                                 prev_bridge = bridge;
3147                                 bridge = bridge->bus->self;
3148                                 if (!bridge || prev_bridge == bridge) {
3149                                         dev_err(dev,
3150                                                 "Failed to find root port"
3151                                                 " to force ECRC\n");
3152                                         return;
3153                                 }
3154                                 cap =
3155                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3156                                 pci_read_config_word(bridge,
3157                                                      cap + PCI_CAP_FLAGS, &val);
3158                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3159                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3160
3161                         dev_info(dev,
3162                                  "Forcing ECRC on non-root port %s"
3163                                  " (enabling on root port %s)\n",
3164                                  pci_name(old_bridge), pci_name(bridge));
3165                 } else {
3166                         dev_err(dev,
3167                                 "Not enabling ECRC on non-root port %s\n",
3168                                 pci_name(bridge));
3169                         return;
3170                 }
3171         }
3172
3173         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3174         if (!cap)
3175                 return;
3176
3177         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3178         if (ret) {
3179                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3180                         pci_name(bridge));
3181                 dev_err(dev, "\t pci=nommconf in use? "
3182                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3183                 return;
3184         }
3185         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3186                 return;
3187
3188         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3189         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3190         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3191 }
3192
3193 /*
3194  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3195  * when the PCI-E Completion packets are aligned on an 8-byte
3196  * boundary.  Some PCI-E chip sets always align Completion packets; on
3197  * the ones that do not, the alignment can be enforced by enabling
3198  * ECRC generation (if supported).
3199  *
3200  * When PCI-E Completion packets are not aligned, it is actually more
3201  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3202  *
3203  * If the driver can neither enable ECRC nor verify that it has
3204  * already been enabled, then it must use a firmware image which works
3205  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3206  * should also ensure that it never gives the device a Read-DMA which is
3207  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3208  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3209  * firmware image, and set tx_boundary to 4KB.
3210  */
3211
3212 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3213 {
3214         struct pci_dev *pdev = mgp->pdev;
3215         struct device *dev = &pdev->dev;
3216         int status;
3217
3218         mgp->tx_boundary = 4096;
3219         /*
3220          * Verify the max read request size was set to 4KB
3221          * before trying the test with 4KB.
3222          */
3223         status = pcie_get_readrq(pdev);
3224         if (status < 0) {
3225                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3226                 goto abort;
3227         }
3228         if (status != 4096) {
3229                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3230                 mgp->tx_boundary = 2048;
3231         }
3232         /*
3233          * load the optimized firmware (which assumes aligned PCIe
3234          * completions) in order to see if it works on this host.
3235          */
3236         mgp->fw_name = myri10ge_fw_aligned;
3237         status = myri10ge_load_firmware(mgp, 1);
3238         if (status != 0) {
3239                 goto abort;
3240         }
3241
3242         /*
3243          * Enable ECRC if possible
3244          */
3245         myri10ge_enable_ecrc(mgp);
3246
3247         /*
3248          * Run a DMA test which watches for unaligned completions and
3249          * aborts on the first one seen.
3250          */
3251
3252         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3253         if (status == 0)
3254                 return;         /* keep the aligned firmware */
3255
3256         if (status != -E2BIG)
3257                 dev_warn(dev, "DMA test failed: %d\n", status);
3258         if (status == -ENOSYS)
3259                 dev_warn(dev, "Falling back to ethp! "
3260                          "Please install up to date fw\n");
3261 abort:
3262         /* fall back to using the unaligned firmware */
3263         mgp->tx_boundary = 2048;
3264         mgp->fw_name = myri10ge_fw_unaligned;
3265
3266 }
3267
3268 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3269 {
3270         int overridden = 0;
3271
3272         if (myri10ge_force_firmware == 0) {
3273                 int link_width, exp_cap;
3274                 u16 lnk;
3275
3276                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3277                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3278                 link_width = (lnk >> 4) & 0x3f;
3279
3280                 /* Check to see if Link is less than 8 or if the
3281                  * upstream bridge is known to provide aligned
3282                  * completions */
3283                 if (link_width < 8) {
3284                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3285                                  link_width);
3286                         mgp->tx_boundary = 4096;
3287                         mgp->fw_name = myri10ge_fw_aligned;
3288                 } else {
3289                         myri10ge_firmware_probe(mgp);
3290                 }
3291         } else {
3292                 if (myri10ge_force_firmware == 1) {
3293                         dev_info(&mgp->pdev->dev,
3294                                  "Assuming aligned completions (forced)\n");
3295                         mgp->tx_boundary = 4096;
3296                         mgp->fw_name = myri10ge_fw_aligned;
3297                 } else {
3298                         dev_info(&mgp->pdev->dev,
3299                                  "Assuming unaligned completions (forced)\n");
3300                         mgp->tx_boundary = 2048;
3301                         mgp->fw_name = myri10ge_fw_unaligned;
3302                 }
3303         }
3304         if (myri10ge_fw_name != NULL) {
3305                 overridden = 1;
3306                 mgp->fw_name = myri10ge_fw_name;
3307         }
3308         if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3309             myri10ge_fw_names[mgp->board_number] != NULL &&
3310             strlen(myri10ge_fw_names[mgp->board_number])) {
3311                 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3312                 overridden = 1;
3313         }
3314         if (overridden)
3315                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3316                          mgp->fw_name);
3317 }
3318
3319 #ifdef CONFIG_PM
3320 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3321 {
3322         struct myri10ge_priv *mgp;
3323         struct net_device *netdev;
3324
3325         mgp = pci_get_drvdata(pdev);
3326         if (mgp == NULL)
3327                 return -EINVAL;
3328         netdev = mgp->dev;
3329
3330         netif_device_detach(netdev);
3331         if (netif_running(netdev)) {
3332                 netdev_info(netdev, "closing\n");
3333                 rtnl_lock();
3334                 myri10ge_close(netdev);
3335                 rtnl_unlock();
3336         }
3337         myri10ge_dummy_rdma(mgp, 0);
3338         pci_save_state(pdev);
3339         pci_disable_device(pdev);
3340
3341         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3342 }
3343
3344 static int myri10ge_resume(struct pci_dev *pdev)
3345 {
3346         struct myri10ge_priv *mgp;
3347         struct net_device *netdev;
3348         int status;
3349         u16 vendor;
3350
3351         mgp = pci_get_drvdata(pdev);
3352         if (mgp == NULL)
3353                 return -EINVAL;
3354         netdev = mgp->dev;
3355         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3356         msleep(5);              /* give card time to respond */
3357         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3358         if (vendor == 0xffff) {
3359                 netdev_err(mgp->dev, "device disappeared!\n");
3360                 return -EIO;
3361         }
3362
3363         status = pci_restore_state(pdev);
3364         if (status)
3365                 return status;
3366
3367         status = pci_enable_device(pdev);
3368         if (status) {
3369                 dev_err(&pdev->dev, "failed to enable device\n");
3370                 return status;
3371         }
3372
3373         pci_set_master(pdev);
3374
3375         myri10ge_reset(mgp);
3376         myri10ge_dummy_rdma(mgp, 1);
3377
3378         /* Save configuration space to be restored if the
3379          * nic resets due to a parity error */
3380         pci_save_state(pdev);
3381
3382         if (netif_running(netdev)) {
3383                 rtnl_lock();
3384                 status = myri10ge_open(netdev);
3385                 rtnl_unlock();
3386                 if (status != 0)
3387                         goto abort_with_enabled;
3388
3389         }
3390         netif_device_attach(netdev);
3391
3392         return 0;
3393
3394 abort_with_enabled:
3395         pci_disable_device(pdev);
3396         return -EIO;
3397
3398 }
3399 #endif                          /* CONFIG_PM */
3400
3401 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3402 {
3403         struct pci_dev *pdev = mgp->pdev;
3404         int vs = mgp->vendor_specific_offset;
3405         u32 reboot;
3406
3407         /*enter read32 mode */
3408         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3409
3410         /*read REBOOT_STATUS (0xfffffff0) */
3411         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3412         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3413         return reboot;
3414 }
3415
3416 /*
3417  * This watchdog is used to check whether the board has suffered
3418  * from a parity error and needs to be recovered.
3419  */
3420 static void myri10ge_watchdog(struct work_struct *work)
3421 {
3422         struct myri10ge_priv *mgp =
3423             container_of(work, struct myri10ge_priv, watchdog_work);
3424         struct myri10ge_tx_buf *tx;
3425         u32 reboot;
3426         int status, rebooted;
3427         int i;
3428         u16 cmd, vendor;
3429
3430         mgp->watchdog_resets++;
3431         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3432         rebooted = 0;
3433         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3434                 /* Bus master DMA disabled?  Check to see
3435                  * if the card rebooted due to a parity error
3436                  * For now, just report it */
3437                 reboot = myri10ge_read_reboot(mgp);
3438                 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3439                            reboot,
3440                            myri10ge_reset_recover ? "" : " not");
3441                 if (myri10ge_reset_recover == 0)
3442                         return;
3443                 rtnl_lock();
3444                 mgp->rebooted = 1;
3445                 rebooted = 1;
3446                 myri10ge_close(mgp->dev);
3447                 myri10ge_reset_recover--;
3448                 mgp->rebooted = 0;
3449                 /*
3450                  * A rebooted nic will come back with config space as
3451                  * it was after power was applied to PCIe bus.
3452                  * Attempt to restore config space which was saved
3453                  * when the driver was loaded, or the last time the
3454                  * nic was resumed from power saving mode.
3455                  */
3456                 pci_restore_state(mgp->pdev);
3457
3458                 /* save state again for accounting reasons */
3459                 pci_save_state(mgp->pdev);
3460
3461         } else {
3462                 /* if we get back -1's from our slot, perhaps somebody
3463                  * powered off our card.  Don't try to reset it in
3464                  * this case */
3465                 if (cmd == 0xffff) {
3466                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3467                         if (vendor == 0xffff) {
3468                                 netdev_err(mgp->dev, "device disappeared!\n");
3469                                 return;
3470                         }
3471                 }
3472                 /* Perhaps it is a software error.  Try to reset */
3473
3474                 netdev_err(mgp->dev, "device timeout, resetting\n");
3475                 for (i = 0; i < mgp->num_slices; i++) {
3476                         tx = &mgp->ss[i].tx;
3477                         netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3478                                    i, tx->queue_active, tx->req,
3479                                    tx->done, tx->pkt_start, tx->pkt_done,
3480                                    (int)ntohl(mgp->ss[i].fw_stats->
3481                                               send_done_count));
3482                         msleep(2000);
3483                         netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3484                                     i, tx->queue_active, tx->req,
3485                                     tx->done, tx->pkt_start, tx->pkt_done,
3486                                     (int)ntohl(mgp->ss[i].fw_stats->
3487                                                send_done_count));
3488                 }
3489         }
3490
3491         if (!rebooted) {
3492                 rtnl_lock();
3493                 myri10ge_close(mgp->dev);
3494         }
3495         status = myri10ge_load_firmware(mgp, 1);
3496         if (status != 0)
3497                 netdev_err(mgp->dev, "failed to load firmware\n");
3498         else
3499                 myri10ge_open(mgp->dev);
3500         rtnl_unlock();
3501 }
3502
3503 /*
3504  * We use our own timer routine rather than relying upon
3505  * netdev->tx_timeout because we have a very large hardware transmit
3506  * queue.  Due to the large queue, the netdev->tx_timeout function
3507  * cannot detect a NIC with a parity error in a timely fashion if the
3508  * NIC is lightly loaded.
3509  */
3510 static void myri10ge_watchdog_timer(unsigned long arg)
3511 {
3512         struct myri10ge_priv *mgp;
3513         struct myri10ge_slice_state *ss;
3514         int i, reset_needed, busy_slice_cnt;
3515         u32 rx_pause_cnt;
3516         u16 cmd;
3517
3518         mgp = (struct myri10ge_priv *)arg;
3519
3520         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3521         busy_slice_cnt = 0;
3522         for (i = 0, reset_needed = 0;
3523              i < mgp->num_slices && reset_needed == 0; ++i) {
3524
3525                 ss = &mgp->ss[i];
3526                 if (ss->rx_small.watchdog_needed) {
3527                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3528                                                 mgp->small_bytes + MXGEFW_PAD,
3529                                                 1);
3530                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3531                             myri10ge_fill_thresh)
3532                                 ss->rx_small.watchdog_needed = 0;
3533                 }
3534                 if (ss->rx_big.watchdog_needed) {
3535                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3536                                                 mgp->big_bytes, 1);
3537                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3538                             myri10ge_fill_thresh)
3539                                 ss->rx_big.watchdog_needed = 0;
3540                 }
3541
3542                 if (ss->tx.req != ss->tx.done &&
3543                     ss->tx.done == ss->watchdog_tx_done &&
3544                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3545                         /* nic seems like it might be stuck.. */
3546                         if (rx_pause_cnt != mgp->watchdog_pause) {
3547                                 if (net_ratelimit())
3548                                         netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3549                                                    i);
3550                         } else {
3551                                 netdev_warn(mgp->dev, "slice %d stuck:", i);
3552                                 reset_needed = 1;
3553                         }
3554                 }
3555                 if (ss->watchdog_tx_done != ss->tx.done ||
3556                     ss->watchdog_rx_done != ss->rx_done.cnt) {
3557                         busy_slice_cnt++;
3558                 }
3559                 ss->watchdog_tx_done = ss->tx.done;
3560                 ss->watchdog_tx_req = ss->tx.req;
3561                 ss->watchdog_rx_done = ss->rx_done.cnt;
3562         }
3563         /* if we've sent or received no traffic, poll the NIC to
3564          * ensure it is still there.  Otherwise, we risk not noticing
3565          * an error in a timely fashion */
3566         if (busy_slice_cnt == 0) {
3567                 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3568                 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3569                         reset_needed = 1;
3570                 }
3571         }
3572         mgp->watchdog_pause = rx_pause_cnt;
3573
3574         if (reset_needed) {
3575                 schedule_work(&mgp->watchdog_work);
3576         } else {
3577                 /* rearm timer */
3578                 mod_timer(&mgp->watchdog_timer,
3579                           jiffies + myri10ge_watchdog_timeout * HZ);
3580         }
3581 }
3582
3583 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3584 {
3585         struct myri10ge_slice_state *ss;
3586         struct pci_dev *pdev = mgp->pdev;
3587         size_t bytes;
3588         int i;
3589
3590         if (mgp->ss == NULL)
3591                 return;
3592
3593         for (i = 0; i < mgp->num_slices; i++) {
3594                 ss = &mgp->ss[i];
3595                 if (ss->rx_done.entry != NULL) {
3596                         bytes = mgp->max_intr_slots *
3597                             sizeof(*ss->rx_done.entry);
3598                         dma_free_coherent(&pdev->dev, bytes,
3599                                           ss->rx_done.entry, ss->rx_done.bus);
3600                         ss->rx_done.entry = NULL;
3601                 }
3602                 if (ss->fw_stats != NULL) {
3603                         bytes = sizeof(*ss->fw_stats);
3604                         dma_free_coherent(&pdev->dev, bytes,
3605                                           ss->fw_stats, ss->fw_stats_bus);
3606                         ss->fw_stats = NULL;
3607                 }
3608         }
3609         kfree(mgp->ss);
3610         mgp->ss = NULL;
3611 }
3612
3613 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3614 {
3615         struct myri10ge_slice_state *ss;
3616         struct pci_dev *pdev = mgp->pdev;
3617         size_t bytes;
3618         int i;
3619
3620         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3621         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3622         if (mgp->ss == NULL) {
3623                 return -ENOMEM;
3624         }
3625
3626         for (i = 0; i < mgp->num_slices; i++) {
3627                 ss = &mgp->ss[i];
3628                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3629                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3630                                                        &ss->rx_done.bus,
3631                                                        GFP_KERNEL);
3632                 if (ss->rx_done.entry == NULL)
3633                         goto abort;
3634                 memset(ss->rx_done.entry, 0, bytes);
3635                 bytes = sizeof(*ss->fw_stats);
3636                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3637                                                   &ss->fw_stats_bus,
3638                                                   GFP_KERNEL);
3639                 if (ss->fw_stats == NULL)
3640                         goto abort;
3641                 ss->mgp = mgp;
3642                 ss->dev = mgp->dev;
3643                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3644                                myri10ge_napi_weight);
3645         }
3646         return 0;
3647 abort:
3648         myri10ge_free_slices(mgp);
3649         return -ENOMEM;
3650 }
3651
3652 /*
3653  * This function determines the number of slices supported.
3654  * The number slices is the minumum of the number of CPUS,
3655  * the number of MSI-X irqs supported, the number of slices
3656  * supported by the firmware
3657  */
3658 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3659 {
3660         struct myri10ge_cmd cmd;
3661         struct pci_dev *pdev = mgp->pdev;
3662         char *old_fw;
3663         int i, status, ncpus, msix_cap;
3664
3665         mgp->num_slices = 1;
3666         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3667         ncpus = num_online_cpus();
3668
3669         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3670             (myri10ge_max_slices == -1 && ncpus < 2))
3671                 return;
3672
3673         /* try to load the slice aware rss firmware */
3674         old_fw = mgp->fw_name;
3675         if (myri10ge_fw_name != NULL) {
3676                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3677                          myri10ge_fw_name);
3678                 mgp->fw_name = myri10ge_fw_name;
3679         } else if (old_fw == myri10ge_fw_aligned)
3680                 mgp->fw_name = myri10ge_fw_rss_aligned;
3681         else
3682                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3683         status = myri10ge_load_firmware(mgp, 0);
3684         if (status != 0) {
3685                 dev_info(&pdev->dev, "Rss firmware not found\n");
3686                 return;
3687         }
3688
3689         /* hit the board with a reset to ensure it is alive */
3690         memset(&cmd, 0, sizeof(cmd));
3691         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3692         if (status != 0) {
3693                 dev_err(&mgp->pdev->dev, "failed reset\n");
3694                 goto abort_with_fw;
3695         }
3696
3697         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3698
3699         /* tell it the size of the interrupt queues */
3700         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3701         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3702         if (status != 0) {
3703                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3704                 goto abort_with_fw;
3705         }
3706
3707         /* ask the maximum number of slices it supports */
3708         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3709         if (status != 0)
3710                 goto abort_with_fw;
3711         else
3712                 mgp->num_slices = cmd.data0;
3713
3714         /* Only allow multiple slices if MSI-X is usable */
3715         if (!myri10ge_msi) {
3716                 goto abort_with_fw;
3717         }
3718
3719         /* if the admin did not specify a limit to how many
3720          * slices we should use, cap it automatically to the
3721          * number of CPUs currently online */
3722         if (myri10ge_max_slices == -1)
3723                 myri10ge_max_slices = ncpus;
3724
3725         if (mgp->num_slices > myri10ge_max_slices)
3726                 mgp->num_slices = myri10ge_max_slices;
3727
3728         /* Now try to allocate as many MSI-X vectors as we have
3729          * slices. We give up on MSI-X if we can only get a single
3730          * vector. */
3731
3732         mgp->msix_vectors = kzalloc(mgp->num_slices *
3733                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3734         if (mgp->msix_vectors == NULL)
3735                 goto disable_msix;
3736         for (i = 0; i < mgp->num_slices; i++) {
3737                 mgp->msix_vectors[i].entry = i;
3738         }
3739
3740         while (mgp->num_slices > 1) {
3741                 /* make sure it is a power of two */
3742                 while (!is_power_of_2(mgp->num_slices))
3743                         mgp->num_slices--;
3744                 if (mgp->num_slices == 1)
3745                         goto disable_msix;
3746                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3747                                          mgp->num_slices);
3748                 if (status == 0) {
3749                         pci_disable_msix(pdev);
3750                         return;
3751                 }
3752                 if (status > 0)
3753                         mgp->num_slices = status;
3754                 else
3755                         goto disable_msix;
3756         }
3757
3758 disable_msix:
3759         if (mgp->msix_vectors != NULL) {
3760                 kfree(mgp->msix_vectors);
3761                 mgp->msix_vectors = NULL;
3762         }
3763
3764 abort_with_fw:
3765         mgp->num_slices = 1;
3766         mgp->fw_name = old_fw;
3767         myri10ge_load_firmware(mgp, 0);
3768 }
3769
3770 static const struct net_device_ops myri10ge_netdev_ops = {
3771         .ndo_open               = myri10ge_open,
3772         .ndo_stop               = myri10ge_close,
3773         .ndo_start_xmit         = myri10ge_xmit,
3774         .ndo_get_stats          = myri10ge_get_stats,
3775         .ndo_validate_addr      = eth_validate_addr,
3776         .ndo_change_mtu         = myri10ge_change_mtu,
3777         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3778         .ndo_set_mac_address    = myri10ge_set_mac_address,
3779 };
3780
3781 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3782 {
3783         struct net_device *netdev;
3784         struct myri10ge_priv *mgp;
3785         struct device *dev = &pdev->dev;
3786         int i;
3787         int status = -ENXIO;
3788         int dac_enabled;
3789         unsigned hdr_offset, ss_offset;
3790         static int board_number;
3791
3792         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3793         if (netdev == NULL) {
3794                 dev_err(dev, "Could not allocate ethernet device\n");
3795                 return -ENOMEM;
3796         }
3797
3798         SET_NETDEV_DEV(netdev, &pdev->dev);
3799
3800         mgp = netdev_priv(netdev);
3801         mgp->dev = netdev;
3802         mgp->pdev = pdev;
3803         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3804         mgp->pause = myri10ge_flow_control;
3805         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3806         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3807         mgp->board_number = board_number;
3808         init_waitqueue_head(&mgp->down_wq);
3809
3810         if (pci_enable_device(pdev)) {
3811                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3812                 status = -ENODEV;
3813                 goto abort_with_netdev;
3814         }
3815
3816         /* Find the vendor-specific cap so we can check
3817          * the reboot register later on */
3818         mgp->vendor_specific_offset
3819             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3820
3821         /* Set our max read request to 4KB */
3822         status = pcie_set_readrq(pdev, 4096);
3823         if (status != 0) {
3824                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3825                         status);
3826                 goto abort_with_enabled;
3827         }
3828
3829         pci_set_master(pdev);
3830         dac_enabled = 1;
3831         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3832         if (status != 0) {
3833                 dac_enabled = 0;
3834                 dev_err(&pdev->dev,
3835                         "64-bit pci address mask was refused, "
3836                         "trying 32-bit\n");
3837                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3838         }
3839         if (status != 0) {
3840                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3841                 goto abort_with_enabled;
3842         }
3843         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3844         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3845                                       &mgp->cmd_bus, GFP_KERNEL);
3846         if (mgp->cmd == NULL)
3847                 goto abort_with_enabled;
3848
3849         mgp->board_span = pci_resource_len(pdev, 0);
3850         mgp->iomem_base = pci_resource_start(pdev, 0);
3851         mgp->mtrr = -1;
3852         mgp->wc_enabled = 0;
3853 #ifdef CONFIG_MTRR
3854         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3855                              MTRR_TYPE_WRCOMB, 1);
3856         if (mgp->mtrr >= 0)
3857                 mgp->wc_enabled = 1;
3858 #endif
3859         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3860         if (mgp->sram == NULL) {
3861                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3862                         mgp->board_span, mgp->iomem_base);
3863                 status = -ENXIO;
3864                 goto abort_with_mtrr;
3865         }
3866         hdr_offset =
3867             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3868         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3869         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3870         if (mgp->sram_size > mgp->board_span ||
3871             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3872                 dev_err(&pdev->dev,
3873                         "invalid sram_size %dB or board span %ldB\n",
3874                         mgp->sram_size, mgp->board_span);
3875                 goto abort_with_ioremap;
3876         }
3877         memcpy_fromio(mgp->eeprom_strings,
3878                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3879         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3880         status = myri10ge_read_mac_addr(mgp);
3881         if (status)
3882                 goto abort_with_ioremap;
3883
3884         for (i = 0; i < ETH_ALEN; i++)
3885                 netdev->dev_addr[i] = mgp->mac_addr[i];
3886
3887         myri10ge_select_firmware(mgp);
3888
3889         status = myri10ge_load_firmware(mgp, 1);
3890         if (status != 0) {
3891                 dev_err(&pdev->dev, "failed to load firmware\n");
3892                 goto abort_with_ioremap;
3893         }
3894         myri10ge_probe_slices(mgp);
3895         status = myri10ge_alloc_slices(mgp);
3896         if (status != 0) {
3897                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3898                 goto abort_with_firmware;
3899         }
3900         netdev->real_num_tx_queues = mgp->num_slices;
3901         status = myri10ge_reset(mgp);
3902         if (status != 0) {
3903                 dev_err(&pdev->dev, "failed reset\n");
3904                 goto abort_with_slices;
3905         }
3906 #ifdef CONFIG_MYRI10GE_DCA
3907         myri10ge_setup_dca(mgp);
3908 #endif
3909         pci_set_drvdata(pdev, mgp);
3910         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3911                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3912         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3913                 myri10ge_initial_mtu = 68;
3914
3915         netdev->netdev_ops = &myri10ge_netdev_ops;
3916         netdev->mtu = myri10ge_initial_mtu;
3917         netdev->base_addr = mgp->iomem_base;
3918         netdev->features = mgp->features;
3919
3920         if (dac_enabled)
3921                 netdev->features |= NETIF_F_HIGHDMA;
3922         netdev->features |= NETIF_F_LRO;
3923
3924         netdev->vlan_features |= mgp->features;
3925         if (mgp->fw_ver_tiny < 37)
3926                 netdev->vlan_features &= ~NETIF_F_TSO6;
3927         if (mgp->fw_ver_tiny < 32)
3928                 netdev->vlan_features &= ~NETIF_F_TSO;
3929
3930         /* make sure we can get an irq, and that MSI can be
3931          * setup (if available).  Also ensure netdev->irq
3932          * is set to correct value if MSI is enabled */
3933         status = myri10ge_request_irq(mgp);
3934         if (status != 0)
3935                 goto abort_with_firmware;
3936         netdev->irq = pdev->irq;
3937         myri10ge_free_irq(mgp);
3938
3939         /* Save configuration space to be restored if the
3940          * nic resets due to a parity error */
3941         pci_save_state(pdev);
3942
3943         /* Setup the watchdog timer */
3944         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3945                     (unsigned long)mgp);
3946
3947         spin_lock_init(&mgp->stats_lock);
3948         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3949         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3950         status = register_netdev(netdev);
3951         if (status != 0) {
3952                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3953                 goto abort_with_state;
3954         }
3955         if (mgp->msix_enabled)
3956                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3957                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3958                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3959         else
3960                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3961                          mgp->msi_enabled ? "MSI" : "xPIC",
3962                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3963                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3964
3965         board_number++;
3966         return 0;
3967
3968 abort_with_state:
3969         pci_restore_state(pdev);
3970
3971 abort_with_slices:
3972         myri10ge_free_slices(mgp);
3973
3974 abort_with_firmware:
3975         myri10ge_dummy_rdma(mgp, 0);
3976
3977 abort_with_ioremap:
3978         if (mgp->mac_addr_string != NULL)
3979                 dev_err(&pdev->dev,
3980                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3981                         mgp->mac_addr_string, mgp->serial_number);
3982         iounmap(mgp->sram);
3983
3984 abort_with_mtrr:
3985 #ifdef CONFIG_MTRR
3986         if (mgp->mtrr >= 0)
3987                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3988 #endif
3989         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3990                           mgp->cmd, mgp->cmd_bus);
3991
3992 abort_with_enabled:
3993         pci_disable_device(pdev);
3994
3995 abort_with_netdev:
3996         free_netdev(netdev);
3997         return status;
3998 }
3999
4000 /*
4001  * myri10ge_remove
4002  *
4003  * Does what is necessary to shutdown one Myrinet device. Called
4004  *   once for each Myrinet card by the kernel when a module is
4005  *   unloaded.
4006  */
4007 static void myri10ge_remove(struct pci_dev *pdev)
4008 {
4009         struct myri10ge_priv *mgp;
4010         struct net_device *netdev;
4011
4012         mgp = pci_get_drvdata(pdev);
4013         if (mgp == NULL)
4014                 return;
4015
4016         flush_scheduled_work();
4017         netdev = mgp->dev;
4018         unregister_netdev(netdev);
4019
4020 #ifdef CONFIG_MYRI10GE_DCA
4021         myri10ge_teardown_dca(mgp);
4022 #endif
4023         myri10ge_dummy_rdma(mgp, 0);
4024
4025         /* avoid a memory leak */
4026         pci_restore_state(pdev);
4027
4028         iounmap(mgp->sram);
4029
4030 #ifdef CONFIG_MTRR
4031         if (mgp->mtrr >= 0)
4032                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4033 #endif
4034         myri10ge_free_slices(mgp);
4035         if (mgp->msix_vectors != NULL)
4036                 kfree(mgp->msix_vectors);
4037         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4038                           mgp->cmd, mgp->cmd_bus);
4039
4040         free_netdev(netdev);
4041         pci_disable_device(pdev);
4042         pci_set_drvdata(pdev, NULL);
4043 }
4044
4045 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4046 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4047
4048 static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
4049         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4050         {PCI_DEVICE
4051          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4052         {0},
4053 };
4054
4055 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4056
4057 static struct pci_driver myri10ge_driver = {
4058         .name = "myri10ge",
4059         .probe = myri10ge_probe,
4060         .remove = myri10ge_remove,
4061         .id_table = myri10ge_pci_tbl,
4062 #ifdef CONFIG_PM
4063         .suspend = myri10ge_suspend,
4064         .resume = myri10ge_resume,
4065 #endif
4066 };
4067
4068 #ifdef CONFIG_MYRI10GE_DCA
4069 static int
4070 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4071 {
4072         int err = driver_for_each_device(&myri10ge_driver.driver,
4073                                          NULL, &event,
4074                                          myri10ge_notify_dca_device);
4075
4076         if (err)
4077                 return NOTIFY_BAD;
4078         return NOTIFY_DONE;
4079 }
4080
4081 static struct notifier_block myri10ge_dca_notifier = {
4082         .notifier_call = myri10ge_notify_dca,
4083         .next = NULL,
4084         .priority = 0,
4085 };
4086 #endif                          /* CONFIG_MYRI10GE_DCA */
4087
4088 static __init int myri10ge_init_module(void)
4089 {
4090         pr_info("Version %s\n", MYRI10GE_VERSION_STR);
4091
4092         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4093                 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4094                        myri10ge_rss_hash);
4095                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4096         }
4097 #ifdef CONFIG_MYRI10GE_DCA
4098         dca_register_notify(&myri10ge_dca_notifier);
4099 #endif
4100         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4101                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4102
4103         return pci_register_driver(&myri10ge_driver);
4104 }
4105
4106 module_init(myri10ge_init_module);
4107
4108 static __exit void myri10ge_cleanup_module(void)
4109 {
4110 #ifdef CONFIG_MYRI10GE_DCA
4111         dca_unregister_notify(&myri10ge_dca_notifier);
4112 #endif
4113         pci_unregister_driver(&myri10ge_driver);
4114 }
4115
4116 module_exit(myri10ge_cleanup_module);