1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
36 * Contact Information:
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
53 #include <linux/inet.h>
55 #include <linux/ethtool.h>
56 #include <linux/firmware.h>
57 #include <linux/delay.h>
58 #include <linux/version.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
68 #include <asm/byteorder.h>
70 #include <asm/processor.h>
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
78 #define MYRI10GE_VERSION_STR "1.3.2-1.287"
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
85 #define MYRI10GE_MAX_ETHER_MTU 9014
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
105 struct myri10ge_rx_buffer_state {
108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
112 struct myri10ge_tx_buffer_state {
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
119 struct myri10ge_cmd {
125 struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
136 int mask; /* number of rx slots -1 */
140 struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
154 struct myri10ge_rx_done {
155 struct mcp_slot *entry;
159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
163 struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
172 struct net_device *dev;
173 struct napi_struct napi;
174 struct net_device_stats stats;
177 unsigned long board_span;
178 unsigned long iomem_base;
179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
189 unsigned int rdma_tags_available;
191 __be32 __iomem *intr_coal_delay_ptr;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char *product_code_string;
209 char fw_version[128];
213 int adopted_rx_filter_bug;
214 u8 mac_addr[6]; /* eeprom mac address */
215 unsigned long serial_number;
216 int vendor_specific_offset;
217 int fw_multicast_support;
218 unsigned long features;
227 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
228 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
230 static char *myri10ge_fw_name = NULL;
231 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
232 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
234 static int myri10ge_ecrc_enable = 1;
235 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
236 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
238 static int myri10ge_max_intr_slots = 1024;
239 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
240 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots");
242 static int myri10ge_small_bytes = -1; /* -1 == auto */
243 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
244 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
246 static int myri10ge_msi = 1; /* enable msi by default */
247 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
248 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
250 static int myri10ge_intr_coal_delay = 75;
251 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
252 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
254 static int myri10ge_flow_control = 1;
255 module_param(myri10ge_flow_control, int, S_IRUGO);
256 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
258 static int myri10ge_deassert_wait = 1;
259 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
260 MODULE_PARM_DESC(myri10ge_deassert_wait,
261 "Wait when deasserting legacy interrupts");
263 static int myri10ge_force_firmware = 0;
264 module_param(myri10ge_force_firmware, int, S_IRUGO);
265 MODULE_PARM_DESC(myri10ge_force_firmware,
266 "Force firmware to assume aligned completions");
268 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
269 module_param(myri10ge_initial_mtu, int, S_IRUGO);
270 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
272 static int myri10ge_napi_weight = 64;
273 module_param(myri10ge_napi_weight, int, S_IRUGO);
274 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
276 static int myri10ge_watchdog_timeout = 1;
277 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
278 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
280 static int myri10ge_max_irq_loops = 1048576;
281 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
282 MODULE_PARM_DESC(myri10ge_max_irq_loops,
283 "Set stuck legacy IRQ detection threshold");
285 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
287 static int myri10ge_debug = -1; /* defaults above */
288 module_param(myri10ge_debug, int, 0);
289 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
291 static int myri10ge_lro = 1;
292 module_param(myri10ge_lro, int, S_IRUGO);
293 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
295 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
296 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
297 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
298 "Number of LRO packets to be aggregated");
300 static int myri10ge_fill_thresh = 256;
301 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
302 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
304 static int myri10ge_reset_recover = 1;
306 static int myri10ge_wcfifo = 0;
307 module_param(myri10ge_wcfifo, int, S_IRUGO);
308 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
310 #define MYRI10GE_FW_OFFSET 1024*1024
311 #define MYRI10GE_HIGHPART_TO_U32(X) \
312 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
313 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
315 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
317 static void myri10ge_set_multicast_list(struct net_device *dev);
318 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
320 static inline void put_be32(__be32 val, __be32 __iomem * p)
322 __raw_writel((__force __u32) val, (__force void __iomem *)p);
326 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
327 struct myri10ge_cmd *data, int atomic)
330 char buf_bytes[sizeof(*buf) + 8];
331 struct mcp_cmd_response *response = mgp->cmd;
332 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
333 u32 dma_low, dma_high, result, value;
336 /* ensure buf is aligned to 8 bytes */
337 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
339 buf->data0 = htonl(data->data0);
340 buf->data1 = htonl(data->data1);
341 buf->data2 = htonl(data->data2);
342 buf->cmd = htonl(cmd);
343 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
344 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
346 buf->response_addr.low = htonl(dma_low);
347 buf->response_addr.high = htonl(dma_high);
348 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
350 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
352 /* wait up to 15ms. Longest command is the DMA benchmark,
353 * which is capped at 5ms, but runs from a timeout handler
354 * that runs every 7.8ms. So a 15ms timeout leaves us with
358 /* if atomic is set, do not sleep,
359 * and try to get the completion quickly
360 * (1ms will be enough for those commands) */
361 for (sleep_total = 0;
363 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
367 /* use msleep for most command */
368 for (sleep_total = 0;
370 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
375 result = ntohl(response->result);
376 value = ntohl(response->data);
377 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
381 } else if (result == MXGEFW_CMD_UNKNOWN) {
383 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
386 dev_err(&mgp->pdev->dev,
387 "command %d failed, result = %d\n",
393 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
399 * The eeprom strings on the lanaiX have the format
402 * PT:ddd mmm xx xx:xx:xx xx\0
403 * PV:ddd mmm xx xx:xx:xx xx\0
405 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
410 ptr = mgp->eeprom_strings;
411 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
413 while (*ptr != '\0' && ptr < limit) {
414 if (memcmp(ptr, "MAC=", 4) == 0) {
416 mgp->mac_addr_string = ptr;
417 for (i = 0; i < 6; i++) {
418 if ((ptr + 2) > limit)
421 simple_strtoul(ptr, &ptr, 16);
425 if (memcmp(ptr, "PC=", 3) == 0) {
427 mgp->product_code_string = ptr;
429 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
431 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
433 while (ptr < limit && *ptr++) ;
439 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
444 * Enable or disable periodic RDMAs from the host to make certain
445 * chipsets resend dropped PCIe messages
448 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
450 char __iomem *submit;
451 __be32 buf[16] __attribute__ ((__aligned__(8)));
452 u32 dma_low, dma_high;
455 /* clear confirmation addr */
459 /* send a rdma command to the PCIe engine, and wait for the
460 * response in the confirmation address. The firmware should
461 * write a -1 there to indicate it is alive and well
463 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
464 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
466 buf[0] = htonl(dma_high); /* confirm addr MSW */
467 buf[1] = htonl(dma_low); /* confirm addr LSW */
468 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
469 buf[3] = htonl(dma_high); /* dummy addr MSW */
470 buf[4] = htonl(dma_low); /* dummy addr LSW */
471 buf[5] = htonl(enable); /* enable? */
473 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
475 myri10ge_pio_copy(submit, &buf, sizeof(buf));
476 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
478 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
479 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
480 (enable ? "enable" : "disable"));
484 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
485 struct mcp_gen_header *hdr)
487 struct device *dev = &mgp->pdev->dev;
489 /* check firmware type */
490 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
491 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
495 /* save firmware version for ethtool */
496 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
498 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
499 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
501 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
502 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
503 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
504 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
505 MXGEFW_VERSION_MINOR);
511 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
513 unsigned crc, reread_crc;
514 const struct firmware *fw;
515 struct device *dev = &mgp->pdev->dev;
516 struct mcp_gen_header *hdr;
521 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
522 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
525 goto abort_with_nothing;
530 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
531 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
532 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
538 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
539 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
540 dev_err(dev, "Bad firmware file\n");
544 hdr = (void *)(fw->data + hdr_offset);
546 status = myri10ge_validate_firmware(mgp, hdr);
550 crc = crc32(~0, fw->data, fw->size);
551 for (i = 0; i < fw->size; i += 256) {
552 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
554 min(256U, (unsigned)(fw->size - i)));
558 /* corruption checking is good for parity recovery and buggy chipset */
559 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
560 reread_crc = crc32(~0, fw->data, fw->size);
561 if (crc != reread_crc) {
562 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
563 (unsigned)fw->size, reread_crc, crc);
567 *size = (u32) fw->size;
570 release_firmware(fw);
576 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
578 struct mcp_gen_header *hdr;
579 struct device *dev = &mgp->pdev->dev;
580 const size_t bytes = sizeof(struct mcp_gen_header);
584 /* find running firmware header */
585 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
587 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
588 dev_err(dev, "Running firmware has bad header offset (%d)\n",
593 /* copy header of running firmware from SRAM to host memory to
594 * validate firmware */
595 hdr = kmalloc(bytes, GFP_KERNEL);
597 dev_err(dev, "could not malloc firmware hdr\n");
600 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
601 status = myri10ge_validate_firmware(mgp, hdr);
604 /* check to see if adopted firmware has bug where adopting
605 * it will cause broadcasts to be filtered unless the NIC
606 * is kept in ALLMULTI mode */
607 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
608 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
609 mgp->adopted_rx_filter_bug = 1;
610 dev_warn(dev, "Adopting fw %d.%d.%d: "
611 "working around rx filter bug\n",
612 mgp->fw_ver_major, mgp->fw_ver_minor,
618 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
620 char __iomem *submit;
621 __be32 buf[16] __attribute__ ((__aligned__(8)));
622 u32 dma_low, dma_high, size;
624 struct myri10ge_cmd cmd;
627 status = myri10ge_load_hotplug_firmware(mgp, &size);
629 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
631 /* Do not attempt to adopt firmware if there
636 status = myri10ge_adopt_running_firmware(mgp);
638 dev_err(&mgp->pdev->dev,
639 "failed to adopt running firmware\n");
642 dev_info(&mgp->pdev->dev,
643 "Successfully adopted running firmware\n");
644 if (mgp->tx.boundary == 4096) {
645 dev_warn(&mgp->pdev->dev,
646 "Using firmware currently running on NIC"
648 dev_warn(&mgp->pdev->dev,
649 "performance consider loading optimized "
651 dev_warn(&mgp->pdev->dev, "via hotplug\n");
654 mgp->fw_name = "adopted";
655 mgp->tx.boundary = 2048;
659 /* clear confirmation addr */
663 /* send a reload command to the bootstrap MCP, and wait for the
664 * response in the confirmation address. The firmware should
665 * write a -1 there to indicate it is alive and well
667 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
668 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
670 buf[0] = htonl(dma_high); /* confirm addr MSW */
671 buf[1] = htonl(dma_low); /* confirm addr LSW */
672 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
674 /* FIX: All newest firmware should un-protect the bottom of
675 * the sram before handoff. However, the very first interfaces
676 * do not. Therefore the handoff copy must skip the first 8 bytes
678 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
679 buf[4] = htonl(size - 8); /* length of code */
680 buf[5] = htonl(8); /* where to copy to */
681 buf[6] = htonl(0); /* where to jump to */
683 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
685 myri10ge_pio_copy(submit, &buf, sizeof(buf));
690 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
694 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
695 dev_err(&mgp->pdev->dev, "handoff failed\n");
698 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
699 myri10ge_dummy_rdma(mgp, 1);
701 /* probe for IPv6 TSO support */
702 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
703 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
706 mgp->max_tso6 = cmd.data0;
707 mgp->features |= NETIF_F_TSO6;
712 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
714 struct myri10ge_cmd cmd;
717 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
718 | (addr[2] << 8) | addr[3]);
720 cmd.data1 = ((addr[4] << 8) | (addr[5]));
722 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
726 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
728 struct myri10ge_cmd cmd;
731 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
732 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
736 "myri10ge: %s: Failed to set flow control mode\n",
745 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
747 struct myri10ge_cmd cmd;
750 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
751 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
753 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
757 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
759 struct myri10ge_cmd cmd;
762 struct page *dmatest_page;
763 dma_addr_t dmatest_bus;
766 dmatest_page = alloc_page(GFP_KERNEL);
769 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
772 /* Run a small DMA test.
773 * The magic multipliers to the length tell the firmware
774 * to do DMA read, write, or read+write tests. The
775 * results are returned in cmd.data0. The upper 16
776 * bits or the return is the number of transfers completed.
777 * The lower 16 bits is the time in 0.5us ticks that the
778 * transfers took to complete.
781 len = mgp->tx.boundary;
783 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
784 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
785 cmd.data2 = len * 0x10000;
786 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
791 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
792 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
793 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
794 cmd.data2 = len * 0x1;
795 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
800 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
802 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
803 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
804 cmd.data2 = len * 0x10001;
805 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
810 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
811 (cmd.data0 & 0xffff);
814 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
815 put_page(dmatest_page);
817 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
818 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
824 static int myri10ge_reset(struct myri10ge_priv *mgp)
826 struct myri10ge_cmd cmd;
830 /* try to send a reset command to the card to see if it
832 memset(&cmd, 0, sizeof(cmd));
833 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
835 dev_err(&mgp->pdev->dev, "failed reset\n");
839 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
841 /* Now exchange information about interrupts */
843 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
844 memset(mgp->rx_done.entry, 0, bytes);
845 cmd.data0 = (u32) bytes;
846 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
847 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
848 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
849 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
852 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
853 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
854 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
856 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
858 status |= myri10ge_send_cmd
859 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
860 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
862 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
865 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
867 memset(mgp->rx_done.entry, 0, bytes);
869 /* reset mcp/driver shared state back to 0 */
872 mgp->tx.pkt_start = 0;
873 mgp->tx.pkt_done = 0;
875 mgp->rx_small.cnt = 0;
876 mgp->rx_done.idx = 0;
877 mgp->rx_done.cnt = 0;
878 mgp->link_changes = 0;
879 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
880 myri10ge_change_pause(mgp, mgp->pause);
881 myri10ge_set_multicast_list(mgp->dev);
886 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
887 struct mcp_kreq_ether_recv *src)
892 src->addr_low = htonl(DMA_32BIT_MASK);
893 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
895 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
898 put_be32(low, &dst->addr_low);
902 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
904 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
906 if ((skb->protocol == htons(ETH_P_8021Q)) &&
907 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
908 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
910 skb->ip_summed = CHECKSUM_COMPLETE;
915 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
916 struct skb_frag_struct *rx_frags, int len, int hlen)
918 struct skb_frag_struct *skb_frags;
920 skb->len = skb->data_len = len;
921 skb->truesize = len + sizeof(struct sk_buff);
922 /* attach the page(s) */
924 skb_frags = skb_shinfo(skb)->frags;
926 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
927 len -= rx_frags->size;
930 skb_shinfo(skb)->nr_frags++;
933 /* pskb_may_pull is not available in irq context, but
934 * skb_pull() (for ether_pad and eth_type_trans()) requires
935 * the beginning of the packet in skb_headlen(), move it
937 skb_copy_to_linear_data(skb, va, hlen);
938 skb_shinfo(skb)->frags[0].page_offset += hlen;
939 skb_shinfo(skb)->frags[0].size -= hlen;
940 skb->data_len -= hlen;
942 skb_pull(skb, MXGEFW_PAD);
946 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
947 int bytes, int watchdog)
952 if (unlikely(rx->watchdog_needed && !watchdog))
955 /* try to refill entire ring */
956 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
957 idx = rx->fill_cnt & rx->mask;
958 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
959 /* we can use part of previous page */
962 /* we need a new page */
964 alloc_pages(GFP_ATOMIC | __GFP_COMP,
965 MYRI10GE_ALLOC_ORDER);
966 if (unlikely(page == NULL)) {
967 if (rx->fill_cnt - rx->cnt < 16)
968 rx->watchdog_needed = 1;
973 rx->bus = pci_map_page(mgp->pdev, page, 0,
977 rx->info[idx].page = rx->page;
978 rx->info[idx].page_offset = rx->page_offset;
979 /* note that this is the address of the start of the
981 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
982 rx->shadow[idx].addr_low =
983 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
984 rx->shadow[idx].addr_high =
985 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
987 /* start next packet on a cacheline boundary */
988 rx->page_offset += SKB_DATA_ALIGN(bytes);
990 #if MYRI10GE_ALLOC_SIZE > 4096
991 /* don't cross a 4KB boundary */
992 if ((rx->page_offset >> 12) !=
993 ((rx->page_offset + bytes - 1) >> 12))
994 rx->page_offset = (rx->page_offset + 4096) & ~4095;
998 /* copy 8 descriptors to the firmware at a time */
999 if ((idx & 7) == 7) {
1000 if (rx->wc_fifo == NULL)
1001 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1002 &rx->shadow[idx - 7]);
1005 myri10ge_pio_copy(rx->wc_fifo,
1006 &rx->shadow[idx - 7], 64);
1013 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1014 struct myri10ge_rx_buffer_state *info, int bytes)
1016 /* unmap the recvd page if we're the only or last user of it */
1017 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1018 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1019 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1020 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1021 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1025 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1026 * page into an skb */
1029 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1030 int bytes, int len, __wsum csum)
1032 struct sk_buff *skb;
1033 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1034 int i, idx, hlen, remainder;
1035 struct pci_dev *pdev = mgp->pdev;
1036 struct net_device *dev = mgp->dev;
1040 idx = rx->cnt & rx->mask;
1041 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1043 /* Fill skb_frag_struct(s) with data from our receive */
1044 for (i = 0, remainder = len; remainder > 0; i++) {
1045 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1046 rx_frags[i].page = rx->info[idx].page;
1047 rx_frags[i].page_offset = rx->info[idx].page_offset;
1048 if (remainder < MYRI10GE_ALLOC_SIZE)
1049 rx_frags[i].size = remainder;
1051 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1053 idx = rx->cnt & rx->mask;
1054 remainder -= MYRI10GE_ALLOC_SIZE;
1057 if (mgp->csum_flag && myri10ge_lro) {
1058 rx_frags[0].page_offset += MXGEFW_PAD;
1059 rx_frags[0].size -= MXGEFW_PAD;
1061 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
1063 /* opaque, will come back in get_frag_header */
1064 (void *)(__force unsigned long)csum,
1069 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1071 /* allocate an skb to attach the page(s) to. This is done
1072 * after trying LRO, so as to avoid skb allocation overheads */
1074 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1075 if (unlikely(skb == NULL)) {
1076 mgp->stats.rx_dropped++;
1079 put_page(rx_frags[i].page);
1084 /* Attach the pages to the skb, and trim off any padding */
1085 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1086 if (skb_shinfo(skb)->frags[0].size <= 0) {
1087 put_page(skb_shinfo(skb)->frags[0].page);
1088 skb_shinfo(skb)->nr_frags = 0;
1090 skb->protocol = eth_type_trans(skb, dev);
1092 if (mgp->csum_flag) {
1093 if ((skb->protocol == htons(ETH_P_IP)) ||
1094 (skb->protocol == htons(ETH_P_IPV6))) {
1096 skb->ip_summed = CHECKSUM_COMPLETE;
1098 myri10ge_vlan_ip_csum(skb, csum);
1100 netif_receive_skb(skb);
1101 dev->last_rx = jiffies;
1105 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1107 struct pci_dev *pdev = mgp->pdev;
1108 struct myri10ge_tx_buf *tx = &mgp->tx;
1109 struct sk_buff *skb;
1112 while (tx->pkt_done != mcp_index) {
1113 idx = tx->done & tx->mask;
1114 skb = tx->info[idx].skb;
1117 tx->info[idx].skb = NULL;
1118 if (tx->info[idx].last) {
1120 tx->info[idx].last = 0;
1123 len = pci_unmap_len(&tx->info[idx], len);
1124 pci_unmap_len_set(&tx->info[idx], len, 0);
1126 mgp->stats.tx_bytes += skb->len;
1127 mgp->stats.tx_packets++;
1128 dev_kfree_skb_irq(skb);
1130 pci_unmap_single(pdev,
1131 pci_unmap_addr(&tx->info[idx],
1136 pci_unmap_page(pdev,
1137 pci_unmap_addr(&tx->info[idx],
1142 /* start the queue if we've stopped it */
1143 if (netif_queue_stopped(mgp->dev)
1144 && tx->req - tx->done < (tx->mask >> 1)) {
1146 netif_wake_queue(mgp->dev);
1150 static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
1152 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1153 unsigned long rx_bytes = 0;
1154 unsigned long rx_packets = 0;
1155 unsigned long rx_ok;
1157 int idx = rx_done->idx;
1158 int cnt = rx_done->cnt;
1163 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1164 length = ntohs(rx_done->entry[idx].length);
1165 rx_done->entry[idx].length = 0;
1166 checksum = csum_unfold(rx_done->entry[idx].checksum);
1167 if (length <= mgp->small_bytes)
1168 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1172 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1175 rx_packets += rx_ok;
1176 rx_bytes += rx_ok * (unsigned long)length;
1178 idx = cnt & (myri10ge_max_intr_slots - 1);
1183 mgp->stats.rx_packets += rx_packets;
1184 mgp->stats.rx_bytes += rx_bytes;
1187 lro_flush_all(&rx_done->lro_mgr);
1189 /* restock receive rings if needed */
1190 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1191 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1192 mgp->small_bytes + MXGEFW_PAD, 0);
1193 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1194 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1199 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1201 struct mcp_irq_data *stats = mgp->fw_stats;
1203 if (unlikely(stats->stats_updated)) {
1204 unsigned link_up = ntohl(stats->link_up);
1205 if (mgp->link_state != link_up) {
1206 mgp->link_state = link_up;
1208 if (mgp->link_state == MXGEFW_LINK_UP) {
1209 if (netif_msg_link(mgp))
1211 "myri10ge: %s: link up\n",
1213 netif_carrier_on(mgp->dev);
1214 mgp->link_changes++;
1216 if (netif_msg_link(mgp))
1218 "myri10ge: %s: link %s\n",
1220 (link_up == MXGEFW_LINK_MYRINET ?
1221 "mismatch (Myrinet detected)" :
1223 netif_carrier_off(mgp->dev);
1224 mgp->link_changes++;
1227 if (mgp->rdma_tags_available !=
1228 ntohl(mgp->fw_stats->rdma_tags_available)) {
1229 mgp->rdma_tags_available =
1230 ntohl(mgp->fw_stats->rdma_tags_available);
1231 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1232 "%d tags left\n", mgp->dev->name,
1233 mgp->rdma_tags_available);
1235 mgp->down_cnt += stats->link_down;
1236 if (stats->link_down)
1237 wake_up(&mgp->down_wq);
1241 static int myri10ge_poll(struct napi_struct *napi, int budget)
1243 struct myri10ge_priv *mgp =
1244 container_of(napi, struct myri10ge_priv, napi);
1245 struct net_device *netdev = mgp->dev;
1248 /* process as many rx events as NAPI will allow */
1249 work_done = myri10ge_clean_rx_done(mgp, budget);
1251 if (work_done < budget) {
1252 netif_rx_complete(netdev, napi);
1253 put_be32(htonl(3), mgp->irq_claim);
1258 static irqreturn_t myri10ge_intr(int irq, void *arg)
1260 struct myri10ge_priv *mgp = arg;
1261 struct mcp_irq_data *stats = mgp->fw_stats;
1262 struct myri10ge_tx_buf *tx = &mgp->tx;
1263 u32 send_done_count;
1266 /* make sure it is our IRQ, and that the DMA has finished */
1267 if (unlikely(!stats->valid))
1270 /* low bit indicates receives are present, so schedule
1271 * napi poll handler */
1272 if (stats->valid & 1)
1273 netif_rx_schedule(mgp->dev, &mgp->napi);
1275 if (!mgp->msi_enabled) {
1276 put_be32(0, mgp->irq_deassert);
1277 if (!myri10ge_deassert_wait)
1283 /* Wait for IRQ line to go low, if using INTx */
1287 /* check for transmit completes and receives */
1288 send_done_count = ntohl(stats->send_done_count);
1289 if (send_done_count != tx->pkt_done)
1290 myri10ge_tx_done(mgp, (int)send_done_count);
1291 if (unlikely(i > myri10ge_max_irq_loops)) {
1292 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1295 schedule_work(&mgp->watchdog_work);
1297 if (likely(stats->valid == 0))
1303 myri10ge_check_statblock(mgp);
1305 put_be32(htonl(3), mgp->irq_claim + 1);
1306 return (IRQ_HANDLED);
1310 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1312 struct myri10ge_priv *mgp = netdev_priv(netdev);
1316 cmd->autoneg = AUTONEG_DISABLE;
1317 cmd->speed = SPEED_10000;
1318 cmd->duplex = DUPLEX_FULL;
1321 * parse the product code to deterimine the interface type
1322 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1323 * after the 3rd dash in the driver's cached copy of the
1324 * EEPROM's product code string.
1326 ptr = mgp->product_code_string;
1328 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1332 for (i = 0; i < 3; i++, ptr++) {
1333 ptr = strchr(ptr, '-');
1335 printk(KERN_ERR "myri10ge: %s: Invalid product "
1336 "code %s\n", netdev->name,
1337 mgp->product_code_string);
1341 if (*ptr == 'R' || *ptr == 'Q') {
1342 /* We've found either an XFP or quad ribbon fiber */
1343 cmd->port = PORT_FIBRE;
1349 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1351 struct myri10ge_priv *mgp = netdev_priv(netdev);
1353 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1354 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1355 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1356 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1360 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1362 struct myri10ge_priv *mgp = netdev_priv(netdev);
1363 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1368 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1370 struct myri10ge_priv *mgp = netdev_priv(netdev);
1372 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1373 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1378 myri10ge_get_pauseparam(struct net_device *netdev,
1379 struct ethtool_pauseparam *pause)
1381 struct myri10ge_priv *mgp = netdev_priv(netdev);
1384 pause->rx_pause = mgp->pause;
1385 pause->tx_pause = mgp->pause;
1389 myri10ge_set_pauseparam(struct net_device *netdev,
1390 struct ethtool_pauseparam *pause)
1392 struct myri10ge_priv *mgp = netdev_priv(netdev);
1394 if (pause->tx_pause != mgp->pause)
1395 return myri10ge_change_pause(mgp, pause->tx_pause);
1396 if (pause->rx_pause != mgp->pause)
1397 return myri10ge_change_pause(mgp, pause->tx_pause);
1398 if (pause->autoneg != 0)
1404 myri10ge_get_ringparam(struct net_device *netdev,
1405 struct ethtool_ringparam *ring)
1407 struct myri10ge_priv *mgp = netdev_priv(netdev);
1409 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1410 ring->rx_max_pending = mgp->rx_big.mask + 1;
1411 ring->rx_jumbo_max_pending = 0;
1412 ring->tx_max_pending = mgp->rx_small.mask + 1;
1413 ring->rx_mini_pending = ring->rx_mini_max_pending;
1414 ring->rx_pending = ring->rx_max_pending;
1415 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1416 ring->tx_pending = ring->tx_max_pending;
1419 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1421 struct myri10ge_priv *mgp = netdev_priv(netdev);
1428 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1430 struct myri10ge_priv *mgp = netdev_priv(netdev);
1432 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1438 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1440 struct myri10ge_priv *mgp = netdev_priv(netdev);
1441 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1444 netdev->features |= flags;
1446 netdev->features &= ~flags;
1450 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1451 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1452 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1453 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1454 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1455 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1456 "tx_heartbeat_errors", "tx_window_errors",
1457 /* device-specific stats */
1458 "tx_boundary", "WC", "irq", "MSI",
1459 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1460 "serial_number", "tx_pkt_start", "tx_pkt_done",
1461 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1462 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1463 "link_changes", "link_up", "dropped_link_overflow",
1464 "dropped_link_error_or_filtered",
1465 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1466 "dropped_unicast_filtered", "dropped_multicast_filtered",
1467 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1468 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1469 "LRO avg aggr", "LRO no_desc"
1472 #define MYRI10GE_NET_STATS_LEN 21
1473 #define MYRI10GE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_stats)
1476 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1478 switch (stringset) {
1480 memcpy(data, *myri10ge_gstrings_stats,
1481 sizeof(myri10ge_gstrings_stats));
1486 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1490 return MYRI10GE_STATS_LEN;
1497 myri10ge_get_ethtool_stats(struct net_device *netdev,
1498 struct ethtool_stats *stats, u64 * data)
1500 struct myri10ge_priv *mgp = netdev_priv(netdev);
1503 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1504 data[i] = ((unsigned long *)&mgp->stats)[i];
1506 data[i++] = (unsigned int)mgp->tx.boundary;
1507 data[i++] = (unsigned int)mgp->wc_enabled;
1508 data[i++] = (unsigned int)mgp->pdev->irq;
1509 data[i++] = (unsigned int)mgp->msi_enabled;
1510 data[i++] = (unsigned int)mgp->read_dma;
1511 data[i++] = (unsigned int)mgp->write_dma;
1512 data[i++] = (unsigned int)mgp->read_write_dma;
1513 data[i++] = (unsigned int)mgp->serial_number;
1514 data[i++] = (unsigned int)mgp->tx.pkt_start;
1515 data[i++] = (unsigned int)mgp->tx.pkt_done;
1516 data[i++] = (unsigned int)mgp->tx.req;
1517 data[i++] = (unsigned int)mgp->tx.done;
1518 data[i++] = (unsigned int)mgp->rx_small.cnt;
1519 data[i++] = (unsigned int)mgp->rx_big.cnt;
1520 data[i++] = (unsigned int)mgp->wake_queue;
1521 data[i++] = (unsigned int)mgp->stop_queue;
1522 data[i++] = (unsigned int)mgp->watchdog_resets;
1523 data[i++] = (unsigned int)mgp->tx_linearized;
1524 data[i++] = (unsigned int)mgp->link_changes;
1525 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1526 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1528 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1529 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1530 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1531 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1533 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
1535 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1536 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1537 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1538 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1539 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1540 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1541 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1542 if (mgp->rx_done.lro_mgr.stats.flushed)
1543 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1544 mgp->rx_done.lro_mgr.stats.flushed;
1547 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
1550 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1552 struct myri10ge_priv *mgp = netdev_priv(netdev);
1553 mgp->msg_enable = value;
1556 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1558 struct myri10ge_priv *mgp = netdev_priv(netdev);
1559 return mgp->msg_enable;
1562 static const struct ethtool_ops myri10ge_ethtool_ops = {
1563 .get_settings = myri10ge_get_settings,
1564 .get_drvinfo = myri10ge_get_drvinfo,
1565 .get_coalesce = myri10ge_get_coalesce,
1566 .set_coalesce = myri10ge_set_coalesce,
1567 .get_pauseparam = myri10ge_get_pauseparam,
1568 .set_pauseparam = myri10ge_set_pauseparam,
1569 .get_ringparam = myri10ge_get_ringparam,
1570 .get_rx_csum = myri10ge_get_rx_csum,
1571 .set_rx_csum = myri10ge_set_rx_csum,
1572 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1573 .set_sg = ethtool_op_set_sg,
1574 .set_tso = myri10ge_set_tso,
1575 .get_link = ethtool_op_get_link,
1576 .get_strings = myri10ge_get_strings,
1577 .get_sset_count = myri10ge_get_sset_count,
1578 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1579 .set_msglevel = myri10ge_set_msglevel,
1580 .get_msglevel = myri10ge_get_msglevel
1583 static int myri10ge_allocate_rings(struct net_device *dev)
1585 struct myri10ge_priv *mgp;
1586 struct myri10ge_cmd cmd;
1587 int tx_ring_size, rx_ring_size;
1588 int tx_ring_entries, rx_ring_entries;
1592 mgp = netdev_priv(dev);
1594 /* get ring sizes */
1596 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1597 tx_ring_size = cmd.data0;
1598 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1601 rx_ring_size = cmd.data0;
1603 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1604 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1605 mgp->tx.mask = tx_ring_entries - 1;
1606 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1610 /* allocate the host shadow rings */
1612 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1613 * sizeof(*mgp->tx.req_list);
1614 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1615 if (mgp->tx.req_bytes == NULL)
1616 goto abort_with_nothing;
1618 /* ensure req_list entries are aligned to 8 bytes */
1619 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1620 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1622 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1623 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1624 if (mgp->rx_small.shadow == NULL)
1625 goto abort_with_tx_req_bytes;
1627 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1628 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1629 if (mgp->rx_big.shadow == NULL)
1630 goto abort_with_rx_small_shadow;
1632 /* allocate the host info rings */
1634 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1635 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1636 if (mgp->tx.info == NULL)
1637 goto abort_with_rx_big_shadow;
1639 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1640 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1641 if (mgp->rx_small.info == NULL)
1642 goto abort_with_tx_info;
1644 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1645 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1646 if (mgp->rx_big.info == NULL)
1647 goto abort_with_rx_small_info;
1649 /* Fill the receive rings */
1650 mgp->rx_big.cnt = 0;
1651 mgp->rx_small.cnt = 0;
1652 mgp->rx_big.fill_cnt = 0;
1653 mgp->rx_small.fill_cnt = 0;
1654 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1655 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1656 mgp->rx_small.watchdog_needed = 0;
1657 mgp->rx_big.watchdog_needed = 0;
1658 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1659 mgp->small_bytes + MXGEFW_PAD, 0);
1661 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1662 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1663 dev->name, mgp->rx_small.fill_cnt);
1664 goto abort_with_rx_small_ring;
1667 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1668 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1669 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1670 dev->name, mgp->rx_big.fill_cnt);
1671 goto abort_with_rx_big_ring;
1676 abort_with_rx_big_ring:
1677 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1678 int idx = i & mgp->rx_big.mask;
1679 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1681 put_page(mgp->rx_big.info[idx].page);
1684 abort_with_rx_small_ring:
1685 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1686 int idx = i & mgp->rx_small.mask;
1687 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1688 mgp->small_bytes + MXGEFW_PAD);
1689 put_page(mgp->rx_small.info[idx].page);
1692 kfree(mgp->rx_big.info);
1694 abort_with_rx_small_info:
1695 kfree(mgp->rx_small.info);
1698 kfree(mgp->tx.info);
1700 abort_with_rx_big_shadow:
1701 kfree(mgp->rx_big.shadow);
1703 abort_with_rx_small_shadow:
1704 kfree(mgp->rx_small.shadow);
1706 abort_with_tx_req_bytes:
1707 kfree(mgp->tx.req_bytes);
1708 mgp->tx.req_bytes = NULL;
1709 mgp->tx.req_list = NULL;
1715 static void myri10ge_free_rings(struct net_device *dev)
1717 struct myri10ge_priv *mgp;
1718 struct sk_buff *skb;
1719 struct myri10ge_tx_buf *tx;
1722 mgp = netdev_priv(dev);
1724 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1725 idx = i & mgp->rx_big.mask;
1726 if (i == mgp->rx_big.fill_cnt - 1)
1727 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1728 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1730 put_page(mgp->rx_big.info[idx].page);
1733 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1734 idx = i & mgp->rx_small.mask;
1735 if (i == mgp->rx_small.fill_cnt - 1)
1736 mgp->rx_small.info[idx].page_offset =
1737 MYRI10GE_ALLOC_SIZE;
1738 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1739 mgp->small_bytes + MXGEFW_PAD);
1740 put_page(mgp->rx_small.info[idx].page);
1743 while (tx->done != tx->req) {
1744 idx = tx->done & tx->mask;
1745 skb = tx->info[idx].skb;
1748 tx->info[idx].skb = NULL;
1750 len = pci_unmap_len(&tx->info[idx], len);
1751 pci_unmap_len_set(&tx->info[idx], len, 0);
1753 mgp->stats.tx_dropped++;
1754 dev_kfree_skb_any(skb);
1756 pci_unmap_single(mgp->pdev,
1757 pci_unmap_addr(&tx->info[idx],
1762 pci_unmap_page(mgp->pdev,
1763 pci_unmap_addr(&tx->info[idx],
1768 kfree(mgp->rx_big.info);
1770 kfree(mgp->rx_small.info);
1772 kfree(mgp->tx.info);
1774 kfree(mgp->rx_big.shadow);
1776 kfree(mgp->rx_small.shadow);
1778 kfree(mgp->tx.req_bytes);
1779 mgp->tx.req_bytes = NULL;
1780 mgp->tx.req_list = NULL;
1783 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1785 struct pci_dev *pdev = mgp->pdev;
1789 status = pci_enable_msi(pdev);
1792 "Error %d setting up MSI; falling back to xPIC\n",
1795 mgp->msi_enabled = 1;
1797 mgp->msi_enabled = 0;
1799 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1800 mgp->dev->name, mgp);
1802 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1803 if (mgp->msi_enabled)
1804 pci_disable_msi(pdev);
1809 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1811 struct pci_dev *pdev = mgp->pdev;
1813 free_irq(pdev->irq, mgp);
1814 if (mgp->msi_enabled)
1815 pci_disable_msi(pdev);
1819 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1820 void **ip_hdr, void **tcpudp_hdr,
1821 u64 * hdr_flags, void *priv)
1824 struct vlan_ethhdr *veh;
1826 u8 *va = page_address(frag->page) + frag->page_offset;
1827 unsigned long ll_hlen;
1828 /* passed opaque through lro_receive_frags() */
1829 __wsum csum = (__force __wsum) (unsigned long)priv;
1831 /* find the mac header, aborting if not IPv4 */
1833 eh = (struct ethhdr *)va;
1836 if (eh->h_proto != htons(ETH_P_IP)) {
1837 if (eh->h_proto == htons(ETH_P_8021Q)) {
1838 veh = (struct vlan_ethhdr *)va;
1839 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1842 ll_hlen += VLAN_HLEN;
1845 * HW checksum starts ETH_HLEN bytes into
1846 * frame, so we must subtract off the VLAN
1847 * header's checksum before csum can be used
1849 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1855 *hdr_flags = LRO_IPV4;
1857 iph = (struct iphdr *)(va + ll_hlen);
1859 if (iph->protocol != IPPROTO_TCP)
1861 *hdr_flags |= LRO_TCP;
1862 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1864 /* verify the IP checksum */
1865 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1868 /* verify the checksum */
1869 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1870 ntohs(iph->tot_len) - (iph->ihl << 2),
1871 IPPROTO_TCP, csum)))
1877 static int myri10ge_open(struct net_device *dev)
1879 struct myri10ge_priv *mgp;
1880 struct myri10ge_cmd cmd;
1881 struct net_lro_mgr *lro_mgr;
1882 int status, big_pow2;
1884 mgp = netdev_priv(dev);
1886 if (mgp->running != MYRI10GE_ETH_STOPPED)
1889 mgp->running = MYRI10GE_ETH_STARTING;
1890 status = myri10ge_reset(mgp);
1892 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1893 goto abort_with_nothing;
1896 status = myri10ge_request_irq(mgp);
1898 goto abort_with_nothing;
1900 /* decide what small buffer size to use. For good TCP rx
1901 * performance, it is important to not receive 1514 byte
1902 * frames into jumbo buffers, as it confuses the socket buffer
1903 * accounting code, leading to drops and erratic performance.
1906 if (dev->mtu <= ETH_DATA_LEN)
1907 /* enough for a TCP header */
1908 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1909 ? (128 - MXGEFW_PAD)
1910 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1912 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1913 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1915 /* Override the small buffer size? */
1916 if (myri10ge_small_bytes > 0)
1917 mgp->small_bytes = myri10ge_small_bytes;
1919 /* get the lanai pointers to the send and receive rings */
1921 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1923 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1926 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1927 mgp->rx_small.lanai =
1928 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1930 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1932 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1936 "myri10ge: %s: failed to get ring sizes or locations\n",
1938 mgp->running = MYRI10GE_ETH_STOPPED;
1939 goto abort_with_irq;
1942 if (myri10ge_wcfifo && mgp->wc_enabled) {
1943 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1944 mgp->rx_small.wc_fifo =
1945 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1946 mgp->rx_big.wc_fifo =
1947 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1949 mgp->tx.wc_fifo = NULL;
1950 mgp->rx_small.wc_fifo = NULL;
1951 mgp->rx_big.wc_fifo = NULL;
1954 /* Firmware needs the big buff size as a power of 2. Lie and
1955 * tell him the buffer is larger, because we only use 1
1956 * buffer/pkt, and the mtu will prevent overruns.
1958 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1959 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1960 while (!is_power_of_2(big_pow2))
1962 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1964 big_pow2 = MYRI10GE_ALLOC_SIZE;
1965 mgp->big_bytes = big_pow2;
1968 status = myri10ge_allocate_rings(dev);
1970 goto abort_with_irq;
1972 /* now give firmware buffers sizes, and MTU */
1973 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1974 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1975 cmd.data0 = mgp->small_bytes;
1977 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1978 cmd.data0 = big_pow2;
1980 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1982 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1984 goto abort_with_rings;
1987 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1988 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1989 cmd.data2 = sizeof(struct mcp_irq_data);
1990 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1991 if (status == -ENOSYS) {
1992 dma_addr_t bus = mgp->fw_stats_bus;
1993 bus += offsetof(struct mcp_irq_data, send_done_count);
1994 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1995 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1996 status = myri10ge_send_cmd(mgp,
1997 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1999 /* Firmware cannot support multicast without STATS_DMA_V2 */
2000 mgp->fw_multicast_support = 0;
2002 mgp->fw_multicast_support = 1;
2005 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2007 goto abort_with_rings;
2010 mgp->link_state = ~0U;
2011 mgp->rdma_tags_available = 15;
2013 lro_mgr = &mgp->rx_done.lro_mgr;
2015 lro_mgr->features = LRO_F_NAPI;
2016 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2017 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2018 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2019 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
2020 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2021 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2022 lro_mgr->frag_align_pad = 2;
2023 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2024 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2026 napi_enable(&mgp->napi); /* must happen prior to any irq */
2028 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2030 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2032 goto abort_with_rings;
2035 mgp->wake_queue = 0;
2036 mgp->stop_queue = 0;
2037 mgp->running = MYRI10GE_ETH_RUNNING;
2038 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2039 add_timer(&mgp->watchdog_timer);
2040 netif_wake_queue(dev);
2044 myri10ge_free_rings(dev);
2047 myri10ge_free_irq(mgp);
2050 mgp->running = MYRI10GE_ETH_STOPPED;
2054 static int myri10ge_close(struct net_device *dev)
2056 struct myri10ge_priv *mgp;
2057 struct myri10ge_cmd cmd;
2058 int status, old_down_cnt;
2060 mgp = netdev_priv(dev);
2062 if (mgp->running != MYRI10GE_ETH_RUNNING)
2065 if (mgp->tx.req_bytes == NULL)
2068 del_timer_sync(&mgp->watchdog_timer);
2069 mgp->running = MYRI10GE_ETH_STOPPING;
2070 napi_disable(&mgp->napi);
2071 netif_carrier_off(dev);
2072 netif_stop_queue(dev);
2073 old_down_cnt = mgp->down_cnt;
2075 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2077 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2080 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2081 if (old_down_cnt == mgp->down_cnt)
2082 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2084 netif_tx_disable(dev);
2085 myri10ge_free_irq(mgp);
2086 myri10ge_free_rings(dev);
2088 mgp->running = MYRI10GE_ETH_STOPPED;
2092 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2093 * backwards one at a time and handle ring wraps */
2096 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2097 struct mcp_kreq_ether_send *src, int cnt)
2099 int idx, starting_slot;
2100 starting_slot = tx->req;
2103 idx = (starting_slot + cnt) & tx->mask;
2104 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2110 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2111 * at most 32 bytes at a time, so as to avoid involving the software
2112 * pio handler in the nic. We re-write the first segment's flags
2113 * to mark them valid only after writing the entire chain.
2117 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2121 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2122 struct mcp_kreq_ether_send *srcp;
2125 idx = tx->req & tx->mask;
2127 last_flags = src->flags;
2130 dst = dstp = &tx->lanai[idx];
2133 if ((idx + cnt) < tx->mask) {
2134 for (i = 0; i < (cnt - 1); i += 2) {
2135 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2136 mb(); /* force write every 32 bytes */
2141 /* submit all but the first request, and ensure
2142 * that it is submitted below */
2143 myri10ge_submit_req_backwards(tx, src, cnt);
2147 /* submit the first request */
2148 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2149 mb(); /* barrier before setting valid flag */
2152 /* re-write the last 32-bits with the valid flags */
2153 src->flags = last_flags;
2154 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2160 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2161 struct mcp_kreq_ether_send *src, int cnt)
2166 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2172 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2173 * needs to be so that we don't overrun it */
2174 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2181 * Transmit a packet. We need to split the packet so that a single
2182 * segment does not cross myri10ge->tx.boundary, so this makes segment
2183 * counting tricky. So rather than try to count segments up front, we
2184 * just give up if there are too few segments to hold a reasonably
2185 * fragmented packet currently available. If we run
2186 * out of segments while preparing a packet for DMA, we just linearize
2190 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2192 struct myri10ge_priv *mgp = netdev_priv(dev);
2193 struct mcp_kreq_ether_send *req;
2194 struct myri10ge_tx_buf *tx = &mgp->tx;
2195 struct skb_frag_struct *frag;
2198 __be32 high_swapped;
2200 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2201 u16 pseudo_hdr_offset, cksum_offset;
2202 int cum_len, seglen, boundary, rdma_count;
2207 avail = tx->mask - 1 - (tx->req - tx->done);
2210 max_segments = MXGEFW_MAX_SEND_DESC;
2212 if (skb_is_gso(skb)) {
2213 mss = skb_shinfo(skb)->gso_size;
2214 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2217 if ((unlikely(avail < max_segments))) {
2218 /* we are out of transmit resources */
2220 netif_stop_queue(dev);
2224 /* Setup checksum offloading, if needed */
2226 pseudo_hdr_offset = 0;
2228 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2229 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2230 cksum_offset = skb_transport_offset(skb);
2231 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2232 /* If the headers are excessively large, then we must
2233 * fall back to a software checksum */
2234 if (unlikely(!mss && (cksum_offset > 255 ||
2235 pseudo_hdr_offset > 127))) {
2236 if (skb_checksum_help(skb))
2239 pseudo_hdr_offset = 0;
2241 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2242 flags |= MXGEFW_FLAGS_CKSUM;
2248 if (mss) { /* TSO */
2249 /* this removes any CKSUM flag from before */
2250 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2252 /* negative cum_len signifies to the
2253 * send loop that we are still in the
2254 * header portion of the TSO packet.
2255 * TSO header can be at most 1KB long */
2256 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2258 /* for IPv6 TSO, the checksum offset stores the
2259 * TCP header length, to save the firmware from
2260 * the need to parse the headers */
2261 if (skb_is_gso_v6(skb)) {
2262 cksum_offset = tcp_hdrlen(skb);
2263 /* Can only handle headers <= max_tso6 long */
2264 if (unlikely(-cum_len > mgp->max_tso6))
2265 return myri10ge_sw_tso(skb, dev);
2267 /* for TSO, pseudo_hdr_offset holds mss.
2268 * The firmware figures out where to put
2269 * the checksum by parsing the header. */
2270 pseudo_hdr_offset = mss;
2272 /* Mark small packets, and pad out tiny packets */
2273 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2274 flags |= MXGEFW_FLAGS_SMALL;
2276 /* pad frames to at least ETH_ZLEN bytes */
2277 if (unlikely(skb->len < ETH_ZLEN)) {
2278 if (skb_padto(skb, ETH_ZLEN)) {
2279 /* The packet is gone, so we must
2281 mgp->stats.tx_dropped += 1;
2284 /* adjust the len to account for the zero pad
2285 * so that the nic can know how long it is */
2286 skb->len = ETH_ZLEN;
2290 /* map the skb for DMA */
2291 len = skb->len - skb->data_len;
2292 idx = tx->req & tx->mask;
2293 tx->info[idx].skb = skb;
2294 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2295 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2296 pci_unmap_len_set(&tx->info[idx], len, len);
2298 frag_cnt = skb_shinfo(skb)->nr_frags;
2303 /* "rdma_count" is the number of RDMAs belonging to the
2304 * current packet BEFORE the current send request. For
2305 * non-TSO packets, this is equal to "count".
2306 * For TSO packets, rdma_count needs to be reset
2307 * to 0 after a segment cut.
2309 * The rdma_count field of the send request is
2310 * the number of RDMAs of the packet starting at
2311 * that request. For TSO send requests with one ore more cuts
2312 * in the middle, this is the number of RDMAs starting
2313 * after the last cut in the request. All previous
2314 * segments before the last cut implicitly have 1 RDMA.
2316 * Since the number of RDMAs is not known beforehand,
2317 * it must be filled-in retroactively - after each
2318 * segmentation cut or at the end of the entire packet.
2322 /* Break the SKB or Fragment up into pieces which
2323 * do not cross mgp->tx.boundary */
2324 low = MYRI10GE_LOWPART_TO_U32(bus);
2325 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2330 if (unlikely(count == max_segments))
2331 goto abort_linearize;
2333 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2334 seglen = boundary - low;
2337 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2338 cum_len_next = cum_len + seglen;
2339 if (mss) { /* TSO */
2340 (req - rdma_count)->rdma_count = rdma_count + 1;
2342 if (likely(cum_len >= 0)) { /* payload */
2343 int next_is_first, chop;
2345 chop = (cum_len_next > mss);
2346 cum_len_next = cum_len_next % mss;
2347 next_is_first = (cum_len_next == 0);
2348 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2349 flags_next |= next_is_first *
2351 rdma_count |= -(chop | next_is_first);
2352 rdma_count += chop & !next_is_first;
2353 } else if (likely(cum_len_next >= 0)) { /* header ends */
2359 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2360 flags_next = MXGEFW_FLAGS_TSO_PLD |
2361 MXGEFW_FLAGS_FIRST |
2362 (small * MXGEFW_FLAGS_SMALL);
2365 req->addr_high = high_swapped;
2366 req->addr_low = htonl(low);
2367 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2368 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2369 req->rdma_count = 1;
2370 req->length = htons(seglen);
2371 req->cksum_offset = cksum_offset;
2372 req->flags = flags | ((cum_len & 1) * odd_flag);
2376 cum_len = cum_len_next;
2381 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2382 if (unlikely(cksum_offset > seglen))
2383 cksum_offset -= seglen;
2388 if (frag_idx == frag_cnt)
2391 /* map next fragment for DMA */
2392 idx = (count + tx->req) & tx->mask;
2393 frag = &skb_shinfo(skb)->frags[frag_idx];
2396 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2397 len, PCI_DMA_TODEVICE);
2398 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2399 pci_unmap_len_set(&tx->info[idx], len, len);
2402 (req - rdma_count)->rdma_count = rdma_count;
2406 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2407 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2408 MXGEFW_FLAGS_FIRST)));
2409 idx = ((count - 1) + tx->req) & tx->mask;
2410 tx->info[idx].last = 1;
2411 if (tx->wc_fifo == NULL)
2412 myri10ge_submit_req(tx, tx->req_list, count);
2414 myri10ge_submit_req_wc(tx, tx->req_list, count);
2416 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2418 netif_stop_queue(dev);
2420 dev->trans_start = jiffies;
2424 /* Free any DMA resources we've alloced and clear out the skb
2425 * slot so as to not trip up assertions, and to avoid a
2426 * double-free if linearizing fails */
2428 last_idx = (idx + 1) & tx->mask;
2429 idx = tx->req & tx->mask;
2430 tx->info[idx].skb = NULL;
2432 len = pci_unmap_len(&tx->info[idx], len);
2434 if (tx->info[idx].skb != NULL)
2435 pci_unmap_single(mgp->pdev,
2436 pci_unmap_addr(&tx->info[idx],
2440 pci_unmap_page(mgp->pdev,
2441 pci_unmap_addr(&tx->info[idx],
2444 pci_unmap_len_set(&tx->info[idx], len, 0);
2445 tx->info[idx].skb = NULL;
2447 idx = (idx + 1) & tx->mask;
2448 } while (idx != last_idx);
2449 if (skb_is_gso(skb)) {
2451 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2456 if (skb_linearize(skb))
2459 mgp->tx_linearized++;
2463 dev_kfree_skb_any(skb);
2464 mgp->stats.tx_dropped += 1;
2469 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2471 struct sk_buff *segs, *curr;
2472 struct myri10ge_priv *mgp = dev->priv;
2475 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2483 status = myri10ge_xmit(curr, dev);
2485 dev_kfree_skb_any(curr);
2490 dev_kfree_skb_any(segs);
2495 dev_kfree_skb_any(skb);
2499 dev_kfree_skb_any(skb);
2500 mgp->stats.tx_dropped += 1;
2504 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2506 struct myri10ge_priv *mgp = netdev_priv(dev);
2510 static void myri10ge_set_multicast_list(struct net_device *dev)
2512 struct myri10ge_cmd cmd;
2513 struct myri10ge_priv *mgp;
2514 struct dev_mc_list *mc_list;
2515 __be32 data[2] = { 0, 0 };
2517 DECLARE_MAC_BUF(mac);
2519 mgp = netdev_priv(dev);
2520 /* can be called from atomic contexts,
2521 * pass 1 to force atomicity in myri10ge_send_cmd() */
2522 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2524 /* This firmware is known to not support multicast */
2525 if (!mgp->fw_multicast_support)
2528 /* Disable multicast filtering */
2530 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2532 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2533 " error status: %d\n", dev->name, err);
2537 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2538 /* request to disable multicast filtering, so quit here */
2542 /* Flush the filters */
2544 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2548 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2549 ", error status: %d\n", dev->name, err);
2553 /* Walk the multicast list, and add each address */
2554 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2555 memcpy(data, &mc_list->dmi_addr, 6);
2556 cmd.data0 = ntohl(data[0]);
2557 cmd.data1 = ntohl(data[1]);
2558 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2562 printk(KERN_ERR "myri10ge: %s: Failed "
2563 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2564 "%d\t", dev->name, err);
2565 printk(KERN_ERR "MAC %s\n",
2566 print_mac(mac, mc_list->dmi_addr));
2570 /* Enable multicast filtering */
2571 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2573 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2574 "error status: %d\n", dev->name, err);
2584 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2586 struct sockaddr *sa = addr;
2587 struct myri10ge_priv *mgp = netdev_priv(dev);
2590 if (!is_valid_ether_addr(sa->sa_data))
2591 return -EADDRNOTAVAIL;
2593 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2596 "myri10ge: %s: changing mac address failed with %d\n",
2601 /* change the dev structure */
2602 memcpy(dev->dev_addr, sa->sa_data, 6);
2606 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2608 struct myri10ge_priv *mgp = netdev_priv(dev);
2611 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2612 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2613 dev->name, new_mtu);
2616 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2617 dev->name, dev->mtu, new_mtu);
2619 /* if we change the mtu on an active device, we must
2620 * reset the device so the firmware sees the change */
2621 myri10ge_close(dev);
2631 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2632 * Only do it if the bridge is a root port since we don't want to disturb
2633 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2636 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2638 struct pci_dev *bridge = mgp->pdev->bus->self;
2639 struct device *dev = &mgp->pdev->dev;
2646 if (!myri10ge_ecrc_enable || !bridge)
2649 /* check that the bridge is a root port */
2650 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2651 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2652 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2653 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2654 if (myri10ge_ecrc_enable > 1) {
2655 struct pci_dev *old_bridge = bridge;
2657 /* Walk the hierarchy up to the root port
2658 * where ECRC has to be enabled */
2660 bridge = bridge->bus->self;
2663 "Failed to find root port"
2664 " to force ECRC\n");
2668 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2669 pci_read_config_word(bridge,
2670 cap + PCI_CAP_FLAGS, &val);
2671 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2672 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2675 "Forcing ECRC on non-root port %s"
2676 " (enabling on root port %s)\n",
2677 pci_name(old_bridge), pci_name(bridge));
2680 "Not enabling ECRC on non-root port %s\n",
2686 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2690 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2692 dev_err(dev, "failed reading ext-conf-space of %s\n",
2694 dev_err(dev, "\t pci=nommconf in use? "
2695 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2698 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2701 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2702 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2703 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2707 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2708 * when the PCI-E Completion packets are aligned on an 8-byte
2709 * boundary. Some PCI-E chip sets always align Completion packets; on
2710 * the ones that do not, the alignment can be enforced by enabling
2711 * ECRC generation (if supported).
2713 * When PCI-E Completion packets are not aligned, it is actually more
2714 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2716 * If the driver can neither enable ECRC nor verify that it has
2717 * already been enabled, then it must use a firmware image which works
2718 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2719 * should also ensure that it never gives the device a Read-DMA which is
2720 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2721 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2722 * firmware image, and set tx.boundary to 4KB.
2725 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2727 struct pci_dev *pdev = mgp->pdev;
2728 struct device *dev = &pdev->dev;
2731 mgp->tx.boundary = 4096;
2733 * Verify the max read request size was set to 4KB
2734 * before trying the test with 4KB.
2736 status = pcie_get_readrq(pdev);
2738 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2741 if (status != 4096) {
2742 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2743 mgp->tx.boundary = 2048;
2746 * load the optimized firmware (which assumes aligned PCIe
2747 * completions) in order to see if it works on this host.
2749 mgp->fw_name = myri10ge_fw_aligned;
2750 status = myri10ge_load_firmware(mgp);
2756 * Enable ECRC if possible
2758 myri10ge_enable_ecrc(mgp);
2761 * Run a DMA test which watches for unaligned completions and
2762 * aborts on the first one seen.
2765 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2767 return; /* keep the aligned firmware */
2769 if (status != -E2BIG)
2770 dev_warn(dev, "DMA test failed: %d\n", status);
2771 if (status == -ENOSYS)
2772 dev_warn(dev, "Falling back to ethp! "
2773 "Please install up to date fw\n");
2775 /* fall back to using the unaligned firmware */
2776 mgp->tx.boundary = 2048;
2777 mgp->fw_name = myri10ge_fw_unaligned;
2781 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2783 if (myri10ge_force_firmware == 0) {
2784 int link_width, exp_cap;
2787 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2788 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2789 link_width = (lnk >> 4) & 0x3f;
2791 /* Check to see if Link is less than 8 or if the
2792 * upstream bridge is known to provide aligned
2794 if (link_width < 8) {
2795 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2797 mgp->tx.boundary = 4096;
2798 mgp->fw_name = myri10ge_fw_aligned;
2800 myri10ge_firmware_probe(mgp);
2803 if (myri10ge_force_firmware == 1) {
2804 dev_info(&mgp->pdev->dev,
2805 "Assuming aligned completions (forced)\n");
2806 mgp->tx.boundary = 4096;
2807 mgp->fw_name = myri10ge_fw_aligned;
2809 dev_info(&mgp->pdev->dev,
2810 "Assuming unaligned completions (forced)\n");
2811 mgp->tx.boundary = 2048;
2812 mgp->fw_name = myri10ge_fw_unaligned;
2815 if (myri10ge_fw_name != NULL) {
2816 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2818 mgp->fw_name = myri10ge_fw_name;
2823 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2825 struct myri10ge_priv *mgp;
2826 struct net_device *netdev;
2828 mgp = pci_get_drvdata(pdev);
2833 netif_device_detach(netdev);
2834 if (netif_running(netdev)) {
2835 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2837 myri10ge_close(netdev);
2840 myri10ge_dummy_rdma(mgp, 0);
2841 pci_save_state(pdev);
2842 pci_disable_device(pdev);
2844 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2847 static int myri10ge_resume(struct pci_dev *pdev)
2849 struct myri10ge_priv *mgp;
2850 struct net_device *netdev;
2854 mgp = pci_get_drvdata(pdev);
2858 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2859 msleep(5); /* give card time to respond */
2860 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2861 if (vendor == 0xffff) {
2862 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2867 status = pci_restore_state(pdev);
2871 status = pci_enable_device(pdev);
2873 dev_err(&pdev->dev, "failed to enable device\n");
2877 pci_set_master(pdev);
2879 myri10ge_reset(mgp);
2880 myri10ge_dummy_rdma(mgp, 1);
2882 /* Save configuration space to be restored if the
2883 * nic resets due to a parity error */
2884 pci_save_state(pdev);
2886 if (netif_running(netdev)) {
2888 status = myri10ge_open(netdev);
2891 goto abort_with_enabled;
2894 netif_device_attach(netdev);
2899 pci_disable_device(pdev);
2903 #endif /* CONFIG_PM */
2905 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2907 struct pci_dev *pdev = mgp->pdev;
2908 int vs = mgp->vendor_specific_offset;
2911 /*enter read32 mode */
2912 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2914 /*read REBOOT_STATUS (0xfffffff0) */
2915 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2916 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2921 * This watchdog is used to check whether the board has suffered
2922 * from a parity error and needs to be recovered.
2924 static void myri10ge_watchdog(struct work_struct *work)
2926 struct myri10ge_priv *mgp =
2927 container_of(work, struct myri10ge_priv, watchdog_work);
2932 mgp->watchdog_resets++;
2933 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2934 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2935 /* Bus master DMA disabled? Check to see
2936 * if the card rebooted due to a parity error
2937 * For now, just report it */
2938 reboot = myri10ge_read_reboot(mgp);
2940 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2941 mgp->dev->name, reboot,
2942 myri10ge_reset_recover ? " " : " not");
2943 if (myri10ge_reset_recover == 0)
2946 myri10ge_reset_recover--;
2949 * A rebooted nic will come back with config space as
2950 * it was after power was applied to PCIe bus.
2951 * Attempt to restore config space which was saved
2952 * when the driver was loaded, or the last time the
2953 * nic was resumed from power saving mode.
2955 pci_restore_state(mgp->pdev);
2957 /* save state again for accounting reasons */
2958 pci_save_state(mgp->pdev);
2961 /* if we get back -1's from our slot, perhaps somebody
2962 * powered off our card. Don't try to reset it in
2964 if (cmd == 0xffff) {
2965 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2966 if (vendor == 0xffff) {
2968 "myri10ge: %s: device disappeared!\n",
2973 /* Perhaps it is a software error. Try to reset */
2975 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2977 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2978 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2979 mgp->tx.pkt_start, mgp->tx.pkt_done,
2980 (int)ntohl(mgp->fw_stats->send_done_count));
2982 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2983 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2984 mgp->tx.pkt_start, mgp->tx.pkt_done,
2985 (int)ntohl(mgp->fw_stats->send_done_count));
2988 myri10ge_close(mgp->dev);
2989 status = myri10ge_load_firmware(mgp);
2991 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2994 myri10ge_open(mgp->dev);
2999 * We use our own timer routine rather than relying upon
3000 * netdev->tx_timeout because we have a very large hardware transmit
3001 * queue. Due to the large queue, the netdev->tx_timeout function
3002 * cannot detect a NIC with a parity error in a timely fashion if the
3003 * NIC is lightly loaded.
3005 static void myri10ge_watchdog_timer(unsigned long arg)
3007 struct myri10ge_priv *mgp;
3010 mgp = (struct myri10ge_priv *)arg;
3012 if (mgp->rx_small.watchdog_needed) {
3013 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
3014 mgp->small_bytes + MXGEFW_PAD, 1);
3015 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
3016 myri10ge_fill_thresh)
3017 mgp->rx_small.watchdog_needed = 0;
3019 if (mgp->rx_big.watchdog_needed) {
3020 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
3021 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
3022 myri10ge_fill_thresh)
3023 mgp->rx_big.watchdog_needed = 0;
3025 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
3027 if (mgp->tx.req != mgp->tx.done &&
3028 mgp->tx.done == mgp->watchdog_tx_done &&
3029 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
3030 /* nic seems like it might be stuck.. */
3031 if (rx_pause_cnt != mgp->watchdog_pause) {
3032 if (net_ratelimit())
3033 printk(KERN_WARNING "myri10ge %s:"
3034 "TX paused, check link partner\n",
3037 schedule_work(&mgp->watchdog_work);
3042 mod_timer(&mgp->watchdog_timer,
3043 jiffies + myri10ge_watchdog_timeout * HZ);
3044 mgp->watchdog_tx_done = mgp->tx.done;
3045 mgp->watchdog_tx_req = mgp->tx.req;
3046 mgp->watchdog_pause = rx_pause_cnt;
3049 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3051 struct net_device *netdev;
3052 struct myri10ge_priv *mgp;
3053 struct device *dev = &pdev->dev;
3056 int status = -ENXIO;
3059 netdev = alloc_etherdev(sizeof(*mgp));
3060 if (netdev == NULL) {
3061 dev_err(dev, "Could not allocate ethernet device\n");
3065 SET_NETDEV_DEV(netdev, &pdev->dev);
3067 mgp = netdev_priv(netdev);
3069 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
3071 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3072 mgp->pause = myri10ge_flow_control;
3073 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3074 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3075 init_waitqueue_head(&mgp->down_wq);
3077 if (pci_enable_device(pdev)) {
3078 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3080 goto abort_with_netdev;
3083 /* Find the vendor-specific cap so we can check
3084 * the reboot register later on */
3085 mgp->vendor_specific_offset
3086 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3088 /* Set our max read request to 4KB */
3089 status = pcie_set_readrq(pdev, 4096);
3091 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3093 goto abort_with_netdev;
3096 pci_set_master(pdev);
3098 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3102 "64-bit pci address mask was refused, "
3104 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3107 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3108 goto abort_with_netdev;
3110 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3111 &mgp->cmd_bus, GFP_KERNEL);
3112 if (mgp->cmd == NULL)
3113 goto abort_with_netdev;
3115 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3116 &mgp->fw_stats_bus, GFP_KERNEL);
3117 if (mgp->fw_stats == NULL)
3118 goto abort_with_cmd;
3120 mgp->board_span = pci_resource_len(pdev, 0);
3121 mgp->iomem_base = pci_resource_start(pdev, 0);
3123 mgp->wc_enabled = 0;
3125 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3126 MTRR_TYPE_WRCOMB, 1);
3128 mgp->wc_enabled = 1;
3130 /* Hack. need to get rid of these magic numbers */
3132 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3133 if (mgp->sram_size > mgp->board_span) {
3134 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3138 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3139 if (mgp->sram == NULL) {
3140 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3141 mgp->board_span, mgp->iomem_base);
3145 memcpy_fromio(mgp->eeprom_strings,
3146 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3147 MYRI10GE_EEPROM_STRINGS_SIZE);
3148 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3149 status = myri10ge_read_mac_addr(mgp);
3151 goto abort_with_ioremap;
3153 for (i = 0; i < ETH_ALEN; i++)
3154 netdev->dev_addr[i] = mgp->mac_addr[i];
3156 /* allocate rx done ring */
3157 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3158 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3159 &mgp->rx_done.bus, GFP_KERNEL);
3160 if (mgp->rx_done.entry == NULL)
3161 goto abort_with_ioremap;
3162 memset(mgp->rx_done.entry, 0, bytes);
3164 myri10ge_select_firmware(mgp);
3166 status = myri10ge_load_firmware(mgp);
3168 dev_err(&pdev->dev, "failed to load firmware\n");
3169 goto abort_with_rx_done;
3172 status = myri10ge_reset(mgp);
3174 dev_err(&pdev->dev, "failed reset\n");
3175 goto abort_with_firmware;
3178 pci_set_drvdata(pdev, mgp);
3179 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3180 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3181 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3182 myri10ge_initial_mtu = 68;
3183 netdev->mtu = myri10ge_initial_mtu;
3184 netdev->open = myri10ge_open;
3185 netdev->stop = myri10ge_close;
3186 netdev->hard_start_xmit = myri10ge_xmit;
3187 netdev->get_stats = myri10ge_get_stats;
3188 netdev->base_addr = mgp->iomem_base;
3189 netdev->change_mtu = myri10ge_change_mtu;
3190 netdev->set_multicast_list = myri10ge_set_multicast_list;
3191 netdev->set_mac_address = myri10ge_set_mac_address;
3192 netdev->features = mgp->features;
3194 netdev->features |= NETIF_F_HIGHDMA;
3196 /* make sure we can get an irq, and that MSI can be
3197 * setup (if available). Also ensure netdev->irq
3198 * is set to correct value if MSI is enabled */
3199 status = myri10ge_request_irq(mgp);
3201 goto abort_with_firmware;
3202 netdev->irq = pdev->irq;
3203 myri10ge_free_irq(mgp);
3205 /* Save configuration space to be restored if the
3206 * nic resets due to a parity error */
3207 pci_save_state(pdev);
3209 /* Setup the watchdog timer */
3210 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3211 (unsigned long)mgp);
3213 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3214 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3215 status = register_netdev(netdev);
3217 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3218 goto abort_with_state;
3220 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3221 (mgp->msi_enabled ? "MSI" : "xPIC"),
3222 netdev->irq, mgp->tx.boundary, mgp->fw_name,
3223 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3228 pci_restore_state(pdev);
3230 abort_with_firmware:
3231 myri10ge_dummy_rdma(mgp, 0);
3234 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3235 dma_free_coherent(&pdev->dev, bytes,
3236 mgp->rx_done.entry, mgp->rx_done.bus);
3244 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3246 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3247 mgp->fw_stats, mgp->fw_stats_bus);
3250 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3251 mgp->cmd, mgp->cmd_bus);
3255 free_netdev(netdev);
3262 * Does what is necessary to shutdown one Myrinet device. Called
3263 * once for each Myrinet card by the kernel when a module is
3266 static void myri10ge_remove(struct pci_dev *pdev)
3268 struct myri10ge_priv *mgp;
3269 struct net_device *netdev;
3272 mgp = pci_get_drvdata(pdev);
3276 flush_scheduled_work();
3278 unregister_netdev(netdev);
3280 myri10ge_dummy_rdma(mgp, 0);
3282 /* avoid a memory leak */
3283 pci_restore_state(pdev);
3285 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3286 dma_free_coherent(&pdev->dev, bytes,
3287 mgp->rx_done.entry, mgp->rx_done.bus);
3293 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3295 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3296 mgp->fw_stats, mgp->fw_stats_bus);
3298 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3299 mgp->cmd, mgp->cmd_bus);
3301 free_netdev(netdev);
3302 pci_set_drvdata(pdev, NULL);
3305 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3306 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3308 static struct pci_device_id myri10ge_pci_tbl[] = {
3309 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3311 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3315 static struct pci_driver myri10ge_driver = {
3317 .probe = myri10ge_probe,
3318 .remove = myri10ge_remove,
3319 .id_table = myri10ge_pci_tbl,
3321 .suspend = myri10ge_suspend,
3322 .resume = myri10ge_resume,
3326 static __init int myri10ge_init_module(void)
3328 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3329 MYRI10GE_VERSION_STR);
3330 return pci_register_driver(&myri10ge_driver);
3333 module_init(myri10ge_init_module);
3335 static __exit void myri10ge_cleanup_module(void)
3337 pci_unregister_driver(&myri10ge_driver);
3340 module_exit(myri10ge_cleanup_module);