1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
27 * big endian support with CFG:BEM instead of cpu_to_le32
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
54 #include <asm/uaccess.h>
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
84 static int dspcfg_workaround = 1;
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
89 The media type is usually passed in 'options[]'.
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
95 /* Operational parameters that are set at compile time. */
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 3*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] __devinitdata =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
134 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
135 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
137 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
138 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
139 MODULE_LICENSE("GPL");
141 module_param(mtu, int, 0);
142 module_param(debug, int, 0);
143 module_param(rx_copybreak, int, 0);
144 module_param(dspcfg_workaround, int, 1);
145 module_param_array(options, int, NULL, 0);
146 module_param_array(full_duplex, int, NULL, 0);
147 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
148 MODULE_PARM_DESC(debug, "DP8381x default debug level");
149 MODULE_PARM_DESC(rx_copybreak,
150 "DP8381x copy breakpoint for copy-only-tiny-frames");
151 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
152 MODULE_PARM_DESC(options,
153 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
154 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
159 I. Board Compatibility
161 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
162 It also works with other chips in in the DP83810 series.
164 II. Board-specific settings
166 This driver requires the PCI interrupt line to be valid.
167 It honors the EEPROM-set values.
169 III. Driver operation
173 This driver uses two statically allocated fixed-size descriptor lists
174 formed into rings by a branch from the final descriptor to the beginning of
175 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
176 The NatSemi design uses a 'next descriptor' pointer that the driver forms
179 IIIb/c. Transmit/Receive Structure
181 This driver uses a zero-copy receive and transmit scheme.
182 The driver allocates full frame size skbuffs for the Rx ring buffers at
183 open() time and passes the skb->data field to the chip as receive data
184 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
185 a fresh skbuff is allocated and the frame is copied to the new skbuff.
186 When the incoming frame is larger, the skbuff is passed directly up the
187 protocol stack. Buffers consumed this way are replaced by newly allocated
188 skbuffs in a later phase of receives.
190 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
191 using a full-sized skbuff for small frames vs. the copying costs of larger
192 frames. New boards are typically used in generously configured machines
193 and the underfilled buffers have negligible impact compared to the benefit of
194 a single allocation size, so the default value of zero results in never
195 copying packets. When copying is done, the cost is usually mitigated by using
196 a combined copy/checksum routine. Copying also preloads the cache, which is
197 most useful with small frames.
199 A subtle aspect of the operation is that unaligned buffers are not permitted
200 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
201 longword aligned for further processing. On copies frames are put into the
202 skbuff at an offset of "+2", 16-byte aligning the IP header.
204 IIId. Synchronization
206 Most operations are synchronized on the np->lock irq spinlock, except the
207 performance critical codepaths:
209 The rx process only runs in the interrupt handler. Access from outside
210 the interrupt handler is only permitted after disable_irq().
212 The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
213 is set, then access is permitted under spin_lock_irq(&np->lock).
215 Thus configuration functions that want to access everything must call
216 disable_irq(dev->irq);
217 netif_tx_lock_bh(dev);
218 spin_lock_irq(&np->lock);
222 NatSemi PCI network controllers are very uncommon.
226 http://www.scyld.com/expert/100mbps.html
227 http://www.scyld.com/expert/NWay.html
228 Datasheet is available from:
229 http://www.national.com/pf/DP/DP83815.html
239 * Support for fibre connections on Am79C874:
240 * This phy needs a special setup when connected to a fibre cable.
241 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
243 #define PHYID_AM79C874 0x0022561b
246 MII_MCTRL = 0x15, /* mode control register */
247 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
248 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
252 NATSEMI_FLAG_IGNORE_PHY = 0x1,
255 /* array of board data directly indexed by pci_tbl[x].driver_data */
256 static const struct {
259 unsigned int eeprom_size;
260 } natsemi_pci_info[] __devinitdata = {
261 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
262 { "NatSemi DP8381[56]", 0, 24 },
265 static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
266 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
267 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
268 { } /* terminate list */
270 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
272 /* Offsets to the device registers.
273 Unlike software-only systems, device drivers interact with complex hardware.
274 It's not useful to define symbolic names for every register bit in the
277 enum register_offsets {
285 IntrHoldoff = 0x1C, /* DP83816 only */
312 /* These are from the spec, around page 78... on a separate table.
313 * The meaning of these registers depend on the value of PGSEL. */
320 /* the values for the 'magic' registers above (PGSEL=1) */
321 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
322 #define TSTDAT_VAL 0x0
323 #define DSPCFG_VAL 0x5040
324 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
325 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
326 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
327 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
329 /* misc PCI space registers */
330 enum pci_register_offsets {
344 enum ChipConfig_bits {
348 CfgAnegEnable = 0x2000,
350 CfgAnegFull = 0x8000,
351 CfgAnegDone = 0x8000000,
352 CfgFullDuplex = 0x20000000,
353 CfgSpeed100 = 0x40000000,
354 CfgLink = 0x80000000,
360 EE_ChipSelect = 0x08,
367 enum PCIBusCfg_bits {
371 /* Bits in the interrupt status/mask registers. */
372 enum IntrStatus_bits {
376 IntrRxEarly = 0x0008,
378 IntrRxOverrun = 0x0020,
383 IntrTxUnderrun = 0x0400,
388 IntrHighBits = 0x8000,
389 RxStatusFIFOOver = 0x10000,
390 IntrPCIErr = 0xf00000,
391 RxResetDone = 0x1000000,
392 TxResetDone = 0x2000000,
393 IntrAbnormalSummary = 0xCD20,
397 * Default Interrupts:
398 * Rx OK, Rx Packet Error, Rx Overrun,
399 * Tx OK, Tx Packet Error, Tx Underrun,
400 * MIB Service, Phy Interrupt, High Bits,
401 * Rx Status FIFO overrun,
402 * Received Target Abort, Received Master Abort,
403 * Signalled System Error, Received Parity Error
405 #define DEFAULT_INTR 0x00f1cd65
410 TxMxdmaMask = 0x700000,
412 TxMxdma_4 = 0x100000,
413 TxMxdma_8 = 0x200000,
414 TxMxdma_16 = 0x300000,
415 TxMxdma_32 = 0x400000,
416 TxMxdma_64 = 0x500000,
417 TxMxdma_128 = 0x600000,
418 TxMxdma_256 = 0x700000,
419 TxCollRetry = 0x800000,
420 TxAutoPad = 0x10000000,
421 TxMacLoop = 0x20000000,
422 TxHeartIgn = 0x40000000,
423 TxCarrierIgn = 0x80000000
428 * - 256 byte DMA burst length
429 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
430 * - 64 bytes initial drain threshold (i.e. begin actual transmission
431 * when 64 byte are in the fifo)
432 * - on tx underruns, increase drain threshold by 64.
433 * - at most use a drain threshold of 1472 bytes: The sum of the fill
434 * threshold and the drain threshold must be less than 2016 bytes.
437 #define TX_FLTH_VAL ((512/32) << 8)
438 #define TX_DRTH_VAL_START (64/32)
439 #define TX_DRTH_VAL_INC 2
440 #define TX_DRTH_VAL_LIMIT (1472/32)
444 RxMxdmaMask = 0x700000,
446 RxMxdma_4 = 0x100000,
447 RxMxdma_8 = 0x200000,
448 RxMxdma_16 = 0x300000,
449 RxMxdma_32 = 0x400000,
450 RxMxdma_64 = 0x500000,
451 RxMxdma_128 = 0x600000,
452 RxMxdma_256 = 0x700000,
453 RxAcceptLong = 0x8000000,
454 RxAcceptTx = 0x10000000,
455 RxAcceptRunt = 0x40000000,
456 RxAcceptErr = 0x80000000
458 #define RX_DRTH_VAL (128/8)
476 WakeMagicSecure = 0x400,
477 SecureHack = 0x100000,
479 WokeUnicast = 0x800000,
480 WokeMulticast = 0x1000000,
481 WokeBroadcast = 0x2000000,
483 WokePMatch0 = 0x8000000,
484 WokePMatch1 = 0x10000000,
485 WokePMatch2 = 0x20000000,
486 WokePMatch3 = 0x40000000,
487 WokeMagic = 0x80000000,
488 WakeOptsSummary = 0x7ff
491 enum RxFilterAddr_bits {
492 RFCRAddressMask = 0x3ff,
493 AcceptMulticast = 0x00200000,
494 AcceptMyPhys = 0x08000000,
495 AcceptAllPhys = 0x10000000,
496 AcceptAllMulticast = 0x20000000,
497 AcceptBroadcast = 0x40000000,
498 RxFilterEnable = 0x80000000
501 enum StatsCtrl_bits {
508 enum MIntrCtrl_bits {
516 #define PHY_ADDR_NONE 32
517 #define PHY_ADDR_INTERNAL 1
519 /* values we might find in the silicon revision register */
520 #define SRR_DP83815_C 0x0302
521 #define SRR_DP83815_D 0x0403
522 #define SRR_DP83816_A4 0x0504
523 #define SRR_DP83816_A5 0x0505
525 /* The Rx and Tx buffer descriptors. */
526 /* Note that using only 32 bit fields simplifies conversion to big-endian
535 /* Bits in network_desc.status */
536 enum desc_status_bits {
537 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
538 DescNoCRC=0x10000000, DescPktOK=0x08000000,
541 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
542 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
543 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
544 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
546 DescRxAbort=0x04000000, DescRxOver=0x02000000,
547 DescRxDest=0x01800000, DescRxLong=0x00400000,
548 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
549 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
550 DescRxLoop=0x00020000, DesRxColl=0x00010000,
553 struct netdev_private {
554 /* Descriptor rings first for alignment */
556 struct netdev_desc *rx_ring;
557 struct netdev_desc *tx_ring;
558 /* The addresses of receive-in-place skbuffs */
559 struct sk_buff *rx_skbuff[RX_RING_SIZE];
560 dma_addr_t rx_dma[RX_RING_SIZE];
561 /* address of a sent-in-place packet/buffer, for later free() */
562 struct sk_buff *tx_skbuff[TX_RING_SIZE];
563 dma_addr_t tx_dma[TX_RING_SIZE];
564 struct net_device_stats stats;
565 /* Media monitoring timer */
566 struct timer_list timer;
567 /* Frequently used values: keep some adjacent for cache effect */
568 struct pci_dev *pci_dev;
569 struct netdev_desc *rx_head_desc;
570 /* Producer/consumer ring indices */
571 unsigned int cur_rx, dirty_rx;
572 unsigned int cur_tx, dirty_tx;
573 /* Based on MTU+slack. */
574 unsigned int rx_buf_sz;
576 /* Interrupt status */
578 /* Do not touch the nic registers */
580 /* Don't pay attention to the reported link state. */
582 /* external phy that is used: only valid if dev->if_port != PORT_TP */
584 int phy_addr_external;
585 unsigned int full_duplex;
589 /* FIFO and PCI burst thresholds */
590 u32 tx_config, rx_config;
591 /* original contents of ClkRun register */
593 /* silicon revision */
595 /* expected DSPCFG value */
597 int dspcfg_workaround;
598 /* parms saved in ethtool format */
599 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
600 u8 duplex; /* Duplex, half or full */
601 u8 autoneg; /* Autonegotiation enabled */
602 /* MII transceiver section */
611 static void move_int_phy(struct net_device *dev, int addr);
612 static int eeprom_read(void __iomem *ioaddr, int location);
613 static int mdio_read(struct net_device *dev, int reg);
614 static void mdio_write(struct net_device *dev, int reg, u16 data);
615 static void init_phy_fixup(struct net_device *dev);
616 static int miiport_read(struct net_device *dev, int phy_id, int reg);
617 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
618 static int find_mii(struct net_device *dev);
619 static void natsemi_reset(struct net_device *dev);
620 static void natsemi_reload_eeprom(struct net_device *dev);
621 static void natsemi_stop_rxtx(struct net_device *dev);
622 static int netdev_open(struct net_device *dev);
623 static void do_cable_magic(struct net_device *dev);
624 static void undo_cable_magic(struct net_device *dev);
625 static void check_link(struct net_device *dev);
626 static void netdev_timer(unsigned long data);
627 static void dump_ring(struct net_device *dev);
628 static void tx_timeout(struct net_device *dev);
629 static int alloc_ring(struct net_device *dev);
630 static void refill_rx(struct net_device *dev);
631 static void init_ring(struct net_device *dev);
632 static void drain_tx(struct net_device *dev);
633 static void drain_ring(struct net_device *dev);
634 static void free_ring(struct net_device *dev);
635 static void reinit_ring(struct net_device *dev);
636 static void init_registers(struct net_device *dev);
637 static int start_tx(struct sk_buff *skb, struct net_device *dev);
638 static irqreturn_t intr_handler(int irq, void *dev_instance);
639 static void netdev_error(struct net_device *dev, int intr_status);
640 static int natsemi_poll(struct net_device *dev, int *budget);
641 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
642 static void netdev_tx_done(struct net_device *dev);
643 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
644 #ifdef CONFIG_NET_POLL_CONTROLLER
645 static void natsemi_poll_controller(struct net_device *dev);
647 static void __set_rx_mode(struct net_device *dev);
648 static void set_rx_mode(struct net_device *dev);
649 static void __get_stats(struct net_device *dev);
650 static struct net_device_stats *get_stats(struct net_device *dev);
651 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
652 static int netdev_set_wol(struct net_device *dev, u32 newval);
653 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
654 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
655 static int netdev_get_sopass(struct net_device *dev, u8 *data);
656 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
657 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
658 static void enable_wol_mode(struct net_device *dev, int enable_intr);
659 static int netdev_close(struct net_device *dev);
660 static int netdev_get_regs(struct net_device *dev, u8 *buf);
661 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
662 static const struct ethtool_ops ethtool_ops;
664 #define NATSEMI_ATTR(_name) \
665 static ssize_t natsemi_show_##_name(struct device *dev, \
666 struct device_attribute *attr, char *buf); \
667 static ssize_t natsemi_set_##_name(struct device *dev, \
668 struct device_attribute *attr, \
669 const char *buf, size_t count); \
670 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
672 #define NATSEMI_CREATE_FILE(_dev, _name) \
673 device_create_file(&_dev->dev, &dev_attr_##_name)
674 #define NATSEMI_REMOVE_FILE(_dev, _name) \
675 device_create_file(&_dev->dev, &dev_attr_##_name)
677 NATSEMI_ATTR(dspcfg_workaround);
679 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
680 struct device_attribute *attr,
683 struct netdev_private *np = netdev_priv(to_net_dev(dev));
685 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
688 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
689 struct device_attribute *attr,
690 const char *buf, size_t count)
692 struct netdev_private *np = netdev_priv(to_net_dev(dev));
696 /* Find out the new setting */
697 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
699 else if (!strncmp("off", buf, count - 1)
700 || !strncmp("0", buf, count - 1))
705 spin_lock_irqsave(&np->lock, flags);
707 np->dspcfg_workaround = new_setting;
709 spin_unlock_irqrestore(&np->lock, flags);
714 static inline void __iomem *ns_ioaddr(struct net_device *dev)
716 return (void __iomem *) dev->base_addr;
719 static inline void natsemi_irq_enable(struct net_device *dev)
721 writel(1, ns_ioaddr(dev) + IntrEnable);
722 readl(ns_ioaddr(dev) + IntrEnable);
725 static inline void natsemi_irq_disable(struct net_device *dev)
727 writel(0, ns_ioaddr(dev) + IntrEnable);
728 readl(ns_ioaddr(dev) + IntrEnable);
731 static void move_int_phy(struct net_device *dev, int addr)
733 struct netdev_private *np = netdev_priv(dev);
734 void __iomem *ioaddr = ns_ioaddr(dev);
738 * The internal phy is visible on the external mii bus. Therefore we must
739 * move it away before we can send commands to an external phy.
740 * There are two addresses we must avoid:
741 * - the address on the external phy that is used for transmission.
742 * - the address that we want to access. User space can access phys
743 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
744 * phy that is used for transmission.
749 if (target == np->phy_addr_external)
751 writew(target, ioaddr + PhyCtrl);
752 readw(ioaddr + PhyCtrl);
756 static void __devinit natsemi_init_media (struct net_device *dev)
758 struct netdev_private *np = netdev_priv(dev);
762 netif_carrier_on(dev);
764 netif_carrier_off(dev);
766 /* get the initial settings from hardware */
767 tmp = mdio_read(dev, MII_BMCR);
768 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
769 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
770 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
771 np->advertising= mdio_read(dev, MII_ADVERTISE);
773 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
774 && netif_msg_probe(np)) {
775 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
777 pci_name(np->pci_dev),
778 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
779 "enabled, advertise" : "disabled, force",
781 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
784 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
787 if (netif_msg_probe(np))
789 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
790 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
795 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
796 const struct pci_device_id *ent)
798 struct net_device *dev;
799 struct netdev_private *np;
800 int i, option, irq, chip_idx = ent->driver_data;
801 static int find_cnt = -1;
802 unsigned long iostart, iosize;
803 void __iomem *ioaddr;
804 const int pcibar = 1; /* PCI base address register */
808 /* when built into the kernel, we only print version if device is found */
810 static int printed_version;
811 if (!printed_version++)
815 i = pci_enable_device(pdev);
818 /* natsemi has a non-standard PM control register
819 * in PCI config space. Some boards apparently need
820 * to be brought to D0 in this manner.
822 pci_read_config_dword(pdev, PCIPM, &tmp);
823 if (tmp & PCI_PM_CTRL_STATE_MASK) {
824 /* D0 state, disable PME assertion */
825 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
826 pci_write_config_dword(pdev, PCIPM, newtmp);
830 iostart = pci_resource_start(pdev, pcibar);
831 iosize = pci_resource_len(pdev, pcibar);
834 pci_set_master(pdev);
836 dev = alloc_etherdev(sizeof (struct netdev_private));
839 SET_MODULE_OWNER(dev);
840 SET_NETDEV_DEV(dev, &pdev->dev);
842 i = pci_request_regions(pdev, DRV_NAME);
844 goto err_pci_request_regions;
846 ioaddr = ioremap(iostart, iosize);
852 /* Work around the dropped serial bit. */
853 prev_eedata = eeprom_read(ioaddr, 6);
854 for (i = 0; i < 3; i++) {
855 int eedata = eeprom_read(ioaddr, i + 7);
856 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
857 dev->dev_addr[i*2+1] = eedata >> 7;
858 prev_eedata = eedata;
861 dev->base_addr = (unsigned long __force) ioaddr;
864 np = netdev_priv(dev);
867 pci_set_drvdata(pdev, dev);
869 spin_lock_init(&np->lock);
870 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
873 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
874 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
878 np->dspcfg_workaround = dspcfg_workaround;
881 * - If configured to ignore the PHY set up for external.
882 * - If the nic was configured to use an external phy and if find_mii
883 * finds a phy: use external port, first phy that replies.
884 * - Otherwise: internal port.
885 * Note that the phy address for the internal phy doesn't matter:
886 * The address would be used to access a phy over the mii bus, but
887 * the internal phy is accessed through mapped registers.
889 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
890 dev->if_port = PORT_MII;
892 dev->if_port = PORT_TP;
893 /* Reset the chip to erase previous misconfiguration. */
894 natsemi_reload_eeprom(dev);
897 if (dev->if_port != PORT_TP) {
898 np->phy_addr_external = find_mii(dev);
899 /* If we're ignoring the PHY it doesn't matter if we can't
901 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
902 dev->if_port = PORT_TP;
903 np->phy_addr_external = PHY_ADDR_INTERNAL;
906 np->phy_addr_external = PHY_ADDR_INTERNAL;
909 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
911 option = dev->mem_start;
913 /* The lower four bits are the media type. */
919 "natsemi %s: ignoring user supplied media type %d",
920 pci_name(np->pci_dev), option & 15);
922 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
925 /* The chip-specific entries in the device structure. */
926 dev->open = &netdev_open;
927 dev->hard_start_xmit = &start_tx;
928 dev->stop = &netdev_close;
929 dev->get_stats = &get_stats;
930 dev->set_multicast_list = &set_rx_mode;
931 dev->change_mtu = &natsemi_change_mtu;
932 dev->do_ioctl = &netdev_ioctl;
933 dev->tx_timeout = &tx_timeout;
934 dev->watchdog_timeo = TX_TIMEOUT;
935 dev->poll = natsemi_poll;
938 #ifdef CONFIG_NET_POLL_CONTROLLER
939 dev->poll_controller = &natsemi_poll_controller;
941 SET_ETHTOOL_OPS(dev, ðtool_ops);
946 natsemi_init_media(dev);
948 /* save the silicon revision for later querying */
949 np->srr = readl(ioaddr + SiliconRev);
950 if (netif_msg_hw(np))
951 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
952 pci_name(np->pci_dev), np->srr);
954 i = register_netdev(dev);
956 goto err_register_netdev;
958 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
959 goto err_create_file;
961 if (netif_msg_drv(np)) {
962 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
963 dev->name, natsemi_pci_info[chip_idx].name, iostart,
964 pci_name(np->pci_dev));
965 for (i = 0; i < ETH_ALEN-1; i++)
966 printk("%02x:", dev->dev_addr[i]);
967 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
968 if (dev->if_port == PORT_TP)
969 printk(", port TP.\n");
970 else if (np->ignore_phy)
971 printk(", port MII, ignoring PHY\n");
973 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
978 unregister_netdev(dev);
984 pci_release_regions(pdev);
985 pci_set_drvdata(pdev, NULL);
987 err_pci_request_regions:
993 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
994 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
996 /* Delay between EEPROM clock transitions.
997 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
998 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
999 made udelay() unreliable.
1000 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1003 #define eeprom_delay(ee_addr) readl(ee_addr)
1005 #define EE_Write0 (EE_ChipSelect)
1006 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
1008 /* The EEPROM commands include the alway-set leading bit. */
1010 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1013 static int eeprom_read(void __iomem *addr, int location)
1017 void __iomem *ee_addr = addr + EECtrl;
1018 int read_cmd = location | EE_ReadCmd;
1020 writel(EE_Write0, ee_addr);
1022 /* Shift the read command bits out. */
1023 for (i = 10; i >= 0; i--) {
1024 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1025 writel(dataval, ee_addr);
1026 eeprom_delay(ee_addr);
1027 writel(dataval | EE_ShiftClk, ee_addr);
1028 eeprom_delay(ee_addr);
1030 writel(EE_ChipSelect, ee_addr);
1031 eeprom_delay(ee_addr);
1033 for (i = 0; i < 16; i++) {
1034 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1035 eeprom_delay(ee_addr);
1036 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1037 writel(EE_ChipSelect, ee_addr);
1038 eeprom_delay(ee_addr);
1041 /* Terminate the EEPROM access. */
1042 writel(EE_Write0, ee_addr);
1047 /* MII transceiver control section.
1048 * The 83815 series has an internal transceiver, and we present the
1049 * internal management registers as if they were MII connected.
1050 * External Phy registers are referenced through the MII interface.
1053 /* clock transitions >= 20ns (25MHz)
1054 * One readl should be good to PCI @ 100MHz
1056 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1058 static int mii_getbit (struct net_device *dev)
1061 void __iomem *ioaddr = ns_ioaddr(dev);
1063 writel(MII_ShiftClk, ioaddr + EECtrl);
1064 data = readl(ioaddr + EECtrl);
1065 writel(0, ioaddr + EECtrl);
1067 return (data & MII_Data)? 1 : 0;
1070 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1073 void __iomem *ioaddr = ns_ioaddr(dev);
1075 for (i = (1 << (len-1)); i; i >>= 1)
1077 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1078 writel(mdio_val, ioaddr + EECtrl);
1080 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1083 writel(0, ioaddr + EECtrl);
1087 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1094 mii_send_bits (dev, 0xffffffff, 32);
1095 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1096 /* ST,OP = 0110'b for read operation */
1097 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1098 mii_send_bits (dev, cmd, 14);
1100 if (mii_getbit (dev))
1103 for (i = 0; i < 16; i++) {
1105 retval |= mii_getbit (dev);
1112 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1117 mii_send_bits (dev, 0xffffffff, 32);
1118 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1119 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1120 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1121 mii_send_bits (dev, cmd, 32);
1126 static int mdio_read(struct net_device *dev, int reg)
1128 struct netdev_private *np = netdev_priv(dev);
1129 void __iomem *ioaddr = ns_ioaddr(dev);
1131 /* The 83815 series has two ports:
1132 * - an internal transceiver
1133 * - an external mii bus
1135 if (dev->if_port == PORT_TP)
1136 return readw(ioaddr+BasicControl+(reg<<2));
1138 return miiport_read(dev, np->phy_addr_external, reg);
1141 static void mdio_write(struct net_device *dev, int reg, u16 data)
1143 struct netdev_private *np = netdev_priv(dev);
1144 void __iomem *ioaddr = ns_ioaddr(dev);
1146 /* The 83815 series has an internal transceiver; handle separately */
1147 if (dev->if_port == PORT_TP)
1148 writew(data, ioaddr+BasicControl+(reg<<2));
1150 miiport_write(dev, np->phy_addr_external, reg, data);
1153 static void init_phy_fixup(struct net_device *dev)
1155 struct netdev_private *np = netdev_priv(dev);
1156 void __iomem *ioaddr = ns_ioaddr(dev);
1161 /* restore stuff lost when power was out */
1162 tmp = mdio_read(dev, MII_BMCR);
1163 if (np->autoneg == AUTONEG_ENABLE) {
1164 /* renegotiate if something changed */
1165 if ((tmp & BMCR_ANENABLE) == 0
1166 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1168 /* turn on autonegotiation and force negotiation */
1169 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1170 mdio_write(dev, MII_ADVERTISE, np->advertising);
1173 /* turn off auto negotiation, set speed and duplexity */
1174 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1175 if (np->speed == SPEED_100)
1176 tmp |= BMCR_SPEED100;
1177 if (np->duplex == DUPLEX_FULL)
1178 tmp |= BMCR_FULLDPLX;
1180 * Note: there is no good way to inform the link partner
1181 * that our capabilities changed. The user has to unplug
1182 * and replug the network cable after some changes, e.g.
1183 * after switching from 10HD, autoneg off to 100 HD,
1187 mdio_write(dev, MII_BMCR, tmp);
1188 readl(ioaddr + ChipConfig);
1191 /* find out what phy this is */
1192 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1193 + mdio_read(dev, MII_PHYSID2);
1195 /* handle external phys here */
1197 case PHYID_AM79C874:
1198 /* phy specific configuration for fibre/tp operation */
1199 tmp = mdio_read(dev, MII_MCTRL);
1200 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1201 if (dev->if_port == PORT_FIBRE)
1205 mdio_write(dev, MII_MCTRL, tmp);
1210 cfg = readl(ioaddr + ChipConfig);
1211 if (cfg & CfgExtPhy)
1214 /* On page 78 of the spec, they recommend some settings for "optimum
1215 performance" to be done in sequence. These settings optimize some
1216 of the 100Mbit autodetection circuitry. They say we only want to
1217 do this for rev C of the chip, but engineers at NSC (Bradley
1218 Kennedy) recommends always setting them. If you don't, you get
1219 errors on some autonegotiations that make the device unusable.
1221 It seems that the DSP needs a few usec to reinitialize after
1222 the start of the phy. Just retry writing these values until they
1225 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1228 writew(1, ioaddr + PGSEL);
1229 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1230 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1231 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1232 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1233 writew(np->dspcfg, ioaddr + DSPCFG);
1234 writew(SDCFG_VAL, ioaddr + SDCFG);
1235 writew(0, ioaddr + PGSEL);
1236 readl(ioaddr + ChipConfig);
1239 writew(1, ioaddr + PGSEL);
1240 dspcfg = readw(ioaddr + DSPCFG);
1241 writew(0, ioaddr + PGSEL);
1242 if (np->dspcfg == dspcfg)
1246 if (netif_msg_link(np)) {
1247 if (i==NATSEMI_HW_TIMEOUT) {
1249 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1253 "%s: DSPCFG accepted after %d usec.\n",
1258 * Enable PHY Specific event based interrupts. Link state change
1259 * and Auto-Negotiation Completion are among the affected.
1260 * Read the intr status to clear it (needed for wake events).
1262 readw(ioaddr + MIntrStatus);
1263 writew(MICRIntEn, ioaddr + MIntrCtrl);
1266 static int switch_port_external(struct net_device *dev)
1268 struct netdev_private *np = netdev_priv(dev);
1269 void __iomem *ioaddr = ns_ioaddr(dev);
1272 cfg = readl(ioaddr + ChipConfig);
1273 if (cfg & CfgExtPhy)
1276 if (netif_msg_link(np)) {
1277 printk(KERN_INFO "%s: switching to external transceiver.\n",
1281 /* 1) switch back to external phy */
1282 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1283 readl(ioaddr + ChipConfig);
1286 /* 2) reset the external phy: */
1287 /* resetting the external PHY has been known to cause a hub supplying
1288 * power over Ethernet to kill the power. We don't want to kill
1289 * power to this computer, so we avoid resetting the phy.
1292 /* 3) reinit the phy fixup, it got lost during power down. */
1293 move_int_phy(dev, np->phy_addr_external);
1294 init_phy_fixup(dev);
1299 static int switch_port_internal(struct net_device *dev)
1301 struct netdev_private *np = netdev_priv(dev);
1302 void __iomem *ioaddr = ns_ioaddr(dev);
1307 cfg = readl(ioaddr + ChipConfig);
1308 if (!(cfg &CfgExtPhy))
1311 if (netif_msg_link(np)) {
1312 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1315 /* 1) switch back to internal phy: */
1316 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1317 writel(cfg, ioaddr + ChipConfig);
1318 readl(ioaddr + ChipConfig);
1321 /* 2) reset the internal phy: */
1322 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1323 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1324 readl(ioaddr + ChipConfig);
1326 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1327 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1328 if (!(bmcr & BMCR_RESET))
1332 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1334 "%s: phy reset did not complete in %d usec.\n",
1337 /* 3) reinit the phy fixup, it got lost during power down. */
1338 init_phy_fixup(dev);
1343 /* Scan for a PHY on the external mii bus.
1344 * There are two tricky points:
1345 * - Do not scan while the internal phy is enabled. The internal phy will
1346 * crash: e.g. reads from the DSPCFG register will return odd values and
1347 * the nasty random phy reset code will reset the nic every few seconds.
1348 * - The internal phy must be moved around, an external phy could
1349 * have the same address as the internal phy.
1351 static int find_mii(struct net_device *dev)
1353 struct netdev_private *np = netdev_priv(dev);
1358 /* Switch to external phy */
1359 did_switch = switch_port_external(dev);
1361 /* Scan the possible phy addresses:
1363 * PHY address 0 means that the phy is in isolate mode. Not yet
1364 * supported due to lack of test hardware. User space should
1365 * handle it through ethtool.
1367 for (i = 1; i <= 31; i++) {
1368 move_int_phy(dev, i);
1369 tmp = miiport_read(dev, i, MII_BMSR);
1370 if (tmp != 0xffff && tmp != 0x0000) {
1371 /* found something! */
1372 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1373 + mdio_read(dev, MII_PHYSID2);
1374 if (netif_msg_probe(np)) {
1375 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1376 pci_name(np->pci_dev), np->mii, i);
1381 /* And switch back to internal phy: */
1383 switch_port_internal(dev);
1387 /* CFG bits [13:16] [18:23] */
1388 #define CFG_RESET_SAVE 0xfde000
1389 /* WCSR bits [0:4] [9:10] */
1390 #define WCSR_RESET_SAVE 0x61f
1391 /* RFCR bits [20] [22] [27:31] */
1392 #define RFCR_RESET_SAVE 0xf8500000;
1394 static void natsemi_reset(struct net_device *dev)
1402 struct netdev_private *np = netdev_priv(dev);
1403 void __iomem *ioaddr = ns_ioaddr(dev);
1406 * Resetting the chip causes some registers to be lost.
1407 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1408 * we save the state that would have been loaded from EEPROM
1409 * on a normal power-up (see the spec EEPROM map). This assumes
1410 * whoever calls this will follow up with init_registers() eventually.
1414 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1416 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1418 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1420 for (i = 0; i < 3; i++) {
1421 writel(i*2, ioaddr + RxFilterAddr);
1422 pmatch[i] = readw(ioaddr + RxFilterData);
1425 for (i = 0; i < 3; i++) {
1426 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1427 sopass[i] = readw(ioaddr + RxFilterData);
1430 /* now whack the chip */
1431 writel(ChipReset, ioaddr + ChipCmd);
1432 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1433 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1437 if (i==NATSEMI_HW_TIMEOUT) {
1438 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1440 } else if (netif_msg_hw(np)) {
1441 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1446 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1447 /* turn on external phy if it was selected */
1448 if (dev->if_port == PORT_TP)
1449 cfg &= ~(CfgExtPhy | CfgPhyDis);
1451 cfg |= (CfgExtPhy | CfgPhyDis);
1452 writel(cfg, ioaddr + ChipConfig);
1454 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1455 writel(wcsr, ioaddr + WOLCmd);
1457 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1458 /* restore PMATCH */
1459 for (i = 0; i < 3; i++) {
1460 writel(i*2, ioaddr + RxFilterAddr);
1461 writew(pmatch[i], ioaddr + RxFilterData);
1463 for (i = 0; i < 3; i++) {
1464 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1465 writew(sopass[i], ioaddr + RxFilterData);
1468 writel(rfcr, ioaddr + RxFilterAddr);
1471 static void reset_rx(struct net_device *dev)
1474 struct netdev_private *np = netdev_priv(dev);
1475 void __iomem *ioaddr = ns_ioaddr(dev);
1477 np->intr_status &= ~RxResetDone;
1479 writel(RxReset, ioaddr + ChipCmd);
1481 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1482 np->intr_status |= readl(ioaddr + IntrStatus);
1483 if (np->intr_status & RxResetDone)
1487 if (i==NATSEMI_HW_TIMEOUT) {
1488 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1490 } else if (netif_msg_hw(np)) {
1491 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1496 static void natsemi_reload_eeprom(struct net_device *dev)
1498 struct netdev_private *np = netdev_priv(dev);
1499 void __iomem *ioaddr = ns_ioaddr(dev);
1502 writel(EepromReload, ioaddr + PCIBusCfg);
1503 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1505 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1508 if (i==NATSEMI_HW_TIMEOUT) {
1509 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1510 pci_name(np->pci_dev), i*50);
1511 } else if (netif_msg_hw(np)) {
1512 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1513 pci_name(np->pci_dev), i*50);
1517 static void natsemi_stop_rxtx(struct net_device *dev)
1519 void __iomem * ioaddr = ns_ioaddr(dev);
1520 struct netdev_private *np = netdev_priv(dev);
1523 writel(RxOff | TxOff, ioaddr + ChipCmd);
1524 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1525 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1529 if (i==NATSEMI_HW_TIMEOUT) {
1530 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1532 } else if (netif_msg_hw(np)) {
1533 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1538 static int netdev_open(struct net_device *dev)
1540 struct netdev_private *np = netdev_priv(dev);
1541 void __iomem * ioaddr = ns_ioaddr(dev);
1544 /* Reset the chip, just in case. */
1547 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1550 if (netif_msg_ifup(np))
1551 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1552 dev->name, dev->irq);
1553 i = alloc_ring(dev);
1555 free_irq(dev->irq, dev);
1559 spin_lock_irq(&np->lock);
1560 init_registers(dev);
1561 /* now set the MAC address according to dev->dev_addr */
1562 for (i = 0; i < 3; i++) {
1563 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1565 writel(i*2, ioaddr + RxFilterAddr);
1566 writew(mac, ioaddr + RxFilterData);
1568 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1569 spin_unlock_irq(&np->lock);
1571 netif_start_queue(dev);
1573 if (netif_msg_ifup(np))
1574 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1575 dev->name, (int)readl(ioaddr + ChipCmd));
1577 /* Set the timer to check for link beat. */
1578 init_timer(&np->timer);
1579 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1580 np->timer.data = (unsigned long)dev;
1581 np->timer.function = &netdev_timer; /* timer handler */
1582 add_timer(&np->timer);
1587 static void do_cable_magic(struct net_device *dev)
1589 struct netdev_private *np = netdev_priv(dev);
1590 void __iomem *ioaddr = ns_ioaddr(dev);
1592 if (dev->if_port != PORT_TP)
1595 if (np->srr >= SRR_DP83816_A5)
1599 * 100 MBit links with short cables can trip an issue with the chip.
1600 * The problem manifests as lots of CRC errors and/or flickering
1601 * activity LED while idle. This process is based on instructions
1602 * from engineers at National.
1604 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1607 writew(1, ioaddr + PGSEL);
1609 * coefficient visibility should already be enabled via
1612 data = readw(ioaddr + TSTDAT) & 0xff;
1614 * the value must be negative, and within certain values
1615 * (these values all come from National)
1617 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1618 struct netdev_private *np = netdev_priv(dev);
1620 /* the bug has been triggered - fix the coefficient */
1621 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1622 /* lock the value */
1623 data = readw(ioaddr + DSPCFG);
1624 np->dspcfg = data | DSPCFG_LOCK;
1625 writew(np->dspcfg, ioaddr + DSPCFG);
1627 writew(0, ioaddr + PGSEL);
1631 static void undo_cable_magic(struct net_device *dev)
1634 struct netdev_private *np = netdev_priv(dev);
1635 void __iomem * ioaddr = ns_ioaddr(dev);
1637 if (dev->if_port != PORT_TP)
1640 if (np->srr >= SRR_DP83816_A5)
1643 writew(1, ioaddr + PGSEL);
1644 /* make sure the lock bit is clear */
1645 data = readw(ioaddr + DSPCFG);
1646 np->dspcfg = data & ~DSPCFG_LOCK;
1647 writew(np->dspcfg, ioaddr + DSPCFG);
1648 writew(0, ioaddr + PGSEL);
1651 static void check_link(struct net_device *dev)
1653 struct netdev_private *np = netdev_priv(dev);
1654 void __iomem * ioaddr = ns_ioaddr(dev);
1655 int duplex = np->duplex;
1658 /* If we are ignoring the PHY then don't try reading it. */
1660 goto propagate_state;
1662 /* The link status field is latched: it remains low after a temporary
1663 * link failure until it's read. We need the current link status,
1666 mdio_read(dev, MII_BMSR);
1667 bmsr = mdio_read(dev, MII_BMSR);
1669 if (!(bmsr & BMSR_LSTATUS)) {
1670 if (netif_carrier_ok(dev)) {
1671 if (netif_msg_link(np))
1672 printk(KERN_NOTICE "%s: link down.\n",
1674 netif_carrier_off(dev);
1675 undo_cable_magic(dev);
1679 if (!netif_carrier_ok(dev)) {
1680 if (netif_msg_link(np))
1681 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1682 netif_carrier_on(dev);
1683 do_cable_magic(dev);
1686 duplex = np->full_duplex;
1688 if (bmsr & BMSR_ANEGCOMPLETE) {
1689 int tmp = mii_nway_result(
1690 np->advertising & mdio_read(dev, MII_LPA));
1691 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1693 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1698 /* if duplex is set then bit 28 must be set, too */
1699 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1700 if (netif_msg_link(np))
1702 "%s: Setting %s-duplex based on negotiated "
1703 "link capability.\n", dev->name,
1704 duplex ? "full" : "half");
1706 np->rx_config |= RxAcceptTx;
1707 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1709 np->rx_config &= ~RxAcceptTx;
1710 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1712 writel(np->tx_config, ioaddr + TxConfig);
1713 writel(np->rx_config, ioaddr + RxConfig);
1717 static void init_registers(struct net_device *dev)
1719 struct netdev_private *np = netdev_priv(dev);
1720 void __iomem * ioaddr = ns_ioaddr(dev);
1722 init_phy_fixup(dev);
1724 /* clear any interrupts that are pending, such as wake events */
1725 readl(ioaddr + IntrStatus);
1727 writel(np->ring_dma, ioaddr + RxRingPtr);
1728 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1729 ioaddr + TxRingPtr);
1731 /* Initialize other registers.
1732 * Configure the PCI bus bursts and FIFO thresholds.
1733 * Configure for standard, in-spec Ethernet.
1734 * Start with half-duplex. check_link will update
1735 * to the correct settings.
1738 /* DRTH: 2: start tx if 64 bytes are in the fifo
1739 * FLTH: 0x10: refill with next packet if 512 bytes are free
1740 * MXDMA: 0: up to 256 byte bursts.
1741 * MXDMA must be <= FLTH
1745 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1746 TX_FLTH_VAL | TX_DRTH_VAL_START;
1747 writel(np->tx_config, ioaddr + TxConfig);
1749 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1750 * MXDMA 0: up to 256 byte bursts
1752 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1753 /* if receive ring now has bigger buffers than normal, enable jumbo */
1754 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1755 np->rx_config |= RxAcceptLong;
1757 writel(np->rx_config, ioaddr + RxConfig);
1760 * The PME bit is initialized from the EEPROM contents.
1761 * PCI cards probably have PME disabled, but motherboard
1762 * implementations may have PME set to enable WakeOnLan.
1763 * With PME set the chip will scan incoming packets but
1764 * nothing will be written to memory. */
1765 np->SavedClkRun = readl(ioaddr + ClkRun);
1766 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1767 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1768 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1769 dev->name, readl(ioaddr + WOLCmd));
1775 /* Enable interrupts by setting the interrupt mask. */
1776 writel(DEFAULT_INTR, ioaddr + IntrMask);
1777 natsemi_irq_enable(dev);
1779 writel(RxOn | TxOn, ioaddr + ChipCmd);
1780 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1786 * 1) check for link changes. Usually they are handled by the MII interrupt
1787 * but it doesn't hurt to check twice.
1788 * 2) check for sudden death of the NIC:
1789 * It seems that a reference set for this chip went out with incorrect info,
1790 * and there exist boards that aren't quite right. An unexpected voltage
1791 * drop can cause the PHY to get itself in a weird state (basically reset).
1792 * NOTE: this only seems to affect revC chips. The user can disable
1793 * this check via dspcfg_workaround sysfs option.
1794 * 3) check of death of the RX path due to OOM
1796 static void netdev_timer(unsigned long data)
1798 struct net_device *dev = (struct net_device *)data;
1799 struct netdev_private *np = netdev_priv(dev);
1800 void __iomem * ioaddr = ns_ioaddr(dev);
1801 int next_tick = 5*HZ;
1803 if (netif_msg_timer(np)) {
1804 /* DO NOT read the IntrStatus register,
1805 * a read clears any pending interrupts.
1807 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1811 if (dev->if_port == PORT_TP) {
1814 spin_lock_irq(&np->lock);
1815 /* check for a nasty random phy-reset - use dspcfg as a flag */
1816 writew(1, ioaddr+PGSEL);
1817 dspcfg = readw(ioaddr+DSPCFG);
1818 writew(0, ioaddr+PGSEL);
1819 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1820 if (!netif_queue_stopped(dev)) {
1821 spin_unlock_irq(&np->lock);
1822 if (netif_msg_drv(np))
1823 printk(KERN_NOTICE "%s: possible phy reset: "
1824 "re-initializing\n", dev->name);
1825 disable_irq(dev->irq);
1826 spin_lock_irq(&np->lock);
1827 natsemi_stop_rxtx(dev);
1830 init_registers(dev);
1831 spin_unlock_irq(&np->lock);
1832 enable_irq(dev->irq);
1836 spin_unlock_irq(&np->lock);
1839 /* init_registers() calls check_link() for the above case */
1841 spin_unlock_irq(&np->lock);
1844 spin_lock_irq(&np->lock);
1846 spin_unlock_irq(&np->lock);
1849 disable_irq(dev->irq);
1852 enable_irq(dev->irq);
1854 writel(RxOn, ioaddr + ChipCmd);
1859 mod_timer(&np->timer, jiffies + next_tick);
1862 static void dump_ring(struct net_device *dev)
1864 struct netdev_private *np = netdev_priv(dev);
1866 if (netif_msg_pktdata(np)) {
1868 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1869 for (i = 0; i < TX_RING_SIZE; i++) {
1870 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1871 i, np->tx_ring[i].next_desc,
1872 np->tx_ring[i].cmd_status,
1873 np->tx_ring[i].addr);
1875 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1876 for (i = 0; i < RX_RING_SIZE; i++) {
1877 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1878 i, np->rx_ring[i].next_desc,
1879 np->rx_ring[i].cmd_status,
1880 np->rx_ring[i].addr);
1885 static void tx_timeout(struct net_device *dev)
1887 struct netdev_private *np = netdev_priv(dev);
1888 void __iomem * ioaddr = ns_ioaddr(dev);
1890 disable_irq(dev->irq);
1891 spin_lock_irq(&np->lock);
1892 if (!np->hands_off) {
1893 if (netif_msg_tx_err(np))
1895 "%s: Transmit timed out, status %#08x,"
1897 dev->name, readl(ioaddr + IntrStatus));
1902 init_registers(dev);
1905 "%s: tx_timeout while in hands_off state?\n",
1908 spin_unlock_irq(&np->lock);
1909 enable_irq(dev->irq);
1911 dev->trans_start = jiffies;
1912 np->stats.tx_errors++;
1913 netif_wake_queue(dev);
1916 static int alloc_ring(struct net_device *dev)
1918 struct netdev_private *np = netdev_priv(dev);
1919 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1920 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1924 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1928 static void refill_rx(struct net_device *dev)
1930 struct netdev_private *np = netdev_priv(dev);
1932 /* Refill the Rx ring buffers. */
1933 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1934 struct sk_buff *skb;
1935 int entry = np->dirty_rx % RX_RING_SIZE;
1936 if (np->rx_skbuff[entry] == NULL) {
1937 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1938 skb = dev_alloc_skb(buflen);
1939 np->rx_skbuff[entry] = skb;
1941 break; /* Better luck next round. */
1942 skb->dev = dev; /* Mark as being used by this device. */
1943 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1944 skb->data, buflen, PCI_DMA_FROMDEVICE);
1945 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1947 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1949 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1950 if (netif_msg_rx_err(np))
1951 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1956 static void set_bufsize(struct net_device *dev)
1958 struct netdev_private *np = netdev_priv(dev);
1959 if (dev->mtu <= ETH_DATA_LEN)
1960 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1962 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1965 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1966 static void init_ring(struct net_device *dev)
1968 struct netdev_private *np = netdev_priv(dev);
1972 np->dirty_tx = np->cur_tx = 0;
1973 for (i = 0; i < TX_RING_SIZE; i++) {
1974 np->tx_skbuff[i] = NULL;
1975 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1976 +sizeof(struct netdev_desc)
1977 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1978 np->tx_ring[i].cmd_status = 0;
1983 np->cur_rx = RX_RING_SIZE;
1987 np->rx_head_desc = &np->rx_ring[0];
1989 /* Please be carefull before changing this loop - at least gcc-2.95.1
1990 * miscompiles it otherwise.
1992 /* Initialize all Rx descriptors. */
1993 for (i = 0; i < RX_RING_SIZE; i++) {
1994 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1995 +sizeof(struct netdev_desc)
1996 *((i+1)%RX_RING_SIZE));
1997 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1998 np->rx_skbuff[i] = NULL;
2004 static void drain_tx(struct net_device *dev)
2006 struct netdev_private *np = netdev_priv(dev);
2009 for (i = 0; i < TX_RING_SIZE; i++) {
2010 if (np->tx_skbuff[i]) {
2011 pci_unmap_single(np->pci_dev,
2012 np->tx_dma[i], np->tx_skbuff[i]->len,
2014 dev_kfree_skb(np->tx_skbuff[i]);
2015 np->stats.tx_dropped++;
2017 np->tx_skbuff[i] = NULL;
2021 static void drain_rx(struct net_device *dev)
2023 struct netdev_private *np = netdev_priv(dev);
2024 unsigned int buflen = np->rx_buf_sz;
2027 /* Free all the skbuffs in the Rx queue. */
2028 for (i = 0; i < RX_RING_SIZE; i++) {
2029 np->rx_ring[i].cmd_status = 0;
2030 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2031 if (np->rx_skbuff[i]) {
2032 pci_unmap_single(np->pci_dev,
2033 np->rx_dma[i], buflen,
2034 PCI_DMA_FROMDEVICE);
2035 dev_kfree_skb(np->rx_skbuff[i]);
2037 np->rx_skbuff[i] = NULL;
2041 static void drain_ring(struct net_device *dev)
2047 static void free_ring(struct net_device *dev)
2049 struct netdev_private *np = netdev_priv(dev);
2050 pci_free_consistent(np->pci_dev,
2051 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2052 np->rx_ring, np->ring_dma);
2055 static void reinit_rx(struct net_device *dev)
2057 struct netdev_private *np = netdev_priv(dev);
2062 np->cur_rx = RX_RING_SIZE;
2063 np->rx_head_desc = &np->rx_ring[0];
2064 /* Initialize all Rx descriptors. */
2065 for (i = 0; i < RX_RING_SIZE; i++)
2066 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2071 static void reinit_ring(struct net_device *dev)
2073 struct netdev_private *np = netdev_priv(dev);
2078 np->dirty_tx = np->cur_tx = 0;
2079 for (i=0;i<TX_RING_SIZE;i++)
2080 np->tx_ring[i].cmd_status = 0;
2085 static int start_tx(struct sk_buff *skb, struct net_device *dev)
2087 struct netdev_private *np = netdev_priv(dev);
2088 void __iomem * ioaddr = ns_ioaddr(dev);
2090 unsigned long flags;
2092 /* Note: Ordering is important here, set the field with the
2093 "ownership" bit last, and only then increment cur_tx. */
2095 /* Calculate the next Tx descriptor entry. */
2096 entry = np->cur_tx % TX_RING_SIZE;
2098 np->tx_skbuff[entry] = skb;
2099 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2100 skb->data,skb->len, PCI_DMA_TODEVICE);
2102 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2104 spin_lock_irqsave(&np->lock, flags);
2106 if (!np->hands_off) {
2107 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2108 /* StrongARM: Explicitly cache flush np->tx_ring and
2109 * skb->data,skb->len. */
2112 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2113 netdev_tx_done(dev);
2114 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2115 netif_stop_queue(dev);
2117 /* Wake the potentially-idle transmit channel. */
2118 writel(TxOn, ioaddr + ChipCmd);
2120 dev_kfree_skb_irq(skb);
2121 np->stats.tx_dropped++;
2123 spin_unlock_irqrestore(&np->lock, flags);
2125 dev->trans_start = jiffies;
2127 if (netif_msg_tx_queued(np)) {
2128 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2129 dev->name, np->cur_tx, entry);
2134 static void netdev_tx_done(struct net_device *dev)
2136 struct netdev_private *np = netdev_priv(dev);
2138 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2139 int entry = np->dirty_tx % TX_RING_SIZE;
2140 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2142 if (netif_msg_tx_done(np))
2144 "%s: tx frame #%d finished, status %#08x.\n",
2145 dev->name, np->dirty_tx,
2146 le32_to_cpu(np->tx_ring[entry].cmd_status));
2147 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2148 np->stats.tx_packets++;
2149 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2150 } else { /* Various Tx errors */
2152 le32_to_cpu(np->tx_ring[entry].cmd_status);
2153 if (tx_status & (DescTxAbort|DescTxExcColl))
2154 np->stats.tx_aborted_errors++;
2155 if (tx_status & DescTxFIFO)
2156 np->stats.tx_fifo_errors++;
2157 if (tx_status & DescTxCarrier)
2158 np->stats.tx_carrier_errors++;
2159 if (tx_status & DescTxOOWCol)
2160 np->stats.tx_window_errors++;
2161 np->stats.tx_errors++;
2163 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2164 np->tx_skbuff[entry]->len,
2166 /* Free the original skb. */
2167 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2168 np->tx_skbuff[entry] = NULL;
2170 if (netif_queue_stopped(dev)
2171 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2172 /* The ring is no longer full, wake queue. */
2173 netif_wake_queue(dev);
2177 /* The interrupt handler doesn't actually handle interrupts itself, it
2178 * schedules a NAPI poll if there is anything to do. */
2179 static irqreturn_t intr_handler(int irq, void *dev_instance)
2181 struct net_device *dev = dev_instance;
2182 struct netdev_private *np = netdev_priv(dev);
2183 void __iomem * ioaddr = ns_ioaddr(dev);
2185 /* Reading IntrStatus automatically acknowledges so don't do
2186 * that while interrupts are disabled, (for example, while a
2187 * poll is scheduled). */
2188 if (np->hands_off || !readl(ioaddr + IntrEnable))
2191 np->intr_status = readl(ioaddr + IntrStatus);
2193 if (!np->intr_status)
2196 if (netif_msg_intr(np))
2198 "%s: Interrupt, status %#08x, mask %#08x.\n",
2199 dev->name, np->intr_status,
2200 readl(ioaddr + IntrMask));
2202 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2204 if (netif_rx_schedule_prep(dev)) {
2205 /* Disable interrupts and register for poll */
2206 natsemi_irq_disable(dev);
2207 __netif_rx_schedule(dev);
2210 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2211 dev->name, np->intr_status,
2212 readl(ioaddr + IntrMask));
2217 /* This is the NAPI poll routine. As well as the standard RX handling
2218 * it also handles all other interrupts that the chip might raise.
2220 static int natsemi_poll(struct net_device *dev, int *budget)
2222 struct netdev_private *np = netdev_priv(dev);
2223 void __iomem * ioaddr = ns_ioaddr(dev);
2225 int work_to_do = min(*budget, dev->quota);
2229 if (netif_msg_intr(np))
2231 "%s: Poll, status %#08x, mask %#08x.\n",
2232 dev->name, np->intr_status,
2233 readl(ioaddr + IntrMask));
2235 /* netdev_rx() may read IntrStatus again if the RX state
2236 * machine falls over so do it first. */
2237 if (np->intr_status &
2238 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2239 IntrRxErr | IntrRxOverrun)) {
2240 netdev_rx(dev, &work_done, work_to_do);
2243 if (np->intr_status &
2244 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2245 spin_lock(&np->lock);
2246 netdev_tx_done(dev);
2247 spin_unlock(&np->lock);
2250 /* Abnormal error summary/uncommon events handlers. */
2251 if (np->intr_status & IntrAbnormalSummary)
2252 netdev_error(dev, np->intr_status);
2254 *budget -= work_done;
2255 dev->quota -= work_done;
2257 if (work_done >= work_to_do)
2260 np->intr_status = readl(ioaddr + IntrStatus);
2261 } while (np->intr_status);
2263 netif_rx_complete(dev);
2265 /* Reenable interrupts providing nothing is trying to shut
2267 spin_lock(&np->lock);
2268 if (!np->hands_off && netif_running(dev))
2269 natsemi_irq_enable(dev);
2270 spin_unlock(&np->lock);
2275 /* This routine is logically part of the interrupt handler, but separated
2276 for clarity and better register allocation. */
2277 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2279 struct netdev_private *np = netdev_priv(dev);
2280 int entry = np->cur_rx % RX_RING_SIZE;
2281 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2282 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2283 unsigned int buflen = np->rx_buf_sz;
2284 void __iomem * ioaddr = ns_ioaddr(dev);
2286 /* If the driver owns the next entry it's a new packet. Send it up. */
2287 while (desc_status < 0) { /* e.g. & DescOwn */
2289 if (netif_msg_rx_status(np))
2291 " netdev_rx() entry %d status was %#08x.\n",
2292 entry, desc_status);
2296 if (*work_done >= work_to_do)
2301 pkt_len = (desc_status & DescSizeMask) - 4;
2302 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2303 if (desc_status & DescMore) {
2304 unsigned long flags;
2306 if (netif_msg_rx_err(np))
2308 "%s: Oversized(?) Ethernet "
2309 "frame spanned multiple "
2310 "buffers, entry %#08x "
2311 "status %#08x.\n", dev->name,
2312 np->cur_rx, desc_status);
2313 np->stats.rx_length_errors++;
2315 /* The RX state machine has probably
2316 * locked up beneath us. Follow the
2317 * reset procedure documented in
2320 spin_lock_irqsave(&np->lock, flags);
2323 writel(np->ring_dma, ioaddr + RxRingPtr);
2325 spin_unlock_irqrestore(&np->lock, flags);
2327 /* We'll enable RX on exit from this
2332 /* There was an error. */
2333 np->stats.rx_errors++;
2334 if (desc_status & (DescRxAbort|DescRxOver))
2335 np->stats.rx_over_errors++;
2336 if (desc_status & (DescRxLong|DescRxRunt))
2337 np->stats.rx_length_errors++;
2338 if (desc_status & (DescRxInvalid|DescRxAlign))
2339 np->stats.rx_frame_errors++;
2340 if (desc_status & DescRxCRC)
2341 np->stats.rx_crc_errors++;
2343 } else if (pkt_len > np->rx_buf_sz) {
2344 /* if this is the tail of a double buffer
2345 * packet, we've already counted the error
2346 * on the first part. Ignore the second half.
2349 struct sk_buff *skb;
2350 /* Omit CRC size. */
2351 /* Check if the packet is long enough to accept
2352 * without copying to a minimally-sized skbuff. */
2353 if (pkt_len < rx_copybreak
2354 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2355 /* 16 byte align the IP header */
2356 skb_reserve(skb, RX_OFFSET);
2357 pci_dma_sync_single_for_cpu(np->pci_dev,
2360 PCI_DMA_FROMDEVICE);
2361 eth_copy_and_sum(skb,
2362 np->rx_skbuff[entry]->data, pkt_len, 0);
2363 skb_put(skb, pkt_len);
2364 pci_dma_sync_single_for_device(np->pci_dev,
2367 PCI_DMA_FROMDEVICE);
2369 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2370 buflen, PCI_DMA_FROMDEVICE);
2371 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2372 np->rx_skbuff[entry] = NULL;
2374 skb->protocol = eth_type_trans(skb, dev);
2375 netif_receive_skb(skb);
2376 dev->last_rx = jiffies;
2377 np->stats.rx_packets++;
2378 np->stats.rx_bytes += pkt_len;
2380 entry = (++np->cur_rx) % RX_RING_SIZE;
2381 np->rx_head_desc = &np->rx_ring[entry];
2382 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2386 /* Restart Rx engine if stopped. */
2388 mod_timer(&np->timer, jiffies + 1);
2390 writel(RxOn, ioaddr + ChipCmd);
2393 static void netdev_error(struct net_device *dev, int intr_status)
2395 struct netdev_private *np = netdev_priv(dev);
2396 void __iomem * ioaddr = ns_ioaddr(dev);
2398 spin_lock(&np->lock);
2399 if (intr_status & LinkChange) {
2400 u16 lpa = mdio_read(dev, MII_LPA);
2401 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2402 && netif_msg_link(np)) {
2404 "%s: Autonegotiation advertising"
2405 " %#04x partner %#04x.\n", dev->name,
2406 np->advertising, lpa);
2409 /* read MII int status to clear the flag */
2410 readw(ioaddr + MIntrStatus);
2413 if (intr_status & StatsMax) {
2416 if (intr_status & IntrTxUnderrun) {
2417 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2418 np->tx_config += TX_DRTH_VAL_INC;
2419 if (netif_msg_tx_err(np))
2421 "%s: increased tx threshold, txcfg %#08x.\n",
2422 dev->name, np->tx_config);
2424 if (netif_msg_tx_err(np))
2426 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2427 dev->name, np->tx_config);
2429 writel(np->tx_config, ioaddr + TxConfig);
2431 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2432 int wol_status = readl(ioaddr + WOLCmd);
2433 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2434 dev->name, wol_status);
2436 if (intr_status & RxStatusFIFOOver) {
2437 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2438 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2441 np->stats.rx_fifo_errors++;
2443 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2444 if (intr_status & IntrPCIErr) {
2445 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2446 intr_status & IntrPCIErr);
2447 np->stats.tx_fifo_errors++;
2448 np->stats.rx_fifo_errors++;
2450 spin_unlock(&np->lock);
2453 static void __get_stats(struct net_device *dev)
2455 void __iomem * ioaddr = ns_ioaddr(dev);
2456 struct netdev_private *np = netdev_priv(dev);
2458 /* The chip only need report frame silently dropped. */
2459 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2460 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2463 static struct net_device_stats *get_stats(struct net_device *dev)
2465 struct netdev_private *np = netdev_priv(dev);
2467 /* The chip only need report frame silently dropped. */
2468 spin_lock_irq(&np->lock);
2469 if (netif_running(dev) && !np->hands_off)
2471 spin_unlock_irq(&np->lock);
2476 #ifdef CONFIG_NET_POLL_CONTROLLER
2477 static void natsemi_poll_controller(struct net_device *dev)
2479 disable_irq(dev->irq);
2480 intr_handler(dev->irq, dev);
2481 enable_irq(dev->irq);
2485 #define HASH_TABLE 0x200
2486 static void __set_rx_mode(struct net_device *dev)
2488 void __iomem * ioaddr = ns_ioaddr(dev);
2489 struct netdev_private *np = netdev_priv(dev);
2490 u8 mc_filter[64]; /* Multicast hash filter */
2493 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2494 rx_mode = RxFilterEnable | AcceptBroadcast
2495 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2496 } else if ((dev->mc_count > multicast_filter_limit)
2497 || (dev->flags & IFF_ALLMULTI)) {
2498 rx_mode = RxFilterEnable | AcceptBroadcast
2499 | AcceptAllMulticast | AcceptMyPhys;
2501 struct dev_mc_list *mclist;
2503 memset(mc_filter, 0, sizeof(mc_filter));
2504 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2505 i++, mclist = mclist->next) {
2506 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2507 mc_filter[i/8] |= (1 << (i & 0x07));
2509 rx_mode = RxFilterEnable | AcceptBroadcast
2510 | AcceptMulticast | AcceptMyPhys;
2511 for (i = 0; i < 64; i += 2) {
2512 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2513 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2514 ioaddr + RxFilterData);
2517 writel(rx_mode, ioaddr + RxFilterAddr);
2518 np->cur_rx_mode = rx_mode;
2521 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2523 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2528 /* synchronized against open : rtnl_lock() held by caller */
2529 if (netif_running(dev)) {
2530 struct netdev_private *np = netdev_priv(dev);
2531 void __iomem * ioaddr = ns_ioaddr(dev);
2533 disable_irq(dev->irq);
2534 spin_lock(&np->lock);
2536 natsemi_stop_rxtx(dev);
2537 /* drain rx queue */
2539 /* change buffers */
2542 writel(np->ring_dma, ioaddr + RxRingPtr);
2543 /* restart engines */
2544 writel(RxOn | TxOn, ioaddr + ChipCmd);
2545 spin_unlock(&np->lock);
2546 enable_irq(dev->irq);
2551 static void set_rx_mode(struct net_device *dev)
2553 struct netdev_private *np = netdev_priv(dev);
2554 spin_lock_irq(&np->lock);
2557 spin_unlock_irq(&np->lock);
2560 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2562 struct netdev_private *np = netdev_priv(dev);
2563 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2564 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2565 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2568 static int get_regs_len(struct net_device *dev)
2570 return NATSEMI_REGS_SIZE;
2573 static int get_eeprom_len(struct net_device *dev)
2575 struct netdev_private *np = netdev_priv(dev);
2576 return np->eeprom_size;
2579 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2581 struct netdev_private *np = netdev_priv(dev);
2582 spin_lock_irq(&np->lock);
2583 netdev_get_ecmd(dev, ecmd);
2584 spin_unlock_irq(&np->lock);
2588 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2590 struct netdev_private *np = netdev_priv(dev);
2592 spin_lock_irq(&np->lock);
2593 res = netdev_set_ecmd(dev, ecmd);
2594 spin_unlock_irq(&np->lock);
2598 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2600 struct netdev_private *np = netdev_priv(dev);
2601 spin_lock_irq(&np->lock);
2602 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2603 netdev_get_sopass(dev, wol->sopass);
2604 spin_unlock_irq(&np->lock);
2607 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2609 struct netdev_private *np = netdev_priv(dev);
2611 spin_lock_irq(&np->lock);
2612 netdev_set_wol(dev, wol->wolopts);
2613 res = netdev_set_sopass(dev, wol->sopass);
2614 spin_unlock_irq(&np->lock);
2618 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2620 struct netdev_private *np = netdev_priv(dev);
2621 regs->version = NATSEMI_REGS_VER;
2622 spin_lock_irq(&np->lock);
2623 netdev_get_regs(dev, buf);
2624 spin_unlock_irq(&np->lock);
2627 static u32 get_msglevel(struct net_device *dev)
2629 struct netdev_private *np = netdev_priv(dev);
2630 return np->msg_enable;
2633 static void set_msglevel(struct net_device *dev, u32 val)
2635 struct netdev_private *np = netdev_priv(dev);
2636 np->msg_enable = val;
2639 static int nway_reset(struct net_device *dev)
2643 /* if autoneg is off, it's an error */
2644 tmp = mdio_read(dev, MII_BMCR);
2645 if (tmp & BMCR_ANENABLE) {
2646 tmp |= (BMCR_ANRESTART);
2647 mdio_write(dev, MII_BMCR, tmp);
2653 static u32 get_link(struct net_device *dev)
2655 /* LSTATUS is latched low until a read - so read twice */
2656 mdio_read(dev, MII_BMSR);
2657 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2660 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2662 struct netdev_private *np = netdev_priv(dev);
2666 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2670 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2671 spin_lock_irq(&np->lock);
2672 res = netdev_get_eeprom(dev, eebuf);
2673 spin_unlock_irq(&np->lock);
2675 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2680 static const struct ethtool_ops ethtool_ops = {
2681 .get_drvinfo = get_drvinfo,
2682 .get_regs_len = get_regs_len,
2683 .get_eeprom_len = get_eeprom_len,
2684 .get_settings = get_settings,
2685 .set_settings = set_settings,
2688 .get_regs = get_regs,
2689 .get_msglevel = get_msglevel,
2690 .set_msglevel = set_msglevel,
2691 .nway_reset = nway_reset,
2692 .get_link = get_link,
2693 .get_eeprom = get_eeprom,
2696 static int netdev_set_wol(struct net_device *dev, u32 newval)
2698 struct netdev_private *np = netdev_priv(dev);
2699 void __iomem * ioaddr = ns_ioaddr(dev);
2700 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2702 /* translate to bitmasks this chip understands */
2703 if (newval & WAKE_PHY)
2705 if (newval & WAKE_UCAST)
2706 data |= WakeUnicast;
2707 if (newval & WAKE_MCAST)
2708 data |= WakeMulticast;
2709 if (newval & WAKE_BCAST)
2710 data |= WakeBroadcast;
2711 if (newval & WAKE_ARP)
2713 if (newval & WAKE_MAGIC)
2715 if (np->srr >= SRR_DP83815_D) {
2716 if (newval & WAKE_MAGICSECURE) {
2717 data |= WakeMagicSecure;
2721 writel(data, ioaddr + WOLCmd);
2726 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2728 struct netdev_private *np = netdev_priv(dev);
2729 void __iomem * ioaddr = ns_ioaddr(dev);
2730 u32 regval = readl(ioaddr + WOLCmd);
2732 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2733 | WAKE_ARP | WAKE_MAGIC);
2735 if (np->srr >= SRR_DP83815_D) {
2736 /* SOPASS works on revD and higher */
2737 *supported |= WAKE_MAGICSECURE;
2741 /* translate from chip bitmasks */
2742 if (regval & WakePhy)
2744 if (regval & WakeUnicast)
2746 if (regval & WakeMulticast)
2748 if (regval & WakeBroadcast)
2750 if (regval & WakeArp)
2752 if (regval & WakeMagic)
2754 if (regval & WakeMagicSecure) {
2755 /* this can be on in revC, but it's broken */
2756 *cur |= WAKE_MAGICSECURE;
2762 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2764 struct netdev_private *np = netdev_priv(dev);
2765 void __iomem * ioaddr = ns_ioaddr(dev);
2766 u16 *sval = (u16 *)newval;
2769 if (np->srr < SRR_DP83815_D) {
2773 /* enable writing to these registers by disabling the RX filter */
2774 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2775 addr &= ~RxFilterEnable;
2776 writel(addr, ioaddr + RxFilterAddr);
2778 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2779 writel(addr | 0xa, ioaddr + RxFilterAddr);
2780 writew(sval[0], ioaddr + RxFilterData);
2782 writel(addr | 0xc, ioaddr + RxFilterAddr);
2783 writew(sval[1], ioaddr + RxFilterData);
2785 writel(addr | 0xe, ioaddr + RxFilterAddr);
2786 writew(sval[2], ioaddr + RxFilterData);
2788 /* re-enable the RX filter */
2789 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2794 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2796 struct netdev_private *np = netdev_priv(dev);
2797 void __iomem * ioaddr = ns_ioaddr(dev);
2798 u16 *sval = (u16 *)data;
2801 if (np->srr < SRR_DP83815_D) {
2802 sval[0] = sval[1] = sval[2] = 0;
2806 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2807 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2809 writel(addr | 0xa, ioaddr + RxFilterAddr);
2810 sval[0] = readw(ioaddr + RxFilterData);
2812 writel(addr | 0xc, ioaddr + RxFilterAddr);
2813 sval[1] = readw(ioaddr + RxFilterData);
2815 writel(addr | 0xe, ioaddr + RxFilterAddr);
2816 sval[2] = readw(ioaddr + RxFilterData);
2818 writel(addr, ioaddr + RxFilterAddr);
2823 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2825 struct netdev_private *np = netdev_priv(dev);
2828 ecmd->port = dev->if_port;
2829 ecmd->speed = np->speed;
2830 ecmd->duplex = np->duplex;
2831 ecmd->autoneg = np->autoneg;
2832 ecmd->advertising = 0;
2833 if (np->advertising & ADVERTISE_10HALF)
2834 ecmd->advertising |= ADVERTISED_10baseT_Half;
2835 if (np->advertising & ADVERTISE_10FULL)
2836 ecmd->advertising |= ADVERTISED_10baseT_Full;
2837 if (np->advertising & ADVERTISE_100HALF)
2838 ecmd->advertising |= ADVERTISED_100baseT_Half;
2839 if (np->advertising & ADVERTISE_100FULL)
2840 ecmd->advertising |= ADVERTISED_100baseT_Full;
2841 ecmd->supported = (SUPPORTED_Autoneg |
2842 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2843 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2844 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2845 ecmd->phy_address = np->phy_addr_external;
2847 * We intentionally report the phy address of the external
2848 * phy, even if the internal phy is used. This is necessary
2849 * to work around a deficiency of the ethtool interface:
2850 * It's only possible to query the settings of the active
2852 * # ethtool -s ethX port mii
2853 * actually sends an ioctl to switch to port mii with the
2854 * settings that are used for the current active port.
2855 * If we would report a different phy address in this
2857 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2858 * would unintentionally change the phy address.
2860 * Fortunately the phy address doesn't matter with the
2864 /* set information based on active port type */
2865 switch (ecmd->port) {
2868 ecmd->advertising |= ADVERTISED_TP;
2869 ecmd->transceiver = XCVR_INTERNAL;
2872 ecmd->advertising |= ADVERTISED_MII;
2873 ecmd->transceiver = XCVR_EXTERNAL;
2876 ecmd->advertising |= ADVERTISED_FIBRE;
2877 ecmd->transceiver = XCVR_EXTERNAL;
2881 /* if autonegotiation is on, try to return the active speed/duplex */
2882 if (ecmd->autoneg == AUTONEG_ENABLE) {
2883 ecmd->advertising |= ADVERTISED_Autoneg;
2884 tmp = mii_nway_result(
2885 np->advertising & mdio_read(dev, MII_LPA));
2886 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2887 ecmd->speed = SPEED_100;
2889 ecmd->speed = SPEED_10;
2890 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2891 ecmd->duplex = DUPLEX_FULL;
2893 ecmd->duplex = DUPLEX_HALF;
2896 /* ignore maxtxpkt, maxrxpkt for now */
2901 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2903 struct netdev_private *np = netdev_priv(dev);
2905 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2907 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2909 if (ecmd->autoneg == AUTONEG_ENABLE) {
2910 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2911 ADVERTISED_10baseT_Full |
2912 ADVERTISED_100baseT_Half |
2913 ADVERTISED_100baseT_Full)) == 0) {
2916 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2917 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2919 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2926 * If we're ignoring the PHY then autoneg and the internal
2927 * transciever are really not going to work so don't let the
2930 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2931 ecmd->port == PORT_TP))
2935 * maxtxpkt, maxrxpkt: ignored for now.
2938 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2939 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2940 * selects based on ecmd->port.
2942 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2943 * phys that are connected to the mii bus. It's used to apply fibre
2947 /* WHEW! now lets bang some bits */
2949 /* save the parms */
2950 dev->if_port = ecmd->port;
2951 np->autoneg = ecmd->autoneg;
2952 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2953 if (np->autoneg == AUTONEG_ENABLE) {
2954 /* advertise only what has been requested */
2955 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2956 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2957 np->advertising |= ADVERTISE_10HALF;
2958 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2959 np->advertising |= ADVERTISE_10FULL;
2960 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2961 np->advertising |= ADVERTISE_100HALF;
2962 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2963 np->advertising |= ADVERTISE_100FULL;
2965 np->speed = ecmd->speed;
2966 np->duplex = ecmd->duplex;
2967 /* user overriding the initial full duplex parm? */
2968 if (np->duplex == DUPLEX_HALF)
2969 np->full_duplex = 0;
2972 /* get the right phy enabled */
2973 if (ecmd->port == PORT_TP)
2974 switch_port_internal(dev);
2976 switch_port_external(dev);
2978 /* set parms and see how this affected our link status */
2979 init_phy_fixup(dev);
2984 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2989 u32 *rbuf = (u32 *)buf;
2990 void __iomem * ioaddr = ns_ioaddr(dev);
2992 /* read non-mii page 0 of registers */
2993 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2994 rbuf[i] = readl(ioaddr + i*4);
2997 /* read current mii registers */
2998 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2999 rbuf[i] = mdio_read(dev, i & 0x1f);
3001 /* read only the 'magic' registers from page 1 */
3002 writew(1, ioaddr + PGSEL);
3003 rbuf[i++] = readw(ioaddr + PMDCSR);
3004 rbuf[i++] = readw(ioaddr + TSTDAT);
3005 rbuf[i++] = readw(ioaddr + DSPCFG);
3006 rbuf[i++] = readw(ioaddr + SDCFG);
3007 writew(0, ioaddr + PGSEL);
3009 /* read RFCR indexed registers */
3010 rfcr = readl(ioaddr + RxFilterAddr);
3011 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3012 writel(j*2, ioaddr + RxFilterAddr);
3013 rbuf[i++] = readw(ioaddr + RxFilterData);
3015 writel(rfcr, ioaddr + RxFilterAddr);
3017 /* the interrupt status is clear-on-read - see if we missed any */
3018 if (rbuf[4] & rbuf[5]) {
3020 "%s: shoot, we dropped an interrupt (%#08x)\n",
3021 dev->name, rbuf[4] & rbuf[5]);
3027 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3028 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3029 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3030 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3031 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3032 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3033 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3034 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3036 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3039 u16 *ebuf = (u16 *)buf;
3040 void __iomem * ioaddr = ns_ioaddr(dev);
3041 struct netdev_private *np = netdev_priv(dev);
3043 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3044 for (i = 0; i < np->eeprom_size/2; i++) {
3045 ebuf[i] = eeprom_read(ioaddr, i);
3046 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3047 * reads it back "sanely". So we swap it back here in order to
3048 * present it to userland as it is stored. */
3049 ebuf[i] = SWAP_BITS(ebuf[i]);
3054 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3056 struct mii_ioctl_data *data = if_mii(rq);
3057 struct netdev_private *np = netdev_priv(dev);
3060 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3061 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3062 data->phy_id = np->phy_addr_external;
3065 case SIOCGMIIREG: /* Read MII PHY register. */
3066 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3067 /* The phy_id is not enough to uniquely identify
3068 * the intended target. Therefore the command is sent to
3069 * the given mii on the current port.
3071 if (dev->if_port == PORT_TP) {
3072 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3073 data->val_out = mdio_read(dev,
3074 data->reg_num & 0x1f);
3078 move_int_phy(dev, data->phy_id & 0x1f);
3079 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3080 data->reg_num & 0x1f);
3084 case SIOCSMIIREG: /* Write MII PHY register. */
3085 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3086 if (!capable(CAP_NET_ADMIN))
3088 if (dev->if_port == PORT_TP) {
3089 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3090 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3091 np->advertising = data->val_in;
3092 mdio_write(dev, data->reg_num & 0x1f,
3096 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3097 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3098 np->advertising = data->val_in;
3100 move_int_phy(dev, data->phy_id & 0x1f);
3101 miiport_write(dev, data->phy_id & 0x1f,
3102 data->reg_num & 0x1f,
3111 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3113 void __iomem * ioaddr = ns_ioaddr(dev);
3114 struct netdev_private *np = netdev_priv(dev);
3116 if (netif_msg_wol(np))
3117 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3120 /* For WOL we must restart the rx process in silent mode.
3121 * Write NULL to the RxRingPtr. Only possible if
3122 * rx process is stopped
3124 writel(0, ioaddr + RxRingPtr);
3126 /* read WoL status to clear */
3127 readl(ioaddr + WOLCmd);
3129 /* PME on, clear status */
3130 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3132 /* and restart the rx process */
3133 writel(RxOn, ioaddr + ChipCmd);
3136 /* enable the WOL interrupt.
3137 * Could be used to send a netlink message.
3139 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3140 natsemi_irq_enable(dev);
3144 static int netdev_close(struct net_device *dev)
3146 void __iomem * ioaddr = ns_ioaddr(dev);
3147 struct netdev_private *np = netdev_priv(dev);
3149 if (netif_msg_ifdown(np))
3151 "%s: Shutting down ethercard, status was %#04x.\n",
3152 dev->name, (int)readl(ioaddr + ChipCmd));
3153 if (netif_msg_pktdata(np))
3155 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3156 dev->name, np->cur_tx, np->dirty_tx,
3157 np->cur_rx, np->dirty_rx);
3160 * FIXME: what if someone tries to close a device
3161 * that is suspended?
3162 * Should we reenable the nic to switch to
3163 * the final WOL settings?
3166 del_timer_sync(&np->timer);
3167 disable_irq(dev->irq);
3168 spin_lock_irq(&np->lock);
3169 natsemi_irq_disable(dev);
3171 spin_unlock_irq(&np->lock);
3172 enable_irq(dev->irq);
3174 free_irq(dev->irq, dev);
3176 /* Interrupt disabled, interrupt handler released,
3177 * queue stopped, timer deleted, rtnl_lock held
3178 * All async codepaths that access the driver are disabled.
3180 spin_lock_irq(&np->lock);
3182 readl(ioaddr + IntrMask);
3183 readw(ioaddr + MIntrStatus);
3186 writel(StatsFreeze, ioaddr + StatsCtrl);
3188 /* Stop the chip's Tx and Rx processes. */
3189 natsemi_stop_rxtx(dev);
3192 spin_unlock_irq(&np->lock);
3194 /* clear the carrier last - an interrupt could reenable it otherwise */
3195 netif_carrier_off(dev);
3196 netif_stop_queue(dev);
3203 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3205 /* restart the NIC in WOL mode.
3206 * The nic must be stopped for this.
3208 enable_wol_mode(dev, 0);
3210 /* Restore PME enable bit unmolested */
3211 writel(np->SavedClkRun, ioaddr + ClkRun);
3218 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3220 struct net_device *dev = pci_get_drvdata(pdev);
3221 void __iomem * ioaddr = ns_ioaddr(dev);
3223 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3224 unregister_netdev (dev);
3225 pci_release_regions (pdev);
3228 pci_set_drvdata(pdev, NULL);
3234 * The ns83815 chip doesn't have explicit RxStop bits.
3235 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3236 * of the nic, thus this function must be very careful:
3238 * suspend/resume synchronization:
3240 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3241 * start_tx, tx_timeout
3243 * No function accesses the hardware without checking np->hands_off.
3244 * the check occurs under spin_lock_irq(&np->lock);
3246 * * netdev_ioctl: noncritical access.
3247 * * netdev_open: cannot happen due to the device_detach
3248 * * netdev_close: doesn't hurt.
3249 * * netdev_timer: timer stopped by natsemi_suspend.
3250 * * intr_handler: doesn't acquire the spinlock. suspend calls
3251 * disable_irq() to enforce synchronization.
3252 * * natsemi_poll: checks before reenabling interrupts. suspend
3253 * sets hands_off, disables interrupts and then waits with
3254 * netif_poll_disable().
3256 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3259 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3261 struct net_device *dev = pci_get_drvdata (pdev);
3262 struct netdev_private *np = netdev_priv(dev);
3263 void __iomem * ioaddr = ns_ioaddr(dev);
3266 if (netif_running (dev)) {
3267 del_timer_sync(&np->timer);
3269 disable_irq(dev->irq);
3270 spin_lock_irq(&np->lock);
3272 natsemi_irq_disable(dev);
3274 natsemi_stop_rxtx(dev);
3275 netif_stop_queue(dev);
3277 spin_unlock_irq(&np->lock);
3278 enable_irq(dev->irq);
3280 netif_poll_disable(dev);
3282 /* Update the error counts. */
3285 /* pci_power_off(pdev, -1); */
3288 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3289 /* Restore PME enable bit */
3291 /* restart the NIC in WOL mode.
3292 * The nic must be stopped for this.
3293 * FIXME: use the WOL interrupt
3295 enable_wol_mode(dev, 0);
3297 /* Restore PME enable bit unmolested */
3298 writel(np->SavedClkRun, ioaddr + ClkRun);
3302 netif_device_detach(dev);
3308 static int natsemi_resume (struct pci_dev *pdev)
3310 struct net_device *dev = pci_get_drvdata (pdev);
3311 struct netdev_private *np = netdev_priv(dev);
3314 if (netif_device_present(dev))
3316 if (netif_running(dev)) {
3317 BUG_ON(!np->hands_off);
3318 pci_enable_device(pdev);
3319 /* pci_power_on(pdev); */
3323 disable_irq(dev->irq);
3324 spin_lock_irq(&np->lock);
3326 init_registers(dev);
3327 netif_device_attach(dev);
3328 spin_unlock_irq(&np->lock);
3329 enable_irq(dev->irq);
3331 mod_timer(&np->timer, jiffies + 1*HZ);
3333 netif_device_attach(dev);
3334 netif_poll_enable(dev);
3340 #endif /* CONFIG_PM */
3342 static struct pci_driver natsemi_driver = {
3344 .id_table = natsemi_pci_tbl,
3345 .probe = natsemi_probe1,
3346 .remove = __devexit_p(natsemi_remove1),
3348 .suspend = natsemi_suspend,
3349 .resume = natsemi_resume,
3353 static int __init natsemi_init_mod (void)
3355 /* when a module, this is printed whether or not devices are found in probe */
3360 return pci_register_driver(&natsemi_driver);
3363 static void __exit natsemi_exit_mod (void)
3365 pci_unregister_driver (&natsemi_driver);
3368 module_init(natsemi_init_mod);
3369 module_exit(natsemi_exit_mod);