1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
25 Linux kernel modifications:
29 - Bug fixes and better intr performance (Tjeerd)
31 - Now reads correct MAC address from eeprom
33 - Eliminate redundant priv->tx_full flag
34 - Call netif_start_queue from dev->tx_timeout
35 - wmb() in start_tx() to flush data
37 - Clean up PCI enable (davej)
39 - Merge Donald Becker's natsemi.c version 1.07
43 * ethtool support (jgarzik)
44 * Proper initialization of the card (which sometimes
45 fails to occur and leaves the card in a non-functional
48 * Some documented register settings to optimize some
49 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
51 * Polling of the PHY intr for stuff like link state
52 change and auto- negotiation to finally work properly. (uzi)
54 * One-liner removal of a duplicate declaration of
57 Version 1.0.7: (Manfred Spraul)
60 * full reset added into tx_timeout
61 * correct multicast hash generation (both big and little endian)
62 [copied from a natsemi driver version
63 from Myrio Corporation, Greg Smith]
66 version 1.0.8 (Tim Hockin <thockin@sun.com>)
68 * Wake on lan support (Erik Gilling)
69 * MXDMA fixes for serverworks
72 version 1.0.9 (Manfred Spraul)
73 * Main change: fix lack of synchronize
74 netif_close/netif_suspend against a last interrupt
76 * do not enable superflous interrupts (e.g. the
77 drivers relies on TxDone - TxIntr not needed)
78 * wait that the hardware has really stopped in close
80 * workaround for the (at least) gcc-2.95.1 compiler
81 problem. Also simplifies the code a bit.
82 * disable_irq() in tx_timeout - needed to protect
83 against rx interrupts.
84 * stop the nic before switching into silent rx mode
85 for wol (required according to docu).
88 * use long for ee_addr (various)
89 * print pointers properly (DaveM)
90 * include asm/irq.h (?)
93 * check and reset if PHY errors appear (Adrian Sun)
94 * WoL cleanup (Tim Hockin)
95 * Magic number cleanup (Tim Hockin)
96 * Don't reload EEPROM on every reset (Tim Hockin)
97 * Save and restore EEPROM state across reset (Tim Hockin)
98 * MDIO Cleanup (Tim Hockin)
99 * Reformat register offsets/bits (jgarzik)
102 * ETHTOOL_* further support (Tim Hockin)
105 * ETHTOOL_[G]EEPROM support (Tim Hockin)
108 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
111 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
114 * Get rid of cable_magic flag
115 * use new (National provided) solution for cable magic issue
118 * call netdev_rx() for RxErrors (Manfred Spraul)
119 * formatting and cleanups
120 * change options and full_duplex arrays to be zero
122 * enable only the WoL and PHY interrupts in wol mode
125 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
126 * create a function for rx refill (Manfred Spraul)
127 * combine drain_ring and init_ring (Manfred Spraul)
128 * oom handling (Manfred Spraul)
129 * hands_off instead of playing with netif_device_{de,a}ttach
131 * be sure to write the MAC back to the chip (Manfred Spraul)
132 * lengthen EEPROM timeout, and always warn about timeouts
134 * comments update (Manfred)
135 * do the right thing on a phy-reset (Manfred and Tim)
138 * big endian support with CFG:BEM instead of cpu_to_le32
141 #include <linux/config.h>
142 #include <linux/module.h>
143 #include <linux/kernel.h>
144 #include <linux/string.h>
145 #include <linux/timer.h>
146 #include <linux/errno.h>
147 #include <linux/ioport.h>
148 #include <linux/slab.h>
149 #include <linux/interrupt.h>
150 #include <linux/pci.h>
151 #include <linux/netdevice.h>
152 #include <linux/etherdevice.h>
153 #include <linux/skbuff.h>
154 #include <linux/init.h>
155 #include <linux/spinlock.h>
156 #include <linux/ethtool.h>
157 #include <linux/delay.h>
158 #include <linux/rtnetlink.h>
159 #include <linux/mii.h>
160 #include <linux/crc32.h>
161 #include <linux/bitops.h>
162 #include <linux/prefetch.h>
163 #include <asm/processor.h> /* Processor type for cache alignment. */
166 #include <asm/uaccess.h>
168 #define DRV_NAME "natsemi"
169 #define DRV_VERSION "1.07+LK1.0.17"
170 #define DRV_RELDATE "Sep 27, 2002"
174 /* Updated to recommendations in pci-skeleton v2.03. */
176 /* The user-configurable values.
177 These may be modified when a driver module is loaded.*/
179 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
184 static int debug = -1;
188 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
189 This chip uses a 512 element hash table based on the Ethernet CRC. */
190 static const int multicast_filter_limit = 100;
192 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
193 Setting to > 1518 effectively disables this feature. */
194 static int rx_copybreak;
196 /* Used to pass the media type, etc.
197 Both 'options[]' and 'full_duplex[]' should exist for driver
199 The media type is usually passed in 'options[]'.
201 #define MAX_UNITS 8 /* More are supported, limit only on options */
202 static int options[MAX_UNITS];
203 static int full_duplex[MAX_UNITS];
205 /* Operational parameters that are set at compile time. */
207 /* Keep the ring sizes a power of two for compile efficiency.
208 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
209 Making the Tx ring too large decreases the effectiveness of channel
210 bonding and packet priority.
211 There are no ill effects from too-large receive rings. */
212 #define TX_RING_SIZE 16
213 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
214 #define RX_RING_SIZE 32
216 /* Operational parameters that usually are not changed. */
217 /* Time in jiffies before concluding the transmitter is hung. */
218 #define TX_TIMEOUT (2*HZ)
220 #define NATSEMI_HW_TIMEOUT 400
221 #define NATSEMI_TIMER_FREQ 3*HZ
222 #define NATSEMI_PG0_NREGS 64
223 #define NATSEMI_RFDR_NREGS 8
224 #define NATSEMI_PG1_NREGS 4
225 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
227 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
228 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
229 #define NATSEMI_EEPROM_SIZE 24 /* 12 16-bit values */
232 * The nic writes 32-bit values, even if the upper bytes of
233 * a 32-bit value are beyond the end of the buffer.
235 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
236 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
237 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
238 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
240 /* These identify the driver base version and may not be removed. */
241 static char version[] __devinitdata =
242 KERN_INFO DRV_NAME " dp8381x driver, version "
243 DRV_VERSION ", " DRV_RELDATE "\n"
244 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
245 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
246 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
248 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
249 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
250 MODULE_LICENSE("GPL");
252 module_param(mtu, int, 0);
253 module_param(debug, int, 0);
254 module_param(rx_copybreak, int, 0);
255 module_param_array(options, int, NULL, 0);
256 module_param_array(full_duplex, int, NULL, 0);
257 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
258 MODULE_PARM_DESC(debug, "DP8381x default debug level");
259 MODULE_PARM_DESC(rx_copybreak,
260 "DP8381x copy breakpoint for copy-only-tiny-frames");
261 MODULE_PARM_DESC(options,
262 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
263 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
268 I. Board Compatibility
270 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
271 It also works with other chips in in the DP83810 series.
273 II. Board-specific settings
275 This driver requires the PCI interrupt line to be valid.
276 It honors the EEPROM-set values.
278 III. Driver operation
282 This driver uses two statically allocated fixed-size descriptor lists
283 formed into rings by a branch from the final descriptor to the beginning of
284 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
285 The NatSemi design uses a 'next descriptor' pointer that the driver forms
288 IIIb/c. Transmit/Receive Structure
290 This driver uses a zero-copy receive and transmit scheme.
291 The driver allocates full frame size skbuffs for the Rx ring buffers at
292 open() time and passes the skb->data field to the chip as receive data
293 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
294 a fresh skbuff is allocated and the frame is copied to the new skbuff.
295 When the incoming frame is larger, the skbuff is passed directly up the
296 protocol stack. Buffers consumed this way are replaced by newly allocated
297 skbuffs in a later phase of receives.
299 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
300 using a full-sized skbuff for small frames vs. the copying costs of larger
301 frames. New boards are typically used in generously configured machines
302 and the underfilled buffers have negligible impact compared to the benefit of
303 a single allocation size, so the default value of zero results in never
304 copying packets. When copying is done, the cost is usually mitigated by using
305 a combined copy/checksum routine. Copying also preloads the cache, which is
306 most useful with small frames.
308 A subtle aspect of the operation is that unaligned buffers are not permitted
309 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
310 longword aligned for further processing. On copies frames are put into the
311 skbuff at an offset of "+2", 16-byte aligning the IP header.
313 IIId. Synchronization
315 Most operations are synchronized on the np->lock irq spinlock, except the
316 performance critical codepaths:
318 The rx process only runs in the interrupt handler. Access from outside
319 the interrupt handler is only permitted after disable_irq().
321 The rx process usually runs under the dev->xmit_lock. If np->intr_tx_reap
322 is set, then access is permitted under spin_lock_irq(&np->lock).
324 Thus configuration functions that want to access everything must call
325 disable_irq(dev->irq);
326 spin_lock_bh(dev->xmit_lock);
327 spin_lock_irq(&np->lock);
331 NatSemi PCI network controllers are very uncommon.
335 http://www.scyld.com/expert/100mbps.html
336 http://www.scyld.com/expert/NWay.html
337 Datasheet is available from:
338 http://www.national.com/pf/DP/DP83815.html
350 PCI_USES_MASTER = 0x04,
355 /* MMIO operations required */
356 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
360 * Support for fibre connections on Am79C874:
361 * This phy needs a special setup when connected to a fibre cable.
362 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
364 #define PHYID_AM79C874 0x0022561b
366 #define MII_MCTRL 0x15 /* mode control register */
367 #define MII_FX_SEL 0x0001 /* 100BASE-FX (fiber) */
368 #define MII_EN_SCRM 0x0004 /* enable scrambler (tp) */
371 /* array of board data directly indexed by pci_tbl[x].driver_data */
372 static const struct {
375 } natsemi_pci_info[] __devinitdata = {
376 { "NatSemi DP8381[56]", PCI_IOTYPE },
379 static struct pci_device_id natsemi_pci_tbl[] = {
380 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
383 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
385 /* Offsets to the device registers.
386 Unlike software-only systems, device drivers interact with complex hardware.
387 It's not useful to define symbolic names for every register bit in the
390 enum register_offsets {
398 IntrHoldoff = 0x1C, /* DP83816 only */
425 /* These are from the spec, around page 78... on a separate table.
426 * The meaning of these registers depend on the value of PGSEL. */
433 /* the values for the 'magic' registers above (PGSEL=1) */
434 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
435 #define TSTDAT_VAL 0x0
436 #define DSPCFG_VAL 0x5040
437 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
438 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
439 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
440 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
442 /* misc PCI space registers */
443 enum pci_register_offsets {
457 enum ChipConfig_bits {
461 CfgAnegEnable = 0x2000,
463 CfgAnegFull = 0x8000,
464 CfgAnegDone = 0x8000000,
465 CfgFullDuplex = 0x20000000,
466 CfgSpeed100 = 0x40000000,
467 CfgLink = 0x80000000,
473 EE_ChipSelect = 0x08,
480 enum PCIBusCfg_bits {
484 /* Bits in the interrupt status/mask registers. */
485 enum IntrStatus_bits {
489 IntrRxEarly = 0x0008,
491 IntrRxOverrun = 0x0020,
496 IntrTxUnderrun = 0x0400,
501 IntrHighBits = 0x8000,
502 RxStatusFIFOOver = 0x10000,
503 IntrPCIErr = 0xf00000,
504 RxResetDone = 0x1000000,
505 TxResetDone = 0x2000000,
506 IntrAbnormalSummary = 0xCD20,
510 * Default Interrupts:
511 * Rx OK, Rx Packet Error, Rx Overrun,
512 * Tx OK, Tx Packet Error, Tx Underrun,
513 * MIB Service, Phy Interrupt, High Bits,
514 * Rx Status FIFO overrun,
515 * Received Target Abort, Received Master Abort,
516 * Signalled System Error, Received Parity Error
518 #define DEFAULT_INTR 0x00f1cd65
523 TxMxdmaMask = 0x700000,
525 TxMxdma_4 = 0x100000,
526 TxMxdma_8 = 0x200000,
527 TxMxdma_16 = 0x300000,
528 TxMxdma_32 = 0x400000,
529 TxMxdma_64 = 0x500000,
530 TxMxdma_128 = 0x600000,
531 TxMxdma_256 = 0x700000,
532 TxCollRetry = 0x800000,
533 TxAutoPad = 0x10000000,
534 TxMacLoop = 0x20000000,
535 TxHeartIgn = 0x40000000,
536 TxCarrierIgn = 0x80000000
541 * - 256 byte DMA burst length
542 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
543 * - 64 bytes initial drain threshold (i.e. begin actual transmission
544 * when 64 byte are in the fifo)
545 * - on tx underruns, increase drain threshold by 64.
546 * - at most use a drain threshold of 1472 bytes: The sum of the fill
547 * threshold and the drain threshold must be less than 2016 bytes.
550 #define TX_FLTH_VAL ((512/32) << 8)
551 #define TX_DRTH_VAL_START (64/32)
552 #define TX_DRTH_VAL_INC 2
553 #define TX_DRTH_VAL_LIMIT (1472/32)
557 RxMxdmaMask = 0x700000,
559 RxMxdma_4 = 0x100000,
560 RxMxdma_8 = 0x200000,
561 RxMxdma_16 = 0x300000,
562 RxMxdma_32 = 0x400000,
563 RxMxdma_64 = 0x500000,
564 RxMxdma_128 = 0x600000,
565 RxMxdma_256 = 0x700000,
566 RxAcceptLong = 0x8000000,
567 RxAcceptTx = 0x10000000,
568 RxAcceptRunt = 0x40000000,
569 RxAcceptErr = 0x80000000
571 #define RX_DRTH_VAL (128/8)
589 WakeMagicSecure = 0x400,
590 SecureHack = 0x100000,
592 WokeUnicast = 0x800000,
593 WokeMulticast = 0x1000000,
594 WokeBroadcast = 0x2000000,
596 WokePMatch0 = 0x8000000,
597 WokePMatch1 = 0x10000000,
598 WokePMatch2 = 0x20000000,
599 WokePMatch3 = 0x40000000,
600 WokeMagic = 0x80000000,
601 WakeOptsSummary = 0x7ff
604 enum RxFilterAddr_bits {
605 RFCRAddressMask = 0x3ff,
606 AcceptMulticast = 0x00200000,
607 AcceptMyPhys = 0x08000000,
608 AcceptAllPhys = 0x10000000,
609 AcceptAllMulticast = 0x20000000,
610 AcceptBroadcast = 0x40000000,
611 RxFilterEnable = 0x80000000
614 enum StatsCtrl_bits {
621 enum MIntrCtrl_bits {
629 #define PHY_ADDR_NONE 32
630 #define PHY_ADDR_INTERNAL 1
632 /* values we might find in the silicon revision register */
633 #define SRR_DP83815_C 0x0302
634 #define SRR_DP83815_D 0x0403
635 #define SRR_DP83816_A4 0x0504
636 #define SRR_DP83816_A5 0x0505
638 /* The Rx and Tx buffer descriptors. */
639 /* Note that using only 32 bit fields simplifies conversion to big-endian
648 /* Bits in network_desc.status */
649 enum desc_status_bits {
650 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
651 DescNoCRC=0x10000000, DescPktOK=0x08000000,
654 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
655 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
656 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
657 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
659 DescRxAbort=0x04000000, DescRxOver=0x02000000,
660 DescRxDest=0x01800000, DescRxLong=0x00400000,
661 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
662 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
663 DescRxLoop=0x00020000, DesRxColl=0x00010000,
666 struct netdev_private {
667 /* Descriptor rings first for alignment */
669 struct netdev_desc *rx_ring;
670 struct netdev_desc *tx_ring;
671 /* The addresses of receive-in-place skbuffs */
672 struct sk_buff *rx_skbuff[RX_RING_SIZE];
673 dma_addr_t rx_dma[RX_RING_SIZE];
674 /* address of a sent-in-place packet/buffer, for later free() */
675 struct sk_buff *tx_skbuff[TX_RING_SIZE];
676 dma_addr_t tx_dma[TX_RING_SIZE];
677 struct net_device_stats stats;
678 /* Media monitoring timer */
679 struct timer_list timer;
680 /* Frequently used values: keep some adjacent for cache effect */
681 struct pci_dev *pci_dev;
682 struct netdev_desc *rx_head_desc;
683 /* Producer/consumer ring indices */
684 unsigned int cur_rx, dirty_rx;
685 unsigned int cur_tx, dirty_tx;
686 /* Based on MTU+slack. */
687 unsigned int rx_buf_sz;
689 /* Interrupt status */
691 /* Do not touch the nic registers */
693 /* external phy that is used: only valid if dev->if_port != PORT_TP */
695 int phy_addr_external;
696 unsigned int full_duplex;
700 /* FIFO and PCI burst thresholds */
701 u32 tx_config, rx_config;
702 /* original contents of ClkRun register */
704 /* silicon revision */
706 /* expected DSPCFG value */
708 /* parms saved in ethtool format */
709 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
710 u8 duplex; /* Duplex, half or full */
711 u8 autoneg; /* Autonegotiation enabled */
712 /* MII transceiver section */
719 static void move_int_phy(struct net_device *dev, int addr);
720 static int eeprom_read(void __iomem *ioaddr, int location);
721 static int mdio_read(struct net_device *dev, int reg);
722 static void mdio_write(struct net_device *dev, int reg, u16 data);
723 static void init_phy_fixup(struct net_device *dev);
724 static int miiport_read(struct net_device *dev, int phy_id, int reg);
725 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
726 static int find_mii(struct net_device *dev);
727 static void natsemi_reset(struct net_device *dev);
728 static void natsemi_reload_eeprom(struct net_device *dev);
729 static void natsemi_stop_rxtx(struct net_device *dev);
730 static int netdev_open(struct net_device *dev);
731 static void do_cable_magic(struct net_device *dev);
732 static void undo_cable_magic(struct net_device *dev);
733 static void check_link(struct net_device *dev);
734 static void netdev_timer(unsigned long data);
735 static void dump_ring(struct net_device *dev);
736 static void tx_timeout(struct net_device *dev);
737 static int alloc_ring(struct net_device *dev);
738 static void refill_rx(struct net_device *dev);
739 static void init_ring(struct net_device *dev);
740 static void drain_tx(struct net_device *dev);
741 static void drain_ring(struct net_device *dev);
742 static void free_ring(struct net_device *dev);
743 static void reinit_ring(struct net_device *dev);
744 static void init_registers(struct net_device *dev);
745 static int start_tx(struct sk_buff *skb, struct net_device *dev);
746 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
747 static void netdev_error(struct net_device *dev, int intr_status);
748 static int natsemi_poll(struct net_device *dev, int *budget);
749 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
750 static void netdev_tx_done(struct net_device *dev);
751 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
752 #ifdef CONFIG_NET_POLL_CONTROLLER
753 static void natsemi_poll_controller(struct net_device *dev);
755 static void __set_rx_mode(struct net_device *dev);
756 static void set_rx_mode(struct net_device *dev);
757 static void __get_stats(struct net_device *dev);
758 static struct net_device_stats *get_stats(struct net_device *dev);
759 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
760 static int netdev_set_wol(struct net_device *dev, u32 newval);
761 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
762 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
763 static int netdev_get_sopass(struct net_device *dev, u8 *data);
764 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
765 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
766 static void enable_wol_mode(struct net_device *dev, int enable_intr);
767 static int netdev_close(struct net_device *dev);
768 static int netdev_get_regs(struct net_device *dev, u8 *buf);
769 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
770 static struct ethtool_ops ethtool_ops;
772 static inline void __iomem *ns_ioaddr(struct net_device *dev)
774 return (void __iomem *) dev->base_addr;
777 static inline void natsemi_irq_enable(struct net_device *dev)
779 writel(1, ns_ioaddr(dev) + IntrEnable);
780 readl(ns_ioaddr(dev) + IntrEnable);
783 static inline void natsemi_irq_disable(struct net_device *dev)
785 writel(0, ns_ioaddr(dev) + IntrEnable);
786 readl(ns_ioaddr(dev) + IntrEnable);
789 static void move_int_phy(struct net_device *dev, int addr)
791 struct netdev_private *np = netdev_priv(dev);
792 void __iomem *ioaddr = ns_ioaddr(dev);
796 * The internal phy is visible on the external mii bus. Therefore we must
797 * move it away before we can send commands to an external phy.
798 * There are two addresses we must avoid:
799 * - the address on the external phy that is used for transmission.
800 * - the address that we want to access. User space can access phys
801 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
802 * phy that is used for transmission.
807 if (target == np->phy_addr_external)
809 writew(target, ioaddr + PhyCtrl);
810 readw(ioaddr + PhyCtrl);
814 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
815 const struct pci_device_id *ent)
817 struct net_device *dev;
818 struct netdev_private *np;
819 int i, option, irq, chip_idx = ent->driver_data;
820 static int find_cnt = -1;
821 unsigned long iostart, iosize;
822 void __iomem *ioaddr;
823 const int pcibar = 1; /* PCI base address register */
827 /* when built into the kernel, we only print version if device is found */
829 static int printed_version;
830 if (!printed_version++)
834 i = pci_enable_device(pdev);
837 /* natsemi has a non-standard PM control register
838 * in PCI config space. Some boards apparently need
839 * to be brought to D0 in this manner.
841 pci_read_config_dword(pdev, PCIPM, &tmp);
842 if (tmp & PCI_PM_CTRL_STATE_MASK) {
843 /* D0 state, disable PME assertion */
844 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
845 pci_write_config_dword(pdev, PCIPM, newtmp);
849 iostart = pci_resource_start(pdev, pcibar);
850 iosize = pci_resource_len(pdev, pcibar);
853 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
854 pci_set_master(pdev);
856 dev = alloc_etherdev(sizeof (struct netdev_private));
859 SET_MODULE_OWNER(dev);
860 SET_NETDEV_DEV(dev, &pdev->dev);
862 i = pci_request_regions(pdev, DRV_NAME);
864 goto err_pci_request_regions;
866 ioaddr = ioremap(iostart, iosize);
872 /* Work around the dropped serial bit. */
873 prev_eedata = eeprom_read(ioaddr, 6);
874 for (i = 0; i < 3; i++) {
875 int eedata = eeprom_read(ioaddr, i + 7);
876 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
877 dev->dev_addr[i*2+1] = eedata >> 7;
878 prev_eedata = eedata;
881 dev->base_addr = (unsigned long __force) ioaddr;
884 np = netdev_priv(dev);
887 pci_set_drvdata(pdev, dev);
889 spin_lock_init(&np->lock);
890 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
895 * - If the nic was configured to use an external phy and if find_mii
896 * finds a phy: use external port, first phy that replies.
897 * - Otherwise: internal port.
898 * Note that the phy address for the internal phy doesn't matter:
899 * The address would be used to access a phy over the mii bus, but
900 * the internal phy is accessed through mapped registers.
902 if (readl(ioaddr + ChipConfig) & CfgExtPhy)
903 dev->if_port = PORT_MII;
905 dev->if_port = PORT_TP;
906 /* Reset the chip to erase previous misconfiguration. */
907 natsemi_reload_eeprom(dev);
910 if (dev->if_port != PORT_TP) {
911 np->phy_addr_external = find_mii(dev);
912 if (np->phy_addr_external == PHY_ADDR_NONE) {
913 dev->if_port = PORT_TP;
914 np->phy_addr_external = PHY_ADDR_INTERNAL;
917 np->phy_addr_external = PHY_ADDR_INTERNAL;
920 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
922 option = dev->mem_start;
924 /* The lower four bits are the media type. */
930 "natsemi %s: ignoring user supplied media type %d",
931 pci_name(np->pci_dev), option & 15);
933 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
936 /* The chip-specific entries in the device structure. */
937 dev->open = &netdev_open;
938 dev->hard_start_xmit = &start_tx;
939 dev->stop = &netdev_close;
940 dev->get_stats = &get_stats;
941 dev->set_multicast_list = &set_rx_mode;
942 dev->change_mtu = &natsemi_change_mtu;
943 dev->do_ioctl = &netdev_ioctl;
944 dev->tx_timeout = &tx_timeout;
945 dev->watchdog_timeo = TX_TIMEOUT;
946 dev->poll = natsemi_poll;
949 #ifdef CONFIG_NET_POLL_CONTROLLER
950 dev->poll_controller = &natsemi_poll_controller;
952 SET_ETHTOOL_OPS(dev, ðtool_ops);
957 netif_carrier_off(dev);
959 /* get the initial settings from hardware */
960 tmp = mdio_read(dev, MII_BMCR);
961 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
962 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
963 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
964 np->advertising= mdio_read(dev, MII_ADVERTISE);
966 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
967 && netif_msg_probe(np)) {
968 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
970 pci_name(np->pci_dev),
971 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
972 "enabled, advertise" : "disabled, force",
974 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
977 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
980 if (netif_msg_probe(np))
982 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
983 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
986 /* save the silicon revision for later querying */
987 np->srr = readl(ioaddr + SiliconRev);
988 if (netif_msg_hw(np))
989 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
990 pci_name(np->pci_dev), np->srr);
992 i = register_netdev(dev);
994 goto err_register_netdev;
996 if (netif_msg_drv(np)) {
997 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
998 dev->name, natsemi_pci_info[chip_idx].name, iostart,
999 pci_name(np->pci_dev));
1000 for (i = 0; i < ETH_ALEN-1; i++)
1001 printk("%02x:", dev->dev_addr[i]);
1002 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
1003 if (dev->if_port == PORT_TP)
1004 printk(", port TP.\n");
1006 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
1010 err_register_netdev:
1014 pci_release_regions(pdev);
1015 pci_set_drvdata(pdev, NULL);
1017 err_pci_request_regions:
1023 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
1024 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
1026 /* Delay between EEPROM clock transitions.
1027 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
1028 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
1029 made udelay() unreliable.
1030 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1033 #define eeprom_delay(ee_addr) readl(ee_addr)
1035 #define EE_Write0 (EE_ChipSelect)
1036 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
1038 /* The EEPROM commands include the alway-set leading bit. */
1040 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1043 static int eeprom_read(void __iomem *addr, int location)
1047 void __iomem *ee_addr = addr + EECtrl;
1048 int read_cmd = location | EE_ReadCmd;
1050 writel(EE_Write0, ee_addr);
1052 /* Shift the read command bits out. */
1053 for (i = 10; i >= 0; i--) {
1054 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1055 writel(dataval, ee_addr);
1056 eeprom_delay(ee_addr);
1057 writel(dataval | EE_ShiftClk, ee_addr);
1058 eeprom_delay(ee_addr);
1060 writel(EE_ChipSelect, ee_addr);
1061 eeprom_delay(ee_addr);
1063 for (i = 0; i < 16; i++) {
1064 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1065 eeprom_delay(ee_addr);
1066 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1067 writel(EE_ChipSelect, ee_addr);
1068 eeprom_delay(ee_addr);
1071 /* Terminate the EEPROM access. */
1072 writel(EE_Write0, ee_addr);
1077 /* MII transceiver control section.
1078 * The 83815 series has an internal transceiver, and we present the
1079 * internal management registers as if they were MII connected.
1080 * External Phy registers are referenced through the MII interface.
1083 /* clock transitions >= 20ns (25MHz)
1084 * One readl should be good to PCI @ 100MHz
1086 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1088 static int mii_getbit (struct net_device *dev)
1091 void __iomem *ioaddr = ns_ioaddr(dev);
1093 writel(MII_ShiftClk, ioaddr + EECtrl);
1094 data = readl(ioaddr + EECtrl);
1095 writel(0, ioaddr + EECtrl);
1097 return (data & MII_Data)? 1 : 0;
1100 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1103 void __iomem *ioaddr = ns_ioaddr(dev);
1105 for (i = (1 << (len-1)); i; i >>= 1)
1107 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1108 writel(mdio_val, ioaddr + EECtrl);
1110 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1113 writel(0, ioaddr + EECtrl);
1117 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1124 mii_send_bits (dev, 0xffffffff, 32);
1125 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1126 /* ST,OP = 0110'b for read operation */
1127 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1128 mii_send_bits (dev, cmd, 14);
1130 if (mii_getbit (dev))
1133 for (i = 0; i < 16; i++) {
1135 retval |= mii_getbit (dev);
1142 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1147 mii_send_bits (dev, 0xffffffff, 32);
1148 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1149 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1150 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1151 mii_send_bits (dev, cmd, 32);
1156 static int mdio_read(struct net_device *dev, int reg)
1158 struct netdev_private *np = netdev_priv(dev);
1159 void __iomem *ioaddr = ns_ioaddr(dev);
1161 /* The 83815 series has two ports:
1162 * - an internal transceiver
1163 * - an external mii bus
1165 if (dev->if_port == PORT_TP)
1166 return readw(ioaddr+BasicControl+(reg<<2));
1168 return miiport_read(dev, np->phy_addr_external, reg);
1171 static void mdio_write(struct net_device *dev, int reg, u16 data)
1173 struct netdev_private *np = netdev_priv(dev);
1174 void __iomem *ioaddr = ns_ioaddr(dev);
1176 /* The 83815 series has an internal transceiver; handle separately */
1177 if (dev->if_port == PORT_TP)
1178 writew(data, ioaddr+BasicControl+(reg<<2));
1180 miiport_write(dev, np->phy_addr_external, reg, data);
1183 static void init_phy_fixup(struct net_device *dev)
1185 struct netdev_private *np = netdev_priv(dev);
1186 void __iomem *ioaddr = ns_ioaddr(dev);
1191 /* restore stuff lost when power was out */
1192 tmp = mdio_read(dev, MII_BMCR);
1193 if (np->autoneg == AUTONEG_ENABLE) {
1194 /* renegotiate if something changed */
1195 if ((tmp & BMCR_ANENABLE) == 0
1196 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1198 /* turn on autonegotiation and force negotiation */
1199 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1200 mdio_write(dev, MII_ADVERTISE, np->advertising);
1203 /* turn off auto negotiation, set speed and duplexity */
1204 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1205 if (np->speed == SPEED_100)
1206 tmp |= BMCR_SPEED100;
1207 if (np->duplex == DUPLEX_FULL)
1208 tmp |= BMCR_FULLDPLX;
1210 * Note: there is no good way to inform the link partner
1211 * that our capabilities changed. The user has to unplug
1212 * and replug the network cable after some changes, e.g.
1213 * after switching from 10HD, autoneg off to 100 HD,
1217 mdio_write(dev, MII_BMCR, tmp);
1218 readl(ioaddr + ChipConfig);
1221 /* find out what phy this is */
1222 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1223 + mdio_read(dev, MII_PHYSID2);
1225 /* handle external phys here */
1227 case PHYID_AM79C874:
1228 /* phy specific configuration for fibre/tp operation */
1229 tmp = mdio_read(dev, MII_MCTRL);
1230 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1231 if (dev->if_port == PORT_FIBRE)
1235 mdio_write(dev, MII_MCTRL, tmp);
1240 cfg = readl(ioaddr + ChipConfig);
1241 if (cfg & CfgExtPhy)
1244 /* On page 78 of the spec, they recommend some settings for "optimum
1245 performance" to be done in sequence. These settings optimize some
1246 of the 100Mbit autodetection circuitry. They say we only want to
1247 do this for rev C of the chip, but engineers at NSC (Bradley
1248 Kennedy) recommends always setting them. If you don't, you get
1249 errors on some autonegotiations that make the device unusable.
1251 It seems that the DSP needs a few usec to reinitialize after
1252 the start of the phy. Just retry writing these values until they
1255 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1258 writew(1, ioaddr + PGSEL);
1259 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1260 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1261 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1262 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1263 writew(np->dspcfg, ioaddr + DSPCFG);
1264 writew(SDCFG_VAL, ioaddr + SDCFG);
1265 writew(0, ioaddr + PGSEL);
1266 readl(ioaddr + ChipConfig);
1269 writew(1, ioaddr + PGSEL);
1270 dspcfg = readw(ioaddr + DSPCFG);
1271 writew(0, ioaddr + PGSEL);
1272 if (np->dspcfg == dspcfg)
1276 if (netif_msg_link(np)) {
1277 if (i==NATSEMI_HW_TIMEOUT) {
1279 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1283 "%s: DSPCFG accepted after %d usec.\n",
1288 * Enable PHY Specific event based interrupts. Link state change
1289 * and Auto-Negotiation Completion are among the affected.
1290 * Read the intr status to clear it (needed for wake events).
1292 readw(ioaddr + MIntrStatus);
1293 writew(MICRIntEn, ioaddr + MIntrCtrl);
1296 static int switch_port_external(struct net_device *dev)
1298 struct netdev_private *np = netdev_priv(dev);
1299 void __iomem *ioaddr = ns_ioaddr(dev);
1302 cfg = readl(ioaddr + ChipConfig);
1303 if (cfg & CfgExtPhy)
1306 if (netif_msg_link(np)) {
1307 printk(KERN_INFO "%s: switching to external transceiver.\n",
1311 /* 1) switch back to external phy */
1312 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1313 readl(ioaddr + ChipConfig);
1316 /* 2) reset the external phy: */
1317 /* resetting the external PHY has been known to cause a hub supplying
1318 * power over Ethernet to kill the power. We don't want to kill
1319 * power to this computer, so we avoid resetting the phy.
1322 /* 3) reinit the phy fixup, it got lost during power down. */
1323 move_int_phy(dev, np->phy_addr_external);
1324 init_phy_fixup(dev);
1329 static int switch_port_internal(struct net_device *dev)
1331 struct netdev_private *np = netdev_priv(dev);
1332 void __iomem *ioaddr = ns_ioaddr(dev);
1337 cfg = readl(ioaddr + ChipConfig);
1338 if (!(cfg &CfgExtPhy))
1341 if (netif_msg_link(np)) {
1342 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1345 /* 1) switch back to internal phy: */
1346 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1347 writel(cfg, ioaddr + ChipConfig);
1348 readl(ioaddr + ChipConfig);
1351 /* 2) reset the internal phy: */
1352 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1353 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1354 readl(ioaddr + ChipConfig);
1356 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1357 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1358 if (!(bmcr & BMCR_RESET))
1362 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1364 "%s: phy reset did not complete in %d usec.\n",
1367 /* 3) reinit the phy fixup, it got lost during power down. */
1368 init_phy_fixup(dev);
1373 /* Scan for a PHY on the external mii bus.
1374 * There are two tricky points:
1375 * - Do not scan while the internal phy is enabled. The internal phy will
1376 * crash: e.g. reads from the DSPCFG register will return odd values and
1377 * the nasty random phy reset code will reset the nic every few seconds.
1378 * - The internal phy must be moved around, an external phy could
1379 * have the same address as the internal phy.
1381 static int find_mii(struct net_device *dev)
1383 struct netdev_private *np = netdev_priv(dev);
1388 /* Switch to external phy */
1389 did_switch = switch_port_external(dev);
1391 /* Scan the possible phy addresses:
1393 * PHY address 0 means that the phy is in isolate mode. Not yet
1394 * supported due to lack of test hardware. User space should
1395 * handle it through ethtool.
1397 for (i = 1; i <= 31; i++) {
1398 move_int_phy(dev, i);
1399 tmp = miiport_read(dev, i, MII_BMSR);
1400 if (tmp != 0xffff && tmp != 0x0000) {
1401 /* found something! */
1402 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1403 + mdio_read(dev, MII_PHYSID2);
1404 if (netif_msg_probe(np)) {
1405 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1406 pci_name(np->pci_dev), np->mii, i);
1411 /* And switch back to internal phy: */
1413 switch_port_internal(dev);
1417 /* CFG bits [13:16] [18:23] */
1418 #define CFG_RESET_SAVE 0xfde000
1419 /* WCSR bits [0:4] [9:10] */
1420 #define WCSR_RESET_SAVE 0x61f
1421 /* RFCR bits [20] [22] [27:31] */
1422 #define RFCR_RESET_SAVE 0xf8500000;
1424 static void natsemi_reset(struct net_device *dev)
1432 struct netdev_private *np = netdev_priv(dev);
1433 void __iomem *ioaddr = ns_ioaddr(dev);
1436 * Resetting the chip causes some registers to be lost.
1437 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1438 * we save the state that would have been loaded from EEPROM
1439 * on a normal power-up (see the spec EEPROM map). This assumes
1440 * whoever calls this will follow up with init_registers() eventually.
1444 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1446 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1448 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 pmatch[i] = readw(ioaddr + RxFilterData);
1455 for (i = 0; i < 3; i++) {
1456 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1457 sopass[i] = readw(ioaddr + RxFilterData);
1460 /* now whack the chip */
1461 writel(ChipReset, ioaddr + ChipCmd);
1462 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1463 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1467 if (i==NATSEMI_HW_TIMEOUT) {
1468 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1470 } else if (netif_msg_hw(np)) {
1471 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1476 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1477 /* turn on external phy if it was selected */
1478 if (dev->if_port == PORT_TP)
1479 cfg &= ~(CfgExtPhy | CfgPhyDis);
1481 cfg |= (CfgExtPhy | CfgPhyDis);
1482 writel(cfg, ioaddr + ChipConfig);
1484 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1485 writel(wcsr, ioaddr + WOLCmd);
1487 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1488 /* restore PMATCH */
1489 for (i = 0; i < 3; i++) {
1490 writel(i*2, ioaddr + RxFilterAddr);
1491 writew(pmatch[i], ioaddr + RxFilterData);
1493 for (i = 0; i < 3; i++) {
1494 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1495 writew(sopass[i], ioaddr + RxFilterData);
1498 writel(rfcr, ioaddr + RxFilterAddr);
1501 static void natsemi_reload_eeprom(struct net_device *dev)
1503 struct netdev_private *np = netdev_priv(dev);
1504 void __iomem *ioaddr = ns_ioaddr(dev);
1507 writel(EepromReload, ioaddr + PCIBusCfg);
1508 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1510 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1513 if (i==NATSEMI_HW_TIMEOUT) {
1514 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1515 pci_name(np->pci_dev), i*50);
1516 } else if (netif_msg_hw(np)) {
1517 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1518 pci_name(np->pci_dev), i*50);
1522 static void natsemi_stop_rxtx(struct net_device *dev)
1524 void __iomem * ioaddr = ns_ioaddr(dev);
1525 struct netdev_private *np = netdev_priv(dev);
1528 writel(RxOff | TxOff, ioaddr + ChipCmd);
1529 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1530 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1534 if (i==NATSEMI_HW_TIMEOUT) {
1535 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1537 } else if (netif_msg_hw(np)) {
1538 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1543 static int netdev_open(struct net_device *dev)
1545 struct netdev_private *np = netdev_priv(dev);
1546 void __iomem * ioaddr = ns_ioaddr(dev);
1549 /* Reset the chip, just in case. */
1552 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1555 if (netif_msg_ifup(np))
1556 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1557 dev->name, dev->irq);
1558 i = alloc_ring(dev);
1560 free_irq(dev->irq, dev);
1564 spin_lock_irq(&np->lock);
1565 init_registers(dev);
1566 /* now set the MAC address according to dev->dev_addr */
1567 for (i = 0; i < 3; i++) {
1568 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1570 writel(i*2, ioaddr + RxFilterAddr);
1571 writew(mac, ioaddr + RxFilterData);
1573 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1574 spin_unlock_irq(&np->lock);
1576 netif_start_queue(dev);
1578 if (netif_msg_ifup(np))
1579 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1580 dev->name, (int)readl(ioaddr + ChipCmd));
1582 /* Set the timer to check for link beat. */
1583 init_timer(&np->timer);
1584 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1585 np->timer.data = (unsigned long)dev;
1586 np->timer.function = &netdev_timer; /* timer handler */
1587 add_timer(&np->timer);
1592 static void do_cable_magic(struct net_device *dev)
1594 struct netdev_private *np = netdev_priv(dev);
1595 void __iomem *ioaddr = ns_ioaddr(dev);
1597 if (dev->if_port != PORT_TP)
1600 if (np->srr >= SRR_DP83816_A5)
1604 * 100 MBit links with short cables can trip an issue with the chip.
1605 * The problem manifests as lots of CRC errors and/or flickering
1606 * activity LED while idle. This process is based on instructions
1607 * from engineers at National.
1609 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1612 writew(1, ioaddr + PGSEL);
1614 * coefficient visibility should already be enabled via
1617 data = readw(ioaddr + TSTDAT) & 0xff;
1619 * the value must be negative, and within certain values
1620 * (these values all come from National)
1622 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1623 struct netdev_private *np = netdev_priv(dev);
1625 /* the bug has been triggered - fix the coefficient */
1626 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1627 /* lock the value */
1628 data = readw(ioaddr + DSPCFG);
1629 np->dspcfg = data | DSPCFG_LOCK;
1630 writew(np->dspcfg, ioaddr + DSPCFG);
1632 writew(0, ioaddr + PGSEL);
1636 static void undo_cable_magic(struct net_device *dev)
1639 struct netdev_private *np = netdev_priv(dev);
1640 void __iomem * ioaddr = ns_ioaddr(dev);
1642 if (dev->if_port != PORT_TP)
1645 if (np->srr >= SRR_DP83816_A5)
1648 writew(1, ioaddr + PGSEL);
1649 /* make sure the lock bit is clear */
1650 data = readw(ioaddr + DSPCFG);
1651 np->dspcfg = data & ~DSPCFG_LOCK;
1652 writew(np->dspcfg, ioaddr + DSPCFG);
1653 writew(0, ioaddr + PGSEL);
1656 static void check_link(struct net_device *dev)
1658 struct netdev_private *np = netdev_priv(dev);
1659 void __iomem * ioaddr = ns_ioaddr(dev);
1663 /* The link status field is latched: it remains low after a temporary
1664 * link failure until it's read. We need the current link status,
1667 mdio_read(dev, MII_BMSR);
1668 bmsr = mdio_read(dev, MII_BMSR);
1670 if (!(bmsr & BMSR_LSTATUS)) {
1671 if (netif_carrier_ok(dev)) {
1672 if (netif_msg_link(np))
1673 printk(KERN_NOTICE "%s: link down.\n",
1675 netif_carrier_off(dev);
1676 undo_cable_magic(dev);
1680 if (!netif_carrier_ok(dev)) {
1681 if (netif_msg_link(np))
1682 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1683 netif_carrier_on(dev);
1684 do_cable_magic(dev);
1687 duplex = np->full_duplex;
1689 if (bmsr & BMSR_ANEGCOMPLETE) {
1690 int tmp = mii_nway_result(
1691 np->advertising & mdio_read(dev, MII_LPA));
1692 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1694 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1698 /* if duplex is set then bit 28 must be set, too */
1699 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1700 if (netif_msg_link(np))
1702 "%s: Setting %s-duplex based on negotiated "
1703 "link capability.\n", dev->name,
1704 duplex ? "full" : "half");
1706 np->rx_config |= RxAcceptTx;
1707 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1709 np->rx_config &= ~RxAcceptTx;
1710 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1712 writel(np->tx_config, ioaddr + TxConfig);
1713 writel(np->rx_config, ioaddr + RxConfig);
1717 static void init_registers(struct net_device *dev)
1719 struct netdev_private *np = netdev_priv(dev);
1720 void __iomem * ioaddr = ns_ioaddr(dev);
1722 init_phy_fixup(dev);
1724 /* clear any interrupts that are pending, such as wake events */
1725 readl(ioaddr + IntrStatus);
1727 writel(np->ring_dma, ioaddr + RxRingPtr);
1728 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1729 ioaddr + TxRingPtr);
1731 /* Initialize other registers.
1732 * Configure the PCI bus bursts and FIFO thresholds.
1733 * Configure for standard, in-spec Ethernet.
1734 * Start with half-duplex. check_link will update
1735 * to the correct settings.
1738 /* DRTH: 2: start tx if 64 bytes are in the fifo
1739 * FLTH: 0x10: refill with next packet if 512 bytes are free
1740 * MXDMA: 0: up to 256 byte bursts.
1741 * MXDMA must be <= FLTH
1745 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1746 TX_FLTH_VAL | TX_DRTH_VAL_START;
1747 writel(np->tx_config, ioaddr + TxConfig);
1749 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1750 * MXDMA 0: up to 256 byte bursts
1752 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1753 /* if receive ring now has bigger buffers than normal, enable jumbo */
1754 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1755 np->rx_config |= RxAcceptLong;
1757 writel(np->rx_config, ioaddr + RxConfig);
1760 * The PME bit is initialized from the EEPROM contents.
1761 * PCI cards probably have PME disabled, but motherboard
1762 * implementations may have PME set to enable WakeOnLan.
1763 * With PME set the chip will scan incoming packets but
1764 * nothing will be written to memory. */
1765 np->SavedClkRun = readl(ioaddr + ClkRun);
1766 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1767 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1768 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1769 dev->name, readl(ioaddr + WOLCmd));
1775 /* Enable interrupts by setting the interrupt mask. */
1776 writel(DEFAULT_INTR, ioaddr + IntrMask);
1777 writel(1, ioaddr + IntrEnable);
1779 writel(RxOn | TxOn, ioaddr + ChipCmd);
1780 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1786 * 1) check for link changes. Usually they are handled by the MII interrupt
1787 * but it doesn't hurt to check twice.
1788 * 2) check for sudden death of the NIC:
1789 * It seems that a reference set for this chip went out with incorrect info,
1790 * and there exist boards that aren't quite right. An unexpected voltage
1791 * drop can cause the PHY to get itself in a weird state (basically reset).
1792 * NOTE: this only seems to affect revC chips.
1793 * 3) check of death of the RX path due to OOM
1795 static void netdev_timer(unsigned long data)
1797 struct net_device *dev = (struct net_device *)data;
1798 struct netdev_private *np = netdev_priv(dev);
1799 void __iomem * ioaddr = ns_ioaddr(dev);
1800 int next_tick = 5*HZ;
1802 if (netif_msg_timer(np)) {
1803 /* DO NOT read the IntrStatus register,
1804 * a read clears any pending interrupts.
1806 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1810 if (dev->if_port == PORT_TP) {
1813 spin_lock_irq(&np->lock);
1814 /* check for a nasty random phy-reset - use dspcfg as a flag */
1815 writew(1, ioaddr+PGSEL);
1816 dspcfg = readw(ioaddr+DSPCFG);
1817 writew(0, ioaddr+PGSEL);
1818 if (dspcfg != np->dspcfg) {
1819 if (!netif_queue_stopped(dev)) {
1820 spin_unlock_irq(&np->lock);
1821 if (netif_msg_hw(np))
1822 printk(KERN_NOTICE "%s: possible phy reset: "
1823 "re-initializing\n", dev->name);
1824 disable_irq(dev->irq);
1825 spin_lock_irq(&np->lock);
1826 natsemi_stop_rxtx(dev);
1829 init_registers(dev);
1830 spin_unlock_irq(&np->lock);
1831 enable_irq(dev->irq);
1835 spin_unlock_irq(&np->lock);
1838 /* init_registers() calls check_link() for the above case */
1840 spin_unlock_irq(&np->lock);
1843 spin_lock_irq(&np->lock);
1845 spin_unlock_irq(&np->lock);
1848 disable_irq(dev->irq);
1851 enable_irq(dev->irq);
1853 writel(RxOn, ioaddr + ChipCmd);
1858 mod_timer(&np->timer, jiffies + next_tick);
1861 static void dump_ring(struct net_device *dev)
1863 struct netdev_private *np = netdev_priv(dev);
1865 if (netif_msg_pktdata(np)) {
1867 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1868 for (i = 0; i < TX_RING_SIZE; i++) {
1869 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1870 i, np->tx_ring[i].next_desc,
1871 np->tx_ring[i].cmd_status,
1872 np->tx_ring[i].addr);
1874 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1875 for (i = 0; i < RX_RING_SIZE; i++) {
1876 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1877 i, np->rx_ring[i].next_desc,
1878 np->rx_ring[i].cmd_status,
1879 np->rx_ring[i].addr);
1884 static void tx_timeout(struct net_device *dev)
1886 struct netdev_private *np = netdev_priv(dev);
1887 void __iomem * ioaddr = ns_ioaddr(dev);
1889 disable_irq(dev->irq);
1890 spin_lock_irq(&np->lock);
1891 if (!np->hands_off) {
1892 if (netif_msg_tx_err(np))
1894 "%s: Transmit timed out, status %#08x,"
1896 dev->name, readl(ioaddr + IntrStatus));
1901 init_registers(dev);
1904 "%s: tx_timeout while in hands_off state?\n",
1907 spin_unlock_irq(&np->lock);
1908 enable_irq(dev->irq);
1910 dev->trans_start = jiffies;
1911 np->stats.tx_errors++;
1912 netif_wake_queue(dev);
1915 static int alloc_ring(struct net_device *dev)
1917 struct netdev_private *np = netdev_priv(dev);
1918 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1919 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1923 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1927 static void refill_rx(struct net_device *dev)
1929 struct netdev_private *np = netdev_priv(dev);
1931 /* Refill the Rx ring buffers. */
1932 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1933 struct sk_buff *skb;
1934 int entry = np->dirty_rx % RX_RING_SIZE;
1935 if (np->rx_skbuff[entry] == NULL) {
1936 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1937 skb = dev_alloc_skb(buflen);
1938 np->rx_skbuff[entry] = skb;
1940 break; /* Better luck next round. */
1941 skb->dev = dev; /* Mark as being used by this device. */
1942 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1943 skb->data, buflen, PCI_DMA_FROMDEVICE);
1944 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1946 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1948 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1949 if (netif_msg_rx_err(np))
1950 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1955 static void set_bufsize(struct net_device *dev)
1957 struct netdev_private *np = netdev_priv(dev);
1958 if (dev->mtu <= ETH_DATA_LEN)
1959 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1961 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1964 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1965 static void init_ring(struct net_device *dev)
1967 struct netdev_private *np = netdev_priv(dev);
1971 np->dirty_tx = np->cur_tx = 0;
1972 for (i = 0; i < TX_RING_SIZE; i++) {
1973 np->tx_skbuff[i] = NULL;
1974 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1975 +sizeof(struct netdev_desc)
1976 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1977 np->tx_ring[i].cmd_status = 0;
1982 np->cur_rx = RX_RING_SIZE;
1986 np->rx_head_desc = &np->rx_ring[0];
1988 /* Please be carefull before changing this loop - at least gcc-2.95.1
1989 * miscompiles it otherwise.
1991 /* Initialize all Rx descriptors. */
1992 for (i = 0; i < RX_RING_SIZE; i++) {
1993 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1994 +sizeof(struct netdev_desc)
1995 *((i+1)%RX_RING_SIZE));
1996 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1997 np->rx_skbuff[i] = NULL;
2003 static void drain_tx(struct net_device *dev)
2005 struct netdev_private *np = netdev_priv(dev);
2008 for (i = 0; i < TX_RING_SIZE; i++) {
2009 if (np->tx_skbuff[i]) {
2010 pci_unmap_single(np->pci_dev,
2011 np->tx_dma[i], np->tx_skbuff[i]->len,
2013 dev_kfree_skb(np->tx_skbuff[i]);
2014 np->stats.tx_dropped++;
2016 np->tx_skbuff[i] = NULL;
2020 static void drain_rx(struct net_device *dev)
2022 struct netdev_private *np = netdev_priv(dev);
2023 unsigned int buflen = np->rx_buf_sz;
2026 /* Free all the skbuffs in the Rx queue. */
2027 for (i = 0; i < RX_RING_SIZE; i++) {
2028 np->rx_ring[i].cmd_status = 0;
2029 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2030 if (np->rx_skbuff[i]) {
2031 pci_unmap_single(np->pci_dev,
2032 np->rx_dma[i], buflen,
2033 PCI_DMA_FROMDEVICE);
2034 dev_kfree_skb(np->rx_skbuff[i]);
2036 np->rx_skbuff[i] = NULL;
2040 static void drain_ring(struct net_device *dev)
2046 static void free_ring(struct net_device *dev)
2048 struct netdev_private *np = netdev_priv(dev);
2049 pci_free_consistent(np->pci_dev,
2050 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2051 np->rx_ring, np->ring_dma);
2054 static void reinit_rx(struct net_device *dev)
2056 struct netdev_private *np = netdev_priv(dev);
2061 np->cur_rx = RX_RING_SIZE;
2062 np->rx_head_desc = &np->rx_ring[0];
2063 /* Initialize all Rx descriptors. */
2064 for (i = 0; i < RX_RING_SIZE; i++)
2065 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2070 static void reinit_ring(struct net_device *dev)
2072 struct netdev_private *np = netdev_priv(dev);
2077 np->dirty_tx = np->cur_tx = 0;
2078 for (i=0;i<TX_RING_SIZE;i++)
2079 np->tx_ring[i].cmd_status = 0;
2084 static int start_tx(struct sk_buff *skb, struct net_device *dev)
2086 struct netdev_private *np = netdev_priv(dev);
2087 void __iomem * ioaddr = ns_ioaddr(dev);
2090 /* Note: Ordering is important here, set the field with the
2091 "ownership" bit last, and only then increment cur_tx. */
2093 /* Calculate the next Tx descriptor entry. */
2094 entry = np->cur_tx % TX_RING_SIZE;
2096 np->tx_skbuff[entry] = skb;
2097 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2098 skb->data,skb->len, PCI_DMA_TODEVICE);
2100 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2102 spin_lock_irq(&np->lock);
2104 if (!np->hands_off) {
2105 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2106 /* StrongARM: Explicitly cache flush np->tx_ring and
2107 * skb->data,skb->len. */
2110 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2111 netdev_tx_done(dev);
2112 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2113 netif_stop_queue(dev);
2115 /* Wake the potentially-idle transmit channel. */
2116 writel(TxOn, ioaddr + ChipCmd);
2118 dev_kfree_skb_irq(skb);
2119 np->stats.tx_dropped++;
2121 spin_unlock_irq(&np->lock);
2123 dev->trans_start = jiffies;
2125 if (netif_msg_tx_queued(np)) {
2126 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2127 dev->name, np->cur_tx, entry);
2132 static void netdev_tx_done(struct net_device *dev)
2134 struct netdev_private *np = netdev_priv(dev);
2136 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2137 int entry = np->dirty_tx % TX_RING_SIZE;
2138 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2140 if (netif_msg_tx_done(np))
2142 "%s: tx frame #%d finished, status %#08x.\n",
2143 dev->name, np->dirty_tx,
2144 le32_to_cpu(np->tx_ring[entry].cmd_status));
2145 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2146 np->stats.tx_packets++;
2147 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2148 } else { /* Various Tx errors */
2150 le32_to_cpu(np->tx_ring[entry].cmd_status);
2151 if (tx_status & (DescTxAbort|DescTxExcColl))
2152 np->stats.tx_aborted_errors++;
2153 if (tx_status & DescTxFIFO)
2154 np->stats.tx_fifo_errors++;
2155 if (tx_status & DescTxCarrier)
2156 np->stats.tx_carrier_errors++;
2157 if (tx_status & DescTxOOWCol)
2158 np->stats.tx_window_errors++;
2159 np->stats.tx_errors++;
2161 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2162 np->tx_skbuff[entry]->len,
2164 /* Free the original skb. */
2165 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2166 np->tx_skbuff[entry] = NULL;
2168 if (netif_queue_stopped(dev)
2169 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2170 /* The ring is no longer full, wake queue. */
2171 netif_wake_queue(dev);
2175 /* The interrupt handler doesn't actually handle interrupts itself, it
2176 * schedules a NAPI poll if there is anything to do. */
2177 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
2179 struct net_device *dev = dev_instance;
2180 struct netdev_private *np = netdev_priv(dev);
2181 void __iomem * ioaddr = ns_ioaddr(dev);
2186 /* Reading automatically acknowledges. */
2187 np->intr_status = readl(ioaddr + IntrStatus);
2189 if (netif_msg_intr(np))
2191 "%s: Interrupt, status %#08x, mask %#08x.\n",
2192 dev->name, np->intr_status,
2193 readl(ioaddr + IntrMask));
2195 if (!np->intr_status)
2198 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2200 if (netif_rx_schedule_prep(dev)) {
2201 /* Disable interrupts and register for poll */
2202 natsemi_irq_disable(dev);
2203 __netif_rx_schedule(dev);
2208 /* This is the NAPI poll routine. As well as the standard RX handling
2209 * it also handles all other interrupts that the chip might raise.
2211 static int natsemi_poll(struct net_device *dev, int *budget)
2213 struct netdev_private *np = netdev_priv(dev);
2214 void __iomem * ioaddr = ns_ioaddr(dev);
2216 int work_to_do = min(*budget, dev->quota);
2220 if (np->intr_status &
2221 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2222 spin_lock(&np->lock);
2223 netdev_tx_done(dev);
2224 spin_unlock(&np->lock);
2227 /* Abnormal error summary/uncommon events handlers. */
2228 if (np->intr_status & IntrAbnormalSummary)
2229 netdev_error(dev, np->intr_status);
2231 if (np->intr_status &
2232 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2233 IntrRxErr | IntrRxOverrun)) {
2234 netdev_rx(dev, &work_done, work_to_do);
2237 *budget -= work_done;
2238 dev->quota -= work_done;
2240 if (work_done >= work_to_do)
2243 np->intr_status = readl(ioaddr + IntrStatus);
2244 } while (np->intr_status);
2246 netif_rx_complete(dev);
2248 /* Reenable interrupts providing nothing is trying to shut
2250 spin_lock(&np->lock);
2251 if (!np->hands_off && netif_running(dev))
2252 natsemi_irq_enable(dev);
2253 spin_unlock(&np->lock);
2258 /* This routine is logically part of the interrupt handler, but separated
2259 for clarity and better register allocation. */
2260 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2262 struct netdev_private *np = netdev_priv(dev);
2263 int entry = np->cur_rx % RX_RING_SIZE;
2264 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2265 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2266 unsigned int buflen = np->rx_buf_sz;
2267 void __iomem * ioaddr = ns_ioaddr(dev);
2269 /* If the driver owns the next entry it's a new packet. Send it up. */
2270 while (desc_status < 0) { /* e.g. & DescOwn */
2272 if (netif_msg_rx_status(np))
2274 " netdev_rx() entry %d status was %#08x.\n",
2275 entry, desc_status);
2279 if (*work_done >= work_to_do)
2284 pkt_len = (desc_status & DescSizeMask) - 4;
2285 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2286 if (desc_status & DescMore) {
2287 if (netif_msg_rx_err(np))
2289 "%s: Oversized(?) Ethernet "
2290 "frame spanned multiple "
2291 "buffers, entry %#08x "
2292 "status %#08x.\n", dev->name,
2293 np->cur_rx, desc_status);
2294 np->stats.rx_length_errors++;
2296 /* There was an error. */
2297 np->stats.rx_errors++;
2298 if (desc_status & (DescRxAbort|DescRxOver))
2299 np->stats.rx_over_errors++;
2300 if (desc_status & (DescRxLong|DescRxRunt))
2301 np->stats.rx_length_errors++;
2302 if (desc_status & (DescRxInvalid|DescRxAlign))
2303 np->stats.rx_frame_errors++;
2304 if (desc_status & DescRxCRC)
2305 np->stats.rx_crc_errors++;
2307 } else if (pkt_len > np->rx_buf_sz) {
2308 /* if this is the tail of a double buffer
2309 * packet, we've already counted the error
2310 * on the first part. Ignore the second half.
2313 struct sk_buff *skb;
2314 /* Omit CRC size. */
2315 /* Check if the packet is long enough to accept
2316 * without copying to a minimally-sized skbuff. */
2317 if (pkt_len < rx_copybreak
2318 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2320 /* 16 byte align the IP header */
2321 skb_reserve(skb, RX_OFFSET);
2322 pci_dma_sync_single_for_cpu(np->pci_dev,
2325 PCI_DMA_FROMDEVICE);
2326 eth_copy_and_sum(skb,
2327 np->rx_skbuff[entry]->data, pkt_len, 0);
2328 skb_put(skb, pkt_len);
2329 pci_dma_sync_single_for_device(np->pci_dev,
2332 PCI_DMA_FROMDEVICE);
2334 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2335 buflen, PCI_DMA_FROMDEVICE);
2336 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2337 np->rx_skbuff[entry] = NULL;
2339 skb->protocol = eth_type_trans(skb, dev);
2340 netif_receive_skb(skb);
2341 dev->last_rx = jiffies;
2342 np->stats.rx_packets++;
2343 np->stats.rx_bytes += pkt_len;
2345 entry = (++np->cur_rx) % RX_RING_SIZE;
2346 np->rx_head_desc = &np->rx_ring[entry];
2347 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2351 /* Restart Rx engine if stopped. */
2353 mod_timer(&np->timer, jiffies + 1);
2355 writel(RxOn, ioaddr + ChipCmd);
2358 static void netdev_error(struct net_device *dev, int intr_status)
2360 struct netdev_private *np = netdev_priv(dev);
2361 void __iomem * ioaddr = ns_ioaddr(dev);
2363 spin_lock(&np->lock);
2364 if (intr_status & LinkChange) {
2365 u16 lpa = mdio_read(dev, MII_LPA);
2366 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2367 && netif_msg_link(np)) {
2369 "%s: Autonegotiation advertising"
2370 " %#04x partner %#04x.\n", dev->name,
2371 np->advertising, lpa);
2374 /* read MII int status to clear the flag */
2375 readw(ioaddr + MIntrStatus);
2378 if (intr_status & StatsMax) {
2381 if (intr_status & IntrTxUnderrun) {
2382 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2383 np->tx_config += TX_DRTH_VAL_INC;
2384 if (netif_msg_tx_err(np))
2386 "%s: increased tx threshold, txcfg %#08x.\n",
2387 dev->name, np->tx_config);
2389 if (netif_msg_tx_err(np))
2391 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2392 dev->name, np->tx_config);
2394 writel(np->tx_config, ioaddr + TxConfig);
2396 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2397 int wol_status = readl(ioaddr + WOLCmd);
2398 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2399 dev->name, wol_status);
2401 if (intr_status & RxStatusFIFOOver) {
2402 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2403 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2406 np->stats.rx_fifo_errors++;
2408 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2409 if (intr_status & IntrPCIErr) {
2410 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2411 intr_status & IntrPCIErr);
2412 np->stats.tx_fifo_errors++;
2413 np->stats.rx_fifo_errors++;
2415 spin_unlock(&np->lock);
2418 static void __get_stats(struct net_device *dev)
2420 void __iomem * ioaddr = ns_ioaddr(dev);
2421 struct netdev_private *np = netdev_priv(dev);
2423 /* The chip only need report frame silently dropped. */
2424 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2425 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2428 static struct net_device_stats *get_stats(struct net_device *dev)
2430 struct netdev_private *np = netdev_priv(dev);
2432 /* The chip only need report frame silently dropped. */
2433 spin_lock_irq(&np->lock);
2434 if (netif_running(dev) && !np->hands_off)
2436 spin_unlock_irq(&np->lock);
2441 #ifdef CONFIG_NET_POLL_CONTROLLER
2442 static void natsemi_poll_controller(struct net_device *dev)
2444 disable_irq(dev->irq);
2445 intr_handler(dev->irq, dev, NULL);
2446 enable_irq(dev->irq);
2450 #define HASH_TABLE 0x200
2451 static void __set_rx_mode(struct net_device *dev)
2453 void __iomem * ioaddr = ns_ioaddr(dev);
2454 struct netdev_private *np = netdev_priv(dev);
2455 u8 mc_filter[64]; /* Multicast hash filter */
2458 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2459 /* Unconditionally log net taps. */
2460 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2462 rx_mode = RxFilterEnable | AcceptBroadcast
2463 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2464 } else if ((dev->mc_count > multicast_filter_limit)
2465 || (dev->flags & IFF_ALLMULTI)) {
2466 rx_mode = RxFilterEnable | AcceptBroadcast
2467 | AcceptAllMulticast | AcceptMyPhys;
2469 struct dev_mc_list *mclist;
2471 memset(mc_filter, 0, sizeof(mc_filter));
2472 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2473 i++, mclist = mclist->next) {
2474 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2475 mc_filter[i/8] |= (1 << (i & 0x07));
2477 rx_mode = RxFilterEnable | AcceptBroadcast
2478 | AcceptMulticast | AcceptMyPhys;
2479 for (i = 0; i < 64; i += 2) {
2480 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2481 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2482 ioaddr + RxFilterData);
2485 writel(rx_mode, ioaddr + RxFilterAddr);
2486 np->cur_rx_mode = rx_mode;
2489 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2491 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2496 /* synchronized against open : rtnl_lock() held by caller */
2497 if (netif_running(dev)) {
2498 struct netdev_private *np = netdev_priv(dev);
2499 void __iomem * ioaddr = ns_ioaddr(dev);
2501 disable_irq(dev->irq);
2502 spin_lock(&np->lock);
2504 natsemi_stop_rxtx(dev);
2505 /* drain rx queue */
2507 /* change buffers */
2510 writel(np->ring_dma, ioaddr + RxRingPtr);
2511 /* restart engines */
2512 writel(RxOn | TxOn, ioaddr + ChipCmd);
2513 spin_unlock(&np->lock);
2514 enable_irq(dev->irq);
2519 static void set_rx_mode(struct net_device *dev)
2521 struct netdev_private *np = netdev_priv(dev);
2522 spin_lock_irq(&np->lock);
2525 spin_unlock_irq(&np->lock);
2528 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2530 struct netdev_private *np = netdev_priv(dev);
2531 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2532 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2533 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2536 static int get_regs_len(struct net_device *dev)
2538 return NATSEMI_REGS_SIZE;
2541 static int get_eeprom_len(struct net_device *dev)
2543 return NATSEMI_EEPROM_SIZE;
2546 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2548 struct netdev_private *np = netdev_priv(dev);
2549 spin_lock_irq(&np->lock);
2550 netdev_get_ecmd(dev, ecmd);
2551 spin_unlock_irq(&np->lock);
2555 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2557 struct netdev_private *np = netdev_priv(dev);
2559 spin_lock_irq(&np->lock);
2560 res = netdev_set_ecmd(dev, ecmd);
2561 spin_unlock_irq(&np->lock);
2565 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2567 struct netdev_private *np = netdev_priv(dev);
2568 spin_lock_irq(&np->lock);
2569 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2570 netdev_get_sopass(dev, wol->sopass);
2571 spin_unlock_irq(&np->lock);
2574 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2576 struct netdev_private *np = netdev_priv(dev);
2578 spin_lock_irq(&np->lock);
2579 netdev_set_wol(dev, wol->wolopts);
2580 res = netdev_set_sopass(dev, wol->sopass);
2581 spin_unlock_irq(&np->lock);
2585 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2587 struct netdev_private *np = netdev_priv(dev);
2588 regs->version = NATSEMI_REGS_VER;
2589 spin_lock_irq(&np->lock);
2590 netdev_get_regs(dev, buf);
2591 spin_unlock_irq(&np->lock);
2594 static u32 get_msglevel(struct net_device *dev)
2596 struct netdev_private *np = netdev_priv(dev);
2597 return np->msg_enable;
2600 static void set_msglevel(struct net_device *dev, u32 val)
2602 struct netdev_private *np = netdev_priv(dev);
2603 np->msg_enable = val;
2606 static int nway_reset(struct net_device *dev)
2610 /* if autoneg is off, it's an error */
2611 tmp = mdio_read(dev, MII_BMCR);
2612 if (tmp & BMCR_ANENABLE) {
2613 tmp |= (BMCR_ANRESTART);
2614 mdio_write(dev, MII_BMCR, tmp);
2620 static u32 get_link(struct net_device *dev)
2622 /* LSTATUS is latched low until a read - so read twice */
2623 mdio_read(dev, MII_BMSR);
2624 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2627 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2629 struct netdev_private *np = netdev_priv(dev);
2630 u8 eebuf[NATSEMI_EEPROM_SIZE];
2633 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2634 spin_lock_irq(&np->lock);
2635 res = netdev_get_eeprom(dev, eebuf);
2636 spin_unlock_irq(&np->lock);
2638 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2642 static struct ethtool_ops ethtool_ops = {
2643 .get_drvinfo = get_drvinfo,
2644 .get_regs_len = get_regs_len,
2645 .get_eeprom_len = get_eeprom_len,
2646 .get_settings = get_settings,
2647 .set_settings = set_settings,
2650 .get_regs = get_regs,
2651 .get_msglevel = get_msglevel,
2652 .set_msglevel = set_msglevel,
2653 .nway_reset = nway_reset,
2654 .get_link = get_link,
2655 .get_eeprom = get_eeprom,
2658 static int netdev_set_wol(struct net_device *dev, u32 newval)
2660 struct netdev_private *np = netdev_priv(dev);
2661 void __iomem * ioaddr = ns_ioaddr(dev);
2662 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2664 /* translate to bitmasks this chip understands */
2665 if (newval & WAKE_PHY)
2667 if (newval & WAKE_UCAST)
2668 data |= WakeUnicast;
2669 if (newval & WAKE_MCAST)
2670 data |= WakeMulticast;
2671 if (newval & WAKE_BCAST)
2672 data |= WakeBroadcast;
2673 if (newval & WAKE_ARP)
2675 if (newval & WAKE_MAGIC)
2677 if (np->srr >= SRR_DP83815_D) {
2678 if (newval & WAKE_MAGICSECURE) {
2679 data |= WakeMagicSecure;
2683 writel(data, ioaddr + WOLCmd);
2688 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2690 struct netdev_private *np = netdev_priv(dev);
2691 void __iomem * ioaddr = ns_ioaddr(dev);
2692 u32 regval = readl(ioaddr + WOLCmd);
2694 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2695 | WAKE_ARP | WAKE_MAGIC);
2697 if (np->srr >= SRR_DP83815_D) {
2698 /* SOPASS works on revD and higher */
2699 *supported |= WAKE_MAGICSECURE;
2703 /* translate from chip bitmasks */
2704 if (regval & WakePhy)
2706 if (regval & WakeUnicast)
2708 if (regval & WakeMulticast)
2710 if (regval & WakeBroadcast)
2712 if (regval & WakeArp)
2714 if (regval & WakeMagic)
2716 if (regval & WakeMagicSecure) {
2717 /* this can be on in revC, but it's broken */
2718 *cur |= WAKE_MAGICSECURE;
2724 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2726 struct netdev_private *np = netdev_priv(dev);
2727 void __iomem * ioaddr = ns_ioaddr(dev);
2728 u16 *sval = (u16 *)newval;
2731 if (np->srr < SRR_DP83815_D) {
2735 /* enable writing to these registers by disabling the RX filter */
2736 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2737 addr &= ~RxFilterEnable;
2738 writel(addr, ioaddr + RxFilterAddr);
2740 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2741 writel(addr | 0xa, ioaddr + RxFilterAddr);
2742 writew(sval[0], ioaddr + RxFilterData);
2744 writel(addr | 0xc, ioaddr + RxFilterAddr);
2745 writew(sval[1], ioaddr + RxFilterData);
2747 writel(addr | 0xe, ioaddr + RxFilterAddr);
2748 writew(sval[2], ioaddr + RxFilterData);
2750 /* re-enable the RX filter */
2751 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2756 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2758 struct netdev_private *np = netdev_priv(dev);
2759 void __iomem * ioaddr = ns_ioaddr(dev);
2760 u16 *sval = (u16 *)data;
2763 if (np->srr < SRR_DP83815_D) {
2764 sval[0] = sval[1] = sval[2] = 0;
2768 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2769 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2771 writel(addr | 0xa, ioaddr + RxFilterAddr);
2772 sval[0] = readw(ioaddr + RxFilterData);
2774 writel(addr | 0xc, ioaddr + RxFilterAddr);
2775 sval[1] = readw(ioaddr + RxFilterData);
2777 writel(addr | 0xe, ioaddr + RxFilterAddr);
2778 sval[2] = readw(ioaddr + RxFilterData);
2780 writel(addr, ioaddr + RxFilterAddr);
2785 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2787 struct netdev_private *np = netdev_priv(dev);
2790 ecmd->port = dev->if_port;
2791 ecmd->speed = np->speed;
2792 ecmd->duplex = np->duplex;
2793 ecmd->autoneg = np->autoneg;
2794 ecmd->advertising = 0;
2795 if (np->advertising & ADVERTISE_10HALF)
2796 ecmd->advertising |= ADVERTISED_10baseT_Half;
2797 if (np->advertising & ADVERTISE_10FULL)
2798 ecmd->advertising |= ADVERTISED_10baseT_Full;
2799 if (np->advertising & ADVERTISE_100HALF)
2800 ecmd->advertising |= ADVERTISED_100baseT_Half;
2801 if (np->advertising & ADVERTISE_100FULL)
2802 ecmd->advertising |= ADVERTISED_100baseT_Full;
2803 ecmd->supported = (SUPPORTED_Autoneg |
2804 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2805 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2806 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2807 ecmd->phy_address = np->phy_addr_external;
2809 * We intentionally report the phy address of the external
2810 * phy, even if the internal phy is used. This is necessary
2811 * to work around a deficiency of the ethtool interface:
2812 * It's only possible to query the settings of the active
2814 * # ethtool -s ethX port mii
2815 * actually sends an ioctl to switch to port mii with the
2816 * settings that are used for the current active port.
2817 * If we would report a different phy address in this
2819 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2820 * would unintentionally change the phy address.
2822 * Fortunately the phy address doesn't matter with the
2826 /* set information based on active port type */
2827 switch (ecmd->port) {
2830 ecmd->advertising |= ADVERTISED_TP;
2831 ecmd->transceiver = XCVR_INTERNAL;
2834 ecmd->advertising |= ADVERTISED_MII;
2835 ecmd->transceiver = XCVR_EXTERNAL;
2838 ecmd->advertising |= ADVERTISED_FIBRE;
2839 ecmd->transceiver = XCVR_EXTERNAL;
2843 /* if autonegotiation is on, try to return the active speed/duplex */
2844 if (ecmd->autoneg == AUTONEG_ENABLE) {
2845 ecmd->advertising |= ADVERTISED_Autoneg;
2846 tmp = mii_nway_result(
2847 np->advertising & mdio_read(dev, MII_LPA));
2848 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2849 ecmd->speed = SPEED_100;
2851 ecmd->speed = SPEED_10;
2852 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2853 ecmd->duplex = DUPLEX_FULL;
2855 ecmd->duplex = DUPLEX_HALF;
2858 /* ignore maxtxpkt, maxrxpkt for now */
2863 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2865 struct netdev_private *np = netdev_priv(dev);
2867 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2869 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2871 if (ecmd->autoneg == AUTONEG_ENABLE) {
2872 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2873 ADVERTISED_10baseT_Full |
2874 ADVERTISED_100baseT_Half |
2875 ADVERTISED_100baseT_Full)) == 0) {
2878 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2879 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2881 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2888 * maxtxpkt, maxrxpkt: ignored for now.
2891 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2892 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2893 * selects based on ecmd->port.
2895 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2896 * phys that are connected to the mii bus. It's used to apply fibre
2900 /* WHEW! now lets bang some bits */
2902 /* save the parms */
2903 dev->if_port = ecmd->port;
2904 np->autoneg = ecmd->autoneg;
2905 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2906 if (np->autoneg == AUTONEG_ENABLE) {
2907 /* advertise only what has been requested */
2908 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2909 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2910 np->advertising |= ADVERTISE_10HALF;
2911 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2912 np->advertising |= ADVERTISE_10FULL;
2913 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2914 np->advertising |= ADVERTISE_100HALF;
2915 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2916 np->advertising |= ADVERTISE_100FULL;
2918 np->speed = ecmd->speed;
2919 np->duplex = ecmd->duplex;
2920 /* user overriding the initial full duplex parm? */
2921 if (np->duplex == DUPLEX_HALF)
2922 np->full_duplex = 0;
2925 /* get the right phy enabled */
2926 if (ecmd->port == PORT_TP)
2927 switch_port_internal(dev);
2929 switch_port_external(dev);
2931 /* set parms and see how this affected our link status */
2932 init_phy_fixup(dev);
2937 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2942 u32 *rbuf = (u32 *)buf;
2943 void __iomem * ioaddr = ns_ioaddr(dev);
2945 /* read non-mii page 0 of registers */
2946 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2947 rbuf[i] = readl(ioaddr + i*4);
2950 /* read current mii registers */
2951 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2952 rbuf[i] = mdio_read(dev, i & 0x1f);
2954 /* read only the 'magic' registers from page 1 */
2955 writew(1, ioaddr + PGSEL);
2956 rbuf[i++] = readw(ioaddr + PMDCSR);
2957 rbuf[i++] = readw(ioaddr + TSTDAT);
2958 rbuf[i++] = readw(ioaddr + DSPCFG);
2959 rbuf[i++] = readw(ioaddr + SDCFG);
2960 writew(0, ioaddr + PGSEL);
2962 /* read RFCR indexed registers */
2963 rfcr = readl(ioaddr + RxFilterAddr);
2964 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
2965 writel(j*2, ioaddr + RxFilterAddr);
2966 rbuf[i++] = readw(ioaddr + RxFilterData);
2968 writel(rfcr, ioaddr + RxFilterAddr);
2970 /* the interrupt status is clear-on-read - see if we missed any */
2971 if (rbuf[4] & rbuf[5]) {
2973 "%s: shoot, we dropped an interrupt (%#08x)\n",
2974 dev->name, rbuf[4] & rbuf[5]);
2980 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
2981 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
2982 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
2983 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
2984 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
2985 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
2986 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
2987 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
2989 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
2992 u16 *ebuf = (u16 *)buf;
2993 void __iomem * ioaddr = ns_ioaddr(dev);
2995 /* eeprom_read reads 16 bits, and indexes by 16 bits */
2996 for (i = 0; i < NATSEMI_EEPROM_SIZE/2; i++) {
2997 ebuf[i] = eeprom_read(ioaddr, i);
2998 /* The EEPROM itself stores data bit-swapped, but eeprom_read
2999 * reads it back "sanely". So we swap it back here in order to
3000 * present it to userland as it is stored. */
3001 ebuf[i] = SWAP_BITS(ebuf[i]);
3006 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3008 struct mii_ioctl_data *data = if_mii(rq);
3009 struct netdev_private *np = netdev_priv(dev);
3012 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3013 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3014 data->phy_id = np->phy_addr_external;
3017 case SIOCGMIIREG: /* Read MII PHY register. */
3018 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3019 /* The phy_id is not enough to uniquely identify
3020 * the intended target. Therefore the command is sent to
3021 * the given mii on the current port.
3023 if (dev->if_port == PORT_TP) {
3024 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3025 data->val_out = mdio_read(dev,
3026 data->reg_num & 0x1f);
3030 move_int_phy(dev, data->phy_id & 0x1f);
3031 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3032 data->reg_num & 0x1f);
3036 case SIOCSMIIREG: /* Write MII PHY register. */
3037 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3038 if (!capable(CAP_NET_ADMIN))
3040 if (dev->if_port == PORT_TP) {
3041 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3042 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3043 np->advertising = data->val_in;
3044 mdio_write(dev, data->reg_num & 0x1f,
3048 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3049 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3050 np->advertising = data->val_in;
3052 move_int_phy(dev, data->phy_id & 0x1f);
3053 miiport_write(dev, data->phy_id & 0x1f,
3054 data->reg_num & 0x1f,
3063 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3065 void __iomem * ioaddr = ns_ioaddr(dev);
3066 struct netdev_private *np = netdev_priv(dev);
3068 if (netif_msg_wol(np))
3069 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3072 /* For WOL we must restart the rx process in silent mode.
3073 * Write NULL to the RxRingPtr. Only possible if
3074 * rx process is stopped
3076 writel(0, ioaddr + RxRingPtr);
3078 /* read WoL status to clear */
3079 readl(ioaddr + WOLCmd);
3081 /* PME on, clear status */
3082 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3084 /* and restart the rx process */
3085 writel(RxOn, ioaddr + ChipCmd);
3088 /* enable the WOL interrupt.
3089 * Could be used to send a netlink message.
3091 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3092 writel(1, ioaddr + IntrEnable);
3096 static int netdev_close(struct net_device *dev)
3098 void __iomem * ioaddr = ns_ioaddr(dev);
3099 struct netdev_private *np = netdev_priv(dev);
3101 if (netif_msg_ifdown(np))
3103 "%s: Shutting down ethercard, status was %#04x.\n",
3104 dev->name, (int)readl(ioaddr + ChipCmd));
3105 if (netif_msg_pktdata(np))
3107 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3108 dev->name, np->cur_tx, np->dirty_tx,
3109 np->cur_rx, np->dirty_rx);
3112 * FIXME: what if someone tries to close a device
3113 * that is suspended?
3114 * Should we reenable the nic to switch to
3115 * the final WOL settings?
3118 del_timer_sync(&np->timer);
3119 disable_irq(dev->irq);
3120 spin_lock_irq(&np->lock);
3121 natsemi_irq_disable(dev);
3123 spin_unlock_irq(&np->lock);
3124 enable_irq(dev->irq);
3126 free_irq(dev->irq, dev);
3128 /* Interrupt disabled, interrupt handler released,
3129 * queue stopped, timer deleted, rtnl_lock held
3130 * All async codepaths that access the driver are disabled.
3132 spin_lock_irq(&np->lock);
3134 readl(ioaddr + IntrMask);
3135 readw(ioaddr + MIntrStatus);
3138 writel(StatsFreeze, ioaddr + StatsCtrl);
3140 /* Stop the chip's Tx and Rx processes. */
3141 natsemi_stop_rxtx(dev);
3144 spin_unlock_irq(&np->lock);
3146 /* clear the carrier last - an interrupt could reenable it otherwise */
3147 netif_carrier_off(dev);
3148 netif_stop_queue(dev);
3155 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3157 /* restart the NIC in WOL mode.
3158 * The nic must be stopped for this.
3160 enable_wol_mode(dev, 0);
3162 /* Restore PME enable bit unmolested */
3163 writel(np->SavedClkRun, ioaddr + ClkRun);
3170 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3172 struct net_device *dev = pci_get_drvdata(pdev);
3173 void __iomem * ioaddr = ns_ioaddr(dev);
3175 unregister_netdev (dev);
3176 pci_release_regions (pdev);
3179 pci_set_drvdata(pdev, NULL);
3185 * The ns83815 chip doesn't have explicit RxStop bits.
3186 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3187 * of the nic, thus this function must be very careful:
3189 * suspend/resume synchronization:
3191 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3192 * start_tx, tx_timeout
3194 * No function accesses the hardware without checking np->hands_off.
3195 * the check occurs under spin_lock_irq(&np->lock);
3197 * * netdev_ioctl: noncritical access.
3198 * * netdev_open: cannot happen due to the device_detach
3199 * * netdev_close: doesn't hurt.
3200 * * netdev_timer: timer stopped by natsemi_suspend.
3201 * * intr_handler: doesn't acquire the spinlock. suspend calls
3202 * disable_irq() to enforce synchronization.
3203 * * natsemi_poll: checks before reenabling interrupts. suspend
3204 * sets hands_off, disables interrupts and then waits with
3205 * netif_poll_disable().
3207 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3210 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3212 struct net_device *dev = pci_get_drvdata (pdev);
3213 struct netdev_private *np = netdev_priv(dev);
3214 void __iomem * ioaddr = ns_ioaddr(dev);
3217 if (netif_running (dev)) {
3218 del_timer_sync(&np->timer);
3220 disable_irq(dev->irq);
3221 spin_lock_irq(&np->lock);
3223 writel(0, ioaddr + IntrEnable);
3225 natsemi_stop_rxtx(dev);
3226 netif_stop_queue(dev);
3228 spin_unlock_irq(&np->lock);
3229 enable_irq(dev->irq);
3231 netif_poll_disable(dev);
3233 /* Update the error counts. */
3236 /* pci_power_off(pdev, -1); */
3239 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3240 /* Restore PME enable bit */
3242 /* restart the NIC in WOL mode.
3243 * The nic must be stopped for this.
3244 * FIXME: use the WOL interrupt
3246 enable_wol_mode(dev, 0);
3248 /* Restore PME enable bit unmolested */
3249 writel(np->SavedClkRun, ioaddr + ClkRun);
3253 netif_device_detach(dev);
3259 static int natsemi_resume (struct pci_dev *pdev)
3261 struct net_device *dev = pci_get_drvdata (pdev);
3262 struct netdev_private *np = netdev_priv(dev);
3265 if (netif_device_present(dev))
3267 if (netif_running(dev)) {
3268 BUG_ON(!np->hands_off);
3269 pci_enable_device(pdev);
3270 /* pci_power_on(pdev); */
3274 disable_irq(dev->irq);
3275 spin_lock_irq(&np->lock);
3277 init_registers(dev);
3278 netif_device_attach(dev);
3279 spin_unlock_irq(&np->lock);
3280 enable_irq(dev->irq);
3282 mod_timer(&np->timer, jiffies + 1*HZ);
3284 netif_device_attach(dev);
3285 netif_poll_enable(dev);
3291 #endif /* CONFIG_PM */
3293 static struct pci_driver natsemi_driver = {
3295 .id_table = natsemi_pci_tbl,
3296 .probe = natsemi_probe1,
3297 .remove = __devexit_p(natsemi_remove1),
3299 .suspend = natsemi_suspend,
3300 .resume = natsemi_resume,
3304 static int __init natsemi_init_mod (void)
3306 /* when a module, this is printed whether or not devices are found in probe */
3311 return pci_module_init (&natsemi_driver);
3314 static void __exit natsemi_exit_mod (void)
3316 pci_unregister_driver (&natsemi_driver);
3319 module_init(natsemi_init_mod);
3320 module_exit(natsemi_exit_mod);