2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/compiler.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
42 #include <linux/pci.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
47 #include <linux/tcp.h>
48 #include <linux/skbuff.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
57 #include <linux/vmalloc.h>
59 #include <asm/system.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
63 #include <asm/pgtable.h>
65 #include "netxen_nic_hw.h"
67 #define _NETXEN_NIC_LINUX_MAJOR 4
68 #define _NETXEN_NIC_LINUX_MINOR 0
69 #define _NETXEN_NIC_LINUX_SUBVERSION 11
70 #define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
72 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
74 #define NETXEN_NUM_FLASH_SECTORS (64)
75 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
76 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
77 * NETXEN_FLASH_SECTOR_SIZE)
79 #define PHAN_VENDOR_ID 0x4040
81 #define RCV_DESC_RINGSIZE \
82 (sizeof(struct rcv_desc) * adapter->num_rxd)
83 #define STATUS_DESC_RINGSIZE \
84 (sizeof(struct status_desc) * adapter->num_rxd)
85 #define LRO_DESC_RINGSIZE \
86 (sizeof(rcvDesc_t) * adapter->num_lro_rxd)
88 (sizeof(struct netxen_cmd_buffer) * adapter->num_txd)
89 #define RCV_BUFFSIZE \
90 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
91 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
93 #define NETXEN_RCV_PRODUCER_OFFSET 0
94 #define NETXEN_RCV_PEG_DB_ID 2
95 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
96 #define FLASH_SUCCESS 0
98 #define ADDR_IN_WINDOW1(off) \
99 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
105 #define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
108 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
111 #define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
114 #define NX_P2_C0 0x24
115 #define NX_P2_C1 0x25
116 #define NX_P3_A0 0x30
117 #define NX_P3_A2 0x30
118 #define NX_P3_B0 0x40
119 #define NX_P3_B1 0x41
121 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
122 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
124 #define FIRST_PAGE_GROUP_START 0
125 #define FIRST_PAGE_GROUP_END 0x100000
127 #define SECOND_PAGE_GROUP_START 0x6000000
128 #define SECOND_PAGE_GROUP_END 0x68BC000
130 #define THIRD_PAGE_GROUP_START 0x70E4000
131 #define THIRD_PAGE_GROUP_END 0x8000000
133 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
134 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
135 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
137 #define P2_MAX_MTU (8000)
138 #define P3_MAX_MTU (9600)
139 #define NX_ETHERMTU 1500
140 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
142 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
143 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
144 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
145 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
147 #define MAX_RX_BUFFER_LENGTH 1760
148 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
149 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
150 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
151 #define RX_JUMBO_DMA_MAP_LEN \
152 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
153 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
156 * Maximum number of ring contexts
158 #define MAX_RING_CTX 1
160 /* Opcodes to be used with the commands */
161 #define TX_ETHER_PKT 0x01
162 #define TX_TCP_PKT 0x02
163 #define TX_UDP_PKT 0x03
164 #define TX_IP_PKT 0x04
165 #define TX_TCP_LSO 0x05
166 #define TX_TCP_LSO6 0x06
167 #define TX_IPSEC 0x07
168 #define TX_IPSEC_CMD 0x0a
169 #define TX_TCPV6_PKT 0x0b
170 #define TX_UDPV6_PKT 0x0c
172 /* The following opcodes are for internal consumption. */
173 #define NETXEN_CONTROL_OP 0x10
174 #define PEGNET_REQUEST 0x11
176 #define MAX_NUM_CARDS 4
178 #define MAX_BUFFERS_PER_CMD 32
181 * Following are the states of the Phantom. Phantom will set them and
182 * Host will read to check if the fields are correct.
184 #define PHAN_INITIALIZE_START 0xff00
185 #define PHAN_INITIALIZE_FAILED 0xffff
186 #define PHAN_INITIALIZE_COMPLETE 0xff01
188 /* Host writes the following to notify that it has done the init-handshake */
189 #define PHAN_INITIALIZE_ACK 0xf00f
191 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
193 #define RCV_RING_NORMAL 0
194 #define RCV_RING_JUMBO 1
195 #define RCV_RING_LRO 2
197 #define MAX_CMD_DESCRIPTORS 4096
198 #define MAX_RCV_DESCRIPTORS 16384
199 #define MAX_CMD_DESCRIPTORS_HOST 1024
200 #define MAX_RCV_DESCRIPTORS_1G 2048
201 #define MAX_RCV_DESCRIPTORS_10G 4096
202 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
203 #define MAX_LRO_RCV_DESCRIPTORS 8
204 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
205 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
206 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
207 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
208 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
209 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
210 MAX_LRO_RCV_DESCRIPTORS)
211 #define MIN_TX_COUNT 4096
212 #define MIN_RX_COUNT 4096
213 #define NETXEN_CTX_SIGNATURE 0xdee0
214 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
215 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
217 #define PHAN_PEG_RCV_INITIALIZED 0xff01
218 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
220 #define get_next_index(index, length) \
221 (((index) + 1) & ((length) - 1))
223 #define get_index_range(index,length,count) \
224 (((index) + (count)) & ((length) - 1))
226 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
227 #define MPORT_MULTI_FUNCTION_MODE 0x2222
229 #include "netxen_nic_phan_reg.h"
232 * NetXen host-peg signal message structure
234 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
235 * Bit 2 : priv_id => must be 1
236 * Bit 3-17 : count => for doorbell
237 * Bit 18-27 : ctx_id => Context id
241 typedef u32 netxen_ctx_msg;
243 #define netxen_set_msg_peg_id(config_word, val) \
244 ((config_word) &= ~3, (config_word) |= val & 3)
245 #define netxen_set_msg_privid(config_word) \
246 ((config_word) |= 1 << 2)
247 #define netxen_set_msg_count(config_word, val) \
248 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
249 #define netxen_set_msg_ctxid(config_word, val) \
250 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
251 #define netxen_set_msg_opcode(config_word, val) \
252 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
254 struct netxen_rcv_context {
255 __le64 rcv_ring_addr;
256 __le32 rcv_ring_size;
260 struct netxen_ring_ctx {
262 /* one command ring */
263 __le64 cmd_consumer_offset;
264 __le64 cmd_ring_addr;
265 __le32 cmd_ring_size;
268 /* three receive rings */
269 struct netxen_rcv_context rcv_ctx[3];
271 /* one status ring */
272 __le64 sts_ring_addr;
273 __le32 sts_ring_size;
276 } __attribute__ ((aligned(64)));
279 * Following data structures describe the descriptors that will be used.
280 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
281 * we are doing LSO (above the 1500 size packet) only.
285 * The size of reference handle been changed to 16 bits to pass the MSS fields
289 #define FLAGS_CHECKSUM_ENABLED 0x01
290 #define FLAGS_LSO_ENABLED 0x02
291 #define FLAGS_IPSEC_SA_ADD 0x04
292 #define FLAGS_IPSEC_SA_DELETE 0x08
293 #define FLAGS_VLAN_TAGGED 0x10
295 #define netxen_set_cmd_desc_port(cmd_desc, var) \
296 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
297 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
298 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
300 #define netxen_set_tx_port(_desc, _port) \
301 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
303 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
304 (_desc)->flags_opcode = \
305 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
307 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
308 (_desc)->num_of_buffers_total_length = \
309 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
311 struct cmd_desc_type0 {
312 u8 tcp_hdr_offset; /* For LSO only */
313 u8 ip_hdr_offset; /* For LSO only */
314 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
316 /* Bit pattern: 0-7 total number of segments,
317 8-31 Total size of the packet */
318 __le32 num_of_buffers_total_length;
321 __le32 addr_low_part2;
322 __le32 addr_high_part2;
327 __le16 reference_handle; /* changed to u16 to add mss */
328 __le16 mss; /* passed by NDIS_PACKET for LSO */
329 /* Bit pattern 0-3 port, 0-3 ctx id */
331 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
332 __le16 conn_id; /* IPSec offoad only */
336 __le32 addr_low_part3;
337 __le32 addr_high_part3;
343 __le32 addr_low_part1;
344 __le32 addr_high_part1;
349 __le16 buffer_length[4];
353 __le32 addr_low_part4;
354 __le32 addr_high_part4;
361 } __attribute__ ((aligned(64)));
363 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
365 __le16 reference_handle;
367 __le32 buffer_length; /* allocated buffer length (usually 2K) */
371 /* opcode field in status_desc */
372 #define NETXEN_NIC_RXPKT_DESC 0x04
373 #define NETXEN_OLD_RXPKT_DESC 0x3f
375 /* for status field in status_desc */
376 #define STATUS_NEED_CKSUM (1)
377 #define STATUS_CKSUM_OK (2)
379 /* owner bits of status_desc */
380 #define STATUS_OWNER_HOST (0x1ULL << 56)
381 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
383 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
385 #define netxen_get_sts_desc_lro_cnt(status_desc) \
386 ((status_desc)->lro & 0x7F)
387 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
388 (((status_desc)->lro & 0x80) >> 7)
390 #define netxen_get_sts_port(sts_data) \
392 #define netxen_get_sts_status(sts_data) \
393 (((sts_data) >> 4) & 0x0F)
394 #define netxen_get_sts_type(sts_data) \
395 (((sts_data) >> 8) & 0x0F)
396 #define netxen_get_sts_totallength(sts_data) \
397 (((sts_data) >> 12) & 0xFFFF)
398 #define netxen_get_sts_refhandle(sts_data) \
399 (((sts_data) >> 28) & 0xFFFF)
400 #define netxen_get_sts_prot(sts_data) \
401 (((sts_data) >> 44) & 0x0F)
402 #define netxen_get_sts_pkt_offset(sts_data) \
403 (((sts_data) >> 48) & 0x1F)
404 #define netxen_get_sts_opcode(sts_data) \
405 (((sts_data) >> 58) & 0x03F)
408 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
409 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
410 53-55 desc_cnt, 56-57 owner, 58-63 opcode
412 __le64 status_desc_data;
420 /* Bit pattern: 0-6 lro_count indicates frag
421 * sequence, 7 last_frag indicates last frag
425 /* chained buffers */
430 __le16 frag_handles[4];
433 } __attribute__ ((aligned(16)));
436 NETXEN_RCV_PEG_0 = 0,
439 /* The version of the main data structure */
440 #define NETXEN_BDINFO_VERSION 1
442 /* Magic number to let user know flash is programmed */
443 #define NETXEN_BDINFO_MAGIC 0x12345678
445 /* Max number of Gig ports on a Phantom board */
446 #define NETXEN_MAX_PORTS 4
449 NETXEN_BRDTYPE_P1_BD = 0x0000,
450 NETXEN_BRDTYPE_P1_SB = 0x0001,
451 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
452 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
454 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
455 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
456 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
457 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
458 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
460 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
461 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
462 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
464 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
465 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
466 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
467 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
468 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
469 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
470 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
471 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
472 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
473 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
474 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
475 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
476 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
477 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
482 NETXEN_BRDMFG_INVENTEC = 1
486 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
487 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
488 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
489 MEM_ORG_256Mbx4 = 0x3,
490 MEM_ORG_256Mbx8 = 0x4,
491 MEM_ORG_256Mbx16 = 0x5,
492 MEM_ORG_512Mbx4 = 0x6,
493 MEM_ORG_512Mbx8 = 0x7,
494 MEM_ORG_512Mbx16 = 0x8,
497 MEM_ORG_1Gbx16 = 0xb,
500 MEM_ORG_2Gbx16 = 0xe,
501 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
502 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
503 } netxen_mn_mem_org_t;
506 MEM_ORG_512Kx36 = 0x0,
509 } netxen_sn_mem_org_t;
514 MEM_DEPTH_16MB = 0x3,
515 MEM_DEPTH_32MB = 0x4,
516 MEM_DEPTH_64MB = 0x5,
517 MEM_DEPTH_128MB = 0x6,
518 MEM_DEPTH_256MB = 0x7,
519 MEM_DEPTH_512MB = 0x8,
524 MEM_DEPTH_16GB = 0xd,
526 } netxen_mem_depth_t;
528 struct netxen_board_info {
540 u32 port_mask; /* available niu ports */
541 u32 peg_mask; /* available pegs */
542 u32 icache_ok; /* can we run with icache? */
543 u32 dcache_ok; /* can we run with dcache? */
551 /* MN-related config */
552 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
553 u32 mn_sync_shift_cclk;
554 u32 mn_sync_shift_mclk;
556 u32 mn_crystal_freq; /* in MHz */
557 u32 mn_speed; /* in MHz */
560 u32 mn_ranks_0; /* ranks per slot */
561 u32 mn_ranks_1; /* ranks per slot */
572 u32 mn_mode_reg; /* MIU DDR Mode Register */
573 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
574 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
575 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
576 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
578 /* SN-related config */
579 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
580 u32 sn_pt_mode; /* pass through mode */
595 u32 magic; /* indicates flash has been initialized */
602 #define FLASH_NUM_PORTS (4)
604 struct netxen_flash_mac_addr {
608 struct netxen_user_old_info {
620 /* primary image status */
622 u32 secondary_present;
624 /* MAC address , 4 ports */
625 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
627 #define FLASH_NUM_MAC_PER_PORT 32
628 struct netxen_user_info {
629 u8 flash_md5[16 * 64];
636 /* primary image status */
638 u32 secondary_present;
640 /* MAC address , 4 ports, 32 address per port */
641 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
645 /* Any user defined data */
649 * Flash Layout - new format.
651 struct netxen_new_user_info {
652 u8 flash_md5[16 * 64];
659 /* primary image status */
661 u32 secondary_present;
663 /* MAC address , 4 ports, 32 address per port */
664 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
668 /* Any user defined data */
671 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
672 #define SECONDARY_IMAGE_ABSENT 0xffffffff
673 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
674 #define PRIMARY_IMAGE_BAD 0xffffffff
676 /* Flash memory map */
678 NETXEN_CRBINIT_START = 0, /* Crbinit section */
679 NETXEN_BRDCFG_START = 0x4000, /* board config */
680 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
681 NETXEN_BOOTLD_START = 0x10000, /* bootld */
682 NETXEN_IMAGE_START = 0x43000, /* compressed image */
683 NETXEN_SECONDARY_START = 0x200000, /* backup images */
684 NETXEN_PXE_START = 0x3E0000, /* user defined region */
685 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
686 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
687 } netxen_flash_map_t;
689 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
690 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
691 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
692 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
693 #define NX_FW_MIN_SIZE (0x3fffff)
694 #define NX_P2_MN_ROMIMAGE "nxromimg.bin"
695 #define NX_P3_CT_ROMIMAGE "nx3fwct.bin"
696 #define NX_P3_MN_ROMIMAGE "nx3fwmn.bin"
698 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
700 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
701 #define NETXEN_INIT_SECTOR (0)
702 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
703 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
704 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
705 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
706 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
707 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
708 #define NETXEN_NUM_CONFIG_SECTORS (1)
709 #define PFX "NetXen: "
710 extern char netxen_nic_driver_name[];
712 /* Note: Make sure to not call this before adapter->port is valid */
713 #if !defined(NETXEN_DEBUG)
714 #define DPRINTK(klevel, fmt, args...) do { \
717 #define DPRINTK(klevel, fmt, args...) do { \
718 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
719 (adapter != NULL && adapter->netdev != NULL) ? \
720 adapter->netdev->name : NULL, \
724 /* Number of status descriptors to handle per interrupt */
725 #define MAX_STATUS_HANDLE (128)
728 * netxen_skb_frag{} is to contain mapping info for each SG list. This
729 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
731 struct netxen_skb_frag {
736 #define _netxen_set_bits(config_word, start, bits, val) {\
737 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
738 unsigned long long __tvalue = (val); \
739 (config_word) &= ~__tmask; \
740 (config_word) |= (((__tvalue) << (start)) & __tmask); \
743 #define _netxen_clear_bits(config_word, start, bits) {\
744 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
745 (config_word) &= ~__tmask; \
748 /* Following defines are for the state of the buffers */
749 #define NETXEN_BUFFER_FREE 0
750 #define NETXEN_BUFFER_BUSY 1
753 * There will be one netxen_buffer per skb packet. These will be
754 * used to save the dma info for pci_unmap_page()
756 struct netxen_cmd_buffer {
758 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
762 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
763 struct netxen_rx_buffer {
764 struct list_head list;
772 #define NETXEN_NIC_GBE 0x01
773 #define NETXEN_NIC_XGBE 0x02
776 * One hardware_context{} per adapter
777 * contains interrupt info as well shared hardware info.
779 struct netxen_hardware_context {
780 void __iomem *pci_base0;
781 void __iomem *pci_base1;
782 void __iomem *pci_base2;
783 void __iomem *db_base;
784 unsigned long db_len;
785 unsigned long pci_len0;
789 unsigned long mn_win_crb;
790 unsigned long ms_win_crb;
797 /* Address of cmd ring in Phantom */
798 struct cmd_desc_type0 *cmd_desc_head;
799 dma_addr_t cmd_desc_phys_addr;
800 struct netxen_adapter *adapter;
804 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
805 #define ETHERNET_FCS_SIZE 4
807 struct netxen_adapter_stats {
825 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
826 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
828 struct nx_host_rds_ring {
830 u32 crb_rcv_producer; /* reg offset */
831 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
832 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
833 struct list_head free_list;
838 dma_addr_t phys_addr;
842 * Receive context. There is one such structure per instance of the
843 * receive processing. Any state information that is relevant to
844 * the receive, and is must be in this structure. The global data may be
847 struct netxen_recv_context {
852 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
853 u32 status_rx_consumer;
854 u32 crb_sts_consumer; /* reg offset */
855 dma_addr_t rcv_status_desc_phys_addr;
856 struct status_desc *rcv_status_desc_head;
859 /* New HW context creation */
861 #define NX_OS_CRB_RETRY_COUNT 4000
862 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
863 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
865 #define NX_CDRP_CLEAR 0x00000000
866 #define NX_CDRP_CMD_BIT 0x80000000
869 * All responses must have the NX_CDRP_CMD_BIT cleared
870 * in the crb NX_CDRP_CRB_OFFSET.
872 #define NX_CDRP_FORM_RSP(rsp) (rsp)
873 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
875 #define NX_CDRP_RSP_OK 0x00000001
876 #define NX_CDRP_RSP_FAIL 0x00000002
877 #define NX_CDRP_RSP_TIMEOUT 0x00000003
880 * All commands must have the NX_CDRP_CMD_BIT set in
881 * the crb NX_CDRP_CRB_OFFSET.
883 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
884 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
886 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
887 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
888 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
889 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
890 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
891 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
892 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
893 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
894 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
895 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
896 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
897 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
898 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
899 #define NX_CDRP_CMD_SET_MTU 0x00000012
900 #define NX_CDRP_CMD_MAX 0x00000013
902 #define NX_RCODE_SUCCESS 0
903 #define NX_RCODE_NO_HOST_MEM 1
904 #define NX_RCODE_NO_HOST_RESOURCE 2
905 #define NX_RCODE_NO_CARD_CRB 3
906 #define NX_RCODE_NO_CARD_MEM 4
907 #define NX_RCODE_NO_CARD_RESOURCE 5
908 #define NX_RCODE_INVALID_ARGS 6
909 #define NX_RCODE_INVALID_ACTION 7
910 #define NX_RCODE_INVALID_STATE 8
911 #define NX_RCODE_NOT_SUPPORTED 9
912 #define NX_RCODE_NOT_PERMITTED 10
913 #define NX_RCODE_NOT_READY 11
914 #define NX_RCODE_DOES_NOT_EXIST 12
915 #define NX_RCODE_ALREADY_EXISTS 13
916 #define NX_RCODE_BAD_SIGNATURE 14
917 #define NX_RCODE_CMD_NOT_IMPL 15
918 #define NX_RCODE_CMD_INVALID 16
919 #define NX_RCODE_TIMEOUT 17
920 #define NX_RCODE_CMD_FAILED 18
921 #define NX_RCODE_MAX_EXCEEDED 19
922 #define NX_RCODE_MAX 20
924 #define NX_DESTROY_CTX_RESET 0
925 #define NX_DESTROY_CTX_D3_RESET 1
926 #define NX_DESTROY_CTX_MAX 2
931 #define NX_CAP_BIT(class, bit) (1 << bit)
932 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
933 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
934 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
935 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
936 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
937 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
938 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
939 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
940 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
945 #define NX_HOST_CTX_STATE_FREED 0
946 #define NX_HOST_CTX_STATE_ALLOCATED 1
947 #define NX_HOST_CTX_STATE_ACTIVE 2
948 #define NX_HOST_CTX_STATE_DISABLED 3
949 #define NX_HOST_CTX_STATE_QUIESCED 4
950 #define NX_HOST_CTX_STATE_MAX 5
957 __le64 host_phys_addr; /* Ring base addr */
958 __le32 ring_size; /* Ring entries */
960 __le16 rsvd; /* Padding */
961 } nx_hostrq_sds_ring_t;
964 __le64 host_phys_addr; /* Ring base addr */
965 __le64 buff_size; /* Packet buffer size */
966 __le32 ring_size; /* Ring entries */
967 __le32 ring_kind; /* Class of ring */
968 } nx_hostrq_rds_ring_t;
971 __le64 host_rsp_dma_addr; /* Response dma'd here */
972 __le32 capabilities[4]; /* Flag bit vector */
973 __le32 host_int_crb_mode; /* Interrupt crb usage */
974 __le32 host_rds_crb_mode; /* RDS crb usage */
975 /* These ring offsets are relative to data[0] below */
976 __le32 rds_ring_offset; /* Offset to RDS config */
977 __le32 sds_ring_offset; /* Offset to SDS config */
978 __le16 num_rds_rings; /* Count of RDS rings */
979 __le16 num_sds_rings; /* Count of SDS rings */
980 __le16 rsvd1; /* Padding */
981 __le16 rsvd2; /* Padding */
982 u8 reserved[128]; /* reserve space for future expansion*/
983 /* MUST BE 64-bit aligned.
984 The following is packed:
986 - N hostrq_sds_rings */
988 } nx_hostrq_rx_ctx_t;
991 __le32 host_producer_crb; /* Crb to use */
992 __le32 rsvd1; /* Padding */
993 } nx_cardrsp_rds_ring_t;
996 __le32 host_consumer_crb; /* Crb to use */
997 __le32 interrupt_crb; /* Crb to use */
998 } nx_cardrsp_sds_ring_t;
1001 /* These ring offsets are relative to data[0] below */
1002 __le32 rds_ring_offset; /* Offset to RDS config */
1003 __le32 sds_ring_offset; /* Offset to SDS config */
1004 __le32 host_ctx_state; /* Starting State */
1005 __le32 num_fn_per_port; /* How many PCI fn share the port */
1006 __le16 num_rds_rings; /* Count of RDS rings */
1007 __le16 num_sds_rings; /* Count of SDS rings */
1008 __le16 context_id; /* Handle for context */
1009 u8 phys_port; /* Physical id of port */
1010 u8 virt_port; /* Virtual/Logical id of port */
1011 u8 reserved[128]; /* save space for future expansion */
1012 /* MUST BE 64-bit aligned.
1013 The following is packed:
1014 - N cardrsp_rds_rings
1015 - N cardrs_sds_rings */
1017 } nx_cardrsp_rx_ctx_t;
1019 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1020 (sizeof(HOSTRQ_RX) + \
1021 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1022 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1024 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1025 (sizeof(CARDRSP_RX) + \
1026 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1027 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1034 __le64 host_phys_addr; /* Ring base addr */
1035 __le32 ring_size; /* Ring entries */
1036 __le32 rsvd; /* Padding */
1037 } nx_hostrq_cds_ring_t;
1040 __le64 host_rsp_dma_addr; /* Response dma'd here */
1041 __le64 cmd_cons_dma_addr; /* */
1042 __le64 dummy_dma_addr; /* */
1043 __le32 capabilities[4]; /* Flag bit vector */
1044 __le32 host_int_crb_mode; /* Interrupt crb usage */
1045 __le32 rsvd1; /* Padding */
1046 __le16 rsvd2; /* Padding */
1047 __le16 interrupt_ctl;
1049 __le16 rsvd3; /* Padding */
1050 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1051 u8 reserved[128]; /* future expansion */
1052 } nx_hostrq_tx_ctx_t;
1055 __le32 host_producer_crb; /* Crb to use */
1056 __le32 interrupt_crb; /* Crb to use */
1057 } nx_cardrsp_cds_ring_t;
1060 __le32 host_ctx_state; /* Starting state */
1061 __le16 context_id; /* Handle for context */
1062 u8 phys_port; /* Physical id of port */
1063 u8 virt_port; /* Virtual/Logical id of port */
1064 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1065 u8 reserved[128]; /* future expansion */
1066 } nx_cardrsp_tx_ctx_t;
1068 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1069 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1073 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1074 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1075 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1076 #define NX_HOST_RDS_CRB_MODE_MAX 3
1078 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1079 #define NX_HOST_INT_CRB_MODE_SHARED 1
1080 #define NX_HOST_INT_CRB_MODE_NORX 2
1081 #define NX_HOST_INT_CRB_MODE_NOTX 3
1082 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1087 #define MC_COUNT_P2 16
1088 #define MC_COUNT_P3 38
1090 #define NETXEN_MAC_NOOP 0
1091 #define NETXEN_MAC_ADD 1
1092 #define NETXEN_MAC_DEL 2
1094 typedef struct nx_mac_list_s {
1095 struct nx_mac_list_s *next;
1096 uint8_t mac_addr[MAX_ADDR_LEN];
1100 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1101 * adjusted based on configured MTU.
1103 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1104 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1105 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1106 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1108 #define NETXEN_NIC_INTR_DEFAULT 0x04
1112 uint16_t rx_packets;
1113 uint16_t rx_time_us;
1114 uint16_t tx_packets;
1115 uint16_t tx_time_us;
1118 } nx_nic_intr_coalesce_data_t;
1121 uint16_t stats_time_us;
1122 uint16_t rate_sample_time;
1125 uint32_t low_threshold;
1126 uint32_t high_threshold;
1127 nx_nic_intr_coalesce_data_t normal;
1128 nx_nic_intr_coalesce_data_t low;
1129 nx_nic_intr_coalesce_data_t high;
1130 nx_nic_intr_coalesce_data_t irq;
1131 } nx_nic_intr_coalesce_t;
1133 #define NX_HOST_REQUEST 0x13
1134 #define NX_NIC_REQUEST 0x14
1136 #define NX_MAC_EVENT 0x1
1139 NX_NIC_H2C_OPCODE_START = 0,
1140 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1141 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1142 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1143 NX_NIC_H2C_OPCODE_CONFIG_LED,
1144 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1145 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1146 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1147 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1148 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1149 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1150 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1151 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1152 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1153 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1154 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1155 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1156 NX_NIC_H2C_OPCODE_LAST
1159 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1160 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1161 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1175 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1177 #define NETXEN_NIC_MSI_ENABLED 0x02
1178 #define NETXEN_NIC_MSIX_ENABLED 0x04
1179 #define NETXEN_IS_MSI_FAMILY(adapter) \
1180 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1182 #define MSIX_ENTRIES_PER_ADAPTER 1
1183 #define NETXEN_MSIX_TBL_SPACE 8192
1184 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1186 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1188 #define NETXEN_NETDEV_WEIGHT 120
1189 #define NETXEN_ADAPTER_UP_MAGIC 777
1190 #define NETXEN_NIC_PEG_TUNE 0
1192 struct netxen_dummy_dma {
1194 dma_addr_t phys_addr;
1197 struct netxen_adapter {
1198 struct netxen_hardware_context ahw;
1200 struct net_device *netdev;
1201 struct pci_dev *pdev;
1203 struct napi_struct napi;
1204 struct net_device_stats net_stats;
1211 uint8_t max_mc_count;
1212 nx_mac_list_t *mac_list;
1214 struct netxen_legacy_intr_set legacy_intr;
1217 struct work_struct watchdog_task;
1218 struct timer_list watchdog_timer;
1219 struct work_struct tx_timeout_task;
1223 rwlock_t adapter_lock;
1226 __le32 *cmd_consumer;
1227 u32 last_cmd_consumer;
1228 u32 crb_addr_cmd_producer;
1229 u32 crb_addr_cmd_consumer;
1240 int driver_mismatch;
1247 u8 max_possible_rss_rings;
1248 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1250 struct netxen_adapter_stats stats;
1258 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1261 * Receive instances. These can be either one per port,
1262 * or one per peg, etc.
1264 struct netxen_recv_context recv_ctx;
1267 struct netxen_dummy_dma dummy_dma;
1268 nx_nic_intr_coalesce_t coal;
1270 /* Context interface shared between card and host */
1271 struct netxen_ring_ctx *ctx_desc;
1272 dma_addr_t ctx_desc_phys_addr;
1275 int (*enable_phy_interrupts) (struct netxen_adapter *);
1276 int (*disable_phy_interrupts) (struct netxen_adapter *);
1277 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1278 int (*set_mtu) (struct netxen_adapter *, int);
1279 int (*set_promisc) (struct netxen_adapter *, u32);
1280 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1281 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1282 int (*init_port) (struct netxen_adapter *, int);
1283 int (*stop_port) (struct netxen_adapter *);
1285 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1286 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1287 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1288 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1289 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1290 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1291 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1292 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1293 unsigned long (*pci_set_window)(struct netxen_adapter *,
1294 unsigned long long);
1295 }; /* netxen_adapter structure */
1298 * NetXen dma watchdog control structure
1300 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1301 * Bit 1 : disable_request => 1 req disable dma watchdog
1302 * Bit 2 : enable_request => 1 req enable dma watchdog
1306 #define netxen_set_dma_watchdog_disable_req(config_word) \
1307 _netxen_set_bits(config_word, 1, 1, 1)
1308 #define netxen_set_dma_watchdog_enable_req(config_word) \
1309 _netxen_set_bits(config_word, 2, 1, 1)
1310 #define netxen_get_dma_watchdog_enabled(config_word) \
1311 ((config_word) & 0x1)
1312 #define netxen_get_dma_watchdog_disabled(config_word) \
1313 (((config_word) >> 1) & 0x1)
1315 /* Max number of xmit producer threads that can run simultaneously */
1316 #define MAX_XMIT_PRODUCERS 16
1318 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1319 ((adapter)->ahw.pci_base0 + (off))
1320 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1321 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1322 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1323 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1325 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1328 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1329 return (adapter->ahw.pci_base0 + off);
1330 } else if ((off < SECOND_PAGE_GROUP_END) &&
1331 (off >= SECOND_PAGE_GROUP_START)) {
1332 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1333 } else if ((off < THIRD_PAGE_GROUP_END) &&
1334 (off >= THIRD_PAGE_GROUP_START)) {
1335 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1340 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1343 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1344 return adapter->ahw.pci_base0;
1345 } else if ((off < SECOND_PAGE_GROUP_END) &&
1346 (off >= SECOND_PAGE_GROUP_START)) {
1347 return adapter->ahw.pci_base1;
1348 } else if ((off < THIRD_PAGE_GROUP_END) &&
1349 (off >= THIRD_PAGE_GROUP_START)) {
1350 return adapter->ahw.pci_base2;
1355 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1356 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1357 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1358 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1359 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1361 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1362 long reg, __u32 val);
1364 /* Functions available from netxen_nic_hw.c */
1365 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1366 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1367 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1368 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1369 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1370 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1371 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1372 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1374 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1375 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1376 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1378 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1379 ulong off, void *data, int len);
1380 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1381 ulong off, void *data, int len);
1382 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1383 u64 off, void *data, int size);
1384 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1385 u64 off, void *data, int size);
1386 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1388 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1389 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1391 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1392 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1393 unsigned long long addr);
1394 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1397 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1398 ulong off, void *data, int len);
1399 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1400 ulong off, void *data, int len);
1401 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1402 u64 off, void *data, int size);
1403 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1404 u64 off, void *data, int size);
1405 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1406 unsigned long off, int data);
1407 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1409 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1410 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1412 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1413 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1414 unsigned long long addr);
1416 /* Functions from netxen_nic_init.c */
1417 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1418 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1419 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1420 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1421 int netxen_load_firmware(struct netxen_adapter *adapter);
1422 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1424 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1425 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1426 u8 *bytes, size_t size);
1427 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1428 u8 *bytes, size_t size);
1429 int netxen_flash_unlock(struct netxen_adapter *adapter);
1430 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1431 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1432 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1433 void netxen_halt_pegs(struct netxen_adapter *adapter);
1435 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1437 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1438 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1440 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1441 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1443 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1444 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1446 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1447 int netxen_init_firmware(struct netxen_adapter *adapter);
1448 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1449 void netxen_watchdog_task(struct work_struct *work);
1450 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid);
1451 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1452 int netxen_process_rcv_ring(struct netxen_adapter *adapter, int max);
1453 void netxen_p2_nic_set_multi(struct net_device *netdev);
1454 void netxen_p3_nic_set_multi(struct net_device *netdev);
1455 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1456 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1457 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1459 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1460 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1462 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1463 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1465 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1466 uint32_t crb_producer);
1469 * NetXen Board information
1472 #define NETXEN_MAX_SHORT_NAME 32
1473 struct netxen_brdinfo {
1474 netxen_brdtype_t brdtype; /* type of board */
1475 long ports; /* max no of physical ports */
1476 char short_name[NETXEN_MAX_SHORT_NAME];
1479 static const struct netxen_brdinfo netxen_boards[] = {
1480 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1481 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1482 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1483 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1484 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1485 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1486 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1487 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1488 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1489 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1490 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1491 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1492 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1493 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1494 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1495 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1496 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1497 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1498 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1501 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1503 static inline void get_brd_name_by_type(u32 type, char *name)
1506 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1507 if (netxen_boards[i].brdtype == type) {
1508 strcpy(name, netxen_boards[i].short_name);
1519 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1523 /* check if already inactive */
1524 if (adapter->hw_read_wx(adapter,
1525 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1526 printk(KERN_ERR "failed to read dma watchdog status\n");
1528 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1531 /* Send the disable request */
1532 netxen_set_dma_watchdog_disable_req(ctrl);
1533 netxen_crb_writelit_adapter(adapter,
1534 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1540 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1544 if (adapter->hw_read_wx(adapter,
1545 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1546 printk(KERN_ERR "failed to read dma watchdog status\n");
1548 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1552 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1556 if (adapter->hw_read_wx(adapter,
1557 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1558 printk(KERN_ERR "failed to read dma watchdog status\n");
1560 if (netxen_get_dma_watchdog_enabled(ctrl))
1563 /* send the wakeup request */
1564 netxen_set_dma_watchdog_enable_req(ctrl);
1566 netxen_crb_writelit_adapter(adapter,
1567 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1573 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1574 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1575 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1576 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1577 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1580 extern struct ethtool_ops netxen_nic_ethtool_ops;
1582 #endif /* __NETXEN_NIC_H_ */