2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
35 #define MS_WIN(addr) (addr & 0x0ffc0000)
37 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
39 #define CRB_BLK(off) ((off >> 20) & 0x3f)
40 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41 #define CRB_WINDOW_2M (0x130060)
42 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43 #define CRB_INDIRECT_2M (0x1e0000UL)
45 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
51 static inline u64 readq(void __iomem *addr)
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
58 static inline void writeq(u64 val, void __iomem *addr)
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
65 #define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
68 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
75 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
90 static crb_128M_2M_block_map_t
91 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
92 {{{0, 0, 0, 0} } }, /* 0: PCI */
93 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
94 {1, 0x0110000, 0x0120000, 0x130000},
95 {1, 0x0120000, 0x0122000, 0x124000},
96 {1, 0x0130000, 0x0132000, 0x126000},
97 {1, 0x0140000, 0x0142000, 0x128000},
98 {1, 0x0150000, 0x0152000, 0x12a000},
99 {1, 0x0160000, 0x0170000, 0x110000},
100 {1, 0x0170000, 0x0172000, 0x12e000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x01e0000, 0x01e0800, 0x122000},
108 {0, 0x0000000, 0x0000000, 0x000000} } },
109 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
110 {{{0, 0, 0, 0} } }, /* 3: */
111 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
112 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
113 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
114 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
115 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x08f0000, 0x08f2000, 0x172000} } },
131 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {1, 0x09f0000, 0x09f2000, 0x176000} } },
147 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
163 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
179 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
180 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
181 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
182 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
183 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
184 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
185 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
186 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
187 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
188 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
189 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
190 {{{0, 0, 0, 0} } }, /* 23: */
191 {{{0, 0, 0, 0} } }, /* 24: */
192 {{{0, 0, 0, 0} } }, /* 25: */
193 {{{0, 0, 0, 0} } }, /* 26: */
194 {{{0, 0, 0, 0} } }, /* 27: */
195 {{{0, 0, 0, 0} } }, /* 28: */
196 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
197 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
198 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
199 {{{0} } }, /* 32: PCI */
200 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
201 {1, 0x2110000, 0x2120000, 0x130000},
202 {1, 0x2120000, 0x2122000, 0x124000},
203 {1, 0x2130000, 0x2132000, 0x126000},
204 {1, 0x2140000, 0x2142000, 0x128000},
205 {1, 0x2150000, 0x2152000, 0x12a000},
206 {1, 0x2160000, 0x2170000, 0x110000},
207 {1, 0x2170000, 0x2172000, 0x12e000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000} } },
216 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
222 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
223 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
224 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
225 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
226 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
227 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
228 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
229 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
230 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
231 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
232 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
233 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
235 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
236 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
237 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
238 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
239 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
240 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
241 {{{0} } }, /* 59: I2C0 */
242 {{{0} } }, /* 60: I2C1 */
243 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
244 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
245 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
249 * top 12 bits of crb internal address (hub, agent)
251 static unsigned crb_hub_agt[64] =
254 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
259 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
260 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
265 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
266 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
267 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
269 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
281 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
282 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
284 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
286 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
287 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
293 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
302 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
303 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
304 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
309 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
311 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
315 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
319 /* PCI Windowing for DDR regions. */
321 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
323 #define NETXEN_PCIE_SEM_TIMEOUT 10000
326 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
328 int done = 0, timeout = 0;
331 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
334 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
340 NXWR32(adapter, id_reg, adapter->portnum);
346 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
348 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
351 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
365 u32 port = adapter->physical_port;
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
389 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
394 u32 port = adapter->physical_port;
395 u16 board_type = adapter->ahw.board_type;
397 if (port > NETXEN_NIU_MAX_XG_PORTS)
400 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
402 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
404 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
405 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
406 reg = (0x20 << port);
408 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
412 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
417 reg = NXRD32(adapter,
418 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
420 if (mode == NETXEN_NIU_PROMISC_MODE)
421 reg = (reg | 0x2000UL);
423 reg = (reg & ~0x2000UL);
425 if (mode == NETXEN_NIU_ALLMULTI_MODE)
426 reg = (reg | 0x1000UL);
428 reg = (reg & ~0x1000UL);
431 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
435 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
440 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
445 u8 phy = adapter->physical_port;
447 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
450 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
451 mac_hi = addr[2] | ((u32)addr[3] << 8) |
452 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
454 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
455 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
457 /* write twice to flush */
458 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
460 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
467 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
470 u16 port = adapter->physical_port;
471 u8 *addr = adapter->mac_addr;
473 if (adapter->mc_enabled)
476 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
477 val |= (1UL << (28+port));
478 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
480 /* add broadcast addr to filter */
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
485 /* add station addr to filter */
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
489 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
491 adapter->mc_enabled = 1;
496 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
499 u16 port = adapter->physical_port;
500 u8 *addr = adapter->mac_addr;
502 if (!adapter->mc_enabled)
505 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
506 val &= ~(1UL << (28+port));
507 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
514 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
515 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
517 adapter->mc_enabled = 0;
522 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
526 u16 port = adapter->physical_port;
531 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
532 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
537 void netxen_p2_nic_set_multi(struct net_device *netdev)
539 struct netxen_adapter *adapter = netdev_priv(netdev);
540 struct dev_mc_list *mc_ptr;
544 memset(null_addr, 0, 6);
546 if (netdev->flags & IFF_PROMISC) {
548 adapter->set_promisc(adapter,
549 NETXEN_NIU_PROMISC_MODE);
551 /* Full promiscuous mode */
552 netxen_nic_disable_mcast_filter(adapter);
557 if (netdev->mc_count == 0) {
558 adapter->set_promisc(adapter,
559 NETXEN_NIU_NON_PROMISC_MODE);
560 netxen_nic_disable_mcast_filter(adapter);
564 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
565 if (netdev->flags & IFF_ALLMULTI ||
566 netdev->mc_count > adapter->max_mc_count) {
567 netxen_nic_disable_mcast_filter(adapter);
571 netxen_nic_enable_mcast_filter(adapter);
573 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
574 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
576 if (index != netdev->mc_count)
577 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
578 netxen_nic_driver_name, netdev->name);
580 /* Clear out remaining addresses */
581 for (; index < adapter->max_mc_count; index++)
582 netxen_nic_set_mcast_addr(adapter, index, null_addr);
586 netxen_send_cmd_descs(struct netxen_adapter *adapter,
587 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
589 u32 i, producer, consumer;
590 struct netxen_cmd_buffer *pbuf;
591 struct cmd_desc_type0 *cmd_desc;
592 struct nx_host_tx_ring *tx_ring;
596 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
599 tx_ring = adapter->tx_ring;
600 __netif_tx_lock_bh(tx_ring->txq);
602 producer = tx_ring->producer;
603 consumer = tx_ring->sw_consumer;
605 if (nr_desc >= netxen_tx_avail(tx_ring)) {
606 netif_tx_stop_queue(tx_ring->txq);
607 __netif_tx_unlock_bh(tx_ring->txq);
612 cmd_desc = &cmd_desc_arr[i];
614 pbuf = &tx_ring->cmd_buf_arr[producer];
616 pbuf->frag_count = 0;
618 memcpy(&tx_ring->desc_head[producer],
619 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
621 producer = get_next_index(producer, tx_ring->num_desc);
624 } while (i != nr_desc);
626 tx_ring->producer = producer;
628 netxen_nic_update_cmd_producer(adapter, tx_ring);
630 __netif_tx_unlock_bh(tx_ring->txq);
636 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
639 nx_mac_req_t *mac_req;
642 memset(&req, 0, sizeof(nx_nic_req_t));
643 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
645 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
646 req.req_hdr = cpu_to_le64(word);
648 mac_req = (nx_mac_req_t *)&req.words[0];
650 memcpy(mac_req->mac_addr, addr, 6);
652 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
655 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
656 u8 *addr, struct list_head *del_list)
658 struct list_head *head;
661 /* look up if already exists */
662 list_for_each(head, del_list) {
663 cur = list_entry(head, nx_mac_list_t, list);
665 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
666 list_move_tail(head, &adapter->mac_list);
671 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
673 printk(KERN_ERR "%s: failed to add mac address filter\n",
674 adapter->netdev->name);
677 memcpy(cur->mac_addr, addr, ETH_ALEN);
678 list_add_tail(&cur->list, &adapter->mac_list);
679 return nx_p3_sre_macaddr_change(adapter,
680 cur->mac_addr, NETXEN_MAC_ADD);
683 void netxen_p3_nic_set_multi(struct net_device *netdev)
685 struct netxen_adapter *adapter = netdev_priv(netdev);
686 struct dev_mc_list *mc_ptr;
687 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
688 u32 mode = VPORT_MISS_MODE_DROP;
690 struct list_head *head;
693 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
696 list_splice_tail_init(&adapter->mac_list, &del_list);
698 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
699 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
701 if (netdev->flags & IFF_PROMISC) {
702 mode = VPORT_MISS_MODE_ACCEPT_ALL;
706 if ((netdev->flags & IFF_ALLMULTI) ||
707 (netdev->mc_count > adapter->max_mc_count)) {
708 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
712 if (netdev->mc_count > 0) {
713 for (mc_ptr = netdev->mc_list; mc_ptr;
714 mc_ptr = mc_ptr->next) {
715 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
720 adapter->set_promisc(adapter, mode);
722 while (!list_empty(head)) {
723 cur = list_entry(head->next, nx_mac_list_t, list);
725 nx_p3_sre_macaddr_change(adapter,
726 cur->mac_addr, NETXEN_MAC_DEL);
727 list_del(&cur->list);
732 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
737 memset(&req, 0, sizeof(nx_nic_req_t));
739 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
741 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
742 ((u64)adapter->portnum << 16);
743 req.req_hdr = cpu_to_le64(word);
745 req.words[0] = cpu_to_le64(mode);
747 return netxen_send_cmd_descs(adapter,
748 (struct cmd_desc_type0 *)&req, 1);
751 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
754 struct list_head *head = &adapter->mac_list;
756 while (!list_empty(head)) {
757 cur = list_entry(head->next, nx_mac_list_t, list);
758 nx_p3_sre_macaddr_change(adapter,
759 cur->mac_addr, NETXEN_MAC_DEL);
760 list_del(&cur->list);
765 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
767 /* assuming caller has already copied new addr to netdev */
768 netxen_p3_nic_set_multi(adapter->netdev);
772 #define NETXEN_CONFIG_INTR_COALESCE 3
775 * Send the interrupt coalescing parameter set by ethtool to the card.
777 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
783 memset(&req, 0, sizeof(nx_nic_req_t));
785 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
787 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
788 req.req_hdr = cpu_to_le64(word);
790 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
792 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
794 printk(KERN_ERR "ERROR. Could not send "
795 "interrupt coalescing parameters\n");
801 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
807 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
810 memset(&req, 0, sizeof(nx_nic_req_t));
812 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
814 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
815 req.req_hdr = cpu_to_le64(word);
817 req.words[0] = cpu_to_le64(enable);
819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
821 printk(KERN_ERR "ERROR. Could not send "
822 "configure hw lro request\n");
825 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
830 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
836 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
839 memset(&req, 0, sizeof(nx_nic_req_t));
841 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
843 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
844 ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
847 req.words[0] = cpu_to_le64(enable);
849 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
851 printk(KERN_ERR "ERROR. Could not send "
852 "configure bridge mode request\n");
855 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
861 #define RSS_HASHTYPE_IP_TCP 0x3
863 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
869 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
870 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
871 0x255b0ec26d5a56daULL };
874 memset(&req, 0, sizeof(nx_nic_req_t));
875 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
877 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
878 req.req_hdr = cpu_to_le64(word);
882 * bits 3-0: hash_method
883 * 5-4: hash_type_ipv4
884 * 7-6: hash_type_ipv6
886 * 9: use indirection table
888 * 63-48: indirection table mask
890 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
891 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
892 ((u64)(enable & 0x1) << 8) |
894 req.words[0] = cpu_to_le64(word);
895 for (i = 0; i < 5; i++)
896 req.words[i+1] = cpu_to_le64(key[i]);
899 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
901 printk(KERN_ERR "%s: could not configure RSS\n",
902 adapter->netdev->name);
908 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
914 memset(&req, 0, sizeof(nx_nic_req_t));
915 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
917 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
918 req.req_hdr = cpu_to_le64(word);
920 req.words[0] = cpu_to_le64(cmd);
921 req.words[1] = cpu_to_le64(ip);
923 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
925 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
926 adapter->netdev->name,
927 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
932 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
938 memset(&req, 0, sizeof(nx_nic_req_t));
939 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
941 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
942 req.req_hdr = cpu_to_le64(word);
943 req.words[0] = cpu_to_le64(enable | (enable << 8));
945 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
947 printk(KERN_ERR "%s: could not configure link notification\n",
948 adapter->netdev->name);
954 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
960 memset(&req, 0, sizeof(nx_nic_req_t));
961 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
963 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
964 ((u64)adapter->portnum << 16) |
965 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
967 req.req_hdr = cpu_to_le64(word);
969 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
971 printk(KERN_ERR "%s: could not cleanup lro flows\n",
972 adapter->netdev->name);
978 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
979 * @returns 0 on success, negative on failure
982 #define MTU_FUDGE_FACTOR 100
984 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
986 struct netxen_adapter *adapter = netdev_priv(netdev);
990 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
991 max_mtu = P3_MAX_MTU;
993 max_mtu = P2_MAX_MTU;
996 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
997 netdev->name, max_mtu);
1001 if (adapter->set_mtu)
1002 rc = adapter->set_mtu(adapter, mtu);
1010 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1011 int size, __le32 * buf)
1018 for (i = 0; i < size / sizeof(u32); i++) {
1019 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1021 *ptr32 = cpu_to_le32(v);
1023 addr += sizeof(u32);
1025 if ((char *)buf + size > (char *)ptr32) {
1027 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1029 local = cpu_to_le32(v);
1030 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1036 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1038 __le32 *pmac = (__le32 *) mac;
1041 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1043 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1046 if (*mac == cpu_to_le64(~0ULL)) {
1048 offset = NX_OLD_MAC_ADDR_OFFSET +
1049 (adapter->portnum * sizeof(u64));
1051 if (netxen_get_flash_block(adapter,
1052 offset, sizeof(u64), pmac) == -1)
1055 if (*mac == cpu_to_le64(~0ULL))
1061 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1063 uint32_t crbaddr, mac_hi, mac_lo;
1064 int pci_func = adapter->ahw.pci_func;
1066 crbaddr = CRB_MAC_BLOCK_START +
1067 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1069 mac_lo = NXRD32(adapter, crbaddr);
1070 mac_hi = NXRD32(adapter, crbaddr+4);
1073 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1075 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1081 * Changes the CRB window to the specified window.
1084 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1087 void __iomem *offset;
1089 u8 func = adapter->ahw.pci_func;
1091 if (adapter->ahw.crb_win == window)
1094 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1095 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1097 writel(window, offset);
1099 if (window == readl(offset))
1102 if (printk_ratelimit())
1103 dev_warn(&adapter->pdev->dev,
1104 "failed to set CRB window to %d\n",
1105 (window == NETXEN_WINDOW_ONE));
1108 } while (--count > 0);
1111 adapter->ahw.crb_win = window;
1115 * Returns < 0 if off is not valid,
1116 * 1 if window access is needed. 'off' is set to offset from
1117 * CRB space in 128M pci map
1118 * 0 if no window access is needed. 'off' is set to 2M addr
1119 * In: 'off' is offset from base in 128M pci map
1122 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1123 ulong off, void __iomem **addr)
1125 crb_128M_2M_sub_block_map_t *m;
1128 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1131 off -= NETXEN_PCI_CRBSPACE;
1136 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1138 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1139 *addr = adapter->ahw.pci_base0 + m->start_2M +
1140 (off - m->start_128M);
1145 * Not in direct map, use crb window
1147 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1153 * In: 'off' is offset from CRB space in 128M pci map
1154 * Out: 'off' is 2M pci map addr
1155 * side effect: lock crb window
1158 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1161 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1163 off -= NETXEN_PCI_CRBSPACE;
1165 window = CRB_HI(off);
1167 if (adapter->ahw.crb_win == window)
1170 writel(window, addr);
1171 if (readl(addr) != window) {
1172 if (printk_ratelimit())
1173 dev_warn(&adapter->pdev->dev,
1174 "failed to set CRB window to %d off 0x%lx\n",
1177 adapter->ahw.crb_win = window;
1180 static void __iomem *
1181 netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1182 ulong win_off, void __iomem **mem_ptr)
1184 ulong off = win_off;
1186 resource_size_t mem_base;
1188 if (ADDR_IN_WINDOW1(win_off))
1189 off = NETXEN_CRB_NORMAL(win_off);
1191 addr = pci_base_offset(adapter, off);
1195 if (adapter->ahw.pci_len0 == 0)
1196 off -= NETXEN_PCI_CRBSPACE;
1198 mem_base = pci_resource_start(adapter->pdev, 0);
1199 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1201 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1207 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1209 unsigned long flags;
1210 void __iomem *addr, *mem_ptr = NULL;
1212 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1216 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1217 netxen_nic_io_write_128M(adapter, addr, data);
1218 } else { /* Window 0 */
1219 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1220 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1222 netxen_nic_pci_set_crbwindow_128M(adapter,
1224 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1234 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1236 unsigned long flags;
1237 void __iomem *addr, *mem_ptr = NULL;
1240 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1244 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1245 data = netxen_nic_io_read_128M(adapter, addr);
1246 } else { /* Window 0 */
1247 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1248 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1250 netxen_nic_pci_set_crbwindow_128M(adapter,
1252 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1262 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1264 unsigned long flags;
1266 void __iomem *addr = NULL;
1268 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1276 /* indirect access */
1277 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1278 crb_win_lock(adapter);
1279 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1281 crb_win_unlock(adapter);
1282 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1286 dev_err(&adapter->pdev->dev,
1287 "%s: invalid offset: 0x%016lx\n", __func__, off);
1293 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1295 unsigned long flags;
1298 void __iomem *addr = NULL;
1300 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1306 /* indirect access */
1307 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1308 crb_win_lock(adapter);
1309 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1311 crb_win_unlock(adapter);
1312 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1316 dev_err(&adapter->pdev->dev,
1317 "%s: invalid offset: 0x%016lx\n", __func__, off);
1322 /* window 1 registers only */
1323 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1324 void __iomem *addr, u32 data)
1326 read_lock(&adapter->ahw.crb_lock);
1328 read_unlock(&adapter->ahw.crb_lock);
1331 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1336 read_lock(&adapter->ahw.crb_lock);
1338 read_unlock(&adapter->ahw.crb_lock);
1343 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1344 void __iomem *addr, u32 data)
1349 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1356 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1358 void __iomem *addr = NULL;
1360 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1361 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1362 (offset > NETXEN_CRB_PCIX_HOST))
1363 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1365 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1367 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1375 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1376 u64 addr, u32 *start)
1378 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1379 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1381 } else if (ADDR_IN_RANGE(addr,
1382 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1383 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1391 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1392 u64 addr, u32 *start)
1395 struct pci_dev *pdev = adapter->pdev;
1397 if ((addr & 0x00ff800) == 0xff800) {
1398 if (printk_ratelimit())
1399 dev_warn(&pdev->dev, "QM access not handled\n");
1403 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1404 window = OCM_WIN_P3P(addr);
1406 window = OCM_WIN(addr);
1408 writel(window, adapter->ahw.ocm_win_crb);
1409 /* read back to flush */
1410 readl(adapter->ahw.ocm_win_crb);
1412 adapter->ahw.ocm_win = window;
1413 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1418 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1421 void __iomem *addr, *mem_ptr = NULL;
1422 resource_size_t mem_base;
1426 spin_lock(&adapter->ahw.mem_lock);
1428 ret = adapter->pci_set_window(adapter, off, &start);
1432 addr = pci_base_offset(adapter, start);
1436 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
1438 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1439 if (mem_ptr == NULL) {
1444 addr = mem_ptr + (start & (PAGE_SIZE - 1));
1447 if (op == 0) /* read */
1448 *data = readq(addr);
1450 writeq(*data, addr);
1453 spin_unlock(&adapter->ahw.mem_lock);
1460 #define MAX_CTL_CHECK 1000
1463 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1467 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1468 void __iomem *mem_crb;
1470 /* Only 64-bit aligned access */
1474 /* P2 has different SIU and MIU test agent base addr */
1475 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1476 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1477 mem_crb = pci_base_offset(adapter,
1478 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1479 addr_hi = SIU_TEST_AGT_ADDR_HI;
1480 data_lo = SIU_TEST_AGT_WRDATA_LO;
1481 data_hi = SIU_TEST_AGT_WRDATA_HI;
1482 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1483 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1487 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1488 mem_crb = pci_base_offset(adapter,
1489 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1490 addr_hi = MIU_TEST_AGT_ADDR_HI;
1491 data_lo = MIU_TEST_AGT_WRDATA_LO;
1492 data_hi = MIU_TEST_AGT_WRDATA_HI;
1493 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1498 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1499 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1500 if (adapter->ahw.pci_len0 != 0) {
1501 return netxen_nic_pci_mem_access_direct(adapter,
1509 spin_lock(&adapter->ahw.mem_lock);
1510 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1512 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1513 writel(off_hi, (mem_crb + addr_hi));
1514 writel(data & 0xffffffff, (mem_crb + data_lo));
1515 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1516 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1517 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1518 (mem_crb + TEST_AGT_CTRL));
1520 for (j = 0; j < MAX_CTL_CHECK; j++) {
1521 temp = readl((mem_crb + TEST_AGT_CTRL));
1522 if ((temp & TA_CTL_BUSY) == 0)
1526 if (j >= MAX_CTL_CHECK) {
1527 if (printk_ratelimit())
1528 dev_err(&adapter->pdev->dev,
1529 "failed to write through agent\n");
1534 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1535 spin_unlock(&adapter->ahw.mem_lock);
1540 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1544 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1546 void __iomem *mem_crb;
1548 /* Only 64-bit aligned access */
1552 /* P2 has different SIU and MIU test agent base addr */
1553 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1554 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1555 mem_crb = pci_base_offset(adapter,
1556 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1557 addr_hi = SIU_TEST_AGT_ADDR_HI;
1558 data_lo = SIU_TEST_AGT_RDDATA_LO;
1559 data_hi = SIU_TEST_AGT_RDDATA_HI;
1560 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1561 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1565 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1566 mem_crb = pci_base_offset(adapter,
1567 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1568 addr_hi = MIU_TEST_AGT_ADDR_HI;
1569 data_lo = MIU_TEST_AGT_RDDATA_LO;
1570 data_hi = MIU_TEST_AGT_RDDATA_HI;
1571 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1576 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1577 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1578 if (adapter->ahw.pci_len0 != 0) {
1579 return netxen_nic_pci_mem_access_direct(adapter,
1587 spin_lock(&adapter->ahw.mem_lock);
1588 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1590 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1591 writel(off_hi, (mem_crb + addr_hi));
1592 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1593 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1595 for (j = 0; j < MAX_CTL_CHECK; j++) {
1596 temp = readl(mem_crb + TEST_AGT_CTRL);
1597 if ((temp & TA_CTL_BUSY) == 0)
1601 if (j >= MAX_CTL_CHECK) {
1602 if (printk_ratelimit())
1603 dev_err(&adapter->pdev->dev,
1604 "failed to read through agent\n");
1608 temp = readl(mem_crb + data_hi);
1609 val = ((u64)temp << 32);
1610 val |= readl(mem_crb + data_lo);
1615 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1616 spin_unlock(&adapter->ahw.mem_lock);
1622 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1628 void __iomem *mem_crb;
1630 /* Only 64-bit aligned access */
1634 /* P3 onward, test agent base for MIU and SIU is same */
1635 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1636 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1637 mem_crb = netxen_get_ioaddr(adapter,
1638 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1642 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1643 mem_crb = netxen_get_ioaddr(adapter,
1644 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1648 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1649 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1654 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1656 off8 = off & ~(stride-1);
1658 spin_lock(&adapter->ahw.mem_lock);
1660 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1661 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1665 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1666 writel((TA_CTL_START | TA_CTL_ENABLE),
1667 (mem_crb + TEST_AGT_CTRL));
1669 for (j = 0; j < MAX_CTL_CHECK; j++) {
1670 temp = readl(mem_crb + TEST_AGT_CTRL);
1671 if ((temp & TA_CTL_BUSY) == 0)
1675 if (j >= MAX_CTL_CHECK) {
1680 i = (off & 0xf) ? 0 : 2;
1681 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1682 mem_crb + MIU_TEST_AGT_WRDATA(i));
1683 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1684 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1685 i = (off & 0xf) ? 2 : 0;
1688 writel(data & 0xffffffff,
1689 mem_crb + MIU_TEST_AGT_WRDATA(i));
1690 writel((data >> 32) & 0xffffffff,
1691 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1693 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1694 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1695 (mem_crb + TEST_AGT_CTRL));
1697 for (j = 0; j < MAX_CTL_CHECK; j++) {
1698 temp = readl(mem_crb + TEST_AGT_CTRL);
1699 if ((temp & TA_CTL_BUSY) == 0)
1703 if (j >= MAX_CTL_CHECK) {
1704 if (printk_ratelimit())
1705 dev_err(&adapter->pdev->dev,
1706 "failed to write through agent\n");
1712 spin_unlock(&adapter->ahw.mem_lock);
1718 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1724 void __iomem *mem_crb;
1726 /* Only 64-bit aligned access */
1730 /* P3 onward, test agent base for MIU and SIU is same */
1731 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1732 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1733 mem_crb = netxen_get_ioaddr(adapter,
1734 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1738 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1739 mem_crb = netxen_get_ioaddr(adapter,
1740 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1744 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1745 return netxen_nic_pci_mem_access_direct(adapter,
1752 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1754 off8 = off & ~(stride-1);
1756 spin_lock(&adapter->ahw.mem_lock);
1758 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1759 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1760 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1761 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1763 for (j = 0; j < MAX_CTL_CHECK; j++) {
1764 temp = readl(mem_crb + TEST_AGT_CTRL);
1765 if ((temp & TA_CTL_BUSY) == 0)
1769 if (j >= MAX_CTL_CHECK) {
1770 if (printk_ratelimit())
1771 dev_err(&adapter->pdev->dev,
1772 "failed to read through agent\n");
1775 off8 = MIU_TEST_AGT_RDDATA_LO;
1776 if ((stride == 16) && (off & 0xf))
1777 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1779 temp = readl(mem_crb + off8 + 4);
1780 val = (u64)temp << 32;
1781 val |= readl(mem_crb + off8);
1786 spin_unlock(&adapter->ahw.mem_lock);
1792 netxen_setup_hwops(struct netxen_adapter *adapter)
1794 adapter->init_port = netxen_niu_xg_init_port;
1795 adapter->stop_port = netxen_niu_disable_xg_port;
1797 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1798 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1799 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1800 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1801 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1802 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1803 adapter->io_read = netxen_nic_io_read_128M,
1804 adapter->io_write = netxen_nic_io_write_128M,
1806 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1807 adapter->set_multi = netxen_p2_nic_set_multi;
1808 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1809 adapter->set_promisc = netxen_p2_nic_set_promisc;
1812 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1813 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1814 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1815 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1816 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1817 adapter->io_read = netxen_nic_io_read_2M,
1818 adapter->io_write = netxen_nic_io_write_2M,
1820 adapter->set_mtu = nx_fw_cmd_set_mtu;
1821 adapter->set_promisc = netxen_p3_nic_set_promisc;
1822 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1823 adapter->set_multi = netxen_p3_nic_set_multi;
1825 adapter->phy_read = nx_fw_cmd_query_phy;
1826 adapter->phy_write = nx_fw_cmd_set_phy;
1830 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1832 int offset, board_type, magic;
1833 struct pci_dev *pdev = adapter->pdev;
1835 offset = NX_FW_MAGIC_OFFSET;
1836 if (netxen_rom_fast_read(adapter, offset, &magic))
1839 if (magic != NETXEN_BDINFO_MAGIC) {
1840 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1845 offset = NX_BRDTYPE_OFFSET;
1846 if (netxen_rom_fast_read(adapter, offset, &board_type))
1849 adapter->ahw.board_type = board_type;
1851 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1852 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1853 if ((gpio & 0x8000) == 0)
1854 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1857 switch (board_type) {
1858 case NETXEN_BRDTYPE_P2_SB35_4G:
1859 adapter->ahw.port_type = NETXEN_NIC_GBE;
1861 case NETXEN_BRDTYPE_P2_SB31_10G:
1862 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1863 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1864 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1865 case NETXEN_BRDTYPE_P3_HMEZ:
1866 case NETXEN_BRDTYPE_P3_XG_LOM:
1867 case NETXEN_BRDTYPE_P3_10G_CX4:
1868 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1869 case NETXEN_BRDTYPE_P3_IMEZ:
1870 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1871 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1872 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1873 case NETXEN_BRDTYPE_P3_10G_XFP:
1874 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1875 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1877 case NETXEN_BRDTYPE_P1_BD:
1878 case NETXEN_BRDTYPE_P1_SB:
1879 case NETXEN_BRDTYPE_P1_SMAX:
1880 case NETXEN_BRDTYPE_P1_SOCK:
1881 case NETXEN_BRDTYPE_P3_REF_QG:
1882 case NETXEN_BRDTYPE_P3_4_GB:
1883 case NETXEN_BRDTYPE_P3_4_GB_MM:
1884 adapter->ahw.port_type = NETXEN_NIC_GBE;
1886 case NETXEN_BRDTYPE_P3_10G_TP:
1887 adapter->ahw.port_type = (adapter->portnum < 2) ?
1888 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1891 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1892 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1899 /* NIU access sections */
1901 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1903 new_mtu += MTU_FUDGE_FACTOR;
1904 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1909 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1911 new_mtu += MTU_FUDGE_FACTOR;
1912 if (adapter->physical_port == 0)
1913 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1915 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1919 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1925 if (!netif_carrier_ok(adapter->netdev)) {
1926 adapter->link_speed = 0;
1927 adapter->link_duplex = -1;
1928 adapter->link_autoneg = AUTONEG_ENABLE;
1932 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1933 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1934 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1935 adapter->link_speed = SPEED_1000;
1936 adapter->link_duplex = DUPLEX_FULL;
1937 adapter->link_autoneg = AUTONEG_DISABLE;
1941 if (adapter->phy_read &&
1942 adapter->phy_read(adapter,
1943 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1945 if (netxen_get_phy_link(status)) {
1946 switch (netxen_get_phy_speed(status)) {
1948 adapter->link_speed = SPEED_10;
1951 adapter->link_speed = SPEED_100;
1954 adapter->link_speed = SPEED_1000;
1957 adapter->link_speed = 0;
1960 switch (netxen_get_phy_duplex(status)) {
1962 adapter->link_duplex = DUPLEX_HALF;
1965 adapter->link_duplex = DUPLEX_FULL;
1968 adapter->link_duplex = -1;
1971 if (adapter->phy_read &&
1972 adapter->phy_read(adapter,
1973 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1975 adapter->link_autoneg = autoneg;
1980 adapter->link_speed = 0;
1981 adapter->link_duplex = -1;
1987 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1991 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1994 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1995 if (wol_cfg & (1UL << adapter->portnum)) {
1996 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1997 if (wol_cfg & (1 << adapter->portnum))