1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "1.0"
37 #define DRV_MODULE_RELDATE "Nov 14, 2008"
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64 readq(void __iomem *reg)
54 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
57 static void writeq(u64 val, void __iomem *reg)
59 writel(val & 0xffffffff, reg);
60 writel(val >> 32, reg + 0x4UL);
64 static struct pci_device_id niu_pci_tbl[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71 #define NIU_TX_TIMEOUT (5 * HZ)
73 #define nr64(reg) readq(np->regs + (reg))
74 #define nw64(reg, val) writeq((val), np->regs + (reg))
76 #define nr64_mac(reg) readq(np->mac_regs + (reg))
77 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91 static int debug = -1;
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "NIU debug level");
95 #define niudbg(TYPE, f, a...) \
96 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
100 #define niuinfo(TYPE, f, a...) \
101 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
105 #define niuwarn(TYPE, f, a...) \
106 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
110 #define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112 #define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
115 static int serdes_init_10g_serdes(struct niu *np);
117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118 u64 bits, int limit, int delay)
120 while (--limit >= 0) {
121 u64 val = nr64_mac(reg);
132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133 u64 bits, int limit, int delay,
134 const char *reg_name)
139 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
141 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np->dev->name, (unsigned long long) bits, reg_name,
144 (unsigned long long) nr64_mac(reg));
148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154 u64 bits, int limit, int delay)
156 while (--limit >= 0) {
157 u64 val = nr64_ipp(reg);
168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169 u64 bits, int limit, int delay,
170 const char *reg_name)
179 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
181 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np->dev->name, (unsigned long long) bits, reg_name,
184 (unsigned long long) nr64_ipp(reg));
188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay)
196 while (--limit >= 0) {
208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214 u64 bits, int limit, int delay,
215 const char *reg_name)
220 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np->dev->name, (unsigned long long) bits, reg_name,
225 (unsigned long long) nr64(reg));
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
236 u64 val = (u64) lp->timer;
239 val |= LDG_IMGMT_ARM;
241 nw64(LDG_IMGMT(lp->ldg_num), val);
244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
246 unsigned long mask_reg, bits;
249 if (ldn < 0 || ldn > LDN_MAX)
253 mask_reg = LD_IM0(ldn);
256 mask_reg = LD_IM1(ldn - 64);
260 val = nr64(mask_reg);
270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
272 struct niu_parent *parent = np->parent;
275 for (i = 0; i <= LDN_MAX; i++) {
278 if (parent->ldg_map[i] != lp->ldg_num)
281 err = niu_ldn_irq_enable(np, i, on);
288 static int niu_enable_interrupts(struct niu *np, int on)
292 for (i = 0; i < np->num_ldg; i++) {
293 struct niu_ldg *lp = &np->ldg[i];
296 err = niu_enable_ldn_in_ldg(np, lp, on);
300 for (i = 0; i < np->num_ldg; i++)
301 niu_ldg_rearm(np, &np->ldg[i], on);
306 static u32 phy_encode(u32 type, int port)
308 return (type << (port * 2));
311 static u32 phy_decode(u32 val, int port)
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
316 static int mdio_wait(struct niu *np)
321 while (--limit > 0) {
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
332 static int mdio_read(struct niu *np, int port, int dev, int reg)
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342 return mdio_wait(np);
345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
362 static int mii_read(struct niu *np, int port, int reg)
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365 return mdio_wait(np);
368 static int mii_write(struct niu *np, int port, int reg, int data)
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385 ESR2_TI_PLL_TX_CFG_L(channel),
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389 ESR2_TI_PLL_TX_CFG_H(channel),
394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399 ESR2_TI_PLL_RX_CFG_L(channel),
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_RX_CFG_H(channel),
408 /* Mode is always 10G fiber. */
409 static int serdes_init_niu_10g_fiber(struct niu *np)
411 struct niu_link_config *lp = &np->link_config;
415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418 PLL_RX_CFG_EQ_LP_ADAPTIVE);
420 if (lp->loopback_mode == LOOPBACK_PHY) {
421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
426 tx_cfg |= PLL_TX_CFG_ENTEST;
427 rx_cfg |= PLL_RX_CFG_ENTEST;
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i = 0; i < 4; i++) {
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
437 for (i = 0; i < 4; i++) {
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
446 static int serdes_init_niu_1g_serdes(struct niu *np)
448 struct niu_link_config *lp = &np->link_config;
449 u16 pll_cfg, pll_sts;
451 u64 uninitialized_var(sig), mask, val;
456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457 PLL_TX_CFG_RATE_HALF);
458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460 PLL_RX_CFG_RATE_HALF);
463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
465 if (lp->loopback_mode == LOOPBACK_PHY) {
466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
471 tx_cfg |= PLL_TX_CFG_ENTEST;
472 rx_cfg |= PLL_RX_CFG_ENTEST;
475 /* Initialize PLL for 1G */
476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479 ESR2_TI_PLL_CFG_L, pll_cfg);
481 dev_err(np->device, PFX "NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
487 pll_sts = PLL_CFG_ENPLL;
489 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 ESR2_TI_PLL_STS_L, pll_sts);
492 dev_err(np->device, PFX "NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i = 0; i < 4; i++) {
502 err = esr2_set_tx_cfg(np, i, tx_cfg);
507 for (i = 0; i < 4; i++) {
508 err = esr2_set_rx_cfg(np, i, rx_cfg);
515 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
520 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
528 while (max_retry--) {
529 sig = nr64(ESR_INT_SIGNALS);
530 if ((sig & mask) == val)
536 if ((sig & mask) != val) {
537 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
545 static int serdes_init_niu_10g_serdes(struct niu *np)
547 struct niu_link_config *lp = &np->link_config;
548 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
550 u64 uninitialized_var(sig), mask, val;
554 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557 PLL_RX_CFG_EQ_LP_ADAPTIVE);
559 if (lp->loopback_mode == LOOPBACK_PHY) {
560 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
562 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
565 tx_cfg |= PLL_TX_CFG_ENTEST;
566 rx_cfg |= PLL_RX_CFG_ENTEST;
569 /* Initialize PLL for 10G */
570 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
572 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
575 dev_err(np->device, PFX "NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
581 pll_sts = PLL_CFG_ENPLL;
583 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
586 dev_err(np->device, PFX "NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i = 0; i < 4; i++) {
596 err = esr2_set_tx_cfg(np, i, tx_cfg);
601 for (i = 0; i < 4; i++) {
602 err = esr2_set_rx_cfg(np, i, rx_cfg);
607 /* check if serdes is ready */
611 mask = ESR_INT_SIGNALS_P0_BITS;
612 val = (ESR_INT_SRDY0_P0 |
622 mask = ESR_INT_SIGNALS_P1_BITS;
623 val = (ESR_INT_SRDY0_P1 |
636 while (max_retry--) {
637 sig = nr64(ESR_INT_SIGNALS);
638 if ((sig & mask) == val)
644 if ((sig & mask) != val) {
645 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np->port, (int) (sig & mask), (int) val);
649 /* 10G failed, try initializing at 1G */
650 err = serdes_init_niu_1g_serdes(np);
652 np->flags &= ~NIU_FLAGS_10G;
653 np->mac_xcvr = MAC_XCVR_PCS;
655 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656 "Link Failed \n", np->port);
663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
667 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
669 *val = (err & 0xffff);
670 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671 ESR_RXTX_CTRL_H(chan));
673 *val |= ((err & 0xffff) << 16);
679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
683 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 ESR_GLUE_CTRL0_L(chan));
686 *val = (err & 0xffff);
687 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688 ESR_GLUE_CTRL0_H(chan));
690 *val |= ((err & 0xffff) << 16);
697 static int esr_read_reset(struct niu *np, u32 *val)
701 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 ESR_RXTX_RESET_CTRL_L);
704 *val = (err & 0xffff);
705 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_RXTX_RESET_CTRL_H);
708 *val |= ((err & 0xffff) << 16);
715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_CTRL_L(chan), val & 0xffff);
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_CTRL_H(chan), (val >> 16));
727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
731 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_GLUE_CTRL0_H(chan), (val >> 16));
739 static int esr_reset(struct niu *np)
741 u32 uninitialized_var(reset);
744 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 ESR_RXTX_RESET_CTRL_L, 0x0000);
748 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 ESR_RXTX_RESET_CTRL_H, 0xffff);
754 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 ESR_RXTX_RESET_CTRL_L, 0xffff);
760 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761 ESR_RXTX_RESET_CTRL_H, 0x0000);
766 err = esr_read_reset(np, &reset);
770 dev_err(np->device, PFX "Port %u ESR_RESET "
771 "did not clear [%08x]\n",
779 static int serdes_init_10g(struct niu *np)
781 struct niu_link_config *lp = &np->link_config;
782 unsigned long ctrl_reg, test_cfg_reg, i;
783 u64 ctrl_val, test_cfg_val, sig, mask, val;
788 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
792 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
799 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800 ENET_SERDES_CTRL_SDET_1 |
801 ENET_SERDES_CTRL_SDET_2 |
802 ENET_SERDES_CTRL_SDET_3 |
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
813 if (lp->loopback_mode == LOOPBACK_PHY) {
814 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815 ENET_SERDES_TEST_MD_0_SHIFT) |
816 (ENET_TEST_MD_PAD_LOOPBACK <<
817 ENET_SERDES_TEST_MD_1_SHIFT) |
818 (ENET_TEST_MD_PAD_LOOPBACK <<
819 ENET_SERDES_TEST_MD_2_SHIFT) |
820 (ENET_TEST_MD_PAD_LOOPBACK <<
821 ENET_SERDES_TEST_MD_3_SHIFT));
824 nw64(ctrl_reg, ctrl_val);
825 nw64(test_cfg_reg, test_cfg_val);
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i = 0; i < 4; i++) {
829 u32 rxtx_ctrl, glue0;
831 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
834 err = esr_read_glue0(np, i, &glue0);
838 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
842 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843 ESR_GLUE_CTRL0_THCNT |
844 ESR_GLUE_CTRL0_BLTIME);
845 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848 (BLTIME_300_CYCLES <<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT));
851 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
854 err = esr_write_glue0(np, i, glue0);
863 sig = nr64(ESR_INT_SIGNALS);
866 mask = ESR_INT_SIGNALS_P0_BITS;
867 val = (ESR_INT_SRDY0_P0 |
877 mask = ESR_INT_SIGNALS_P1_BITS;
878 val = (ESR_INT_SRDY0_P1 |
891 if ((sig & mask) != val) {
892 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
896 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
900 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
905 static int serdes_init_1g(struct niu *np)
909 val = nr64(ENET_SERDES_1_PLL_CFG);
910 val &= ~ENET_SERDES_PLL_FBDIV2;
913 val |= ENET_SERDES_PLL_HRATE0;
916 val |= ENET_SERDES_PLL_HRATE1;
919 val |= ENET_SERDES_PLL_HRATE2;
922 val |= ENET_SERDES_PLL_HRATE3;
927 nw64(ENET_SERDES_1_PLL_CFG, val);
932 static int serdes_init_1g_serdes(struct niu *np)
934 struct niu_link_config *lp = &np->link_config;
935 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936 u64 ctrl_val, test_cfg_val, sig, mask, val;
938 u64 reset_val, val_rd;
940 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942 ENET_SERDES_PLL_FBDIV0;
945 reset_val = ENET_SERDES_RESET_0;
946 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948 pll_cfg = ENET_SERDES_0_PLL_CFG;
951 reset_val = ENET_SERDES_RESET_1;
952 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954 pll_cfg = ENET_SERDES_1_PLL_CFG;
960 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961 ENET_SERDES_CTRL_SDET_1 |
962 ENET_SERDES_CTRL_SDET_2 |
963 ENET_SERDES_CTRL_SDET_3 |
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
974 if (lp->loopback_mode == LOOPBACK_PHY) {
975 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976 ENET_SERDES_TEST_MD_0_SHIFT) |
977 (ENET_TEST_MD_PAD_LOOPBACK <<
978 ENET_SERDES_TEST_MD_1_SHIFT) |
979 (ENET_TEST_MD_PAD_LOOPBACK <<
980 ENET_SERDES_TEST_MD_2_SHIFT) |
981 (ENET_TEST_MD_PAD_LOOPBACK <<
982 ENET_SERDES_TEST_MD_3_SHIFT));
985 nw64(ENET_SERDES_RESET, reset_val);
987 val_rd = nr64(ENET_SERDES_RESET);
988 val_rd &= ~reset_val;
990 nw64(ctrl_reg, ctrl_val);
991 nw64(test_cfg_reg, test_cfg_val);
992 nw64(ENET_SERDES_RESET, val_rd);
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i = 0; i < 4; i++) {
997 u32 rxtx_ctrl, glue0;
999 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1002 err = esr_read_glue0(np, i, &glue0);
1006 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1010 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011 ESR_GLUE_CTRL0_THCNT |
1012 ESR_GLUE_CTRL0_BLTIME);
1013 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016 (BLTIME_300_CYCLES <<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1019 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1022 err = esr_write_glue0(np, i, glue0);
1028 sig = nr64(ESR_INT_SIGNALS);
1031 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1036 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1044 if ((sig & mask) != val) {
1045 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1055 struct niu_link_config *lp = &np->link_config;
1059 unsigned long flags;
1063 current_speed = SPEED_INVALID;
1064 current_duplex = DUPLEX_INVALID;
1066 spin_lock_irqsave(&np->lock, flags);
1068 val = nr64_pcs(PCS_MII_STAT);
1070 if (val & PCS_MII_STAT_LINK_STATUS) {
1072 current_speed = SPEED_1000;
1073 current_duplex = DUPLEX_FULL;
1076 lp->active_speed = current_speed;
1077 lp->active_duplex = current_duplex;
1078 spin_unlock_irqrestore(&np->lock, flags);
1080 *link_up_p = link_up;
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1086 unsigned long flags;
1087 struct niu_link_config *lp = &np->link_config;
1094 if (!(np->flags & NIU_FLAGS_10G))
1095 return link_status_1g_serdes(np, link_up_p);
1097 current_speed = SPEED_INVALID;
1098 current_duplex = DUPLEX_INVALID;
1099 spin_lock_irqsave(&np->lock, flags);
1101 val = nr64_xpcs(XPCS_STATUS(0));
1102 val2 = nr64_mac(XMAC_INTER2);
1103 if (val2 & 0x01000000)
1106 if ((val & 0x1000ULL) && link_ok) {
1108 current_speed = SPEED_10000;
1109 current_duplex = DUPLEX_FULL;
1111 lp->active_speed = current_speed;
1112 lp->active_duplex = current_duplex;
1113 spin_unlock_irqrestore(&np->lock, flags);
1114 *link_up_p = link_up;
1118 static int link_status_mii(struct niu *np, int *link_up_p)
1120 struct niu_link_config *lp = &np->link_config;
1122 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123 int supported, advertising, active_speed, active_duplex;
1125 err = mii_read(np, np->phy_addr, MII_BMCR);
1126 if (unlikely(err < 0))
1130 err = mii_read(np, np->phy_addr, MII_BMSR);
1131 if (unlikely(err < 0))
1135 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136 if (unlikely(err < 0))
1140 err = mii_read(np, np->phy_addr, MII_LPA);
1141 if (unlikely(err < 0))
1145 if (likely(bmsr & BMSR_ESTATEN)) {
1146 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147 if (unlikely(err < 0))
1151 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152 if (unlikely(err < 0))
1156 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157 if (unlikely(err < 0))
1161 estatus = ctrl1000 = stat1000 = 0;
1164 if (bmsr & BMSR_ANEGCAPABLE)
1165 supported |= SUPPORTED_Autoneg;
1166 if (bmsr & BMSR_10HALF)
1167 supported |= SUPPORTED_10baseT_Half;
1168 if (bmsr & BMSR_10FULL)
1169 supported |= SUPPORTED_10baseT_Full;
1170 if (bmsr & BMSR_100HALF)
1171 supported |= SUPPORTED_100baseT_Half;
1172 if (bmsr & BMSR_100FULL)
1173 supported |= SUPPORTED_100baseT_Full;
1174 if (estatus & ESTATUS_1000_THALF)
1175 supported |= SUPPORTED_1000baseT_Half;
1176 if (estatus & ESTATUS_1000_TFULL)
1177 supported |= SUPPORTED_1000baseT_Full;
1178 lp->supported = supported;
1181 if (advert & ADVERTISE_10HALF)
1182 advertising |= ADVERTISED_10baseT_Half;
1183 if (advert & ADVERTISE_10FULL)
1184 advertising |= ADVERTISED_10baseT_Full;
1185 if (advert & ADVERTISE_100HALF)
1186 advertising |= ADVERTISED_100baseT_Half;
1187 if (advert & ADVERTISE_100FULL)
1188 advertising |= ADVERTISED_100baseT_Full;
1189 if (ctrl1000 & ADVERTISE_1000HALF)
1190 advertising |= ADVERTISED_1000baseT_Half;
1191 if (ctrl1000 & ADVERTISE_1000FULL)
1192 advertising |= ADVERTISED_1000baseT_Full;
1194 if (bmcr & BMCR_ANENABLE) {
1197 lp->active_autoneg = 1;
1198 advertising |= ADVERTISED_Autoneg;
1201 neg1000 = (ctrl1000 << 2) & stat1000;
1203 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204 active_speed = SPEED_1000;
1205 else if (neg & LPA_100)
1206 active_speed = SPEED_100;
1207 else if (neg & (LPA_10HALF | LPA_10FULL))
1208 active_speed = SPEED_10;
1210 active_speed = SPEED_INVALID;
1212 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213 active_duplex = DUPLEX_FULL;
1214 else if (active_speed != SPEED_INVALID)
1215 active_duplex = DUPLEX_HALF;
1217 active_duplex = DUPLEX_INVALID;
1219 lp->active_autoneg = 0;
1221 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222 active_speed = SPEED_1000;
1223 else if (bmcr & BMCR_SPEED100)
1224 active_speed = SPEED_100;
1226 active_speed = SPEED_10;
1228 if (bmcr & BMCR_FULLDPLX)
1229 active_duplex = DUPLEX_FULL;
1231 active_duplex = DUPLEX_HALF;
1234 lp->active_advertising = advertising;
1235 lp->active_speed = active_speed;
1236 lp->active_duplex = active_duplex;
1237 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1242 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1244 struct niu_link_config *lp = &np->link_config;
1245 u16 current_speed, bmsr;
1246 unsigned long flags;
1251 current_speed = SPEED_INVALID;
1252 current_duplex = DUPLEX_INVALID;
1254 spin_lock_irqsave(&np->lock, flags);
1258 err = mii_read(np, np->phy_addr, MII_BMSR);
1263 if (bmsr & BMSR_LSTATUS) {
1264 u16 adv, lpa, common, estat;
1266 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1271 err = mii_read(np, np->phy_addr, MII_LPA);
1278 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1283 current_speed = SPEED_1000;
1284 current_duplex = DUPLEX_FULL;
1287 lp->active_speed = current_speed;
1288 lp->active_duplex = current_duplex;
1292 spin_unlock_irqrestore(&np->lock, flags);
1294 *link_up_p = link_up;
1298 static int link_status_1g(struct niu *np, int *link_up_p)
1300 struct niu_link_config *lp = &np->link_config;
1301 unsigned long flags;
1304 spin_lock_irqsave(&np->lock, flags);
1306 err = link_status_mii(np, link_up_p);
1307 lp->supported |= SUPPORTED_TP;
1308 lp->active_advertising |= ADVERTISED_TP;
1310 spin_unlock_irqrestore(&np->lock, flags);
1314 static int bcm8704_reset(struct niu *np)
1318 err = mdio_read(np, np->phy_addr,
1319 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1323 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1329 while (--limit >= 0) {
1330 err = mdio_read(np, np->phy_addr,
1331 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1334 if (!(err & BMCR_RESET))
1338 dev_err(np->device, PFX "Port %u PHY will not reset "
1339 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1345 /* When written, certain PHY registers need to be read back twice
1346 * in order for the bits to settle properly.
1348 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1350 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1353 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1359 static int bcm8706_init_user_dev3(struct niu *np)
1364 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365 BCM8704_USER_OPT_DIGITAL_CTRL);
1368 err &= ~USER_ODIG_CTRL_GPIOS;
1369 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370 err |= USER_ODIG_CTRL_RESV2;
1371 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1381 static int bcm8704_init_user_dev3(struct niu *np)
1385 err = mdio_write(np, np->phy_addr,
1386 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387 (USER_CONTROL_OPTXRST_LVL |
1388 USER_CONTROL_OPBIASFLT_LVL |
1389 USER_CONTROL_OBTMPFLT_LVL |
1390 USER_CONTROL_OPPRFLT_LVL |
1391 USER_CONTROL_OPTXFLT_LVL |
1392 USER_CONTROL_OPRXLOS_LVL |
1393 USER_CONTROL_OPRXFLT_LVL |
1394 USER_CONTROL_OPTXON_LVL |
1395 (0x3f << USER_CONTROL_RES1_SHIFT)));
1399 err = mdio_write(np, np->phy_addr,
1400 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401 (USER_PMD_TX_CTL_XFP_CLKEN |
1402 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404 USER_PMD_TX_CTL_TSCK_LPWREN));
1408 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1411 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1415 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416 BCM8704_USER_OPT_DIGITAL_CTRL);
1419 err &= ~USER_ODIG_CTRL_GPIOS;
1420 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1431 static int mrvl88x2011_act_led(struct niu *np, int val)
1435 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436 MRVL88X2011_LED_8_TO_11_CTL);
1440 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1443 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444 MRVL88X2011_LED_8_TO_11_CTL, err);
1447 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1451 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452 MRVL88X2011_LED_BLINK_CTL);
1454 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458 MRVL88X2011_LED_BLINK_CTL, err);
1464 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1468 /* Set LED functions */
1469 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1474 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1478 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479 MRVL88X2011_GENERAL_CTL);
1483 err |= MRVL88X2011_ENA_XFPREFCLK;
1485 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486 MRVL88X2011_GENERAL_CTL, err);
1490 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491 MRVL88X2011_PMA_PMD_CTL_1);
1495 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496 err |= MRVL88X2011_LOOPBACK;
1498 err &= ~MRVL88X2011_LOOPBACK;
1500 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501 MRVL88X2011_PMA_PMD_CTL_1, err);
1506 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1511 static int xcvr_diag_bcm870x(struct niu *np)
1513 u16 analog_stat0, tx_alarm_status;
1517 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1521 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1524 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1527 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1530 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1534 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1538 /* XXX dig this out it might not be so useful XXX */
1539 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540 BCM8704_USER_ANALOG_STATUS0);
1543 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544 BCM8704_USER_ANALOG_STATUS0);
1549 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550 BCM8704_USER_TX_ALARM_STATUS);
1553 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554 BCM8704_USER_TX_ALARM_STATUS);
1557 tx_alarm_status = err;
1559 if (analog_stat0 != 0x03fc) {
1560 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561 pr_info(PFX "Port %u cable not connected "
1562 "or bad cable.\n", np->port);
1563 } else if (analog_stat0 == 0x639c) {
1564 pr_info(PFX "Port %u optical module is bad "
1565 "or missing.\n", np->port);
1572 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1574 struct niu_link_config *lp = &np->link_config;
1577 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1582 err &= ~BMCR_LOOPBACK;
1584 if (lp->loopback_mode == LOOPBACK_MAC)
1585 err |= BMCR_LOOPBACK;
1587 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1595 static int xcvr_init_10g_bcm8706(struct niu *np)
1600 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1604 val = nr64_mac(XMAC_CONFIG);
1605 val &= ~XMAC_CONFIG_LED_POLARITY;
1606 val |= XMAC_CONFIG_FORCE_LED_ON;
1607 nw64_mac(XMAC_CONFIG, val);
1609 val = nr64(MIF_CONFIG);
1610 val |= MIF_CONFIG_INDIRECT_MODE;
1611 nw64(MIF_CONFIG, val);
1613 err = bcm8704_reset(np);
1617 err = xcvr_10g_set_lb_bcm870x(np);
1621 err = bcm8706_init_user_dev3(np);
1625 err = xcvr_diag_bcm870x(np);
1632 static int xcvr_init_10g_bcm8704(struct niu *np)
1636 err = bcm8704_reset(np);
1640 err = bcm8704_init_user_dev3(np);
1644 err = xcvr_10g_set_lb_bcm870x(np);
1648 err = xcvr_diag_bcm870x(np);
1655 static int xcvr_init_10g(struct niu *np)
1660 val = nr64_mac(XMAC_CONFIG);
1661 val &= ~XMAC_CONFIG_LED_POLARITY;
1662 val |= XMAC_CONFIG_FORCE_LED_ON;
1663 nw64_mac(XMAC_CONFIG, val);
1665 /* XXX shared resource, lock parent XXX */
1666 val = nr64(MIF_CONFIG);
1667 val |= MIF_CONFIG_INDIRECT_MODE;
1668 nw64(MIF_CONFIG, val);
1670 phy_id = phy_decode(np->parent->port_phy, np->port);
1671 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1673 /* handle different phy types */
1674 switch (phy_id & NIU_PHY_ID_MASK) {
1675 case NIU_PHY_ID_MRVL88X2011:
1676 err = xcvr_init_10g_mrvl88x2011(np);
1679 default: /* bcom 8704 */
1680 err = xcvr_init_10g_bcm8704(np);
1687 static int mii_reset(struct niu *np)
1691 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1696 while (--limit >= 0) {
1698 err = mii_read(np, np->phy_addr, MII_BMCR);
1701 if (!(err & BMCR_RESET))
1705 dev_err(np->device, PFX "Port %u MII would not reset, "
1706 "bmcr[%04x]\n", np->port, err);
1713 static int xcvr_init_1g_rgmii(struct niu *np)
1717 u16 bmcr, bmsr, estat;
1719 val = nr64(MIF_CONFIG);
1720 val &= ~MIF_CONFIG_INDIRECT_MODE;
1721 nw64(MIF_CONFIG, val);
1723 err = mii_reset(np);
1727 err = mii_read(np, np->phy_addr, MII_BMSR);
1733 if (bmsr & BMSR_ESTATEN) {
1734 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1741 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1745 if (bmsr & BMSR_ESTATEN) {
1748 if (estat & ESTATUS_1000_TFULL)
1749 ctrl1000 |= ADVERTISE_1000FULL;
1750 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1755 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1757 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1761 err = mii_read(np, np->phy_addr, MII_BMCR);
1764 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1766 err = mii_read(np, np->phy_addr, MII_BMSR);
1773 static int mii_init_common(struct niu *np)
1775 struct niu_link_config *lp = &np->link_config;
1776 u16 bmcr, bmsr, adv, estat;
1779 err = mii_reset(np);
1783 err = mii_read(np, np->phy_addr, MII_BMSR);
1789 if (bmsr & BMSR_ESTATEN) {
1790 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1797 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1801 if (lp->loopback_mode == LOOPBACK_MAC) {
1802 bmcr |= BMCR_LOOPBACK;
1803 if (lp->active_speed == SPEED_1000)
1804 bmcr |= BMCR_SPEED1000;
1805 if (lp->active_duplex == DUPLEX_FULL)
1806 bmcr |= BMCR_FULLDPLX;
1809 if (lp->loopback_mode == LOOPBACK_PHY) {
1812 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813 BCM5464R_AUX_CTL_WRITE_1);
1814 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1822 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823 if ((bmsr & BMSR_10HALF) &&
1824 (lp->advertising & ADVERTISED_10baseT_Half))
1825 adv |= ADVERTISE_10HALF;
1826 if ((bmsr & BMSR_10FULL) &&
1827 (lp->advertising & ADVERTISED_10baseT_Full))
1828 adv |= ADVERTISE_10FULL;
1829 if ((bmsr & BMSR_100HALF) &&
1830 (lp->advertising & ADVERTISED_100baseT_Half))
1831 adv |= ADVERTISE_100HALF;
1832 if ((bmsr & BMSR_100FULL) &&
1833 (lp->advertising & ADVERTISED_100baseT_Full))
1834 adv |= ADVERTISE_100FULL;
1835 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1839 if (likely(bmsr & BMSR_ESTATEN)) {
1841 if ((estat & ESTATUS_1000_THALF) &&
1842 (lp->advertising & ADVERTISED_1000baseT_Half))
1843 ctrl1000 |= ADVERTISE_1000HALF;
1844 if ((estat & ESTATUS_1000_TFULL) &&
1845 (lp->advertising & ADVERTISED_1000baseT_Full))
1846 ctrl1000 |= ADVERTISE_1000FULL;
1847 err = mii_write(np, np->phy_addr,
1848 MII_CTRL1000, ctrl1000);
1853 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1858 if (lp->duplex == DUPLEX_FULL) {
1859 bmcr |= BMCR_FULLDPLX;
1861 } else if (lp->duplex == DUPLEX_HALF)
1866 if (lp->speed == SPEED_1000) {
1867 /* if X-full requested while not supported, or
1868 X-half requested while not supported... */
1869 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1872 bmcr |= BMCR_SPEED1000;
1873 } else if (lp->speed == SPEED_100) {
1874 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875 (!fulldpx && !(bmsr & BMSR_100HALF)))
1877 bmcr |= BMCR_SPEED100;
1878 } else if (lp->speed == SPEED_10) {
1879 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880 (!fulldpx && !(bmsr & BMSR_10HALF)))
1886 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1891 err = mii_read(np, np->phy_addr, MII_BMCR);
1896 err = mii_read(np, np->phy_addr, MII_BMSR);
1901 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902 np->port, bmcr, bmsr);
1908 static int xcvr_init_1g(struct niu *np)
1912 /* XXX shared resource, lock parent XXX */
1913 val = nr64(MIF_CONFIG);
1914 val &= ~MIF_CONFIG_INDIRECT_MODE;
1915 nw64(MIF_CONFIG, val);
1917 return mii_init_common(np);
1920 static int niu_xcvr_init(struct niu *np)
1922 const struct niu_phy_ops *ops = np->phy_ops;
1927 err = ops->xcvr_init(np);
1932 static int niu_serdes_init(struct niu *np)
1934 const struct niu_phy_ops *ops = np->phy_ops;
1938 if (ops->serdes_init)
1939 err = ops->serdes_init(np);
1944 static void niu_init_xif(struct niu *);
1945 static void niu_handle_led(struct niu *, int status);
1947 static int niu_link_status_common(struct niu *np, int link_up)
1949 struct niu_link_config *lp = &np->link_config;
1950 struct net_device *dev = np->dev;
1951 unsigned long flags;
1953 if (!netif_carrier_ok(dev) && link_up) {
1954 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1956 (lp->active_speed == SPEED_10000 ?
1958 (lp->active_speed == SPEED_1000 ?
1960 (lp->active_speed == SPEED_100 ?
1961 "100Mbit/sec" : "10Mbit/sec"))),
1962 (lp->active_duplex == DUPLEX_FULL ?
1965 spin_lock_irqsave(&np->lock, flags);
1967 niu_handle_led(np, 1);
1968 spin_unlock_irqrestore(&np->lock, flags);
1970 netif_carrier_on(dev);
1971 } else if (netif_carrier_ok(dev) && !link_up) {
1972 niuwarn(LINK, "%s: Link is down\n", dev->name);
1973 spin_lock_irqsave(&np->lock, flags);
1974 niu_handle_led(np, 0);
1975 spin_unlock_irqrestore(&np->lock, flags);
1976 netif_carrier_off(dev);
1982 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1984 int err, link_up, pma_status, pcs_status;
1988 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989 MRVL88X2011_10G_PMD_STATUS_2);
1993 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995 MRVL88X2011_PMA_PMD_STATUS_1);
1999 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2001 /* Check PMC Register : 3.0001.2 == 1: read twice */
2002 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003 MRVL88X2011_PMA_PMD_STATUS_1);
2007 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008 MRVL88X2011_PMA_PMD_STATUS_1);
2012 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2014 /* Check XGXS Register : 4.0018.[0-3,12] */
2015 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016 MRVL88X2011_10G_XGXS_LANE_STAT);
2020 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2024 link_up = (pma_status && pcs_status) ? 1 : 0;
2026 np->link_config.active_speed = SPEED_10000;
2027 np->link_config.active_duplex = DUPLEX_FULL;
2030 mrvl88x2011_act_led(np, (link_up ?
2031 MRVL88X2011_LED_CTL_PCS_ACT :
2032 MRVL88X2011_LED_CTL_OFF));
2034 *link_up_p = link_up;
2038 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2043 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044 BCM8704_PMD_RCV_SIGDET);
2047 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2052 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053 BCM8704_PCS_10G_R_STATUS);
2057 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2062 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063 BCM8704_PHYXS_XGXS_LANE_STAT);
2066 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067 PHYXS_XGXS_LANE_STAT_MAGIC |
2068 PHYXS_XGXS_LANE_STAT_PATTEST |
2069 PHYXS_XGXS_LANE_STAT_LANE3 |
2070 PHYXS_XGXS_LANE_STAT_LANE2 |
2071 PHYXS_XGXS_LANE_STAT_LANE1 |
2072 PHYXS_XGXS_LANE_STAT_LANE0)) {
2074 np->link_config.active_speed = SPEED_INVALID;
2075 np->link_config.active_duplex = DUPLEX_INVALID;
2080 np->link_config.active_speed = SPEED_10000;
2081 np->link_config.active_duplex = DUPLEX_FULL;
2085 *link_up_p = link_up;
2086 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
2091 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2097 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2098 BCM8704_PMD_RCV_SIGDET);
2101 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2106 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2107 BCM8704_PCS_10G_R_STATUS);
2110 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2115 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2116 BCM8704_PHYXS_XGXS_LANE_STAT);
2120 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2121 PHYXS_XGXS_LANE_STAT_MAGIC |
2122 PHYXS_XGXS_LANE_STAT_LANE3 |
2123 PHYXS_XGXS_LANE_STAT_LANE2 |
2124 PHYXS_XGXS_LANE_STAT_LANE1 |
2125 PHYXS_XGXS_LANE_STAT_LANE0)) {
2131 np->link_config.active_speed = SPEED_10000;
2132 np->link_config.active_duplex = DUPLEX_FULL;
2136 *link_up_p = link_up;
2140 static int link_status_10g(struct niu *np, int *link_up_p)
2142 unsigned long flags;
2145 spin_lock_irqsave(&np->lock, flags);
2147 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2150 phy_id = phy_decode(np->parent->port_phy, np->port);
2151 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2153 /* handle different phy types */
2154 switch (phy_id & NIU_PHY_ID_MASK) {
2155 case NIU_PHY_ID_MRVL88X2011:
2156 err = link_status_10g_mrvl(np, link_up_p);
2159 default: /* bcom 8704 */
2160 err = link_status_10g_bcom(np, link_up_p);
2165 spin_unlock_irqrestore(&np->lock, flags);
2170 static int niu_10g_phy_present(struct niu *np)
2174 sig = nr64(ESR_INT_SIGNALS);
2177 mask = ESR_INT_SIGNALS_P0_BITS;
2178 val = (ESR_INT_SRDY0_P0 |
2181 ESR_INT_XDP_P0_CH3 |
2182 ESR_INT_XDP_P0_CH2 |
2183 ESR_INT_XDP_P0_CH1 |
2184 ESR_INT_XDP_P0_CH0);
2188 mask = ESR_INT_SIGNALS_P1_BITS;
2189 val = (ESR_INT_SRDY0_P1 |
2192 ESR_INT_XDP_P1_CH3 |
2193 ESR_INT_XDP_P1_CH2 |
2194 ESR_INT_XDP_P1_CH1 |
2195 ESR_INT_XDP_P1_CH0);
2202 if ((sig & mask) != val)
2207 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2209 unsigned long flags;
2212 int phy_present_prev;
2214 spin_lock_irqsave(&np->lock, flags);
2216 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2217 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2219 phy_present = niu_10g_phy_present(np);
2220 if (phy_present != phy_present_prev) {
2223 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2224 if (np->phy_ops->xcvr_init)
2225 err = np->phy_ops->xcvr_init(np);
2228 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2231 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2233 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2237 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2238 err = link_status_10g_bcm8706(np, link_up_p);
2241 spin_unlock_irqrestore(&np->lock, flags);
2246 static int niu_link_status(struct niu *np, int *link_up_p)
2248 const struct niu_phy_ops *ops = np->phy_ops;
2252 if (ops->link_status)
2253 err = ops->link_status(np, link_up_p);
2258 static void niu_timer(unsigned long __opaque)
2260 struct niu *np = (struct niu *) __opaque;
2264 err = niu_link_status(np, &link_up);
2266 niu_link_status_common(np, link_up);
2268 if (netif_carrier_ok(np->dev))
2272 np->timer.expires = jiffies + off;
2274 add_timer(&np->timer);
2277 static const struct niu_phy_ops phy_ops_10g_serdes = {
2278 .serdes_init = serdes_init_10g_serdes,
2279 .link_status = link_status_10g_serdes,
2282 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2283 .serdes_init = serdes_init_niu_10g_serdes,
2284 .link_status = link_status_10g_serdes,
2287 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2288 .serdes_init = serdes_init_niu_1g_serdes,
2289 .link_status = link_status_1g_serdes,
2292 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2293 .xcvr_init = xcvr_init_1g_rgmii,
2294 .link_status = link_status_1g_rgmii,
2297 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2298 .serdes_init = serdes_init_niu_10g_fiber,
2299 .xcvr_init = xcvr_init_10g,
2300 .link_status = link_status_10g,
2303 static const struct niu_phy_ops phy_ops_10g_fiber = {
2304 .serdes_init = serdes_init_10g,
2305 .xcvr_init = xcvr_init_10g,
2306 .link_status = link_status_10g,
2309 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2310 .serdes_init = serdes_init_10g,
2311 .xcvr_init = xcvr_init_10g_bcm8706,
2312 .link_status = link_status_10g_hotplug,
2315 static const struct niu_phy_ops phy_ops_10g_copper = {
2316 .serdes_init = serdes_init_10g,
2317 .link_status = link_status_10g, /* XXX */
2320 static const struct niu_phy_ops phy_ops_1g_fiber = {
2321 .serdes_init = serdes_init_1g,
2322 .xcvr_init = xcvr_init_1g,
2323 .link_status = link_status_1g,
2326 static const struct niu_phy_ops phy_ops_1g_copper = {
2327 .xcvr_init = xcvr_init_1g,
2328 .link_status = link_status_1g,
2331 struct niu_phy_template {
2332 const struct niu_phy_ops *ops;
2336 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2337 .ops = &phy_ops_10g_fiber_niu,
2338 .phy_addr_base = 16,
2341 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2342 .ops = &phy_ops_10g_serdes_niu,
2346 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2347 .ops = &phy_ops_1g_serdes_niu,
2351 static const struct niu_phy_template phy_template_10g_fiber = {
2352 .ops = &phy_ops_10g_fiber,
2356 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2357 .ops = &phy_ops_10g_fiber_hotplug,
2361 static const struct niu_phy_template phy_template_10g_copper = {
2362 .ops = &phy_ops_10g_copper,
2363 .phy_addr_base = 10,
2366 static const struct niu_phy_template phy_template_1g_fiber = {
2367 .ops = &phy_ops_1g_fiber,
2371 static const struct niu_phy_template phy_template_1g_copper = {
2372 .ops = &phy_ops_1g_copper,
2376 static const struct niu_phy_template phy_template_1g_rgmii = {
2377 .ops = &phy_ops_1g_rgmii,
2381 static const struct niu_phy_template phy_template_10g_serdes = {
2382 .ops = &phy_ops_10g_serdes,
2386 static int niu_atca_port_num[4] = {
2390 static int serdes_init_10g_serdes(struct niu *np)
2392 struct niu_link_config *lp = &np->link_config;
2393 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2394 u64 ctrl_val, test_cfg_val, sig, mask, val;
2399 reset_val = ENET_SERDES_RESET_0;
2400 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2401 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2402 pll_cfg = ENET_SERDES_0_PLL_CFG;
2405 reset_val = ENET_SERDES_RESET_1;
2406 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2407 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2408 pll_cfg = ENET_SERDES_1_PLL_CFG;
2414 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2415 ENET_SERDES_CTRL_SDET_1 |
2416 ENET_SERDES_CTRL_SDET_2 |
2417 ENET_SERDES_CTRL_SDET_3 |
2418 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2419 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2420 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2421 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2422 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2423 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2424 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2425 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2428 if (lp->loopback_mode == LOOPBACK_PHY) {
2429 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2430 ENET_SERDES_TEST_MD_0_SHIFT) |
2431 (ENET_TEST_MD_PAD_LOOPBACK <<
2432 ENET_SERDES_TEST_MD_1_SHIFT) |
2433 (ENET_TEST_MD_PAD_LOOPBACK <<
2434 ENET_SERDES_TEST_MD_2_SHIFT) |
2435 (ENET_TEST_MD_PAD_LOOPBACK <<
2436 ENET_SERDES_TEST_MD_3_SHIFT));
2440 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2441 nw64(ctrl_reg, ctrl_val);
2442 nw64(test_cfg_reg, test_cfg_val);
2444 /* Initialize all 4 lanes of the SERDES. */
2445 for (i = 0; i < 4; i++) {
2446 u32 rxtx_ctrl, glue0;
2449 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2452 err = esr_read_glue0(np, i, &glue0);
2456 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2457 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2458 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2460 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2461 ESR_GLUE_CTRL0_THCNT |
2462 ESR_GLUE_CTRL0_BLTIME);
2463 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2464 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2465 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2466 (BLTIME_300_CYCLES <<
2467 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2469 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2472 err = esr_write_glue0(np, i, glue0);
2478 sig = nr64(ESR_INT_SIGNALS);
2481 mask = ESR_INT_SIGNALS_P0_BITS;
2482 val = (ESR_INT_SRDY0_P0 |
2485 ESR_INT_XDP_P0_CH3 |
2486 ESR_INT_XDP_P0_CH2 |
2487 ESR_INT_XDP_P0_CH1 |
2488 ESR_INT_XDP_P0_CH0);
2492 mask = ESR_INT_SIGNALS_P1_BITS;
2493 val = (ESR_INT_SRDY0_P1 |
2496 ESR_INT_XDP_P1_CH3 |
2497 ESR_INT_XDP_P1_CH2 |
2498 ESR_INT_XDP_P1_CH1 |
2499 ESR_INT_XDP_P1_CH0);
2506 if ((sig & mask) != val) {
2508 err = serdes_init_1g_serdes(np);
2510 np->flags &= ~NIU_FLAGS_10G;
2511 np->mac_xcvr = MAC_XCVR_PCS;
2513 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2522 static int niu_determine_phy_disposition(struct niu *np)
2524 struct niu_parent *parent = np->parent;
2525 u8 plat_type = parent->plat_type;
2526 const struct niu_phy_template *tp;
2527 u32 phy_addr_off = 0;
2529 if (plat_type == PLAT_TYPE_NIU) {
2533 NIU_FLAGS_XCVR_SERDES)) {
2534 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2536 tp = &phy_template_niu_10g_serdes;
2538 case NIU_FLAGS_XCVR_SERDES:
2540 tp = &phy_template_niu_1g_serdes;
2542 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2545 tp = &phy_template_niu_10g_fiber;
2546 phy_addr_off += np->port;
2553 NIU_FLAGS_XCVR_SERDES)) {
2556 tp = &phy_template_1g_copper;
2557 if (plat_type == PLAT_TYPE_VF_P0)
2559 else if (plat_type == PLAT_TYPE_VF_P1)
2562 phy_addr_off += (np->port ^ 0x3);
2567 tp = &phy_template_10g_copper;
2570 case NIU_FLAGS_FIBER:
2572 tp = &phy_template_1g_fiber;
2575 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2577 tp = &phy_template_10g_fiber;
2578 if (plat_type == PLAT_TYPE_VF_P0 ||
2579 plat_type == PLAT_TYPE_VF_P1)
2581 phy_addr_off += np->port;
2582 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583 tp = &phy_template_10g_fiber_hotplug;
2591 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593 case NIU_FLAGS_XCVR_SERDES:
2597 tp = &phy_template_10g_serdes;
2601 tp = &phy_template_1g_rgmii;
2607 phy_addr_off = niu_atca_port_num[np->port];
2615 np->phy_ops = tp->ops;
2616 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2621 static int niu_init_link(struct niu *np)
2623 struct niu_parent *parent = np->parent;
2626 if (parent->plat_type == PLAT_TYPE_NIU) {
2627 err = niu_xcvr_init(np);
2632 err = niu_serdes_init(np);
2636 err = niu_xcvr_init(np);
2638 niu_link_status(np, &ignore);
2642 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2644 u16 reg0 = addr[4] << 8 | addr[5];
2645 u16 reg1 = addr[2] << 8 | addr[3];
2646 u16 reg2 = addr[0] << 8 | addr[1];
2648 if (np->flags & NIU_FLAGS_XMAC) {
2649 nw64_mac(XMAC_ADDR0, reg0);
2650 nw64_mac(XMAC_ADDR1, reg1);
2651 nw64_mac(XMAC_ADDR2, reg2);
2653 nw64_mac(BMAC_ADDR0, reg0);
2654 nw64_mac(BMAC_ADDR1, reg1);
2655 nw64_mac(BMAC_ADDR2, reg2);
2659 static int niu_num_alt_addr(struct niu *np)
2661 if (np->flags & NIU_FLAGS_XMAC)
2662 return XMAC_NUM_ALT_ADDR;
2664 return BMAC_NUM_ALT_ADDR;
2667 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2669 u16 reg0 = addr[4] << 8 | addr[5];
2670 u16 reg1 = addr[2] << 8 | addr[3];
2671 u16 reg2 = addr[0] << 8 | addr[1];
2673 if (index >= niu_num_alt_addr(np))
2676 if (np->flags & NIU_FLAGS_XMAC) {
2677 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2681 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2689 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2694 if (index >= niu_num_alt_addr(np))
2697 if (np->flags & NIU_FLAGS_XMAC) {
2698 reg = XMAC_ADDR_CMPEN;
2701 reg = BMAC_ADDR_CMPEN;
2702 mask = 1 << (index + 1);
2705 val = nr64_mac(reg);
2715 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716 int num, int mac_pref)
2718 u64 val = nr64_mac(reg);
2719 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2722 val |= HOST_INFO_MPR;
2726 static int __set_rdc_table_num(struct niu *np,
2727 int xmac_index, int bmac_index,
2728 int rdc_table_num, int mac_pref)
2732 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2734 if (np->flags & NIU_FLAGS_XMAC)
2735 reg = XMAC_HOST_INFO(xmac_index);
2737 reg = BMAC_HOST_INFO(bmac_index);
2738 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2742 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2745 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2748 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2751 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2754 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755 int table_num, int mac_pref)
2757 if (idx >= niu_num_alt_addr(np))
2759 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2762 static u64 vlan_entry_set_parity(u64 reg_val)
2767 port01_mask = 0x00ff;
2768 port23_mask = 0xff00;
2770 if (hweight64(reg_val & port01_mask) & 1)
2771 reg_val |= ENET_VLAN_TBL_PARITY0;
2773 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2775 if (hweight64(reg_val & port23_mask) & 1)
2776 reg_val |= ENET_VLAN_TBL_PARITY1;
2778 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2783 static void vlan_tbl_write(struct niu *np, unsigned long index,
2784 int port, int vpr, int rdc_table)
2786 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2788 reg_val &= ~((ENET_VLAN_TBL_VPR |
2789 ENET_VLAN_TBL_VLANRDCTBLN) <<
2790 ENET_VLAN_TBL_SHIFT(port));
2792 reg_val |= (ENET_VLAN_TBL_VPR <<
2793 ENET_VLAN_TBL_SHIFT(port));
2794 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2796 reg_val = vlan_entry_set_parity(reg_val);
2798 nw64(ENET_VLAN_TBL(index), reg_val);
2801 static void vlan_tbl_clear(struct niu *np)
2805 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806 nw64(ENET_VLAN_TBL(i), 0);
2809 static int tcam_wait_bit(struct niu *np, u64 bit)
2813 while (--limit > 0) {
2814 if (nr64(TCAM_CTL) & bit)
2824 static int tcam_flush(struct niu *np, int index)
2826 nw64(TCAM_KEY_0, 0x00);
2827 nw64(TCAM_KEY_MASK_0, 0xff);
2828 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2830 return tcam_wait_bit(np, TCAM_CTL_STAT);
2834 static int tcam_read(struct niu *np, int index,
2835 u64 *key, u64 *mask)
2839 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2842 key[0] = nr64(TCAM_KEY_0);
2843 key[1] = nr64(TCAM_KEY_1);
2844 key[2] = nr64(TCAM_KEY_2);
2845 key[3] = nr64(TCAM_KEY_3);
2846 mask[0] = nr64(TCAM_KEY_MASK_0);
2847 mask[1] = nr64(TCAM_KEY_MASK_1);
2848 mask[2] = nr64(TCAM_KEY_MASK_2);
2849 mask[3] = nr64(TCAM_KEY_MASK_3);
2855 static int tcam_write(struct niu *np, int index,
2856 u64 *key, u64 *mask)
2858 nw64(TCAM_KEY_0, key[0]);
2859 nw64(TCAM_KEY_1, key[1]);
2860 nw64(TCAM_KEY_2, key[2]);
2861 nw64(TCAM_KEY_3, key[3]);
2862 nw64(TCAM_KEY_MASK_0, mask[0]);
2863 nw64(TCAM_KEY_MASK_1, mask[1]);
2864 nw64(TCAM_KEY_MASK_2, mask[2]);
2865 nw64(TCAM_KEY_MASK_3, mask[3]);
2866 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2868 return tcam_wait_bit(np, TCAM_CTL_STAT);
2872 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2876 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2879 *data = nr64(TCAM_KEY_1);
2885 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2887 nw64(TCAM_KEY_1, assoc_data);
2888 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2890 return tcam_wait_bit(np, TCAM_CTL_STAT);
2893 static void tcam_enable(struct niu *np, int on)
2895 u64 val = nr64(FFLP_CFG_1);
2898 val &= ~FFLP_CFG_1_TCAM_DIS;
2900 val |= FFLP_CFG_1_TCAM_DIS;
2901 nw64(FFLP_CFG_1, val);
2904 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2906 u64 val = nr64(FFLP_CFG_1);
2908 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2910 FFLP_CFG_1_CAMRATIO);
2911 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913 nw64(FFLP_CFG_1, val);
2915 val = nr64(FFLP_CFG_1);
2916 val |= FFLP_CFG_1_FFLPINITDONE;
2917 nw64(FFLP_CFG_1, val);
2920 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2926 if (class < CLASS_CODE_ETHERTYPE1 ||
2927 class > CLASS_CODE_ETHERTYPE2)
2930 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2942 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2948 if (class < CLASS_CODE_ETHERTYPE1 ||
2949 class > CLASS_CODE_ETHERTYPE2 ||
2950 (ether_type & ~(u64)0xffff) != 0)
2953 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2955 val &= ~L2_CLS_ETYPE;
2956 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2963 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2969 if (class < CLASS_CODE_USER_PROG1 ||
2970 class > CLASS_CODE_USER_PROG4)
2973 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2976 val |= L3_CLS_VALID;
2978 val &= ~L3_CLS_VALID;
2985 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2986 int ipv6, u64 protocol_id,
2987 u64 tos_mask, u64 tos_val)
2992 if (class < CLASS_CODE_USER_PROG1 ||
2993 class > CLASS_CODE_USER_PROG4 ||
2994 (protocol_id & ~(u64)0xff) != 0 ||
2995 (tos_mask & ~(u64)0xff) != 0 ||
2996 (tos_val & ~(u64)0xff) != 0)
2999 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3001 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3002 L3_CLS_TOSMASK | L3_CLS_TOS);
3004 val |= L3_CLS_IPVER;
3005 val |= (protocol_id << L3_CLS_PID_SHIFT);
3006 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3007 val |= (tos_val << L3_CLS_TOS_SHIFT);
3014 static int tcam_early_init(struct niu *np)
3020 tcam_set_lat_and_ratio(np,
3021 DEFAULT_TCAM_LATENCY,
3022 DEFAULT_TCAM_ACCESS_RATIO);
3023 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3024 err = tcam_user_eth_class_enable(np, i, 0);
3028 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3029 err = tcam_user_ip_class_enable(np, i, 0);
3037 static int tcam_flush_all(struct niu *np)
3041 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3042 int err = tcam_flush(np, i);
3049 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3051 return ((u64)index | (num_entries == 1 ?
3052 HASH_TBL_ADDR_AUTOINC : 0));
3056 static int hash_read(struct niu *np, unsigned long partition,
3057 unsigned long index, unsigned long num_entries,
3060 u64 val = hash_addr_regval(index, num_entries);
3063 if (partition >= FCRAM_NUM_PARTITIONS ||
3064 index + num_entries > FCRAM_SIZE)
3067 nw64(HASH_TBL_ADDR(partition), val);
3068 for (i = 0; i < num_entries; i++)
3069 data[i] = nr64(HASH_TBL_DATA(partition));
3075 static int hash_write(struct niu *np, unsigned long partition,
3076 unsigned long index, unsigned long num_entries,
3079 u64 val = hash_addr_regval(index, num_entries);
3082 if (partition >= FCRAM_NUM_PARTITIONS ||
3083 index + (num_entries * 8) > FCRAM_SIZE)
3086 nw64(HASH_TBL_ADDR(partition), val);
3087 for (i = 0; i < num_entries; i++)
3088 nw64(HASH_TBL_DATA(partition), data[i]);
3093 static void fflp_reset(struct niu *np)
3097 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3099 nw64(FFLP_CFG_1, 0);
3101 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3102 nw64(FFLP_CFG_1, val);
3105 static void fflp_set_timings(struct niu *np)
3107 u64 val = nr64(FFLP_CFG_1);
3109 val &= ~FFLP_CFG_1_FFLPINITDONE;
3110 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3111 nw64(FFLP_CFG_1, val);
3113 val = nr64(FFLP_CFG_1);
3114 val |= FFLP_CFG_1_FFLPINITDONE;
3115 nw64(FFLP_CFG_1, val);
3117 val = nr64(FCRAM_REF_TMR);
3118 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3119 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3120 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3121 nw64(FCRAM_REF_TMR, val);
3124 static int fflp_set_partition(struct niu *np, u64 partition,
3125 u64 mask, u64 base, int enable)
3130 if (partition >= FCRAM_NUM_PARTITIONS ||
3131 (mask & ~(u64)0x1f) != 0 ||
3132 (base & ~(u64)0x1f) != 0)
3135 reg = FLW_PRT_SEL(partition);
3138 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3139 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3140 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3142 val |= FLW_PRT_SEL_EXT;
3148 static int fflp_disable_all_partitions(struct niu *np)
3152 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3153 int err = fflp_set_partition(np, 0, 0, 0, 0);
3160 static void fflp_llcsnap_enable(struct niu *np, int on)
3162 u64 val = nr64(FFLP_CFG_1);
3165 val |= FFLP_CFG_1_LLCSNAP;
3167 val &= ~FFLP_CFG_1_LLCSNAP;
3168 nw64(FFLP_CFG_1, val);
3171 static void fflp_errors_enable(struct niu *np, int on)
3173 u64 val = nr64(FFLP_CFG_1);
3176 val &= ~FFLP_CFG_1_ERRORDIS;
3178 val |= FFLP_CFG_1_ERRORDIS;
3179 nw64(FFLP_CFG_1, val);
3182 static int fflp_hash_clear(struct niu *np)
3184 struct fcram_hash_ipv4 ent;
3187 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3188 memset(&ent, 0, sizeof(ent));
3189 ent.header = HASH_HEADER_EXT;
3191 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3192 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3199 static int fflp_early_init(struct niu *np)
3201 struct niu_parent *parent;
3202 unsigned long flags;
3205 niu_lock_parent(np, flags);
3207 parent = np->parent;
3209 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3210 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3212 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3214 fflp_set_timings(np);
3215 err = fflp_disable_all_partitions(np);
3217 niudbg(PROBE, "fflp_disable_all_partitions "
3218 "failed, err=%d\n", err);
3223 err = tcam_early_init(np);
3225 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3229 fflp_llcsnap_enable(np, 1);
3230 fflp_errors_enable(np, 0);
3234 err = tcam_flush_all(np);
3236 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3240 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3241 err = fflp_hash_clear(np);
3243 niudbg(PROBE, "fflp_hash_clear failed, "
3251 niudbg(PROBE, "fflp_early_init: Success\n");
3252 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3255 niu_unlock_parent(np, flags);
3259 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3261 if (class_code < CLASS_CODE_USER_PROG1 ||
3262 class_code > CLASS_CODE_SCTP_IPV6)
3265 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3269 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3271 if (class_code < CLASS_CODE_USER_PROG1 ||
3272 class_code > CLASS_CODE_SCTP_IPV6)
3275 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3279 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3280 u32 offset, u32 size)
3282 int i = skb_shinfo(skb)->nr_frags;
3283 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3286 frag->page_offset = offset;
3290 skb->data_len += size;
3291 skb->truesize += size;
3293 skb_shinfo(skb)->nr_frags = i + 1;
3296 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3299 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3301 return (a & (MAX_RBR_RING_SIZE - 1));
3304 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3305 struct page ***link)
3307 unsigned int h = niu_hash_rxaddr(rp, addr);
3308 struct page *p, **pp;
3311 pp = &rp->rxhash[h];
3312 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3313 if (p->index == addr) {
3322 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3324 unsigned int h = niu_hash_rxaddr(rp, base);
3327 page->mapping = (struct address_space *) rp->rxhash[h];
3328 rp->rxhash[h] = page;
3331 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3332 gfp_t mask, int start_index)
3338 page = alloc_page(mask);
3342 addr = np->ops->map_page(np->device, page, 0,
3343 PAGE_SIZE, DMA_FROM_DEVICE);
3345 niu_hash_page(rp, page, addr);
3346 if (rp->rbr_blocks_per_page > 1)
3347 atomic_add(rp->rbr_blocks_per_page - 1,
3348 &compound_head(page)->_count);
3350 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3351 __le32 *rbr = &rp->rbr[start_index + i];
3353 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3354 addr += rp->rbr_block_size;
3360 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3362 int index = rp->rbr_index;
3365 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3366 int err = niu_rbr_add_page(np, rp, mask, index);
3368 if (unlikely(err)) {
3373 rp->rbr_index += rp->rbr_blocks_per_page;
3374 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3375 if (rp->rbr_index == rp->rbr_table_size)
3378 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3379 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3380 rp->rbr_pending = 0;
3385 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3387 unsigned int index = rp->rcr_index;
3392 struct page *page, **link;
3398 val = le64_to_cpup(&rp->rcr[index]);
3399 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3400 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3401 page = niu_find_rxpage(rp, addr, &link);
3403 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3404 RCR_ENTRY_PKTBUFSZ_SHIFT];
3405 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3406 *link = (struct page *) page->mapping;
3407 np->ops->unmap_page(np->device, page->index,
3408 PAGE_SIZE, DMA_FROM_DEVICE);
3410 page->mapping = NULL;
3412 rp->rbr_refill_pending++;
3415 index = NEXT_RCR(rp, index);
3416 if (!(val & RCR_ENTRY_MULTI))
3420 rp->rcr_index = index;
3425 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3427 unsigned int index = rp->rcr_index;
3428 struct sk_buff *skb;
3431 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3433 return niu_rx_pkt_ignore(np, rp);
3437 struct page *page, **link;
3438 u32 rcr_size, append_size;
3443 val = le64_to_cpup(&rp->rcr[index]);
3445 len = (val & RCR_ENTRY_L2_LEN) >>
3446 RCR_ENTRY_L2_LEN_SHIFT;
3449 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3450 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3451 page = niu_find_rxpage(rp, addr, &link);
3453 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3454 RCR_ENTRY_PKTBUFSZ_SHIFT];
3456 off = addr & ~PAGE_MASK;
3457 append_size = rcr_size;
3464 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3465 if ((ptype == RCR_PKT_TYPE_TCP ||
3466 ptype == RCR_PKT_TYPE_UDP) &&
3467 !(val & (RCR_ENTRY_NOPORT |
3469 skb->ip_summed = CHECKSUM_UNNECESSARY;
3471 skb->ip_summed = CHECKSUM_NONE;
3473 if (!(val & RCR_ENTRY_MULTI))
3474 append_size = len - skb->len;
3476 niu_rx_skb_append(skb, page, off, append_size);
3477 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3478 *link = (struct page *) page->mapping;
3479 np->ops->unmap_page(np->device, page->index,
3480 PAGE_SIZE, DMA_FROM_DEVICE);
3482 page->mapping = NULL;
3483 rp->rbr_refill_pending++;
3487 index = NEXT_RCR(rp, index);
3488 if (!(val & RCR_ENTRY_MULTI))
3492 rp->rcr_index = index;
3494 skb_reserve(skb, NET_IP_ALIGN);
3495 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3498 rp->rx_bytes += skb->len;
3500 skb->protocol = eth_type_trans(skb, np->dev);
3501 skb_record_rx_queue(skb, rp->rx_channel);
3502 netif_receive_skb(skb);
3507 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3509 int blocks_per_page = rp->rbr_blocks_per_page;
3510 int err, index = rp->rbr_index;
3513 while (index < (rp->rbr_table_size - blocks_per_page)) {
3514 err = niu_rbr_add_page(np, rp, mask, index);
3518 index += blocks_per_page;
3521 rp->rbr_index = index;
3525 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3529 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3532 page = rp->rxhash[i];
3534 struct page *next = (struct page *) page->mapping;
3535 u64 base = page->index;
3537 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3540 page->mapping = NULL;
3548 for (i = 0; i < rp->rbr_table_size; i++)
3549 rp->rbr[i] = cpu_to_le32(0);
3553 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3555 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3556 struct sk_buff *skb = tb->skb;
3557 struct tx_pkt_hdr *tp;
3561 tp = (struct tx_pkt_hdr *) skb->data;
3562 tx_flags = le64_to_cpup(&tp->flags);
3565 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3566 ((tx_flags & TXHDR_PAD) / 2));
3568 len = skb_headlen(skb);
3569 np->ops->unmap_single(np->device, tb->mapping,
3570 len, DMA_TO_DEVICE);
3572 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3577 idx = NEXT_TX(rp, idx);
3578 len -= MAX_TX_DESC_LEN;
3581 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3582 tb = &rp->tx_buffs[idx];
3583 BUG_ON(tb->skb != NULL);
3584 np->ops->unmap_page(np->device, tb->mapping,
3585 skb_shinfo(skb)->frags[i].size,
3587 idx = NEXT_TX(rp, idx);
3595 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3597 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3599 struct netdev_queue *txq;
3604 index = (rp - np->tx_rings);
3605 txq = netdev_get_tx_queue(np->dev, index);
3608 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3611 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3612 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3613 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3615 rp->last_pkt_cnt = tmp;
3619 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3620 np->dev->name, pkt_cnt, cons);
3623 cons = release_tx_packet(np, rp, cons);
3629 if (unlikely(netif_tx_queue_stopped(txq) &&
3630 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3631 __netif_tx_lock(txq, smp_processor_id());
3632 if (netif_tx_queue_stopped(txq) &&
3633 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3634 netif_tx_wake_queue(txq);
3635 __netif_tx_unlock(txq);
3639 static inline void niu_sync_rx_discard_stats(struct niu *np,
3640 struct rx_ring_info *rp,
3643 /* This elaborate scheme is needed for reading the RX discard
3644 * counters, as they are only 16-bit and can overflow quickly,
3645 * and because the overflow indication bit is not usable as
3646 * the counter value does not wrap, but remains at max value
3649 * In theory and in practice counters can be lost in between
3650 * reading nr64() and clearing the counter nw64(). For this
3651 * reason, the number of counter clearings nw64() is
3652 * limited/reduced though the limit parameter.
3654 int rx_channel = rp->rx_channel;
3657 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3658 * following discard events: IPP (Input Port Process),
3659 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3660 * Block Ring) prefetch buffer is empty.
3662 misc = nr64(RXMISC(rx_channel));
3663 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3664 nw64(RXMISC(rx_channel), 0);
3665 rp->rx_errors += misc & RXMISC_COUNT;
3667 if (unlikely(misc & RXMISC_OFLOW))
3668 dev_err(np->device, "rx-%d: Counter overflow "
3669 "RXMISC discard\n", rx_channel);
3671 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3672 np->dev->name, rx_channel, misc, misc-limit);
3675 /* WRED (Weighted Random Early Discard) by hardware */
3676 wred = nr64(RED_DIS_CNT(rx_channel));
3677 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3678 nw64(RED_DIS_CNT(rx_channel), 0);
3679 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3681 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3682 dev_err(np->device, "rx-%d: Counter overflow "
3683 "WRED discard\n", rx_channel);
3685 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3686 np->dev->name, rx_channel, wred, wred-limit);
3690 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3692 int qlen, rcr_done = 0, work_done = 0;
3693 struct rxdma_mailbox *mbox = rp->mbox;
3697 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3698 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3700 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3701 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3703 mbox->rx_dma_ctl_stat = 0;
3704 mbox->rcrstat_a = 0;
3706 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3707 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3709 rcr_done = work_done = 0;
3710 qlen = min(qlen, budget);
3711 while (work_done < qlen) {
3712 rcr_done += niu_process_rx_pkt(np, rp);
3716 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3719 for (i = 0; i < rp->rbr_refill_pending; i++)
3720 niu_rbr_refill(np, rp, GFP_ATOMIC);
3721 rp->rbr_refill_pending = 0;
3724 stat = (RX_DMA_CTL_STAT_MEX |
3725 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3726 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3728 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3730 /* Only sync discards stats when qlen indicate potential for drops */
3732 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3737 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3740 u32 tx_vec = (v0 >> 32);
3741 u32 rx_vec = (v0 & 0xffffffff);
3742 int i, work_done = 0;
3744 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3745 np->dev->name, (unsigned long long) v0);
3747 for (i = 0; i < np->num_tx_rings; i++) {
3748 struct tx_ring_info *rp = &np->tx_rings[i];
3749 if (tx_vec & (1 << rp->tx_channel))
3750 niu_tx_work(np, rp);
3751 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3754 for (i = 0; i < np->num_rx_rings; i++) {
3755 struct rx_ring_info *rp = &np->rx_rings[i];
3757 if (rx_vec & (1 << rp->rx_channel)) {
3760 this_work_done = niu_rx_work(np, rp,
3763 budget -= this_work_done;
3764 work_done += this_work_done;
3766 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3772 static int niu_poll(struct napi_struct *napi, int budget)
3774 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3775 struct niu *np = lp->np;
3778 work_done = niu_poll_core(np, lp, budget);
3780 if (work_done < budget) {
3781 napi_complete(napi);
3782 niu_ldg_rearm(np, lp, 1);
3787 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3790 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3791 np->dev->name, rp->rx_channel);
3793 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3794 printk("RBR_TMOUT ");
3795 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3797 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3798 printk("BYTE_EN_BUS ");
3799 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3801 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3803 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3804 printk("RCR_SHA_PAR ");
3805 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3806 printk("RBR_PRE_PAR ");
3807 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3809 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3810 printk("RCRINCON ");
3811 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3813 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3815 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3816 printk("RBRLOGPAGE ");
3817 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3818 printk("CFIGLOGPAGE ");
3819 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3825 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3827 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3831 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3832 RX_DMA_CTL_STAT_PORT_FATAL))
3836 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3837 np->dev->name, rp->rx_channel,
3838 (unsigned long long) stat);
3840 niu_log_rxchan_errors(np, rp, stat);
3843 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3844 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3849 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3852 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3853 np->dev->name, rp->tx_channel);
3855 if (cs & TX_CS_MBOX_ERR)
3857 if (cs & TX_CS_PKT_SIZE_ERR)
3858 printk("PKT_SIZE ");
3859 if (cs & TX_CS_TX_RING_OFLOW)
3860 printk("TX_RING_OFLOW ");
3861 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3862 printk("PREF_BUF_PAR ");
3863 if (cs & TX_CS_NACK_PREF)
3864 printk("NACK_PREF ");
3865 if (cs & TX_CS_NACK_PKT_RD)
3866 printk("NACK_PKT_RD ");
3867 if (cs & TX_CS_CONF_PART_ERR)
3868 printk("CONF_PART ");
3869 if (cs & TX_CS_PKT_PRT_ERR)
3875 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3879 cs = nr64(TX_CS(rp->tx_channel));
3880 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3881 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3883 dev_err(np->device, PFX "%s: TX channel %u error, "
3884 "cs[%llx] logh[%llx] logl[%llx]\n",
3885 np->dev->name, rp->tx_channel,
3886 (unsigned long long) cs,
3887 (unsigned long long) logh,
3888 (unsigned long long) logl);
3890 niu_log_txchan_errors(np, rp, cs);
3895 static int niu_mif_interrupt(struct niu *np)
3897 u64 mif_status = nr64(MIF_STATUS);
3900 if (np->flags & NIU_FLAGS_XMAC) {
3901 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3903 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3907 dev_err(np->device, PFX "%s: MIF interrupt, "
3908 "stat[%llx] phy_mdint(%d)\n",
3909 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3914 static void niu_xmac_interrupt(struct niu *np)
3916 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3919 val = nr64_mac(XTXMAC_STATUS);
3920 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3921 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3922 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3923 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3924 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3925 mp->tx_fifo_errors++;
3926 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3927 mp->tx_overflow_errors++;
3928 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3929 mp->tx_max_pkt_size_errors++;
3930 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3931 mp->tx_underflow_errors++;
3933 val = nr64_mac(XRXMAC_STATUS);
3934 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3935 mp->rx_local_faults++;
3936 if (val & XRXMAC_STATUS_RFLT_DET)
3937 mp->rx_remote_faults++;
3938 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3939 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3940 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3941 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3942 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3943 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3944 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3945 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3946 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3947 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3948 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3949 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3950 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3951 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3952 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3953 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3954 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3955 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3956 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3957 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3958 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3959 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3960 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3961 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3962 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3963 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3964 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3965 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3967 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3969 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3970 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3971 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3972 if (val & XRXMAC_STATUS_RXUFLOW)
3973 mp->rx_underflows++;
3974 if (val & XRXMAC_STATUS_RXOFLOW)
3977 val = nr64_mac(XMAC_FC_STAT);
3978 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3979 mp->pause_off_state++;
3980 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3981 mp->pause_on_state++;
3982 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3983 mp->pause_received++;
3986 static void niu_bmac_interrupt(struct niu *np)
3988 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3991 val = nr64_mac(BTXMAC_STATUS);
3992 if (val & BTXMAC_STATUS_UNDERRUN)
3993 mp->tx_underflow_errors++;
3994 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3995 mp->tx_max_pkt_size_errors++;
3996 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3997 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3998 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3999 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4001 val = nr64_mac(BRXMAC_STATUS);
4002 if (val & BRXMAC_STATUS_OVERFLOW)
4004 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4005 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4006 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4007 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4008 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4009 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4010 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4011 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4013 val = nr64_mac(BMAC_CTRL_STATUS);
4014 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4015 mp->pause_off_state++;
4016 if (val & BMAC_CTRL_STATUS_PAUSE)
4017 mp->pause_on_state++;
4018 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4019 mp->pause_received++;
4022 static int niu_mac_interrupt(struct niu *np)
4024 if (np->flags & NIU_FLAGS_XMAC)
4025 niu_xmac_interrupt(np);
4027 niu_bmac_interrupt(np);
4032 static void niu_log_device_error(struct niu *np, u64 stat)
4034 dev_err(np->device, PFX "%s: Core device errors ( ",
4037 if (stat & SYS_ERR_MASK_META2)
4039 if (stat & SYS_ERR_MASK_META1)
4041 if (stat & SYS_ERR_MASK_PEU)
4043 if (stat & SYS_ERR_MASK_TXC)
4045 if (stat & SYS_ERR_MASK_RDMC)
4047 if (stat & SYS_ERR_MASK_TDMC)
4049 if (stat & SYS_ERR_MASK_ZCP)
4051 if (stat & SYS_ERR_MASK_FFLP)
4053 if (stat & SYS_ERR_MASK_IPP)
4055 if (stat & SYS_ERR_MASK_MAC)
4057 if (stat & SYS_ERR_MASK_SMX)
4063 static int niu_device_error(struct niu *np)
4065 u64 stat = nr64(SYS_ERR_STAT);
4067 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4068 np->dev->name, (unsigned long long) stat);
4070 niu_log_device_error(np, stat);
4075 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4076 u64 v0, u64 v1, u64 v2)
4085 if (v1 & 0x00000000ffffffffULL) {
4086 u32 rx_vec = (v1 & 0xffffffff);
4088 for (i = 0; i < np->num_rx_rings; i++) {
4089 struct rx_ring_info *rp = &np->rx_rings[i];
4091 if (rx_vec & (1 << rp->rx_channel)) {
4092 int r = niu_rx_error(np, rp);
4097 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4098 RX_DMA_CTL_STAT_MEX);
4103 if (v1 & 0x7fffffff00000000ULL) {
4104 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4106 for (i = 0; i < np->num_tx_rings; i++) {
4107 struct tx_ring_info *rp = &np->tx_rings[i];
4109 if (tx_vec & (1 << rp->tx_channel)) {
4110 int r = niu_tx_error(np, rp);
4116 if ((v0 | v1) & 0x8000000000000000ULL) {
4117 int r = niu_mif_interrupt(np);
4123 int r = niu_mac_interrupt(np);
4128 int r = niu_device_error(np);
4135 niu_enable_interrupts(np, 0);
4140 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4143 struct rxdma_mailbox *mbox = rp->mbox;
4144 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4146 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4147 RX_DMA_CTL_STAT_RCRTO);
4148 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4150 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4151 np->dev->name, (unsigned long long) stat);
4154 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4157 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4159 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4160 np->dev->name, (unsigned long long) rp->tx_cs);
4163 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4165 struct niu_parent *parent = np->parent;
4169 tx_vec = (v0 >> 32);
4170 rx_vec = (v0 & 0xffffffff);
4172 for (i = 0; i < np->num_rx_rings; i++) {
4173 struct rx_ring_info *rp = &np->rx_rings[i];
4174 int ldn = LDN_RXDMA(rp->rx_channel);
4176 if (parent->ldg_map[ldn] != ldg)
4179 nw64(LD_IM0(ldn), LD_IM0_MASK);
4180 if (rx_vec & (1 << rp->rx_channel))
4181 niu_rxchan_intr(np, rp, ldn);
4184 for (i = 0; i < np->num_tx_rings; i++) {
4185 struct tx_ring_info *rp = &np->tx_rings[i];
4186 int ldn = LDN_TXDMA(rp->tx_channel);
4188 if (parent->ldg_map[ldn] != ldg)
4191 nw64(LD_IM0(ldn), LD_IM0_MASK);
4192 if (tx_vec & (1 << rp->tx_channel))
4193 niu_txchan_intr(np, rp, ldn);
4197 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4198 u64 v0, u64 v1, u64 v2)
4200 if (likely(napi_schedule_prep(&lp->napi))) {
4204 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4205 __napi_schedule(&lp->napi);
4209 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4211 struct niu_ldg *lp = dev_id;
4212 struct niu *np = lp->np;
4213 int ldg = lp->ldg_num;
4214 unsigned long flags;
4217 if (netif_msg_intr(np))
4218 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4221 spin_lock_irqsave(&np->lock, flags);
4223 v0 = nr64(LDSV0(ldg));
4224 v1 = nr64(LDSV1(ldg));
4225 v2 = nr64(LDSV2(ldg));
4227 if (netif_msg_intr(np))
4228 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4229 (unsigned long long) v0,
4230 (unsigned long long) v1,
4231 (unsigned long long) v2);
4233 if (unlikely(!v0 && !v1 && !v2)) {
4234 spin_unlock_irqrestore(&np->lock, flags);
4238 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4239 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4243 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4244 niu_schedule_napi(np, lp, v0, v1, v2);
4246 niu_ldg_rearm(np, lp, 1);
4248 spin_unlock_irqrestore(&np->lock, flags);
4253 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4256 np->ops->free_coherent(np->device,
4257 sizeof(struct rxdma_mailbox),
4258 rp->mbox, rp->mbox_dma);
4262 np->ops->free_coherent(np->device,
4263 MAX_RCR_RING_SIZE * sizeof(__le64),
4264 rp->rcr, rp->rcr_dma);
4266 rp->rcr_table_size = 0;
4270 niu_rbr_free(np, rp);
4272 np->ops->free_coherent(np->device,
4273 MAX_RBR_RING_SIZE * sizeof(__le32),
4274 rp->rbr, rp->rbr_dma);
4276 rp->rbr_table_size = 0;
4283 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4286 np->ops->free_coherent(np->device,
4287 sizeof(struct txdma_mailbox),
4288 rp->mbox, rp->mbox_dma);
4294 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4295 if (rp->tx_buffs[i].skb)
4296 (void) release_tx_packet(np, rp, i);
4299 np->ops->free_coherent(np->device,
4300 MAX_TX_RING_SIZE * sizeof(__le64),
4301 rp->descr, rp->descr_dma);
4310 static void niu_free_channels(struct niu *np)
4315 for (i = 0; i < np->num_rx_rings; i++) {
4316 struct rx_ring_info *rp = &np->rx_rings[i];
4318 niu_free_rx_ring_info(np, rp);
4320 kfree(np->rx_rings);
4321 np->rx_rings = NULL;
4322 np->num_rx_rings = 0;
4326 for (i = 0; i < np->num_tx_rings; i++) {
4327 struct tx_ring_info *rp = &np->tx_rings[i];
4329 niu_free_tx_ring_info(np, rp);
4331 kfree(np->tx_rings);
4332 np->tx_rings = NULL;
4333 np->num_tx_rings = 0;
4337 static int niu_alloc_rx_ring_info(struct niu *np,
4338 struct rx_ring_info *rp)
4340 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4342 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4347 rp->mbox = np->ops->alloc_coherent(np->device,
4348 sizeof(struct rxdma_mailbox),
4349 &rp->mbox_dma, GFP_KERNEL);
4352 if ((unsigned long)rp->mbox & (64UL - 1)) {
4353 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4354 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4358 rp->rcr = np->ops->alloc_coherent(np->device,
4359 MAX_RCR_RING_SIZE * sizeof(__le64),
4360 &rp->rcr_dma, GFP_KERNEL);
4363 if ((unsigned long)rp->rcr & (64UL - 1)) {
4364 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4365 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4368 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4371 rp->rbr = np->ops->alloc_coherent(np->device,
4372 MAX_RBR_RING_SIZE * sizeof(__le32),
4373 &rp->rbr_dma, GFP_KERNEL);
4376 if ((unsigned long)rp->rbr & (64UL - 1)) {
4377 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4378 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4381 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4383 rp->rbr_pending = 0;
4388 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4390 int mtu = np->dev->mtu;
4392 /* These values are recommended by the HW designers for fair
4393 * utilization of DRR amongst the rings.
4395 rp->max_burst = mtu + 32;
4396 if (rp->max_burst > 4096)
4397 rp->max_burst = 4096;
4400 static int niu_alloc_tx_ring_info(struct niu *np,
4401 struct tx_ring_info *rp)
4403 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4405 rp->mbox = np->ops->alloc_coherent(np->device,
4406 sizeof(struct txdma_mailbox),
4407 &rp->mbox_dma, GFP_KERNEL);
4410 if ((unsigned long)rp->mbox & (64UL - 1)) {
4411 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4412 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4416 rp->descr = np->ops->alloc_coherent(np->device,
4417 MAX_TX_RING_SIZE * sizeof(__le64),
4418 &rp->descr_dma, GFP_KERNEL);
4421 if ((unsigned long)rp->descr & (64UL - 1)) {
4422 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4423 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4427 rp->pending = MAX_TX_RING_SIZE;
4432 /* XXX make these configurable... XXX */
4433 rp->mark_freq = rp->pending / 4;
4435 niu_set_max_burst(np, rp);
4440 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4444 bss = min(PAGE_SHIFT, 15);
4446 rp->rbr_block_size = 1 << bss;
4447 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4449 rp->rbr_sizes[0] = 256;
4450 rp->rbr_sizes[1] = 1024;
4451 if (np->dev->mtu > ETH_DATA_LEN) {
4452 switch (PAGE_SIZE) {
4454 rp->rbr_sizes[2] = 4096;
4458 rp->rbr_sizes[2] = 8192;
4462 rp->rbr_sizes[2] = 2048;
4464 rp->rbr_sizes[3] = rp->rbr_block_size;
4467 static int niu_alloc_channels(struct niu *np)
4469 struct niu_parent *parent = np->parent;
4470 int first_rx_channel, first_tx_channel;
4474 first_rx_channel = first_tx_channel = 0;
4475 for (i = 0; i < port; i++) {
4476 first_rx_channel += parent->rxchan_per_port[i];
4477 first_tx_channel += parent->txchan_per_port[i];
4480 np->num_rx_rings = parent->rxchan_per_port[port];
4481 np->num_tx_rings = parent->txchan_per_port[port];
4483 np->dev->real_num_tx_queues = np->num_tx_rings;
4485 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4491 for (i = 0; i < np->num_rx_rings; i++) {
4492 struct rx_ring_info *rp = &np->rx_rings[i];
4495 rp->rx_channel = first_rx_channel + i;
4497 err = niu_alloc_rx_ring_info(np, rp);
4501 niu_size_rbr(np, rp);
4503 /* XXX better defaults, configurable, etc... XXX */
4504 rp->nonsyn_window = 64;
4505 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4506 rp->syn_window = 64;
4507 rp->syn_threshold = rp->rcr_table_size - 64;
4508 rp->rcr_pkt_threshold = 16;
4509 rp->rcr_timeout = 8;
4510 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4511 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4512 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4514 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4519 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4525 for (i = 0; i < np->num_tx_rings; i++) {
4526 struct tx_ring_info *rp = &np->tx_rings[i];
4529 rp->tx_channel = first_tx_channel + i;
4531 err = niu_alloc_tx_ring_info(np, rp);
4539 niu_free_channels(np);
4543 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4547 while (--limit > 0) {
4548 u64 val = nr64(TX_CS(channel));
4549 if (val & TX_CS_SNG_STATE)
4555 static int niu_tx_channel_stop(struct niu *np, int channel)
4557 u64 val = nr64(TX_CS(channel));
4559 val |= TX_CS_STOP_N_GO;
4560 nw64(TX_CS(channel), val);
4562 return niu_tx_cs_sng_poll(np, channel);
4565 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4569 while (--limit > 0) {
4570 u64 val = nr64(TX_CS(channel));
4571 if (!(val & TX_CS_RST))
4577 static int niu_tx_channel_reset(struct niu *np, int channel)
4579 u64 val = nr64(TX_CS(channel));
4583 nw64(TX_CS(channel), val);
4585 err = niu_tx_cs_reset_poll(np, channel);
4587 nw64(TX_RING_KICK(channel), 0);
4592 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4596 nw64(TX_LOG_MASK1(channel), 0);
4597 nw64(TX_LOG_VAL1(channel), 0);
4598 nw64(TX_LOG_MASK2(channel), 0);
4599 nw64(TX_LOG_VAL2(channel), 0);
4600 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4601 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4602 nw64(TX_LOG_PAGE_HDL(channel), 0);
4604 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4605 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4606 nw64(TX_LOG_PAGE_VLD(channel), val);
4608 /* XXX TXDMA 32bit mode? XXX */
4613 static void niu_txc_enable_port(struct niu *np, int on)
4615 unsigned long flags;
4618 niu_lock_parent(np, flags);
4619 val = nr64(TXC_CONTROL);
4620 mask = (u64)1 << np->port;
4622 val |= TXC_CONTROL_ENABLE | mask;
4625 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4626 val &= ~TXC_CONTROL_ENABLE;
4628 nw64(TXC_CONTROL, val);
4629 niu_unlock_parent(np, flags);
4632 static void niu_txc_set_imask(struct niu *np, u64 imask)
4634 unsigned long flags;
4637 niu_lock_parent(np, flags);
4638 val = nr64(TXC_INT_MASK);
4639 val &= ~TXC_INT_MASK_VAL(np->port);
4640 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4641 niu_unlock_parent(np, flags);
4644 static void niu_txc_port_dma_enable(struct niu *np, int on)
4651 for (i = 0; i < np->num_tx_rings; i++)
4652 val |= (1 << np->tx_rings[i].tx_channel);
4654 nw64(TXC_PORT_DMA(np->port), val);
4657 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4659 int err, channel = rp->tx_channel;
4662 err = niu_tx_channel_stop(np, channel);
4666 err = niu_tx_channel_reset(np, channel);
4670 err = niu_tx_channel_lpage_init(np, channel);
4674 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4675 nw64(TX_ENT_MSK(channel), 0);
4677 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4678 TX_RNG_CFIG_STADDR)) {
4679 dev_err(np->device, PFX "%s: TX ring channel %d "
4680 "DMA addr (%llx) is not aligned.\n",
4681 np->dev->name, channel,
4682 (unsigned long long) rp->descr_dma);
4686 /* The length field in TX_RNG_CFIG is measured in 64-byte
4687 * blocks. rp->pending is the number of TX descriptors in
4688 * our ring, 8 bytes each, thus we divide by 8 bytes more
4689 * to get the proper value the chip wants.
4691 ring_len = (rp->pending / 8);
4693 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4695 nw64(TX_RNG_CFIG(channel), val);
4697 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4698 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4699 dev_err(np->device, PFX "%s: TX ring channel %d "
4700 "MBOX addr (%llx) is has illegal bits.\n",
4701 np->dev->name, channel,
4702 (unsigned long long) rp->mbox_dma);
4705 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4706 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4708 nw64(TX_CS(channel), 0);
4710 rp->last_pkt_cnt = 0;
4715 static void niu_init_rdc_groups(struct niu *np)
4717 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4718 int i, first_table_num = tp->first_table_num;
4720 for (i = 0; i < tp->num_tables; i++) {
4721 struct rdc_table *tbl = &tp->tables[i];
4722 int this_table = first_table_num + i;
4725 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4726 nw64(RDC_TBL(this_table, slot),
4727 tbl->rxdma_channel[slot]);
4730 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4733 static void niu_init_drr_weight(struct niu *np)
4735 int type = phy_decode(np->parent->port_phy, np->port);
4740 val = PT_DRR_WEIGHT_DEFAULT_10G;
4745 val = PT_DRR_WEIGHT_DEFAULT_1G;
4748 nw64(PT_DRR_WT(np->port), val);
4751 static int niu_init_hostinfo(struct niu *np)
4753 struct niu_parent *parent = np->parent;
4754 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4755 int i, err, num_alt = niu_num_alt_addr(np);
4756 int first_rdc_table = tp->first_table_num;
4758 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4762 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4766 for (i = 0; i < num_alt; i++) {
4767 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4775 static int niu_rx_channel_reset(struct niu *np, int channel)
4777 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4778 RXDMA_CFIG1_RST, 1000, 10,
4782 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4786 nw64(RX_LOG_MASK1(channel), 0);
4787 nw64(RX_LOG_VAL1(channel), 0);
4788 nw64(RX_LOG_MASK2(channel), 0);
4789 nw64(RX_LOG_VAL2(channel), 0);
4790 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4791 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4792 nw64(RX_LOG_PAGE_HDL(channel), 0);
4794 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4795 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4796 nw64(RX_LOG_PAGE_VLD(channel), val);
4801 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4805 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4806 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4807 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4808 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4809 nw64(RDC_RED_PARA(rp->rx_channel), val);
4812 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4816 switch (rp->rbr_block_size) {
4818 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4821 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4824 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4827 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4832 val |= RBR_CFIG_B_VLD2;
4833 switch (rp->rbr_sizes[2]) {
4835 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4838 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4841 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4844 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850 val |= RBR_CFIG_B_VLD1;
4851 switch (rp->rbr_sizes[1]) {
4853 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4856 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4859 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4862 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868 val |= RBR_CFIG_B_VLD0;
4869 switch (rp->rbr_sizes[0]) {
4871 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4874 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4877 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4880 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4891 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4893 u64 val = nr64(RXDMA_CFIG1(channel));
4897 val |= RXDMA_CFIG1_EN;
4899 val &= ~RXDMA_CFIG1_EN;
4900 nw64(RXDMA_CFIG1(channel), val);
4903 while (--limit > 0) {
4904 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4913 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4915 int err, channel = rp->rx_channel;
4918 err = niu_rx_channel_reset(np, channel);
4922 err = niu_rx_channel_lpage_init(np, channel);
4926 niu_rx_channel_wred_init(np, rp);
4928 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4929 nw64(RX_DMA_CTL_STAT(channel),
4930 (RX_DMA_CTL_STAT_MEX |
4931 RX_DMA_CTL_STAT_RCRTHRES |
4932 RX_DMA_CTL_STAT_RCRTO |
4933 RX_DMA_CTL_STAT_RBR_EMPTY));
4934 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4935 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4936 nw64(RBR_CFIG_A(channel),
4937 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4938 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4939 err = niu_compute_rbr_cfig_b(rp, &val);
4942 nw64(RBR_CFIG_B(channel), val);
4943 nw64(RCRCFIG_A(channel),
4944 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4945 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4946 nw64(RCRCFIG_B(channel),
4947 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4949 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4951 err = niu_enable_rx_channel(np, channel, 1);
4955 nw64(RBR_KICK(channel), rp->rbr_index);
4957 val = nr64(RX_DMA_CTL_STAT(channel));
4958 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4959 nw64(RX_DMA_CTL_STAT(channel), val);
4964 static int niu_init_rx_channels(struct niu *np)
4966 unsigned long flags;
4967 u64 seed = jiffies_64;
4970 niu_lock_parent(np, flags);
4971 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4972 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4973 niu_unlock_parent(np, flags);
4975 /* XXX RXDMA 32bit mode? XXX */
4977 niu_init_rdc_groups(np);
4978 niu_init_drr_weight(np);
4980 err = niu_init_hostinfo(np);
4984 for (i = 0; i < np->num_rx_rings; i++) {
4985 struct rx_ring_info *rp = &np->rx_rings[i];
4987 err = niu_init_one_rx_channel(np, rp);
4995 static int niu_set_ip_frag_rule(struct niu *np)
4997 struct niu_parent *parent = np->parent;
4998 struct niu_classifier *cp = &np->clas;
4999 struct niu_tcam_entry *tp;
5002 /* XXX fix this allocation scheme XXX */
5003 index = cp->tcam_index;
5004 tp = &parent->tcam[index];
5006 /* Note that the noport bit is the same in both ipv4 and
5007 * ipv6 format TCAM entries.
5009 memset(tp, 0, sizeof(*tp));
5010 tp->key[1] = TCAM_V4KEY1_NOPORT;
5011 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5012 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5013 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5014 err = tcam_write(np, index, tp->key, tp->key_mask);
5017 err = tcam_assoc_write(np, index, tp->assoc_data);
5024 static int niu_init_classifier_hw(struct niu *np)
5026 struct niu_parent *parent = np->parent;
5027 struct niu_classifier *cp = &np->clas;
5030 nw64(H1POLY, cp->h1_init);
5031 nw64(H2POLY, cp->h2_init);
5033 err = niu_init_hostinfo(np);
5037 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5038 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5040 vlan_tbl_write(np, i, np->port,
5041 vp->vlan_pref, vp->rdc_num);
5044 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5045 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5047 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5048 ap->rdc_num, ap->mac_pref);
5053 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5054 int index = i - CLASS_CODE_USER_PROG1;
5056 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5059 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5064 err = niu_set_ip_frag_rule(np);
5073 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5075 nw64(ZCP_RAM_DATA0, data[0]);
5076 nw64(ZCP_RAM_DATA1, data[1]);
5077 nw64(ZCP_RAM_DATA2, data[2]);
5078 nw64(ZCP_RAM_DATA3, data[3]);
5079 nw64(ZCP_RAM_DATA4, data[4]);
5080 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5082 (ZCP_RAM_ACC_WRITE |
5083 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5084 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5086 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5090 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5094 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5097 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5098 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5099 (unsigned long long) nr64(ZCP_RAM_ACC));
5105 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5108 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5111 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5112 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5113 (unsigned long long) nr64(ZCP_RAM_ACC));
5117 data[0] = nr64(ZCP_RAM_DATA0);
5118 data[1] = nr64(ZCP_RAM_DATA1);
5119 data[2] = nr64(ZCP_RAM_DATA2);
5120 data[3] = nr64(ZCP_RAM_DATA3);
5121 data[4] = nr64(ZCP_RAM_DATA4);
5126 static void niu_zcp_cfifo_reset(struct niu *np)
5128 u64 val = nr64(RESET_CFIFO);
5130 val |= RESET_CFIFO_RST(np->port);
5131 nw64(RESET_CFIFO, val);
5134 val &= ~RESET_CFIFO_RST(np->port);
5135 nw64(RESET_CFIFO, val);
5138 static int niu_init_zcp(struct niu *np)
5140 u64 data[5], rbuf[5];
5143 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5144 if (np->port == 0 || np->port == 1)
5145 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5147 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5149 max = NIU_CFIFO_ENTRIES;
5157 for (i = 0; i < max; i++) {
5158 err = niu_zcp_write(np, i, data);
5161 err = niu_zcp_read(np, i, rbuf);
5166 niu_zcp_cfifo_reset(np);
5167 nw64(CFIFO_ECC(np->port), 0);
5168 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5169 (void) nr64(ZCP_INT_STAT);
5170 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5175 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5177 u64 val = nr64_ipp(IPP_CFIG);
5179 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5180 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5181 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5182 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5183 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5184 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5185 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5186 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5189 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5191 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5192 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5193 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5194 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5195 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5196 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5199 static int niu_ipp_reset(struct niu *np)
5201 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5202 1000, 100, "IPP_CFIG");
5205 static int niu_init_ipp(struct niu *np)
5207 u64 data[5], rbuf[5], val;
5210 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5211 if (np->port == 0 || np->port == 1)
5212 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5214 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5216 max = NIU_DFIFO_ENTRIES;
5224 for (i = 0; i < max; i++) {
5225 niu_ipp_write(np, i, data);
5226 niu_ipp_read(np, i, rbuf);
5229 (void) nr64_ipp(IPP_INT_STAT);
5230 (void) nr64_ipp(IPP_INT_STAT);
5232 err = niu_ipp_reset(np);
5236 (void) nr64_ipp(IPP_PKT_DIS);
5237 (void) nr64_ipp(IPP_BAD_CS_CNT);
5238 (void) nr64_ipp(IPP_ECC);
5240 (void) nr64_ipp(IPP_INT_STAT);
5242 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5244 val = nr64_ipp(IPP_CFIG);
5245 val &= ~IPP_CFIG_IP_MAX_PKT;
5246 val |= (IPP_CFIG_IPP_ENABLE |
5247 IPP_CFIG_DFIFO_ECC_EN |
5248 IPP_CFIG_DROP_BAD_CRC |
5250 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5251 nw64_ipp(IPP_CFIG, val);
5256 static void niu_handle_led(struct niu *np, int status)
5259 val = nr64_mac(XMAC_CONFIG);
5261 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5262 (np->flags & NIU_FLAGS_FIBER) != 0) {
5264 val |= XMAC_CONFIG_LED_POLARITY;
5265 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5267 val |= XMAC_CONFIG_FORCE_LED_ON;
5268 val &= ~XMAC_CONFIG_LED_POLARITY;
5272 nw64_mac(XMAC_CONFIG, val);
5275 static void niu_init_xif_xmac(struct niu *np)
5277 struct niu_link_config *lp = &np->link_config;
5280 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5281 val = nr64(MIF_CONFIG);
5282 val |= MIF_CONFIG_ATCA_GE;
5283 nw64(MIF_CONFIG, val);
5286 val = nr64_mac(XMAC_CONFIG);
5287 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5289 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5291 if (lp->loopback_mode == LOOPBACK_MAC) {
5292 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5293 val |= XMAC_CONFIG_LOOPBACK;
5295 val &= ~XMAC_CONFIG_LOOPBACK;
5298 if (np->flags & NIU_FLAGS_10G) {
5299 val &= ~XMAC_CONFIG_LFS_DISABLE;
5301 val |= XMAC_CONFIG_LFS_DISABLE;
5302 if (!(np->flags & NIU_FLAGS_FIBER) &&
5303 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5304 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5306 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5309 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5311 if (lp->active_speed == SPEED_100)
5312 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5314 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5316 nw64_mac(XMAC_CONFIG, val);
5318 val = nr64_mac(XMAC_CONFIG);
5319 val &= ~XMAC_CONFIG_MODE_MASK;
5320 if (np->flags & NIU_FLAGS_10G) {
5321 val |= XMAC_CONFIG_MODE_XGMII;
5323 if (lp->active_speed == SPEED_1000)
5324 val |= XMAC_CONFIG_MODE_GMII;
5326 val |= XMAC_CONFIG_MODE_MII;
5329 nw64_mac(XMAC_CONFIG, val);
5332 static void niu_init_xif_bmac(struct niu *np)
5334 struct niu_link_config *lp = &np->link_config;
5337 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5339 if (lp->loopback_mode == LOOPBACK_MAC)
5340 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5342 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5344 if (lp->active_speed == SPEED_1000)
5345 val |= BMAC_XIF_CONFIG_GMII_MODE;
5347 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5349 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5350 BMAC_XIF_CONFIG_LED_POLARITY);
5352 if (!(np->flags & NIU_FLAGS_10G) &&
5353 !(np->flags & NIU_FLAGS_FIBER) &&
5354 lp->active_speed == SPEED_100)
5355 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5357 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5359 nw64_mac(BMAC_XIF_CONFIG, val);
5362 static void niu_init_xif(struct niu *np)
5364 if (np->flags & NIU_FLAGS_XMAC)
5365 niu_init_xif_xmac(np);
5367 niu_init_xif_bmac(np);
5370 static void niu_pcs_mii_reset(struct niu *np)
5373 u64 val = nr64_pcs(PCS_MII_CTL);
5374 val |= PCS_MII_CTL_RST;
5375 nw64_pcs(PCS_MII_CTL, val);
5376 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5378 val = nr64_pcs(PCS_MII_CTL);
5382 static void niu_xpcs_reset(struct niu *np)
5385 u64 val = nr64_xpcs(XPCS_CONTROL1);
5386 val |= XPCS_CONTROL1_RESET;
5387 nw64_xpcs(XPCS_CONTROL1, val);
5388 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5390 val = nr64_xpcs(XPCS_CONTROL1);
5394 static int niu_init_pcs(struct niu *np)
5396 struct niu_link_config *lp = &np->link_config;
5399 switch (np->flags & (NIU_FLAGS_10G |
5401 NIU_FLAGS_XCVR_SERDES)) {
5402 case NIU_FLAGS_FIBER:
5404 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5405 nw64_pcs(PCS_DPATH_MODE, 0);
5406 niu_pcs_mii_reset(np);
5410 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5411 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5413 if (!(np->flags & NIU_FLAGS_XMAC))
5416 /* 10G copper or fiber */
5417 val = nr64_mac(XMAC_CONFIG);
5418 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5419 nw64_mac(XMAC_CONFIG, val);
5423 val = nr64_xpcs(XPCS_CONTROL1);
5424 if (lp->loopback_mode == LOOPBACK_PHY)
5425 val |= XPCS_CONTROL1_LOOPBACK;
5427 val &= ~XPCS_CONTROL1_LOOPBACK;
5428 nw64_xpcs(XPCS_CONTROL1, val);
5430 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5431 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5432 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5436 case NIU_FLAGS_XCVR_SERDES:
5438 niu_pcs_mii_reset(np);
5439 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5440 nw64_pcs(PCS_DPATH_MODE, 0);
5445 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5446 /* 1G RGMII FIBER */
5447 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5448 niu_pcs_mii_reset(np);
5458 static int niu_reset_tx_xmac(struct niu *np)
5460 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5461 (XTXMAC_SW_RST_REG_RS |
5462 XTXMAC_SW_RST_SOFT_RST),
5463 1000, 100, "XTXMAC_SW_RST");
5466 static int niu_reset_tx_bmac(struct niu *np)
5470 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5472 while (--limit >= 0) {
5473 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5478 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5479 "BTXMAC_SW_RST[%llx]\n",
5481 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5488 static int niu_reset_tx_mac(struct niu *np)
5490 if (np->flags & NIU_FLAGS_XMAC)
5491 return niu_reset_tx_xmac(np);
5493 return niu_reset_tx_bmac(np);
5496 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5500 val = nr64_mac(XMAC_MIN);
5501 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5502 XMAC_MIN_RX_MIN_PKT_SIZE);
5503 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5504 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5505 nw64_mac(XMAC_MIN, val);
5507 nw64_mac(XMAC_MAX, max);
5509 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5511 val = nr64_mac(XMAC_IPG);
5512 if (np->flags & NIU_FLAGS_10G) {
5513 val &= ~XMAC_IPG_IPG_XGMII;
5514 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5516 val &= ~XMAC_IPG_IPG_MII_GMII;
5517 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5519 nw64_mac(XMAC_IPG, val);
5521 val = nr64_mac(XMAC_CONFIG);
5522 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5523 XMAC_CONFIG_STRETCH_MODE |
5524 XMAC_CONFIG_VAR_MIN_IPG_EN |
5525 XMAC_CONFIG_TX_ENABLE);
5526 nw64_mac(XMAC_CONFIG, val);
5528 nw64_mac(TXMAC_FRM_CNT, 0);
5529 nw64_mac(TXMAC_BYTE_CNT, 0);
5532 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5536 nw64_mac(BMAC_MIN_FRAME, min);
5537 nw64_mac(BMAC_MAX_FRAME, max);
5539 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5540 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5541 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5543 val = nr64_mac(BTXMAC_CONFIG);
5544 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5545 BTXMAC_CONFIG_ENABLE);
5546 nw64_mac(BTXMAC_CONFIG, val);
5549 static void niu_init_tx_mac(struct niu *np)
5554 if (np->dev->mtu > ETH_DATA_LEN)
5559 /* The XMAC_MIN register only accepts values for TX min which
5560 * have the low 3 bits cleared.
5562 BUILD_BUG_ON(min & 0x7);
5564 if (np->flags & NIU_FLAGS_XMAC)
5565 niu_init_tx_xmac(np, min, max);
5567 niu_init_tx_bmac(np, min, max);
5570 static int niu_reset_rx_xmac(struct niu *np)
5574 nw64_mac(XRXMAC_SW_RST,
5575 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5577 while (--limit >= 0) {
5578 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5579 XRXMAC_SW_RST_SOFT_RST)))
5584 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5585 "XRXMAC_SW_RST[%llx]\n",
5587 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5594 static int niu_reset_rx_bmac(struct niu *np)
5598 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5600 while (--limit >= 0) {
5601 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5606 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5607 "BRXMAC_SW_RST[%llx]\n",
5609 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5616 static int niu_reset_rx_mac(struct niu *np)
5618 if (np->flags & NIU_FLAGS_XMAC)
5619 return niu_reset_rx_xmac(np);
5621 return niu_reset_rx_bmac(np);
5624 static void niu_init_rx_xmac(struct niu *np)
5626 struct niu_parent *parent = np->parent;
5627 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5628 int first_rdc_table = tp->first_table_num;
5632 nw64_mac(XMAC_ADD_FILT0, 0);
5633 nw64_mac(XMAC_ADD_FILT1, 0);
5634 nw64_mac(XMAC_ADD_FILT2, 0);
5635 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5636 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5637 for (i = 0; i < MAC_NUM_HASH; i++)
5638 nw64_mac(XMAC_HASH_TBL(i), 0);
5639 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5640 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5641 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5643 val = nr64_mac(XMAC_CONFIG);
5644 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5645 XMAC_CONFIG_PROMISCUOUS |
5646 XMAC_CONFIG_PROMISC_GROUP |
5647 XMAC_CONFIG_ERR_CHK_DIS |
5648 XMAC_CONFIG_RX_CRC_CHK_DIS |
5649 XMAC_CONFIG_RESERVED_MULTICAST |
5650 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5651 XMAC_CONFIG_ADDR_FILTER_EN |
5652 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5653 XMAC_CONFIG_STRIP_CRC |
5654 XMAC_CONFIG_PASS_FLOW_CTRL |
5655 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5656 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5657 nw64_mac(XMAC_CONFIG, val);
5659 nw64_mac(RXMAC_BT_CNT, 0);
5660 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5661 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5662 nw64_mac(RXMAC_FRAG_CNT, 0);
5663 nw64_mac(RXMAC_HIST_CNT1, 0);
5664 nw64_mac(RXMAC_HIST_CNT2, 0);
5665 nw64_mac(RXMAC_HIST_CNT3, 0);
5666 nw64_mac(RXMAC_HIST_CNT4, 0);
5667 nw64_mac(RXMAC_HIST_CNT5, 0);
5668 nw64_mac(RXMAC_HIST_CNT6, 0);
5669 nw64_mac(RXMAC_HIST_CNT7, 0);
5670 nw64_mac(RXMAC_MPSZER_CNT, 0);
5671 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5672 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5673 nw64_mac(LINK_FAULT_CNT, 0);
5676 static void niu_init_rx_bmac(struct niu *np)
5678 struct niu_parent *parent = np->parent;
5679 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5680 int first_rdc_table = tp->first_table_num;
5684 nw64_mac(BMAC_ADD_FILT0, 0);
5685 nw64_mac(BMAC_ADD_FILT1, 0);
5686 nw64_mac(BMAC_ADD_FILT2, 0);
5687 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5688 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5689 for (i = 0; i < MAC_NUM_HASH; i++)
5690 nw64_mac(BMAC_HASH_TBL(i), 0);
5691 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5692 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5693 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5695 val = nr64_mac(BRXMAC_CONFIG);
5696 val &= ~(BRXMAC_CONFIG_ENABLE |
5697 BRXMAC_CONFIG_STRIP_PAD |
5698 BRXMAC_CONFIG_STRIP_FCS |
5699 BRXMAC_CONFIG_PROMISC |
5700 BRXMAC_CONFIG_PROMISC_GRP |
5701 BRXMAC_CONFIG_ADDR_FILT_EN |
5702 BRXMAC_CONFIG_DISCARD_DIS);
5703 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5704 nw64_mac(BRXMAC_CONFIG, val);
5706 val = nr64_mac(BMAC_ADDR_CMPEN);
5707 val |= BMAC_ADDR_CMPEN_EN0;
5708 nw64_mac(BMAC_ADDR_CMPEN, val);
5711 static void niu_init_rx_mac(struct niu *np)
5713 niu_set_primary_mac(np, np->dev->dev_addr);
5715 if (np->flags & NIU_FLAGS_XMAC)
5716 niu_init_rx_xmac(np);
5718 niu_init_rx_bmac(np);
5721 static void niu_enable_tx_xmac(struct niu *np, int on)
5723 u64 val = nr64_mac(XMAC_CONFIG);
5726 val |= XMAC_CONFIG_TX_ENABLE;
5728 val &= ~XMAC_CONFIG_TX_ENABLE;
5729 nw64_mac(XMAC_CONFIG, val);
5732 static void niu_enable_tx_bmac(struct niu *np, int on)
5734 u64 val = nr64_mac(BTXMAC_CONFIG);
5737 val |= BTXMAC_CONFIG_ENABLE;
5739 val &= ~BTXMAC_CONFIG_ENABLE;
5740 nw64_mac(BTXMAC_CONFIG, val);
5743 static void niu_enable_tx_mac(struct niu *np, int on)
5745 if (np->flags & NIU_FLAGS_XMAC)
5746 niu_enable_tx_xmac(np, on);
5748 niu_enable_tx_bmac(np, on);
5751 static void niu_enable_rx_xmac(struct niu *np, int on)
5753 u64 val = nr64_mac(XMAC_CONFIG);
5755 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5756 XMAC_CONFIG_PROMISCUOUS);
5758 if (np->flags & NIU_FLAGS_MCAST)
5759 val |= XMAC_CONFIG_HASH_FILTER_EN;
5760 if (np->flags & NIU_FLAGS_PROMISC)
5761 val |= XMAC_CONFIG_PROMISCUOUS;
5764 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5766 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5767 nw64_mac(XMAC_CONFIG, val);
5770 static void niu_enable_rx_bmac(struct niu *np, int on)
5772 u64 val = nr64_mac(BRXMAC_CONFIG);
5774 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5775 BRXMAC_CONFIG_PROMISC);
5777 if (np->flags & NIU_FLAGS_MCAST)
5778 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5779 if (np->flags & NIU_FLAGS_PROMISC)
5780 val |= BRXMAC_CONFIG_PROMISC;
5783 val |= BRXMAC_CONFIG_ENABLE;
5785 val &= ~BRXMAC_CONFIG_ENABLE;
5786 nw64_mac(BRXMAC_CONFIG, val);
5789 static void niu_enable_rx_mac(struct niu *np, int on)
5791 if (np->flags & NIU_FLAGS_XMAC)
5792 niu_enable_rx_xmac(np, on);
5794 niu_enable_rx_bmac(np, on);
5797 static int niu_init_mac(struct niu *np)
5802 err = niu_init_pcs(np);
5806 err = niu_reset_tx_mac(np);
5809 niu_init_tx_mac(np);
5810 err = niu_reset_rx_mac(np);
5813 niu_init_rx_mac(np);
5815 /* This looks hookey but the RX MAC reset we just did will
5816 * undo some of the state we setup in niu_init_tx_mac() so we
5817 * have to call it again. In particular, the RX MAC reset will
5818 * set the XMAC_MAX register back to it's default value.
5820 niu_init_tx_mac(np);
5821 niu_enable_tx_mac(np, 1);
5823 niu_enable_rx_mac(np, 1);
5828 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5830 (void) niu_tx_channel_stop(np, rp->tx_channel);
5833 static void niu_stop_tx_channels(struct niu *np)
5837 for (i = 0; i < np->num_tx_rings; i++) {
5838 struct tx_ring_info *rp = &np->tx_rings[i];
5840 niu_stop_one_tx_channel(np, rp);
5844 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5846 (void) niu_tx_channel_reset(np, rp->tx_channel);
5849 static void niu_reset_tx_channels(struct niu *np)
5853 for (i = 0; i < np->num_tx_rings; i++) {
5854 struct tx_ring_info *rp = &np->tx_rings[i];
5856 niu_reset_one_tx_channel(np, rp);
5860 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5862 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5865 static void niu_stop_rx_channels(struct niu *np)
5869 for (i = 0; i < np->num_rx_rings; i++) {
5870 struct rx_ring_info *rp = &np->rx_rings[i];
5872 niu_stop_one_rx_channel(np, rp);
5876 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5878 int channel = rp->rx_channel;
5880 (void) niu_rx_channel_reset(np, channel);
5881 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5882 nw64(RX_DMA_CTL_STAT(channel), 0);
5883 (void) niu_enable_rx_channel(np, channel, 0);
5886 static void niu_reset_rx_channels(struct niu *np)
5890 for (i = 0; i < np->num_rx_rings; i++) {
5891 struct rx_ring_info *rp = &np->rx_rings[i];
5893 niu_reset_one_rx_channel(np, rp);
5897 static void niu_disable_ipp(struct niu *np)
5902 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5903 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5905 while (--limit >= 0 && (rd != wr)) {
5906 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5907 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5910 (rd != 0 && wr != 1)) {
5911 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5912 "rd_ptr[%llx] wr_ptr[%llx]\n",
5914 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5915 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5918 val = nr64_ipp(IPP_CFIG);
5919 val &= ~(IPP_CFIG_IPP_ENABLE |
5920 IPP_CFIG_DFIFO_ECC_EN |
5921 IPP_CFIG_DROP_BAD_CRC |
5923 nw64_ipp(IPP_CFIG, val);
5925 (void) niu_ipp_reset(np);
5928 static int niu_init_hw(struct niu *np)
5932 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5933 niu_txc_enable_port(np, 1);
5934 niu_txc_port_dma_enable(np, 1);
5935 niu_txc_set_imask(np, 0);
5937 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5938 for (i = 0; i < np->num_tx_rings; i++) {
5939 struct tx_ring_info *rp = &np->tx_rings[i];
5941 err = niu_init_one_tx_channel(np, rp);
5946 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5947 err = niu_init_rx_channels(np);
5949 goto out_uninit_tx_channels;
5951 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5952 err = niu_init_classifier_hw(np);
5954 goto out_uninit_rx_channels;
5956 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5957 err = niu_init_zcp(np);
5959 goto out_uninit_rx_channels;
5961 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5962 err = niu_init_ipp(np);
5964 goto out_uninit_rx_channels;
5966 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5967 err = niu_init_mac(np);
5969 goto out_uninit_ipp;
5974 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5975 niu_disable_ipp(np);
5977 out_uninit_rx_channels:
5978 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5979 niu_stop_rx_channels(np);
5980 niu_reset_rx_channels(np);
5982 out_uninit_tx_channels:
5983 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5984 niu_stop_tx_channels(np);
5985 niu_reset_tx_channels(np);
5990 static void niu_stop_hw(struct niu *np)
5992 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5993 niu_enable_interrupts(np, 0);
5995 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5996 niu_enable_rx_mac(np, 0);
5998 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5999 niu_disable_ipp(np);
6001 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6002 niu_stop_tx_channels(np);
6004 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6005 niu_stop_rx_channels(np);
6007 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6008 niu_reset_tx_channels(np);
6010 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6011 niu_reset_rx_channels(np);
6014 static void niu_set_irq_name(struct niu *np)
6016 int port = np->port;
6019 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6022 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6023 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6027 for (i = 0; i < np->num_ldg - j; i++) {
6028 if (i < np->num_rx_rings)
6029 sprintf(np->irq_name[i+j], "%s-rx-%d",
6031 else if (i < np->num_tx_rings + np->num_rx_rings)
6032 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6033 i - np->num_rx_rings);
6037 static int niu_request_irq(struct niu *np)
6041 niu_set_irq_name(np);
6044 for (i = 0; i < np->num_ldg; i++) {
6045 struct niu_ldg *lp = &np->ldg[i];
6047 err = request_irq(lp->irq, niu_interrupt,
6048 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6049 np->irq_name[i], lp);
6058 for (j = 0; j < i; j++) {
6059 struct niu_ldg *lp = &np->ldg[j];
6061 free_irq(lp->irq, lp);
6066 static void niu_free_irq(struct niu *np)
6070 for (i = 0; i < np->num_ldg; i++) {
6071 struct niu_ldg *lp = &np->ldg[i];
6073 free_irq(lp->irq, lp);
6077 static void niu_enable_napi(struct niu *np)
6081 for (i = 0; i < np->num_ldg; i++)
6082 napi_enable(&np->ldg[i].napi);
6085 static void niu_disable_napi(struct niu *np)
6089 for (i = 0; i < np->num_ldg; i++)
6090 napi_disable(&np->ldg[i].napi);
6093 static int niu_open(struct net_device *dev)
6095 struct niu *np = netdev_priv(dev);
6098 netif_carrier_off(dev);
6100 err = niu_alloc_channels(np);
6104 err = niu_enable_interrupts(np, 0);
6106 goto out_free_channels;
6108 err = niu_request_irq(np);
6110 goto out_free_channels;
6112 niu_enable_napi(np);
6114 spin_lock_irq(&np->lock);
6116 err = niu_init_hw(np);
6118 init_timer(&np->timer);
6119 np->timer.expires = jiffies + HZ;
6120 np->timer.data = (unsigned long) np;
6121 np->timer.function = niu_timer;
6123 err = niu_enable_interrupts(np, 1);
6128 spin_unlock_irq(&np->lock);
6131 niu_disable_napi(np);
6135 netif_tx_start_all_queues(dev);
6137 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6138 netif_carrier_on(dev);
6140 add_timer(&np->timer);
6148 niu_free_channels(np);
6154 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6156 cancel_work_sync(&np->reset_task);
6158 niu_disable_napi(np);
6159 netif_tx_stop_all_queues(dev);
6161 del_timer_sync(&np->timer);
6163 spin_lock_irq(&np->lock);
6167 spin_unlock_irq(&np->lock);
6170 static int niu_close(struct net_device *dev)
6172 struct niu *np = netdev_priv(dev);
6174 niu_full_shutdown(np, dev);
6178 niu_free_channels(np);
6180 niu_handle_led(np, 0);
6185 static void niu_sync_xmac_stats(struct niu *np)
6187 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6189 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6190 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6192 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6193 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6194 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6195 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6196 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6197 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6198 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6199 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6200 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6201 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6202 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6203 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6204 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6205 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6206 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6207 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6210 static void niu_sync_bmac_stats(struct niu *np)
6212 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6214 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6215 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6217 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6218 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6219 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6220 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6223 static void niu_sync_mac_stats(struct niu *np)
6225 if (np->flags & NIU_FLAGS_XMAC)
6226 niu_sync_xmac_stats(np);
6228 niu_sync_bmac_stats(np);
6231 static void niu_get_rx_stats(struct niu *np)
6233 unsigned long pkts, dropped, errors, bytes;
6236 pkts = dropped = errors = bytes = 0;
6237 for (i = 0; i < np->num_rx_rings; i++) {
6238 struct rx_ring_info *rp = &np->rx_rings[i];
6240 niu_sync_rx_discard_stats(np, rp, 0);
6242 pkts += rp->rx_packets;
6243 bytes += rp->rx_bytes;
6244 dropped += rp->rx_dropped;
6245 errors += rp->rx_errors;
6247 np->dev->stats.rx_packets = pkts;
6248 np->dev->stats.rx_bytes = bytes;
6249 np->dev->stats.rx_dropped = dropped;
6250 np->dev->stats.rx_errors = errors;
6253 static void niu_get_tx_stats(struct niu *np)
6255 unsigned long pkts, errors, bytes;
6258 pkts = errors = bytes = 0;
6259 for (i = 0; i < np->num_tx_rings; i++) {
6260 struct tx_ring_info *rp = &np->tx_rings[i];
6262 pkts += rp->tx_packets;
6263 bytes += rp->tx_bytes;
6264 errors += rp->tx_errors;
6266 np->dev->stats.tx_packets = pkts;
6267 np->dev->stats.tx_bytes = bytes;
6268 np->dev->stats.tx_errors = errors;
6271 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6273 struct niu *np = netdev_priv(dev);
6275 niu_get_rx_stats(np);
6276 niu_get_tx_stats(np);
6281 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6285 for (i = 0; i < 16; i++)
6286 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6289 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6293 for (i = 0; i < 16; i++)
6294 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6297 static void niu_load_hash(struct niu *np, u16 *hash)
6299 if (np->flags & NIU_FLAGS_XMAC)
6300 niu_load_hash_xmac(np, hash);
6302 niu_load_hash_bmac(np, hash);
6305 static void niu_set_rx_mode(struct net_device *dev)
6307 struct niu *np = netdev_priv(dev);
6308 int i, alt_cnt, err;
6309 struct dev_addr_list *addr;
6310 unsigned long flags;
6311 u16 hash[16] = { 0, };
6313 spin_lock_irqsave(&np->lock, flags);
6314 niu_enable_rx_mac(np, 0);
6316 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6317 if (dev->flags & IFF_PROMISC)
6318 np->flags |= NIU_FLAGS_PROMISC;
6319 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6320 np->flags |= NIU_FLAGS_MCAST;
6322 alt_cnt = dev->uc_count;
6323 if (alt_cnt > niu_num_alt_addr(np)) {
6325 np->flags |= NIU_FLAGS_PROMISC;
6331 for (addr = dev->uc_list; addr; addr = addr->next) {
6332 err = niu_set_alt_mac(np, index,
6335 printk(KERN_WARNING PFX "%s: Error %d "
6336 "adding alt mac %d\n",
6337 dev->name, err, index);
6338 err = niu_enable_alt_mac(np, index, 1);
6340 printk(KERN_WARNING PFX "%s: Error %d "
6341 "enabling alt mac %d\n",
6342 dev->name, err, index);
6348 if (np->flags & NIU_FLAGS_XMAC)
6352 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6353 err = niu_enable_alt_mac(np, i, 0);
6355 printk(KERN_WARNING PFX "%s: Error %d "
6356 "disabling alt mac %d\n",
6360 if (dev->flags & IFF_ALLMULTI) {
6361 for (i = 0; i < 16; i++)
6363 } else if (dev->mc_count > 0) {
6364 for (addr = dev->mc_list; addr; addr = addr->next) {
6365 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6368 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6372 if (np->flags & NIU_FLAGS_MCAST)
6373 niu_load_hash(np, hash);
6375 niu_enable_rx_mac(np, 1);
6376 spin_unlock_irqrestore(&np->lock, flags);
6379 static int niu_set_mac_addr(struct net_device *dev, void *p)
6381 struct niu *np = netdev_priv(dev);
6382 struct sockaddr *addr = p;
6383 unsigned long flags;
6385 if (!is_valid_ether_addr(addr->sa_data))
6388 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6390 if (!netif_running(dev))
6393 spin_lock_irqsave(&np->lock, flags);
6394 niu_enable_rx_mac(np, 0);
6395 niu_set_primary_mac(np, dev->dev_addr);
6396 niu_enable_rx_mac(np, 1);
6397 spin_unlock_irqrestore(&np->lock, flags);
6402 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6407 static void niu_netif_stop(struct niu *np)
6409 np->dev->trans_start = jiffies; /* prevent tx timeout */
6411 niu_disable_napi(np);
6413 netif_tx_disable(np->dev);
6416 static void niu_netif_start(struct niu *np)
6418 /* NOTE: unconditional netif_wake_queue is only appropriate
6419 * so long as all callers are assured to have free tx slots
6420 * (such as after niu_init_hw).
6422 netif_tx_wake_all_queues(np->dev);
6424 niu_enable_napi(np);
6426 niu_enable_interrupts(np, 1);
6429 static void niu_reset_buffers(struct niu *np)
6434 for (i = 0; i < np->num_rx_rings; i++) {
6435 struct rx_ring_info *rp = &np->rx_rings[i];
6437 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6440 page = rp->rxhash[j];
6443 (struct page *) page->mapping;
6444 u64 base = page->index;
6445 base = base >> RBR_DESCR_ADDR_SHIFT;
6446 rp->rbr[k++] = cpu_to_le32(base);
6450 for (; k < MAX_RBR_RING_SIZE; k++) {
6451 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6456 rp->rbr_index = rp->rbr_table_size - 1;
6458 rp->rbr_pending = 0;
6459 rp->rbr_refill_pending = 0;
6463 for (i = 0; i < np->num_tx_rings; i++) {
6464 struct tx_ring_info *rp = &np->tx_rings[i];
6466 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6467 if (rp->tx_buffs[j].skb)
6468 (void) release_tx_packet(np, rp, j);
6471 rp->pending = MAX_TX_RING_SIZE;
6479 static void niu_reset_task(struct work_struct *work)
6481 struct niu *np = container_of(work, struct niu, reset_task);
6482 unsigned long flags;
6485 spin_lock_irqsave(&np->lock, flags);
6486 if (!netif_running(np->dev)) {
6487 spin_unlock_irqrestore(&np->lock, flags);
6491 spin_unlock_irqrestore(&np->lock, flags);
6493 del_timer_sync(&np->timer);
6497 spin_lock_irqsave(&np->lock, flags);
6501 spin_unlock_irqrestore(&np->lock, flags);
6503 niu_reset_buffers(np);
6505 spin_lock_irqsave(&np->lock, flags);
6507 err = niu_init_hw(np);
6509 np->timer.expires = jiffies + HZ;
6510 add_timer(&np->timer);
6511 niu_netif_start(np);
6514 spin_unlock_irqrestore(&np->lock, flags);
6517 static void niu_tx_timeout(struct net_device *dev)
6519 struct niu *np = netdev_priv(dev);
6521 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6524 schedule_work(&np->reset_task);
6527 static void niu_set_txd(struct tx_ring_info *rp, int index,
6528 u64 mapping, u64 len, u64 mark,
6531 __le64 *desc = &rp->descr[index];
6533 *desc = cpu_to_le64(mark |
6534 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6535 (len << TX_DESC_TR_LEN_SHIFT) |
6536 (mapping & TX_DESC_SAD));
6539 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6540 u64 pad_bytes, u64 len)
6542 u16 eth_proto, eth_proto_inner;
6543 u64 csum_bits, l3off, ihl, ret;
6547 eth_proto = be16_to_cpu(ehdr->h_proto);
6548 eth_proto_inner = eth_proto;
6549 if (eth_proto == ETH_P_8021Q) {
6550 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6551 __be16 val = vp->h_vlan_encapsulated_proto;
6553 eth_proto_inner = be16_to_cpu(val);
6557 switch (skb->protocol) {
6558 case cpu_to_be16(ETH_P_IP):
6559 ip_proto = ip_hdr(skb)->protocol;
6560 ihl = ip_hdr(skb)->ihl;
6562 case cpu_to_be16(ETH_P_IPV6):
6563 ip_proto = ipv6_hdr(skb)->nexthdr;
6572 csum_bits = TXHDR_CSUM_NONE;
6573 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6576 csum_bits = (ip_proto == IPPROTO_TCP ?
6578 (ip_proto == IPPROTO_UDP ?
6579 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6581 start = skb_transport_offset(skb) -
6582 (pad_bytes + sizeof(struct tx_pkt_hdr));
6583 stuff = start + skb->csum_offset;
6585 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6586 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6589 l3off = skb_network_offset(skb) -
6590 (pad_bytes + sizeof(struct tx_pkt_hdr));
6592 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6593 (len << TXHDR_LEN_SHIFT) |
6594 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6595 (ihl << TXHDR_IHL_SHIFT) |
6596 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6597 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6598 (ipv6 ? TXHDR_IP_VER : 0) |
6604 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6606 struct niu *np = netdev_priv(dev);
6607 unsigned long align, headroom;
6608 struct netdev_queue *txq;
6609 struct tx_ring_info *rp;
6610 struct tx_pkt_hdr *tp;
6611 unsigned int len, nfg;
6612 struct ethhdr *ehdr;
6616 i = skb_get_queue_mapping(skb);
6617 rp = &np->tx_rings[i];
6618 txq = netdev_get_tx_queue(dev, i);
6620 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6621 netif_tx_stop_queue(txq);
6622 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6623 "queue awake!\n", dev->name);
6625 return NETDEV_TX_BUSY;
6628 if (skb->len < ETH_ZLEN) {
6629 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6631 if (skb_pad(skb, pad_bytes))
6633 skb_put(skb, pad_bytes);
6636 len = sizeof(struct tx_pkt_hdr) + 15;
6637 if (skb_headroom(skb) < len) {
6638 struct sk_buff *skb_new;
6640 skb_new = skb_realloc_headroom(skb, len);
6650 align = ((unsigned long) skb->data & (16 - 1));
6651 headroom = align + sizeof(struct tx_pkt_hdr);
6653 ehdr = (struct ethhdr *) skb->data;
6654 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6656 len = skb->len - sizeof(struct tx_pkt_hdr);
6657 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6660 len = skb_headlen(skb);
6661 mapping = np->ops->map_single(np->device, skb->data,
6662 len, DMA_TO_DEVICE);
6666 rp->tx_buffs[prod].skb = skb;
6667 rp->tx_buffs[prod].mapping = mapping;
6670 if (++rp->mark_counter == rp->mark_freq) {
6671 rp->mark_counter = 0;
6672 mrk |= TX_DESC_MARK;
6677 nfg = skb_shinfo(skb)->nr_frags;
6679 tlen -= MAX_TX_DESC_LEN;
6684 unsigned int this_len = len;
6686 if (this_len > MAX_TX_DESC_LEN)
6687 this_len = MAX_TX_DESC_LEN;
6689 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6692 prod = NEXT_TX(rp, prod);
6693 mapping += this_len;
6697 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6698 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6701 mapping = np->ops->map_page(np->device, frag->page,
6702 frag->page_offset, len,
6705 rp->tx_buffs[prod].skb = NULL;
6706 rp->tx_buffs[prod].mapping = mapping;
6708 niu_set_txd(rp, prod, mapping, len, 0, 0);
6710 prod = NEXT_TX(rp, prod);
6713 if (prod < rp->prod)
6714 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6717 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6719 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6720 netif_tx_stop_queue(txq);
6721 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6722 netif_tx_wake_queue(txq);
6725 dev->trans_start = jiffies;
6728 return NETDEV_TX_OK;
6736 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6738 struct niu *np = netdev_priv(dev);
6739 int err, orig_jumbo, new_jumbo;
6741 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6744 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6745 new_jumbo = (new_mtu > ETH_DATA_LEN);
6749 if (!netif_running(dev) ||
6750 (orig_jumbo == new_jumbo))
6753 niu_full_shutdown(np, dev);
6755 niu_free_channels(np);
6757 niu_enable_napi(np);
6759 err = niu_alloc_channels(np);
6763 spin_lock_irq(&np->lock);
6765 err = niu_init_hw(np);
6767 init_timer(&np->timer);
6768 np->timer.expires = jiffies + HZ;
6769 np->timer.data = (unsigned long) np;
6770 np->timer.function = niu_timer;
6772 err = niu_enable_interrupts(np, 1);
6777 spin_unlock_irq(&np->lock);
6780 netif_tx_start_all_queues(dev);
6781 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6782 netif_carrier_on(dev);
6784 add_timer(&np->timer);
6790 static void niu_get_drvinfo(struct net_device *dev,
6791 struct ethtool_drvinfo *info)
6793 struct niu *np = netdev_priv(dev);
6794 struct niu_vpd *vpd = &np->vpd;
6796 strcpy(info->driver, DRV_MODULE_NAME);
6797 strcpy(info->version, DRV_MODULE_VERSION);
6798 sprintf(info->fw_version, "%d.%d",
6799 vpd->fcode_major, vpd->fcode_minor);
6800 if (np->parent->plat_type != PLAT_TYPE_NIU)
6801 strcpy(info->bus_info, pci_name(np->pdev));
6804 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6806 struct niu *np = netdev_priv(dev);
6807 struct niu_link_config *lp;
6809 lp = &np->link_config;
6811 memset(cmd, 0, sizeof(*cmd));
6812 cmd->phy_address = np->phy_addr;
6813 cmd->supported = lp->supported;
6814 cmd->advertising = lp->active_advertising;
6815 cmd->autoneg = lp->active_autoneg;
6816 cmd->speed = lp->active_speed;
6817 cmd->duplex = lp->active_duplex;
6818 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6819 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6820 XCVR_EXTERNAL : XCVR_INTERNAL;
6825 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6827 struct niu *np = netdev_priv(dev);
6828 struct niu_link_config *lp = &np->link_config;
6830 lp->advertising = cmd->advertising;
6831 lp->speed = cmd->speed;
6832 lp->duplex = cmd->duplex;
6833 lp->autoneg = cmd->autoneg;
6834 return niu_init_link(np);
6837 static u32 niu_get_msglevel(struct net_device *dev)
6839 struct niu *np = netdev_priv(dev);
6840 return np->msg_enable;
6843 static void niu_set_msglevel(struct net_device *dev, u32 value)
6845 struct niu *np = netdev_priv(dev);
6846 np->msg_enable = value;
6849 static int niu_nway_reset(struct net_device *dev)
6851 struct niu *np = netdev_priv(dev);
6853 if (np->link_config.autoneg)
6854 return niu_init_link(np);
6859 static int niu_get_eeprom_len(struct net_device *dev)
6861 struct niu *np = netdev_priv(dev);
6863 return np->eeprom_len;
6866 static int niu_get_eeprom(struct net_device *dev,
6867 struct ethtool_eeprom *eeprom, u8 *data)
6869 struct niu *np = netdev_priv(dev);
6870 u32 offset, len, val;
6872 offset = eeprom->offset;
6875 if (offset + len < offset)
6877 if (offset >= np->eeprom_len)
6879 if (offset + len > np->eeprom_len)
6880 len = eeprom->len = np->eeprom_len - offset;
6883 u32 b_offset, b_count;
6885 b_offset = offset & 3;
6886 b_count = 4 - b_offset;
6890 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6891 memcpy(data, ((char *)&val) + b_offset, b_count);
6897 val = nr64(ESPC_NCR(offset / 4));
6898 memcpy(data, &val, 4);
6904 val = nr64(ESPC_NCR(offset / 4));
6905 memcpy(data, &val, len);
6910 static int niu_ethflow_to_class(int flow_type, u64 *class)
6912 switch (flow_type) {
6914 *class = CLASS_CODE_TCP_IPV4;
6917 *class = CLASS_CODE_UDP_IPV4;
6919 case AH_ESP_V4_FLOW:
6920 *class = CLASS_CODE_AH_ESP_IPV4;
6923 *class = CLASS_CODE_SCTP_IPV4;
6926 *class = CLASS_CODE_TCP_IPV6;
6929 *class = CLASS_CODE_UDP_IPV6;
6931 case AH_ESP_V6_FLOW:
6932 *class = CLASS_CODE_AH_ESP_IPV6;
6935 *class = CLASS_CODE_SCTP_IPV6;
6944 static u64 niu_flowkey_to_ethflow(u64 flow_key)
6948 if (flow_key & FLOW_KEY_PORT)
6949 ethflow |= RXH_DEV_PORT;
6950 if (flow_key & FLOW_KEY_L2DA)
6951 ethflow |= RXH_L2DA;
6952 if (flow_key & FLOW_KEY_VLAN)
6953 ethflow |= RXH_VLAN;
6954 if (flow_key & FLOW_KEY_IPSA)
6955 ethflow |= RXH_IP_SRC;
6956 if (flow_key & FLOW_KEY_IPDA)
6957 ethflow |= RXH_IP_DST;
6958 if (flow_key & FLOW_KEY_PROTO)
6959 ethflow |= RXH_L3_PROTO;
6960 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6961 ethflow |= RXH_L4_B_0_1;
6962 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6963 ethflow |= RXH_L4_B_2_3;
6969 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6973 if (ethflow & RXH_DEV_PORT)
6974 key |= FLOW_KEY_PORT;
6975 if (ethflow & RXH_L2DA)
6976 key |= FLOW_KEY_L2DA;
6977 if (ethflow & RXH_VLAN)
6978 key |= FLOW_KEY_VLAN;
6979 if (ethflow & RXH_IP_SRC)
6980 key |= FLOW_KEY_IPSA;
6981 if (ethflow & RXH_IP_DST)
6982 key |= FLOW_KEY_IPDA;
6983 if (ethflow & RXH_L3_PROTO)
6984 key |= FLOW_KEY_PROTO;
6985 if (ethflow & RXH_L4_B_0_1)
6986 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6987 if (ethflow & RXH_L4_B_2_3)
6988 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6996 static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6998 struct niu *np = netdev_priv(dev);
7003 if (!niu_ethflow_to_class(cmd->flow_type, &class))
7006 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7008 cmd->data = RXH_DISCARD;
7011 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7012 CLASS_CODE_USER_PROG1]);
7016 static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
7018 struct niu *np = netdev_priv(dev);
7021 unsigned long flags;
7023 if (!niu_ethflow_to_class(cmd->flow_type, &class))
7026 if (class < CLASS_CODE_USER_PROG1 ||
7027 class > CLASS_CODE_SCTP_IPV6)
7030 if (cmd->data & RXH_DISCARD) {
7031 niu_lock_parent(np, flags);
7032 flow_key = np->parent->tcam_key[class -
7033 CLASS_CODE_USER_PROG1];
7034 flow_key |= TCAM_KEY_DISC;
7035 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7036 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7037 niu_unlock_parent(np, flags);
7040 /* Discard was set before, but is not set now */
7041 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7043 niu_lock_parent(np, flags);
7044 flow_key = np->parent->tcam_key[class -
7045 CLASS_CODE_USER_PROG1];
7046 flow_key &= ~TCAM_KEY_DISC;
7047 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7049 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7051 niu_unlock_parent(np, flags);
7055 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
7058 niu_lock_parent(np, flags);
7059 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7060 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7061 niu_unlock_parent(np, flags);
7066 static const struct {
7067 const char string[ETH_GSTRING_LEN];
7068 } niu_xmac_stat_keys[] = {
7071 { "tx_fifo_errors" },
7072 { "tx_overflow_errors" },
7073 { "tx_max_pkt_size_errors" },
7074 { "tx_underflow_errors" },
7075 { "rx_local_faults" },
7076 { "rx_remote_faults" },
7077 { "rx_link_faults" },
7078 { "rx_align_errors" },
7090 { "rx_code_violations" },
7091 { "rx_len_errors" },
7092 { "rx_crc_errors" },
7093 { "rx_underflows" },
7095 { "pause_off_state" },
7096 { "pause_on_state" },
7097 { "pause_received" },
7100 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7102 static const struct {
7103 const char string[ETH_GSTRING_LEN];
7104 } niu_bmac_stat_keys[] = {
7105 { "tx_underflow_errors" },
7106 { "tx_max_pkt_size_errors" },
7111 { "rx_align_errors" },
7112 { "rx_crc_errors" },
7113 { "rx_len_errors" },
7114 { "pause_off_state" },
7115 { "pause_on_state" },
7116 { "pause_received" },
7119 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7121 static const struct {
7122 const char string[ETH_GSTRING_LEN];
7123 } niu_rxchan_stat_keys[] = {
7131 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7133 static const struct {
7134 const char string[ETH_GSTRING_LEN];
7135 } niu_txchan_stat_keys[] = {
7142 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7144 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7146 struct niu *np = netdev_priv(dev);
7149 if (stringset != ETH_SS_STATS)
7152 if (np->flags & NIU_FLAGS_XMAC) {
7153 memcpy(data, niu_xmac_stat_keys,
7154 sizeof(niu_xmac_stat_keys));
7155 data += sizeof(niu_xmac_stat_keys);
7157 memcpy(data, niu_bmac_stat_keys,
7158 sizeof(niu_bmac_stat_keys));
7159 data += sizeof(niu_bmac_stat_keys);
7161 for (i = 0; i < np->num_rx_rings; i++) {
7162 memcpy(data, niu_rxchan_stat_keys,
7163 sizeof(niu_rxchan_stat_keys));
7164 data += sizeof(niu_rxchan_stat_keys);
7166 for (i = 0; i < np->num_tx_rings; i++) {
7167 memcpy(data, niu_txchan_stat_keys,
7168 sizeof(niu_txchan_stat_keys));
7169 data += sizeof(niu_txchan_stat_keys);
7173 static int niu_get_stats_count(struct net_device *dev)
7175 struct niu *np = netdev_priv(dev);
7177 return ((np->flags & NIU_FLAGS_XMAC ?
7178 NUM_XMAC_STAT_KEYS :
7179 NUM_BMAC_STAT_KEYS) +
7180 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7181 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7184 static void niu_get_ethtool_stats(struct net_device *dev,
7185 struct ethtool_stats *stats, u64 *data)
7187 struct niu *np = netdev_priv(dev);
7190 niu_sync_mac_stats(np);
7191 if (np->flags & NIU_FLAGS_XMAC) {
7192 memcpy(data, &np->mac_stats.xmac,
7193 sizeof(struct niu_xmac_stats));
7194 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7196 memcpy(data, &np->mac_stats.bmac,
7197 sizeof(struct niu_bmac_stats));
7198 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7200 for (i = 0; i < np->num_rx_rings; i++) {
7201 struct rx_ring_info *rp = &np->rx_rings[i];
7203 niu_sync_rx_discard_stats(np, rp, 0);
7205 data[0] = rp->rx_channel;
7206 data[1] = rp->rx_packets;
7207 data[2] = rp->rx_bytes;
7208 data[3] = rp->rx_dropped;
7209 data[4] = rp->rx_errors;
7212 for (i = 0; i < np->num_tx_rings; i++) {
7213 struct tx_ring_info *rp = &np->tx_rings[i];
7215 data[0] = rp->tx_channel;
7216 data[1] = rp->tx_packets;
7217 data[2] = rp->tx_bytes;
7218 data[3] = rp->tx_errors;
7223 static u64 niu_led_state_save(struct niu *np)
7225 if (np->flags & NIU_FLAGS_XMAC)
7226 return nr64_mac(XMAC_CONFIG);
7228 return nr64_mac(BMAC_XIF_CONFIG);
7231 static void niu_led_state_restore(struct niu *np, u64 val)
7233 if (np->flags & NIU_FLAGS_XMAC)
7234 nw64_mac(XMAC_CONFIG, val);
7236 nw64_mac(BMAC_XIF_CONFIG, val);
7239 static void niu_force_led(struct niu *np, int on)
7243 if (np->flags & NIU_FLAGS_XMAC) {
7245 bit = XMAC_CONFIG_FORCE_LED_ON;
7247 reg = BMAC_XIF_CONFIG;
7248 bit = BMAC_XIF_CONFIG_LINK_LED;
7251 val = nr64_mac(reg);
7259 static int niu_phys_id(struct net_device *dev, u32 data)
7261 struct niu *np = netdev_priv(dev);
7265 if (!netif_running(dev))
7271 orig_led_state = niu_led_state_save(np);
7272 for (i = 0; i < (data * 2); i++) {
7273 int on = ((i % 2) == 0);
7275 niu_force_led(np, on);
7277 if (msleep_interruptible(500))
7280 niu_led_state_restore(np, orig_led_state);
7285 static const struct ethtool_ops niu_ethtool_ops = {
7286 .get_drvinfo = niu_get_drvinfo,
7287 .get_link = ethtool_op_get_link,
7288 .get_msglevel = niu_get_msglevel,
7289 .set_msglevel = niu_set_msglevel,
7290 .nway_reset = niu_nway_reset,
7291 .get_eeprom_len = niu_get_eeprom_len,
7292 .get_eeprom = niu_get_eeprom,
7293 .get_settings = niu_get_settings,
7294 .set_settings = niu_set_settings,
7295 .get_strings = niu_get_strings,
7296 .get_stats_count = niu_get_stats_count,
7297 .get_ethtool_stats = niu_get_ethtool_stats,
7298 .phys_id = niu_phys_id,
7299 .get_rxhash = niu_get_hash_opts,
7300 .set_rxhash = niu_set_hash_opts,
7303 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7306 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7308 if (ldn < 0 || ldn > LDN_MAX)
7311 parent->ldg_map[ldn] = ldg;
7313 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7314 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7315 * the firmware, and we're not supposed to change them.
7316 * Validate the mapping, because if it's wrong we probably
7317 * won't get any interrupts and that's painful to debug.
7319 if (nr64(LDG_NUM(ldn)) != ldg) {
7320 dev_err(np->device, PFX "Port %u, mis-matched "
7322 "for ldn %d, should be %d is %llu\n",
7324 (unsigned long long) nr64(LDG_NUM(ldn)));
7328 nw64(LDG_NUM(ldn), ldg);
7333 static int niu_set_ldg_timer_res(struct niu *np, int res)
7335 if (res < 0 || res > LDG_TIMER_RES_VAL)
7339 nw64(LDG_TIMER_RES, res);
7344 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7346 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7347 (func < 0 || func > 3) ||
7348 (vector < 0 || vector > 0x1f))
7351 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7356 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7358 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7359 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7362 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7366 nw64(ESPC_PIO_STAT, frame);
7370 frame = nr64(ESPC_PIO_STAT);
7371 if (frame & ESPC_PIO_STAT_READ_END)
7374 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7375 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7376 (unsigned long long) frame);
7381 nw64(ESPC_PIO_STAT, frame);
7385 frame = nr64(ESPC_PIO_STAT);
7386 if (frame & ESPC_PIO_STAT_READ_END)
7389 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7390 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7391 (unsigned long long) frame);
7395 frame = nr64(ESPC_PIO_STAT);
7396 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7399 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7401 int err = niu_pci_eeprom_read(np, off);
7407 err = niu_pci_eeprom_read(np, off + 1);
7410 val |= (err & 0xff);
7415 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7417 int err = niu_pci_eeprom_read(np, off);
7424 err = niu_pci_eeprom_read(np, off + 1);
7428 val |= (err & 0xff) << 8;
7433 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7440 for (i = 0; i < namebuf_len; i++) {
7441 int err = niu_pci_eeprom_read(np, off + i);
7448 if (i >= namebuf_len)
7454 static void __devinit niu_vpd_parse_version(struct niu *np)
7456 struct niu_vpd *vpd = &np->vpd;
7457 int len = strlen(vpd->version) + 1;
7458 const char *s = vpd->version;
7461 for (i = 0; i < len - 5; i++) {
7462 if (!strncmp(s + i, "FCode ", 5))
7469 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7471 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7472 vpd->fcode_major, vpd->fcode_minor);
7473 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7474 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7475 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7476 np->flags |= NIU_FLAGS_VPD_VALID;
7479 /* ESPC_PIO_EN_ENABLE must be set */
7480 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7483 unsigned int found_mask = 0;
7484 #define FOUND_MASK_MODEL 0x00000001
7485 #define FOUND_MASK_BMODEL 0x00000002
7486 #define FOUND_MASK_VERS 0x00000004
7487 #define FOUND_MASK_MAC 0x00000008
7488 #define FOUND_MASK_NMAC 0x00000010
7489 #define FOUND_MASK_PHY 0x00000020
7490 #define FOUND_MASK_ALL 0x0000003f
7492 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7494 while (start < end) {
7495 int len, err, instance, type, prop_len;
7500 if (found_mask == FOUND_MASK_ALL) {
7501 niu_vpd_parse_version(np);
7505 err = niu_pci_eeprom_read(np, start + 2);
7511 instance = niu_pci_eeprom_read(np, start);
7512 type = niu_pci_eeprom_read(np, start + 3);
7513 prop_len = niu_pci_eeprom_read(np, start + 4);
7514 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7520 if (!strcmp(namebuf, "model")) {
7521 prop_buf = np->vpd.model;
7522 max_len = NIU_VPD_MODEL_MAX;
7523 found_mask |= FOUND_MASK_MODEL;
7524 } else if (!strcmp(namebuf, "board-model")) {
7525 prop_buf = np->vpd.board_model;
7526 max_len = NIU_VPD_BD_MODEL_MAX;
7527 found_mask |= FOUND_MASK_BMODEL;
7528 } else if (!strcmp(namebuf, "version")) {
7529 prop_buf = np->vpd.version;
7530 max_len = NIU_VPD_VERSION_MAX;
7531 found_mask |= FOUND_MASK_VERS;
7532 } else if (!strcmp(namebuf, "local-mac-address")) {
7533 prop_buf = np->vpd.local_mac;
7535 found_mask |= FOUND_MASK_MAC;
7536 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7537 prop_buf = &np->vpd.mac_num;
7539 found_mask |= FOUND_MASK_NMAC;
7540 } else if (!strcmp(namebuf, "phy-type")) {
7541 prop_buf = np->vpd.phy_type;
7542 max_len = NIU_VPD_PHY_TYPE_MAX;
7543 found_mask |= FOUND_MASK_PHY;
7546 if (max_len && prop_len > max_len) {
7547 dev_err(np->device, PFX "Property '%s' length (%d) is "
7548 "too long.\n", namebuf, prop_len);
7553 u32 off = start + 5 + err;
7556 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7557 "len[%d]\n", namebuf, prop_len);
7558 for (i = 0; i < prop_len; i++)
7559 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7568 /* ESPC_PIO_EN_ENABLE must be set */
7569 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7574 err = niu_pci_eeprom_read16_swp(np, start + 1);
7580 while (start + offset < ESPC_EEPROM_SIZE) {
7581 u32 here = start + offset;
7584 err = niu_pci_eeprom_read(np, here);
7588 err = niu_pci_eeprom_read16_swp(np, here + 1);
7592 here = start + offset + 3;
7593 end = start + offset + err;
7597 err = niu_pci_vpd_scan_props(np, here, end);
7598 if (err < 0 || err == 1)
7603 /* ESPC_PIO_EN_ENABLE must be set */
7604 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7606 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7609 while (start < end) {
7612 /* ROM header signature? */
7613 err = niu_pci_eeprom_read16(np, start + 0);
7617 /* Apply offset to PCI data structure. */
7618 err = niu_pci_eeprom_read16(np, start + 23);
7623 /* Check for "PCIR" signature. */
7624 err = niu_pci_eeprom_read16(np, start + 0);
7627 err = niu_pci_eeprom_read16(np, start + 2);
7631 /* Check for OBP image type. */
7632 err = niu_pci_eeprom_read(np, start + 20);
7636 err = niu_pci_eeprom_read(np, ret + 2);
7640 start = ret + (err * 512);
7644 err = niu_pci_eeprom_read16_swp(np, start + 8);
7649 err = niu_pci_eeprom_read(np, ret + 0);
7659 static int __devinit niu_phy_type_prop_decode(struct niu *np,
7660 const char *phy_prop)
7662 if (!strcmp(phy_prop, "mif")) {
7663 /* 1G copper, MII */
7664 np->flags &= ~(NIU_FLAGS_FIBER |
7666 np->mac_xcvr = MAC_XCVR_MII;
7667 } else if (!strcmp(phy_prop, "xgf")) {
7668 /* 10G fiber, XPCS */
7669 np->flags |= (NIU_FLAGS_10G |
7671 np->mac_xcvr = MAC_XCVR_XPCS;
7672 } else if (!strcmp(phy_prop, "pcs")) {
7674 np->flags &= ~NIU_FLAGS_10G;
7675 np->flags |= NIU_FLAGS_FIBER;
7676 np->mac_xcvr = MAC_XCVR_PCS;
7677 } else if (!strcmp(phy_prop, "xgc")) {
7678 /* 10G copper, XPCS */
7679 np->flags |= NIU_FLAGS_10G;
7680 np->flags &= ~NIU_FLAGS_FIBER;
7681 np->mac_xcvr = MAC_XCVR_XPCS;
7682 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7683 /* 10G Serdes or 1G Serdes, default to 10G */
7684 np->flags |= NIU_FLAGS_10G;
7685 np->flags &= ~NIU_FLAGS_FIBER;
7686 np->flags |= NIU_FLAGS_XCVR_SERDES;
7687 np->mac_xcvr = MAC_XCVR_XPCS;
7694 static int niu_pci_vpd_get_nports(struct niu *np)
7698 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7699 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7700 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7701 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7702 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7704 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7705 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7706 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7707 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7714 static void __devinit niu_pci_vpd_validate(struct niu *np)
7716 struct net_device *dev = np->dev;
7717 struct niu_vpd *vpd = &np->vpd;
7720 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7721 dev_err(np->device, PFX "VPD MAC invalid, "
7722 "falling back to SPROM.\n");
7724 np->flags &= ~NIU_FLAGS_VPD_VALID;
7728 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7729 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7730 np->flags |= NIU_FLAGS_10G;
7731 np->flags &= ~NIU_FLAGS_FIBER;
7732 np->flags |= NIU_FLAGS_XCVR_SERDES;
7733 np->mac_xcvr = MAC_XCVR_PCS;
7735 np->flags |= NIU_FLAGS_FIBER;
7736 np->flags &= ~NIU_FLAGS_10G;
7738 if (np->flags & NIU_FLAGS_10G)
7739 np->mac_xcvr = MAC_XCVR_XPCS;
7740 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7741 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7742 NIU_FLAGS_HOTPLUG_PHY);
7743 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7744 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7746 dev_err(np->device, PFX "Falling back to SPROM.\n");
7747 np->flags &= ~NIU_FLAGS_VPD_VALID;
7751 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7753 val8 = dev->perm_addr[5];
7754 dev->perm_addr[5] += np->port;
7755 if (dev->perm_addr[5] < val8)
7756 dev->perm_addr[4]++;
7758 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7761 static int __devinit niu_pci_probe_sprom(struct niu *np)
7763 struct net_device *dev = np->dev;
7768 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7769 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7772 np->eeprom_len = len;
7774 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7777 for (i = 0; i < len; i++) {
7778 val = nr64(ESPC_NCR(i));
7779 sum += (val >> 0) & 0xff;
7780 sum += (val >> 8) & 0xff;
7781 sum += (val >> 16) & 0xff;
7782 sum += (val >> 24) & 0xff;
7784 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7785 if ((sum & 0xff) != 0xab) {
7786 dev_err(np->device, PFX "Bad SPROM checksum "
7787 "(%x, should be 0xab)\n", (int) (sum & 0xff));
7791 val = nr64(ESPC_PHY_TYPE);
7794 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7795 ESPC_PHY_TYPE_PORT0_SHIFT;
7798 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7799 ESPC_PHY_TYPE_PORT1_SHIFT;
7802 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7803 ESPC_PHY_TYPE_PORT2_SHIFT;
7806 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7807 ESPC_PHY_TYPE_PORT3_SHIFT;
7810 dev_err(np->device, PFX "Bogus port number %u\n",
7814 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7817 case ESPC_PHY_TYPE_1G_COPPER:
7818 /* 1G copper, MII */
7819 np->flags &= ~(NIU_FLAGS_FIBER |
7821 np->mac_xcvr = MAC_XCVR_MII;
7824 case ESPC_PHY_TYPE_1G_FIBER:
7826 np->flags &= ~NIU_FLAGS_10G;
7827 np->flags |= NIU_FLAGS_FIBER;
7828 np->mac_xcvr = MAC_XCVR_PCS;
7831 case ESPC_PHY_TYPE_10G_COPPER:
7832 /* 10G copper, XPCS */
7833 np->flags |= NIU_FLAGS_10G;
7834 np->flags &= ~NIU_FLAGS_FIBER;
7835 np->mac_xcvr = MAC_XCVR_XPCS;
7838 case ESPC_PHY_TYPE_10G_FIBER:
7839 /* 10G fiber, XPCS */
7840 np->flags |= (NIU_FLAGS_10G |
7842 np->mac_xcvr = MAC_XCVR_XPCS;
7846 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7850 val = nr64(ESPC_MAC_ADDR0);
7851 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7852 (unsigned long long) val);
7853 dev->perm_addr[0] = (val >> 0) & 0xff;
7854 dev->perm_addr[1] = (val >> 8) & 0xff;
7855 dev->perm_addr[2] = (val >> 16) & 0xff;
7856 dev->perm_addr[3] = (val >> 24) & 0xff;
7858 val = nr64(ESPC_MAC_ADDR1);
7859 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7860 (unsigned long long) val);
7861 dev->perm_addr[4] = (val >> 0) & 0xff;
7862 dev->perm_addr[5] = (val >> 8) & 0xff;
7864 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7865 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7866 dev_err(np->device, PFX "[ \n");
7867 for (i = 0; i < 6; i++)
7868 printk("%02x ", dev->perm_addr[i]);
7873 val8 = dev->perm_addr[5];
7874 dev->perm_addr[5] += np->port;
7875 if (dev->perm_addr[5] < val8)
7876 dev->perm_addr[4]++;
7878 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7880 val = nr64(ESPC_MOD_STR_LEN);
7881 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7882 (unsigned long long) val);
7886 for (i = 0; i < val; i += 4) {
7887 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7889 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
7890 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
7891 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7892 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7894 np->vpd.model[val] = '\0';
7896 val = nr64(ESPC_BD_MOD_STR_LEN);
7897 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7898 (unsigned long long) val);
7902 for (i = 0; i < val; i += 4) {
7903 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7905 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
7906 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
7907 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7908 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7910 np->vpd.board_model[val] = '\0';
7913 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7914 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7920 static int __devinit niu_get_and_validate_port(struct niu *np)
7922 struct niu_parent *parent = np->parent;
7925 np->flags |= NIU_FLAGS_XMAC;
7927 if (!parent->num_ports) {
7928 if (parent->plat_type == PLAT_TYPE_NIU) {
7929 parent->num_ports = 2;
7931 parent->num_ports = niu_pci_vpd_get_nports(np);
7932 if (!parent->num_ports) {
7933 /* Fall back to SPROM as last resort.
7934 * This will fail on most cards.
7936 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7937 ESPC_NUM_PORTS_MACS_VAL;
7939 /* All of the current probing methods fail on
7940 * Maramba on-board parts.
7942 if (!parent->num_ports)
7943 parent->num_ports = 4;
7948 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7949 np->port, parent->num_ports);
7950 if (np->port >= parent->num_ports)
7956 static int __devinit phy_record(struct niu_parent *parent,
7957 struct phy_probe_info *p,
7958 int dev_id_1, int dev_id_2, u8 phy_port,
7961 u32 id = (dev_id_1 << 16) | dev_id_2;
7964 if (dev_id_1 < 0 || dev_id_2 < 0)
7966 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7967 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7968 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7969 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7972 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7976 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7978 (type == PHY_TYPE_PMA_PMD ?
7980 (type == PHY_TYPE_PCS ?
7984 if (p->cur[type] >= NIU_MAX_PORTS) {
7985 printk(KERN_ERR PFX "Too many PHY ports.\n");
7989 p->phy_id[type][idx] = id;
7990 p->phy_port[type][idx] = phy_port;
7991 p->cur[type] = idx + 1;
7995 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7999 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8000 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8003 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8004 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8011 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8017 for (port = 8; port < 32; port++) {
8018 if (port_has_10g(p, port)) {
8028 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8031 if (p->cur[PHY_TYPE_MII])
8032 *lowest = p->phy_port[PHY_TYPE_MII][0];
8034 return p->cur[PHY_TYPE_MII];
8037 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8039 int num_ports = parent->num_ports;
8042 for (i = 0; i < num_ports; i++) {
8043 parent->rxchan_per_port[i] = (16 / num_ports);
8044 parent->txchan_per_port[i] = (16 / num_ports);
8046 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8049 parent->rxchan_per_port[i],
8050 parent->txchan_per_port[i]);
8054 static void __devinit niu_divide_channels(struct niu_parent *parent,
8055 int num_10g, int num_1g)
8057 int num_ports = parent->num_ports;
8058 int rx_chans_per_10g, rx_chans_per_1g;
8059 int tx_chans_per_10g, tx_chans_per_1g;
8060 int i, tot_rx, tot_tx;
8062 if (!num_10g || !num_1g) {
8063 rx_chans_per_10g = rx_chans_per_1g =
8064 (NIU_NUM_RXCHAN / num_ports);
8065 tx_chans_per_10g = tx_chans_per_1g =
8066 (NIU_NUM_TXCHAN / num_ports);
8068 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8069 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8070 (rx_chans_per_1g * num_1g)) /
8073 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8074 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8075 (tx_chans_per_1g * num_1g)) /
8079 tot_rx = tot_tx = 0;
8080 for (i = 0; i < num_ports; i++) {
8081 int type = phy_decode(parent->port_phy, i);
8083 if (type == PORT_TYPE_10G) {
8084 parent->rxchan_per_port[i] = rx_chans_per_10g;
8085 parent->txchan_per_port[i] = tx_chans_per_10g;
8087 parent->rxchan_per_port[i] = rx_chans_per_1g;
8088 parent->txchan_per_port[i] = tx_chans_per_1g;
8090 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8093 parent->rxchan_per_port[i],
8094 parent->txchan_per_port[i]);
8095 tot_rx += parent->rxchan_per_port[i];
8096 tot_tx += parent->txchan_per_port[i];
8099 if (tot_rx > NIU_NUM_RXCHAN) {
8100 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
8101 "resetting to one per port.\n",
8102 parent->index, tot_rx);
8103 for (i = 0; i < num_ports; i++)
8104 parent->rxchan_per_port[i] = 1;
8106 if (tot_tx > NIU_NUM_TXCHAN) {
8107 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
8108 "resetting to one per port.\n",
8109 parent->index, tot_tx);
8110 for (i = 0; i < num_ports; i++)
8111 parent->txchan_per_port[i] = 1;
8113 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8114 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
8116 parent->index, tot_rx, tot_tx);
8120 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8121 int num_10g, int num_1g)
8123 int i, num_ports = parent->num_ports;
8124 int rdc_group, rdc_groups_per_port;
8125 int rdc_channel_base;
8128 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8130 rdc_channel_base = 0;
8132 for (i = 0; i < num_ports; i++) {
8133 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8134 int grp, num_channels = parent->rxchan_per_port[i];
8135 int this_channel_offset;
8137 tp->first_table_num = rdc_group;
8138 tp->num_tables = rdc_groups_per_port;
8139 this_channel_offset = 0;
8140 for (grp = 0; grp < tp->num_tables; grp++) {
8141 struct rdc_table *rt = &tp->tables[grp];
8144 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8145 parent->index, i, tp->first_table_num + grp);
8146 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8147 rt->rxdma_channel[slot] =
8148 rdc_channel_base + this_channel_offset;
8150 printk("%d ", rt->rxdma_channel[slot]);
8152 if (++this_channel_offset == num_channels)
8153 this_channel_offset = 0;
8158 parent->rdc_default[i] = rdc_channel_base;
8160 rdc_channel_base += num_channels;
8161 rdc_group += rdc_groups_per_port;
8165 static int __devinit fill_phy_probe_info(struct niu *np,
8166 struct niu_parent *parent,
8167 struct phy_probe_info *info)
8169 unsigned long flags;
8172 memset(info, 0, sizeof(*info));
8174 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8175 niu_lock_parent(np, flags);
8177 for (port = 8; port < 32; port++) {
8178 int dev_id_1, dev_id_2;
8180 dev_id_1 = mdio_read(np, port,
8181 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8182 dev_id_2 = mdio_read(np, port,
8183 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8184 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8188 dev_id_1 = mdio_read(np, port,
8189 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8190 dev_id_2 = mdio_read(np, port,
8191 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8192 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8196 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8197 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8198 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8203 niu_unlock_parent(np, flags);
8208 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8210 struct phy_probe_info *info = &parent->phy_probe_info;
8211 int lowest_10g, lowest_1g;
8212 int num_10g, num_1g;
8216 num_10g = num_1g = 0;
8218 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8219 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8222 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8223 parent->num_ports = 4;
8224 val = (phy_encode(PORT_TYPE_1G, 0) |
8225 phy_encode(PORT_TYPE_1G, 1) |
8226 phy_encode(PORT_TYPE_1G, 2) |
8227 phy_encode(PORT_TYPE_1G, 3));
8228 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8231 parent->num_ports = 2;
8232 val = (phy_encode(PORT_TYPE_10G, 0) |
8233 phy_encode(PORT_TYPE_10G, 1));
8234 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8235 (parent->plat_type == PLAT_TYPE_NIU)) {
8236 /* this is the Monza case */
8237 if (np->flags & NIU_FLAGS_10G) {
8238 val = (phy_encode(PORT_TYPE_10G, 0) |
8239 phy_encode(PORT_TYPE_10G, 1));
8241 val = (phy_encode(PORT_TYPE_1G, 0) |
8242 phy_encode(PORT_TYPE_1G, 1));
8245 err = fill_phy_probe_info(np, parent, info);
8249 num_10g = count_10g_ports(info, &lowest_10g);
8250 num_1g = count_1g_ports(info, &lowest_1g);
8252 switch ((num_10g << 4) | num_1g) {
8254 if (lowest_1g == 10)
8255 parent->plat_type = PLAT_TYPE_VF_P0;
8256 else if (lowest_1g == 26)
8257 parent->plat_type = PLAT_TYPE_VF_P1;
8259 goto unknown_vg_1g_port;
8263 val = (phy_encode(PORT_TYPE_10G, 0) |
8264 phy_encode(PORT_TYPE_10G, 1) |
8265 phy_encode(PORT_TYPE_1G, 2) |
8266 phy_encode(PORT_TYPE_1G, 3));
8270 val = (phy_encode(PORT_TYPE_10G, 0) |
8271 phy_encode(PORT_TYPE_10G, 1));
8275 val = phy_encode(PORT_TYPE_10G, np->port);
8279 if (lowest_1g == 10)
8280 parent->plat_type = PLAT_TYPE_VF_P0;
8281 else if (lowest_1g == 26)
8282 parent->plat_type = PLAT_TYPE_VF_P1;
8284 goto unknown_vg_1g_port;
8288 if ((lowest_10g & 0x7) == 0)
8289 val = (phy_encode(PORT_TYPE_10G, 0) |
8290 phy_encode(PORT_TYPE_1G, 1) |
8291 phy_encode(PORT_TYPE_1G, 2) |
8292 phy_encode(PORT_TYPE_1G, 3));
8294 val = (phy_encode(PORT_TYPE_1G, 0) |
8295 phy_encode(PORT_TYPE_10G, 1) |
8296 phy_encode(PORT_TYPE_1G, 2) |
8297 phy_encode(PORT_TYPE_1G, 3));
8301 if (lowest_1g == 10)
8302 parent->plat_type = PLAT_TYPE_VF_P0;
8303 else if (lowest_1g == 26)
8304 parent->plat_type = PLAT_TYPE_VF_P1;
8306 goto unknown_vg_1g_port;
8308 val = (phy_encode(PORT_TYPE_1G, 0) |
8309 phy_encode(PORT_TYPE_1G, 1) |
8310 phy_encode(PORT_TYPE_1G, 2) |
8311 phy_encode(PORT_TYPE_1G, 3));
8315 printk(KERN_ERR PFX "Unsupported port config "
8322 parent->port_phy = val;
8324 if (parent->plat_type == PLAT_TYPE_NIU)
8325 niu_n2_divide_channels(parent);
8327 niu_divide_channels(parent, num_10g, num_1g);
8329 niu_divide_rdc_groups(parent, num_10g, num_1g);
8334 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8339 static int __devinit niu_probe_ports(struct niu *np)
8341 struct niu_parent *parent = np->parent;
8344 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8347 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8348 err = walk_phys(np, parent);
8352 niu_set_ldg_timer_res(np, 2);
8353 for (i = 0; i <= LDN_MAX; i++)
8354 niu_ldn_irq_enable(np, i, 0);
8357 if (parent->port_phy == PORT_PHY_INVALID)
8363 static int __devinit niu_classifier_swstate_init(struct niu *np)
8365 struct niu_classifier *cp = &np->clas;
8367 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8368 np->parent->tcam_num_entries);
8370 cp->tcam_index = (u16) np->port;
8371 cp->h1_init = 0xffffffff;
8372 cp->h2_init = 0xffff;
8374 return fflp_early_init(np);
8377 static void __devinit niu_link_config_init(struct niu *np)
8379 struct niu_link_config *lp = &np->link_config;
8381 lp->advertising = (ADVERTISED_10baseT_Half |
8382 ADVERTISED_10baseT_Full |
8383 ADVERTISED_100baseT_Half |
8384 ADVERTISED_100baseT_Full |
8385 ADVERTISED_1000baseT_Half |
8386 ADVERTISED_1000baseT_Full |
8387 ADVERTISED_10000baseT_Full |
8388 ADVERTISED_Autoneg);
8389 lp->speed = lp->active_speed = SPEED_INVALID;
8390 lp->duplex = DUPLEX_FULL;
8391 lp->active_duplex = DUPLEX_INVALID;
8394 lp->loopback_mode = LOOPBACK_MAC;
8395 lp->active_speed = SPEED_10000;
8396 lp->active_duplex = DUPLEX_FULL;
8398 lp->loopback_mode = LOOPBACK_DISABLED;
8402 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8406 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8407 np->ipp_off = 0x00000;
8408 np->pcs_off = 0x04000;
8409 np->xpcs_off = 0x02000;
8413 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8414 np->ipp_off = 0x08000;
8415 np->pcs_off = 0x0a000;
8416 np->xpcs_off = 0x08000;
8420 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8421 np->ipp_off = 0x04000;
8422 np->pcs_off = 0x0e000;
8423 np->xpcs_off = ~0UL;
8427 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8428 np->ipp_off = 0x0c000;
8429 np->pcs_off = 0x12000;
8430 np->xpcs_off = ~0UL;
8434 dev_err(np->device, PFX "Port %u is invalid, cannot "
8435 "compute MAC block offset.\n", np->port);
8442 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8444 struct msix_entry msi_vec[NIU_NUM_LDG];
8445 struct niu_parent *parent = np->parent;
8446 struct pci_dev *pdev = np->pdev;
8447 int i, num_irqs, err;
8450 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8451 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8452 ldg_num_map[i] = first_ldg + i;
8454 num_irqs = (parent->rxchan_per_port[np->port] +
8455 parent->txchan_per_port[np->port] +
8456 (np->port == 0 ? 3 : 1));
8457 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8460 for (i = 0; i < num_irqs; i++) {
8461 msi_vec[i].vector = 0;
8462 msi_vec[i].entry = i;
8465 err = pci_enable_msix(pdev, msi_vec, num_irqs);
8467 np->flags &= ~NIU_FLAGS_MSIX;
8475 np->flags |= NIU_FLAGS_MSIX;
8476 for (i = 0; i < num_irqs; i++)
8477 np->ldg[i].irq = msi_vec[i].vector;
8478 np->num_ldg = num_irqs;
8481 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8483 #ifdef CONFIG_SPARC64
8484 struct of_device *op = np->op;
8485 const u32 *int_prop;
8488 int_prop = of_get_property(op->node, "interrupts", NULL);
8492 for (i = 0; i < op->num_irqs; i++) {
8493 ldg_num_map[i] = int_prop[i];
8494 np->ldg[i].irq = op->irqs[i];
8497 np->num_ldg = op->num_irqs;
8505 static int __devinit niu_ldg_init(struct niu *np)
8507 struct niu_parent *parent = np->parent;
8508 u8 ldg_num_map[NIU_NUM_LDG];
8509 int first_chan, num_chan;
8510 int i, err, ldg_rotor;
8514 np->ldg[0].irq = np->dev->irq;
8515 if (parent->plat_type == PLAT_TYPE_NIU) {
8516 err = niu_n2_irq_init(np, ldg_num_map);
8520 niu_try_msix(np, ldg_num_map);
8523 for (i = 0; i < np->num_ldg; i++) {
8524 struct niu_ldg *lp = &np->ldg[i];
8526 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8529 lp->ldg_num = ldg_num_map[i];
8530 lp->timer = 2; /* XXX */
8532 /* On N2 NIU the firmware has setup the SID mappings so they go
8533 * to the correct values that will route the LDG to the proper
8534 * interrupt in the NCU interrupt table.
8536 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8537 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8543 /* We adopt the LDG assignment ordering used by the N2 NIU
8544 * 'interrupt' properties because that simplifies a lot of
8545 * things. This ordering is:
8548 * MIF (if port zero)
8549 * SYSERR (if port zero)
8556 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8562 if (ldg_rotor == np->num_ldg)
8566 err = niu_ldg_assign_ldn(np, parent,
8567 ldg_num_map[ldg_rotor],
8573 if (ldg_rotor == np->num_ldg)
8576 err = niu_ldg_assign_ldn(np, parent,
8577 ldg_num_map[ldg_rotor],
8583 if (ldg_rotor == np->num_ldg)
8589 for (i = 0; i < port; i++)
8590 first_chan += parent->rxchan_per_port[port];
8591 num_chan = parent->rxchan_per_port[port];
8593 for (i = first_chan; i < (first_chan + num_chan); i++) {
8594 err = niu_ldg_assign_ldn(np, parent,
8595 ldg_num_map[ldg_rotor],
8600 if (ldg_rotor == np->num_ldg)
8605 for (i = 0; i < port; i++)
8606 first_chan += parent->txchan_per_port[port];
8607 num_chan = parent->txchan_per_port[port];
8608 for (i = first_chan; i < (first_chan + num_chan); i++) {
8609 err = niu_ldg_assign_ldn(np, parent,
8610 ldg_num_map[ldg_rotor],
8615 if (ldg_rotor == np->num_ldg)
8622 static void __devexit niu_ldg_free(struct niu *np)
8624 if (np->flags & NIU_FLAGS_MSIX)
8625 pci_disable_msix(np->pdev);
8628 static int __devinit niu_get_of_props(struct niu *np)
8630 #ifdef CONFIG_SPARC64
8631 struct net_device *dev = np->dev;
8632 struct device_node *dp;
8633 const char *phy_type;
8638 if (np->parent->plat_type == PLAT_TYPE_NIU)
8641 dp = pci_device_to_OF_node(np->pdev);
8643 phy_type = of_get_property(dp, "phy-type", &prop_len);
8645 dev_err(np->device, PFX "%s: OF node lacks "
8646 "phy-type property\n",
8651 if (!strcmp(phy_type, "none"))
8654 strcpy(np->vpd.phy_type, phy_type);
8656 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8657 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8658 dp->full_name, np->vpd.phy_type);
8662 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8664 dev_err(np->device, PFX "%s: OF node lacks "
8665 "local-mac-address property\n",
8669 if (prop_len != dev->addr_len) {
8670 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8672 dp->full_name, prop_len);
8674 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8675 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8678 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8680 dev_err(np->device, PFX "%s: [ \n",
8682 for (i = 0; i < 6; i++)
8683 printk("%02x ", dev->perm_addr[i]);
8688 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8690 model = of_get_property(dp, "model", &prop_len);
8693 strcpy(np->vpd.model, model);
8701 static int __devinit niu_get_invariants(struct niu *np)
8703 int err, have_props;
8706 err = niu_get_of_props(np);
8712 err = niu_init_mac_ipp_pcs_base(np);
8717 err = niu_get_and_validate_port(np);
8722 if (np->parent->plat_type == PLAT_TYPE_NIU)
8725 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8726 offset = niu_pci_vpd_offset(np);
8727 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8730 niu_pci_vpd_fetch(np, offset);
8731 nw64(ESPC_PIO_EN, 0);
8733 if (np->flags & NIU_FLAGS_VPD_VALID) {
8734 niu_pci_vpd_validate(np);
8735 err = niu_get_and_validate_port(np);
8740 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8741 err = niu_get_and_validate_port(np);
8744 err = niu_pci_probe_sprom(np);
8750 err = niu_probe_ports(np);
8756 niu_classifier_swstate_init(np);
8757 niu_link_config_init(np);
8759 err = niu_determine_phy_disposition(np);
8761 err = niu_init_link(np);
8766 static LIST_HEAD(niu_parent_list);
8767 static DEFINE_MUTEX(niu_parent_lock);
8768 static int niu_parent_index;
8770 static ssize_t show_port_phy(struct device *dev,
8771 struct device_attribute *attr, char *buf)
8773 struct platform_device *plat_dev = to_platform_device(dev);
8774 struct niu_parent *p = plat_dev->dev.platform_data;
8775 u32 port_phy = p->port_phy;
8776 char *orig_buf = buf;
8779 if (port_phy == PORT_PHY_UNKNOWN ||
8780 port_phy == PORT_PHY_INVALID)
8783 for (i = 0; i < p->num_ports; i++) {
8784 const char *type_str;
8787 type = phy_decode(port_phy, i);
8788 if (type == PORT_TYPE_10G)
8793 (i == 0) ? "%s" : " %s",
8796 buf += sprintf(buf, "\n");
8797 return buf - orig_buf;
8800 static ssize_t show_plat_type(struct device *dev,
8801 struct device_attribute *attr, char *buf)
8803 struct platform_device *plat_dev = to_platform_device(dev);
8804 struct niu_parent *p = plat_dev->dev.platform_data;
8805 const char *type_str;
8807 switch (p->plat_type) {
8808 case PLAT_TYPE_ATLAS:
8814 case PLAT_TYPE_VF_P0:
8817 case PLAT_TYPE_VF_P1:
8821 type_str = "unknown";
8825 return sprintf(buf, "%s\n", type_str);
8828 static ssize_t __show_chan_per_port(struct device *dev,
8829 struct device_attribute *attr, char *buf,
8832 struct platform_device *plat_dev = to_platform_device(dev);
8833 struct niu_parent *p = plat_dev->dev.platform_data;
8834 char *orig_buf = buf;
8838 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8840 for (i = 0; i < p->num_ports; i++) {
8842 (i == 0) ? "%d" : " %d",
8845 buf += sprintf(buf, "\n");
8847 return buf - orig_buf;
8850 static ssize_t show_rxchan_per_port(struct device *dev,
8851 struct device_attribute *attr, char *buf)
8853 return __show_chan_per_port(dev, attr, buf, 1);
8856 static ssize_t show_txchan_per_port(struct device *dev,
8857 struct device_attribute *attr, char *buf)
8859 return __show_chan_per_port(dev, attr, buf, 1);
8862 static ssize_t show_num_ports(struct device *dev,
8863 struct device_attribute *attr, char *buf)
8865 struct platform_device *plat_dev = to_platform_device(dev);
8866 struct niu_parent *p = plat_dev->dev.platform_data;
8868 return sprintf(buf, "%d\n", p->num_ports);
8871 static struct device_attribute niu_parent_attributes[] = {
8872 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8873 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8874 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8875 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8876 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8880 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8881 union niu_parent_id *id,
8884 struct platform_device *plat_dev;
8885 struct niu_parent *p;
8888 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8890 plat_dev = platform_device_register_simple("niu", niu_parent_index,
8895 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8896 int err = device_create_file(&plat_dev->dev,
8897 &niu_parent_attributes[i]);
8899 goto fail_unregister;
8902 p = kzalloc(sizeof(*p), GFP_KERNEL);
8904 goto fail_unregister;
8906 p->index = niu_parent_index++;
8908 plat_dev->dev.platform_data = p;
8909 p->plat_dev = plat_dev;
8911 memcpy(&p->id, id, sizeof(*id));
8912 p->plat_type = ptype;
8913 INIT_LIST_HEAD(&p->list);
8914 atomic_set(&p->refcnt, 0);
8915 list_add(&p->list, &niu_parent_list);
8916 spin_lock_init(&p->lock);
8918 p->rxdma_clock_divider = 7500;
8920 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8921 if (p->plat_type == PLAT_TYPE_NIU)
8922 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8924 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8925 int index = i - CLASS_CODE_USER_PROG1;
8927 p->tcam_key[index] = TCAM_KEY_TSEL;
8928 p->flow_key[index] = (FLOW_KEY_IPSA |
8931 (FLOW_KEY_L4_BYTE12 <<
8932 FLOW_KEY_L4_0_SHIFT) |
8933 (FLOW_KEY_L4_BYTE12 <<
8934 FLOW_KEY_L4_1_SHIFT));
8937 for (i = 0; i < LDN_MAX + 1; i++)
8938 p->ldg_map[i] = LDG_INVALID;
8943 platform_device_unregister(plat_dev);
8947 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8948 union niu_parent_id *id,
8951 struct niu_parent *p, *tmp;
8952 int port = np->port;
8954 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8957 mutex_lock(&niu_parent_lock);
8959 list_for_each_entry(tmp, &niu_parent_list, list) {
8960 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8966 p = niu_new_parent(np, id, ptype);
8972 sprintf(port_name, "port%d", port);
8973 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8977 p->ports[port] = np;
8978 atomic_inc(&p->refcnt);
8981 mutex_unlock(&niu_parent_lock);
8986 static void niu_put_parent(struct niu *np)
8988 struct niu_parent *p = np->parent;
8992 BUG_ON(!p || p->ports[port] != np);
8994 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8996 sprintf(port_name, "port%d", port);
8998 mutex_lock(&niu_parent_lock);
9000 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9002 p->ports[port] = NULL;
9005 if (atomic_dec_and_test(&p->refcnt)) {
9007 platform_device_unregister(p->plat_dev);
9010 mutex_unlock(&niu_parent_lock);
9013 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9014 u64 *handle, gfp_t flag)
9019 ret = dma_alloc_coherent(dev, size, &dh, flag);
9025 static void niu_pci_free_coherent(struct device *dev, size_t size,
9026 void *cpu_addr, u64 handle)
9028 dma_free_coherent(dev, size, cpu_addr, handle);
9031 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9032 unsigned long offset, size_t size,
9033 enum dma_data_direction direction)
9035 return dma_map_page(dev, page, offset, size, direction);
9038 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9039 size_t size, enum dma_data_direction direction)
9041 dma_unmap_page(dev, dma_address, size, direction);
9044 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9046 enum dma_data_direction direction)
9048 return dma_map_single(dev, cpu_addr, size, direction);
9051 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9053 enum dma_data_direction direction)
9055 dma_unmap_single(dev, dma_address, size, direction);
9058 static const struct niu_ops niu_pci_ops = {
9059 .alloc_coherent = niu_pci_alloc_coherent,
9060 .free_coherent = niu_pci_free_coherent,
9061 .map_page = niu_pci_map_page,
9062 .unmap_page = niu_pci_unmap_page,
9063 .map_single = niu_pci_map_single,
9064 .unmap_single = niu_pci_unmap_single,
9067 static void __devinit niu_driver_version(void)
9069 static int niu_version_printed;
9071 if (niu_version_printed++ == 0)
9072 pr_info("%s", version);
9075 static struct net_device * __devinit niu_alloc_and_init(
9076 struct device *gen_dev, struct pci_dev *pdev,
9077 struct of_device *op, const struct niu_ops *ops,
9080 struct net_device *dev;
9083 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9085 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
9089 SET_NETDEV_DEV(dev, gen_dev);
9091 np = netdev_priv(dev);
9095 np->device = gen_dev;
9098 np->msg_enable = niu_debug;
9100 spin_lock_init(&np->lock);
9101 INIT_WORK(&np->reset_task, niu_reset_task);
9108 static const struct net_device_ops niu_netdev_ops = {
9109 .ndo_open = niu_open,
9110 .ndo_stop = niu_close,
9111 .ndo_start_xmit = niu_start_xmit,
9112 .ndo_get_stats = niu_get_stats,
9113 .ndo_set_multicast_list = niu_set_rx_mode,
9114 .ndo_validate_addr = eth_validate_addr,
9115 .ndo_set_mac_address = niu_set_mac_addr,
9116 .ndo_do_ioctl = niu_ioctl,
9117 .ndo_tx_timeout = niu_tx_timeout,
9118 .ndo_change_mtu = niu_change_mtu,
9121 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9123 dev->netdev_ops = &niu_netdev_ops;
9124 dev->ethtool_ops = &niu_ethtool_ops;
9125 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9128 static void __devinit niu_device_announce(struct niu *np)
9130 struct net_device *dev = np->dev;
9132 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9134 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9135 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9137 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9138 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9139 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9140 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9141 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9144 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9146 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9147 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9148 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9149 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9151 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9152 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9157 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9158 const struct pci_device_id *ent)
9160 union niu_parent_id parent_id;
9161 struct net_device *dev;
9167 niu_driver_version();
9169 err = pci_enable_device(pdev);
9171 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9176 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9177 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9178 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9179 "base addresses, aborting.\n");
9181 goto err_out_disable_pdev;
9184 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9186 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9188 goto err_out_disable_pdev;
9191 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9193 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9195 goto err_out_free_res;
9198 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9199 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9202 goto err_out_free_res;
9204 np = netdev_priv(dev);
9206 memset(&parent_id, 0, sizeof(parent_id));
9207 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9208 parent_id.pci.bus = pdev->bus->number;
9209 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9211 np->parent = niu_get_parent(np, &parent_id,
9215 goto err_out_free_dev;
9218 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9219 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9220 val16 |= (PCI_EXP_DEVCTL_CERE |
9221 PCI_EXP_DEVCTL_NFERE |
9222 PCI_EXP_DEVCTL_FERE |
9223 PCI_EXP_DEVCTL_URRE |
9224 PCI_EXP_DEVCTL_RELAX_EN);
9225 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9227 dma_mask = DMA_44BIT_MASK;
9228 err = pci_set_dma_mask(pdev, dma_mask);
9230 dev->features |= NETIF_F_HIGHDMA;
9231 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9233 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9234 "DMA for consistent allocations, "
9236 goto err_out_release_parent;
9239 if (err || dma_mask == DMA_32BIT_MASK) {
9240 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9242 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9244 goto err_out_release_parent;
9248 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9250 np->regs = pci_ioremap_bar(pdev, 0);
9252 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9255 goto err_out_release_parent;
9258 pci_set_master(pdev);
9259 pci_save_state(pdev);
9261 dev->irq = pdev->irq;
9263 niu_assign_netdev_ops(dev);
9265 err = niu_get_invariants(np);
9268 dev_err(&pdev->dev, PFX "Problem fetching invariants "
9269 "of chip, aborting.\n");
9270 goto err_out_iounmap;
9273 err = register_netdev(dev);
9275 dev_err(&pdev->dev, PFX "Cannot register net device, "
9277 goto err_out_iounmap;
9280 pci_set_drvdata(pdev, dev);
9282 niu_device_announce(np);
9292 err_out_release_parent:
9299 pci_release_regions(pdev);
9301 err_out_disable_pdev:
9302 pci_disable_device(pdev);
9303 pci_set_drvdata(pdev, NULL);
9308 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9310 struct net_device *dev = pci_get_drvdata(pdev);
9313 struct niu *np = netdev_priv(dev);
9315 unregister_netdev(dev);
9326 pci_release_regions(pdev);
9327 pci_disable_device(pdev);
9328 pci_set_drvdata(pdev, NULL);
9332 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9334 struct net_device *dev = pci_get_drvdata(pdev);
9335 struct niu *np = netdev_priv(dev);
9336 unsigned long flags;
9338 if (!netif_running(dev))
9341 flush_scheduled_work();
9344 del_timer_sync(&np->timer);
9346 spin_lock_irqsave(&np->lock, flags);
9347 niu_enable_interrupts(np, 0);
9348 spin_unlock_irqrestore(&np->lock, flags);
9350 netif_device_detach(dev);
9352 spin_lock_irqsave(&np->lock, flags);
9354 spin_unlock_irqrestore(&np->lock, flags);
9356 pci_save_state(pdev);
9361 static int niu_resume(struct pci_dev *pdev)
9363 struct net_device *dev = pci_get_drvdata(pdev);
9364 struct niu *np = netdev_priv(dev);
9365 unsigned long flags;
9368 if (!netif_running(dev))
9371 pci_restore_state(pdev);
9373 netif_device_attach(dev);
9375 spin_lock_irqsave(&np->lock, flags);
9377 err = niu_init_hw(np);
9379 np->timer.expires = jiffies + HZ;
9380 add_timer(&np->timer);
9381 niu_netif_start(np);
9384 spin_unlock_irqrestore(&np->lock, flags);
9389 static struct pci_driver niu_pci_driver = {
9390 .name = DRV_MODULE_NAME,
9391 .id_table = niu_pci_tbl,
9392 .probe = niu_pci_init_one,
9393 .remove = __devexit_p(niu_pci_remove_one),
9394 .suspend = niu_suspend,
9395 .resume = niu_resume,
9398 #ifdef CONFIG_SPARC64
9399 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9400 u64 *dma_addr, gfp_t flag)
9402 unsigned long order = get_order(size);
9403 unsigned long page = __get_free_pages(flag, order);
9407 memset((char *)page, 0, PAGE_SIZE << order);
9408 *dma_addr = __pa(page);
9410 return (void *) page;
9413 static void niu_phys_free_coherent(struct device *dev, size_t size,
9414 void *cpu_addr, u64 handle)
9416 unsigned long order = get_order(size);
9418 free_pages((unsigned long) cpu_addr, order);
9421 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9422 unsigned long offset, size_t size,
9423 enum dma_data_direction direction)
9425 return page_to_phys(page) + offset;
9428 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9429 size_t size, enum dma_data_direction direction)
9431 /* Nothing to do. */
9434 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9436 enum dma_data_direction direction)
9438 return __pa(cpu_addr);
9441 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9443 enum dma_data_direction direction)
9445 /* Nothing to do. */
9448 static const struct niu_ops niu_phys_ops = {
9449 .alloc_coherent = niu_phys_alloc_coherent,
9450 .free_coherent = niu_phys_free_coherent,
9451 .map_page = niu_phys_map_page,
9452 .unmap_page = niu_phys_unmap_page,
9453 .map_single = niu_phys_map_single,
9454 .unmap_single = niu_phys_unmap_single,
9457 static unsigned long res_size(struct resource *r)
9459 return r->end - r->start + 1UL;
9462 static int __devinit niu_of_probe(struct of_device *op,
9463 const struct of_device_id *match)
9465 union niu_parent_id parent_id;
9466 struct net_device *dev;
9471 niu_driver_version();
9473 reg = of_get_property(op->node, "reg", NULL);
9475 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9476 op->node->full_name);
9480 dev = niu_alloc_and_init(&op->dev, NULL, op,
9481 &niu_phys_ops, reg[0] & 0x1);
9486 np = netdev_priv(dev);
9488 memset(&parent_id, 0, sizeof(parent_id));
9489 parent_id.of = of_get_parent(op->node);
9491 np->parent = niu_get_parent(np, &parent_id,
9495 goto err_out_free_dev;
9498 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9500 np->regs = of_ioremap(&op->resource[1], 0,
9501 res_size(&op->resource[1]),
9504 dev_err(&op->dev, PFX "Cannot map device registers, "
9507 goto err_out_release_parent;
9510 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9511 res_size(&op->resource[2]),
9513 if (!np->vir_regs_1) {
9514 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9517 goto err_out_iounmap;
9520 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9521 res_size(&op->resource[3]),
9523 if (!np->vir_regs_2) {
9524 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9527 goto err_out_iounmap;
9530 niu_assign_netdev_ops(dev);
9532 err = niu_get_invariants(np);
9535 dev_err(&op->dev, PFX "Problem fetching invariants "
9536 "of chip, aborting.\n");
9537 goto err_out_iounmap;
9540 err = register_netdev(dev);
9542 dev_err(&op->dev, PFX "Cannot register net device, "
9544 goto err_out_iounmap;
9547 dev_set_drvdata(&op->dev, dev);
9549 niu_device_announce(np);
9554 if (np->vir_regs_1) {
9555 of_iounmap(&op->resource[2], np->vir_regs_1,
9556 res_size(&op->resource[2]));
9557 np->vir_regs_1 = NULL;
9560 if (np->vir_regs_2) {
9561 of_iounmap(&op->resource[3], np->vir_regs_2,
9562 res_size(&op->resource[3]));
9563 np->vir_regs_2 = NULL;
9567 of_iounmap(&op->resource[1], np->regs,
9568 res_size(&op->resource[1]));
9572 err_out_release_parent:
9582 static int __devexit niu_of_remove(struct of_device *op)
9584 struct net_device *dev = dev_get_drvdata(&op->dev);
9587 struct niu *np = netdev_priv(dev);
9589 unregister_netdev(dev);
9591 if (np->vir_regs_1) {
9592 of_iounmap(&op->resource[2], np->vir_regs_1,
9593 res_size(&op->resource[2]));
9594 np->vir_regs_1 = NULL;
9597 if (np->vir_regs_2) {
9598 of_iounmap(&op->resource[3], np->vir_regs_2,
9599 res_size(&op->resource[3]));
9600 np->vir_regs_2 = NULL;
9604 of_iounmap(&op->resource[1], np->regs,
9605 res_size(&op->resource[1]));
9614 dev_set_drvdata(&op->dev, NULL);
9619 static const struct of_device_id niu_match[] = {
9622 .compatible = "SUNW,niusl",
9626 MODULE_DEVICE_TABLE(of, niu_match);
9628 static struct of_platform_driver niu_of_driver = {
9630 .match_table = niu_match,
9631 .probe = niu_of_probe,
9632 .remove = __devexit_p(niu_of_remove),
9635 #endif /* CONFIG_SPARC64 */
9637 static int __init niu_init(void)
9641 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
9643 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9645 #ifdef CONFIG_SPARC64
9646 err = of_register_driver(&niu_of_driver, &of_bus_type);
9650 err = pci_register_driver(&niu_pci_driver);
9651 #ifdef CONFIG_SPARC64
9653 of_unregister_driver(&niu_of_driver);
9660 static void __exit niu_exit(void)
9662 pci_unregister_driver(&niu_pci_driver);
9663 #ifdef CONFIG_SPARC64
9664 of_unregister_driver(&niu_of_driver);
9668 module_init(niu_init);
9669 module_exit(niu_exit);