1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "1.0"
37 #define DRV_MODULE_RELDATE "Nov 14, 2008"
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64 readq(void __iomem *reg)
54 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
57 static void writeq(u64 val, void __iomem *reg)
59 writel(val & 0xffffffff, reg);
60 writel(val >> 32, reg + 0x4UL);
64 static struct pci_device_id niu_pci_tbl[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71 #define NIU_TX_TIMEOUT (5 * HZ)
73 #define nr64(reg) readq(np->regs + (reg))
74 #define nw64(reg, val) writeq((val), np->regs + (reg))
76 #define nr64_mac(reg) readq(np->mac_regs + (reg))
77 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91 static int debug = -1;
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "NIU debug level");
95 #define niudbg(TYPE, f, a...) \
96 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
100 #define niuinfo(TYPE, f, a...) \
101 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
105 #define niuwarn(TYPE, f, a...) \
106 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
110 #define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112 #define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
115 static int serdes_init_10g_serdes(struct niu *np);
117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118 u64 bits, int limit, int delay)
120 while (--limit >= 0) {
121 u64 val = nr64_mac(reg);
132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133 u64 bits, int limit, int delay,
134 const char *reg_name)
139 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
141 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np->dev->name, (unsigned long long) bits, reg_name,
144 (unsigned long long) nr64_mac(reg));
148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154 u64 bits, int limit, int delay)
156 while (--limit >= 0) {
157 u64 val = nr64_ipp(reg);
168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169 u64 bits, int limit, int delay,
170 const char *reg_name)
179 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
181 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np->dev->name, (unsigned long long) bits, reg_name,
184 (unsigned long long) nr64_ipp(reg));
188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay)
196 while (--limit >= 0) {
208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214 u64 bits, int limit, int delay,
215 const char *reg_name)
220 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np->dev->name, (unsigned long long) bits, reg_name,
225 (unsigned long long) nr64(reg));
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
236 u64 val = (u64) lp->timer;
239 val |= LDG_IMGMT_ARM;
241 nw64(LDG_IMGMT(lp->ldg_num), val);
244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
246 unsigned long mask_reg, bits;
249 if (ldn < 0 || ldn > LDN_MAX)
253 mask_reg = LD_IM0(ldn);
256 mask_reg = LD_IM1(ldn - 64);
260 val = nr64(mask_reg);
270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
272 struct niu_parent *parent = np->parent;
275 for (i = 0; i <= LDN_MAX; i++) {
278 if (parent->ldg_map[i] != lp->ldg_num)
281 err = niu_ldn_irq_enable(np, i, on);
288 static int niu_enable_interrupts(struct niu *np, int on)
292 for (i = 0; i < np->num_ldg; i++) {
293 struct niu_ldg *lp = &np->ldg[i];
296 err = niu_enable_ldn_in_ldg(np, lp, on);
300 for (i = 0; i < np->num_ldg; i++)
301 niu_ldg_rearm(np, &np->ldg[i], on);
306 static u32 phy_encode(u32 type, int port)
308 return (type << (port * 2));
311 static u32 phy_decode(u32 val, int port)
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
316 static int mdio_wait(struct niu *np)
321 while (--limit > 0) {
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
332 static int mdio_read(struct niu *np, int port, int dev, int reg)
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342 return mdio_wait(np);
345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
362 static int mii_read(struct niu *np, int port, int reg)
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365 return mdio_wait(np);
368 static int mii_write(struct niu *np, int port, int reg, int data)
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385 ESR2_TI_PLL_TX_CFG_L(channel),
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389 ESR2_TI_PLL_TX_CFG_H(channel),
394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399 ESR2_TI_PLL_RX_CFG_L(channel),
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_RX_CFG_H(channel),
408 /* Mode is always 10G fiber. */
409 static int serdes_init_niu_10g_fiber(struct niu *np)
411 struct niu_link_config *lp = &np->link_config;
415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418 PLL_RX_CFG_EQ_LP_ADAPTIVE);
420 if (lp->loopback_mode == LOOPBACK_PHY) {
421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
426 tx_cfg |= PLL_TX_CFG_ENTEST;
427 rx_cfg |= PLL_RX_CFG_ENTEST;
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i = 0; i < 4; i++) {
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
437 for (i = 0; i < 4; i++) {
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
446 static int serdes_init_niu_1g_serdes(struct niu *np)
448 struct niu_link_config *lp = &np->link_config;
449 u16 pll_cfg, pll_sts;
451 u64 uninitialized_var(sig), mask, val;
456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457 PLL_TX_CFG_RATE_HALF);
458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460 PLL_RX_CFG_RATE_HALF);
463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
465 if (lp->loopback_mode == LOOPBACK_PHY) {
466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
471 tx_cfg |= PLL_TX_CFG_ENTEST;
472 rx_cfg |= PLL_RX_CFG_ENTEST;
475 /* Initialize PLL for 1G */
476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479 ESR2_TI_PLL_CFG_L, pll_cfg);
481 dev_err(np->device, PFX "NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
487 pll_sts = PLL_CFG_ENPLL;
489 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 ESR2_TI_PLL_STS_L, pll_sts);
492 dev_err(np->device, PFX "NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i = 0; i < 4; i++) {
502 err = esr2_set_tx_cfg(np, i, tx_cfg);
507 for (i = 0; i < 4; i++) {
508 err = esr2_set_rx_cfg(np, i, rx_cfg);
515 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
520 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
528 while (max_retry--) {
529 sig = nr64(ESR_INT_SIGNALS);
530 if ((sig & mask) == val)
536 if ((sig & mask) != val) {
537 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
545 static int serdes_init_niu_10g_serdes(struct niu *np)
547 struct niu_link_config *lp = &np->link_config;
548 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
550 u64 uninitialized_var(sig), mask, val;
554 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557 PLL_RX_CFG_EQ_LP_ADAPTIVE);
559 if (lp->loopback_mode == LOOPBACK_PHY) {
560 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
562 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
565 tx_cfg |= PLL_TX_CFG_ENTEST;
566 rx_cfg |= PLL_RX_CFG_ENTEST;
569 /* Initialize PLL for 10G */
570 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
572 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
575 dev_err(np->device, PFX "NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
581 pll_sts = PLL_CFG_ENPLL;
583 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
586 dev_err(np->device, PFX "NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i = 0; i < 4; i++) {
596 err = esr2_set_tx_cfg(np, i, tx_cfg);
601 for (i = 0; i < 4; i++) {
602 err = esr2_set_rx_cfg(np, i, rx_cfg);
607 /* check if serdes is ready */
611 mask = ESR_INT_SIGNALS_P0_BITS;
612 val = (ESR_INT_SRDY0_P0 |
622 mask = ESR_INT_SIGNALS_P1_BITS;
623 val = (ESR_INT_SRDY0_P1 |
636 while (max_retry--) {
637 sig = nr64(ESR_INT_SIGNALS);
638 if ((sig & mask) == val)
644 if ((sig & mask) != val) {
645 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np->port, (int) (sig & mask), (int) val);
649 /* 10G failed, try initializing at 1G */
650 err = serdes_init_niu_1g_serdes(np);
652 np->flags &= ~NIU_FLAGS_10G;
653 np->mac_xcvr = MAC_XCVR_PCS;
655 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656 "Link Failed \n", np->port);
663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
667 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
669 *val = (err & 0xffff);
670 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671 ESR_RXTX_CTRL_H(chan));
673 *val |= ((err & 0xffff) << 16);
679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
683 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 ESR_GLUE_CTRL0_L(chan));
686 *val = (err & 0xffff);
687 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688 ESR_GLUE_CTRL0_H(chan));
690 *val |= ((err & 0xffff) << 16);
697 static int esr_read_reset(struct niu *np, u32 *val)
701 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 ESR_RXTX_RESET_CTRL_L);
704 *val = (err & 0xffff);
705 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_RXTX_RESET_CTRL_H);
708 *val |= ((err & 0xffff) << 16);
715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_CTRL_L(chan), val & 0xffff);
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_CTRL_H(chan), (val >> 16));
727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
731 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_GLUE_CTRL0_H(chan), (val >> 16));
739 static int esr_reset(struct niu *np)
741 u32 uninitialized_var(reset);
744 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 ESR_RXTX_RESET_CTRL_L, 0x0000);
748 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 ESR_RXTX_RESET_CTRL_H, 0xffff);
754 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 ESR_RXTX_RESET_CTRL_L, 0xffff);
760 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761 ESR_RXTX_RESET_CTRL_H, 0x0000);
766 err = esr_read_reset(np, &reset);
770 dev_err(np->device, PFX "Port %u ESR_RESET "
771 "did not clear [%08x]\n",
779 static int serdes_init_10g(struct niu *np)
781 struct niu_link_config *lp = &np->link_config;
782 unsigned long ctrl_reg, test_cfg_reg, i;
783 u64 ctrl_val, test_cfg_val, sig, mask, val;
788 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
792 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
799 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800 ENET_SERDES_CTRL_SDET_1 |
801 ENET_SERDES_CTRL_SDET_2 |
802 ENET_SERDES_CTRL_SDET_3 |
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
813 if (lp->loopback_mode == LOOPBACK_PHY) {
814 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815 ENET_SERDES_TEST_MD_0_SHIFT) |
816 (ENET_TEST_MD_PAD_LOOPBACK <<
817 ENET_SERDES_TEST_MD_1_SHIFT) |
818 (ENET_TEST_MD_PAD_LOOPBACK <<
819 ENET_SERDES_TEST_MD_2_SHIFT) |
820 (ENET_TEST_MD_PAD_LOOPBACK <<
821 ENET_SERDES_TEST_MD_3_SHIFT));
824 nw64(ctrl_reg, ctrl_val);
825 nw64(test_cfg_reg, test_cfg_val);
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i = 0; i < 4; i++) {
829 u32 rxtx_ctrl, glue0;
831 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
834 err = esr_read_glue0(np, i, &glue0);
838 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
842 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843 ESR_GLUE_CTRL0_THCNT |
844 ESR_GLUE_CTRL0_BLTIME);
845 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848 (BLTIME_300_CYCLES <<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT));
851 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
854 err = esr_write_glue0(np, i, glue0);
863 sig = nr64(ESR_INT_SIGNALS);
866 mask = ESR_INT_SIGNALS_P0_BITS;
867 val = (ESR_INT_SRDY0_P0 |
877 mask = ESR_INT_SIGNALS_P1_BITS;
878 val = (ESR_INT_SRDY0_P1 |
891 if ((sig & mask) != val) {
892 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
896 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
900 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
905 static int serdes_init_1g(struct niu *np)
909 val = nr64(ENET_SERDES_1_PLL_CFG);
910 val &= ~ENET_SERDES_PLL_FBDIV2;
913 val |= ENET_SERDES_PLL_HRATE0;
916 val |= ENET_SERDES_PLL_HRATE1;
919 val |= ENET_SERDES_PLL_HRATE2;
922 val |= ENET_SERDES_PLL_HRATE3;
927 nw64(ENET_SERDES_1_PLL_CFG, val);
932 static int serdes_init_1g_serdes(struct niu *np)
934 struct niu_link_config *lp = &np->link_config;
935 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936 u64 ctrl_val, test_cfg_val, sig, mask, val;
938 u64 reset_val, val_rd;
940 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942 ENET_SERDES_PLL_FBDIV0;
945 reset_val = ENET_SERDES_RESET_0;
946 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948 pll_cfg = ENET_SERDES_0_PLL_CFG;
951 reset_val = ENET_SERDES_RESET_1;
952 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954 pll_cfg = ENET_SERDES_1_PLL_CFG;
960 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961 ENET_SERDES_CTRL_SDET_1 |
962 ENET_SERDES_CTRL_SDET_2 |
963 ENET_SERDES_CTRL_SDET_3 |
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
974 if (lp->loopback_mode == LOOPBACK_PHY) {
975 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976 ENET_SERDES_TEST_MD_0_SHIFT) |
977 (ENET_TEST_MD_PAD_LOOPBACK <<
978 ENET_SERDES_TEST_MD_1_SHIFT) |
979 (ENET_TEST_MD_PAD_LOOPBACK <<
980 ENET_SERDES_TEST_MD_2_SHIFT) |
981 (ENET_TEST_MD_PAD_LOOPBACK <<
982 ENET_SERDES_TEST_MD_3_SHIFT));
985 nw64(ENET_SERDES_RESET, reset_val);
987 val_rd = nr64(ENET_SERDES_RESET);
988 val_rd &= ~reset_val;
990 nw64(ctrl_reg, ctrl_val);
991 nw64(test_cfg_reg, test_cfg_val);
992 nw64(ENET_SERDES_RESET, val_rd);
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i = 0; i < 4; i++) {
997 u32 rxtx_ctrl, glue0;
999 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1002 err = esr_read_glue0(np, i, &glue0);
1006 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1010 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011 ESR_GLUE_CTRL0_THCNT |
1012 ESR_GLUE_CTRL0_BLTIME);
1013 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016 (BLTIME_300_CYCLES <<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1019 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1022 err = esr_write_glue0(np, i, glue0);
1028 sig = nr64(ESR_INT_SIGNALS);
1031 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1036 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1044 if ((sig & mask) != val) {
1045 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1055 struct niu_link_config *lp = &np->link_config;
1059 unsigned long flags;
1063 current_speed = SPEED_INVALID;
1064 current_duplex = DUPLEX_INVALID;
1066 spin_lock_irqsave(&np->lock, flags);
1068 val = nr64_pcs(PCS_MII_STAT);
1070 if (val & PCS_MII_STAT_LINK_STATUS) {
1072 current_speed = SPEED_1000;
1073 current_duplex = DUPLEX_FULL;
1076 lp->active_speed = current_speed;
1077 lp->active_duplex = current_duplex;
1078 spin_unlock_irqrestore(&np->lock, flags);
1080 *link_up_p = link_up;
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1086 unsigned long flags;
1087 struct niu_link_config *lp = &np->link_config;
1094 if (!(np->flags & NIU_FLAGS_10G))
1095 return link_status_1g_serdes(np, link_up_p);
1097 current_speed = SPEED_INVALID;
1098 current_duplex = DUPLEX_INVALID;
1099 spin_lock_irqsave(&np->lock, flags);
1101 val = nr64_xpcs(XPCS_STATUS(0));
1102 val2 = nr64_mac(XMAC_INTER2);
1103 if (val2 & 0x01000000)
1106 if ((val & 0x1000ULL) && link_ok) {
1108 current_speed = SPEED_10000;
1109 current_duplex = DUPLEX_FULL;
1111 lp->active_speed = current_speed;
1112 lp->active_duplex = current_duplex;
1113 spin_unlock_irqrestore(&np->lock, flags);
1114 *link_up_p = link_up;
1118 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1120 struct niu_link_config *lp = &np->link_config;
1121 u16 current_speed, bmsr;
1122 unsigned long flags;
1127 current_speed = SPEED_INVALID;
1128 current_duplex = DUPLEX_INVALID;
1130 spin_lock_irqsave(&np->lock, flags);
1134 err = mii_read(np, np->phy_addr, MII_BMSR);
1139 if (bmsr & BMSR_LSTATUS) {
1140 u16 adv, lpa, common, estat;
1142 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1147 err = mii_read(np, np->phy_addr, MII_LPA);
1154 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1159 current_speed = SPEED_1000;
1160 current_duplex = DUPLEX_FULL;
1163 lp->active_speed = current_speed;
1164 lp->active_duplex = current_duplex;
1168 spin_unlock_irqrestore(&np->lock, flags);
1170 *link_up_p = link_up;
1174 static int bcm8704_reset(struct niu *np)
1178 err = mdio_read(np, np->phy_addr,
1179 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1183 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1189 while (--limit >= 0) {
1190 err = mdio_read(np, np->phy_addr,
1191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1194 if (!(err & BMCR_RESET))
1198 dev_err(np->device, PFX "Port %u PHY will not reset "
1199 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1205 /* When written, certain PHY registers need to be read back twice
1206 * in order for the bits to settle properly.
1208 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1210 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1213 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1219 static int bcm8706_init_user_dev3(struct niu *np)
1224 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1225 BCM8704_USER_OPT_DIGITAL_CTRL);
1228 err &= ~USER_ODIG_CTRL_GPIOS;
1229 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1230 err |= USER_ODIG_CTRL_RESV2;
1231 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1232 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1241 static int bcm8704_init_user_dev3(struct niu *np)
1245 err = mdio_write(np, np->phy_addr,
1246 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1247 (USER_CONTROL_OPTXRST_LVL |
1248 USER_CONTROL_OPBIASFLT_LVL |
1249 USER_CONTROL_OBTMPFLT_LVL |
1250 USER_CONTROL_OPPRFLT_LVL |
1251 USER_CONTROL_OPTXFLT_LVL |
1252 USER_CONTROL_OPRXLOS_LVL |
1253 USER_CONTROL_OPRXFLT_LVL |
1254 USER_CONTROL_OPTXON_LVL |
1255 (0x3f << USER_CONTROL_RES1_SHIFT)));
1259 err = mdio_write(np, np->phy_addr,
1260 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1261 (USER_PMD_TX_CTL_XFP_CLKEN |
1262 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1263 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1264 USER_PMD_TX_CTL_TSCK_LPWREN));
1268 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1271 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1275 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1276 BCM8704_USER_OPT_DIGITAL_CTRL);
1279 err &= ~USER_ODIG_CTRL_GPIOS;
1280 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1281 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1282 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1291 static int mrvl88x2011_act_led(struct niu *np, int val)
1295 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1296 MRVL88X2011_LED_8_TO_11_CTL);
1300 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1301 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1303 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1304 MRVL88X2011_LED_8_TO_11_CTL, err);
1307 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1311 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1312 MRVL88X2011_LED_BLINK_CTL);
1314 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1317 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1318 MRVL88X2011_LED_BLINK_CTL, err);
1324 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1328 /* Set LED functions */
1329 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1334 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1338 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1339 MRVL88X2011_GENERAL_CTL);
1343 err |= MRVL88X2011_ENA_XFPREFCLK;
1345 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1346 MRVL88X2011_GENERAL_CTL, err);
1350 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1351 MRVL88X2011_PMA_PMD_CTL_1);
1355 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1356 err |= MRVL88X2011_LOOPBACK;
1358 err &= ~MRVL88X2011_LOOPBACK;
1360 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1361 MRVL88X2011_PMA_PMD_CTL_1, err);
1366 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1367 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1371 static int xcvr_diag_bcm870x(struct niu *np)
1373 u16 analog_stat0, tx_alarm_status;
1377 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1381 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1384 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1387 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1390 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1394 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1398 /* XXX dig this out it might not be so useful XXX */
1399 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1400 BCM8704_USER_ANALOG_STATUS0);
1403 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1404 BCM8704_USER_ANALOG_STATUS0);
1409 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1410 BCM8704_USER_TX_ALARM_STATUS);
1413 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1414 BCM8704_USER_TX_ALARM_STATUS);
1417 tx_alarm_status = err;
1419 if (analog_stat0 != 0x03fc) {
1420 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1421 pr_info(PFX "Port %u cable not connected "
1422 "or bad cable.\n", np->port);
1423 } else if (analog_stat0 == 0x639c) {
1424 pr_info(PFX "Port %u optical module is bad "
1425 "or missing.\n", np->port);
1432 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1434 struct niu_link_config *lp = &np->link_config;
1437 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1442 err &= ~BMCR_LOOPBACK;
1444 if (lp->loopback_mode == LOOPBACK_MAC)
1445 err |= BMCR_LOOPBACK;
1447 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1455 static int xcvr_init_10g_bcm8706(struct niu *np)
1460 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1461 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1464 val = nr64_mac(XMAC_CONFIG);
1465 val &= ~XMAC_CONFIG_LED_POLARITY;
1466 val |= XMAC_CONFIG_FORCE_LED_ON;
1467 nw64_mac(XMAC_CONFIG, val);
1469 val = nr64(MIF_CONFIG);
1470 val |= MIF_CONFIG_INDIRECT_MODE;
1471 nw64(MIF_CONFIG, val);
1473 err = bcm8704_reset(np);
1477 err = xcvr_10g_set_lb_bcm870x(np);
1481 err = bcm8706_init_user_dev3(np);
1485 err = xcvr_diag_bcm870x(np);
1492 static int xcvr_init_10g_bcm8704(struct niu *np)
1496 err = bcm8704_reset(np);
1500 err = bcm8704_init_user_dev3(np);
1504 err = xcvr_10g_set_lb_bcm870x(np);
1508 err = xcvr_diag_bcm870x(np);
1515 static int xcvr_init_10g(struct niu *np)
1520 val = nr64_mac(XMAC_CONFIG);
1521 val &= ~XMAC_CONFIG_LED_POLARITY;
1522 val |= XMAC_CONFIG_FORCE_LED_ON;
1523 nw64_mac(XMAC_CONFIG, val);
1525 /* XXX shared resource, lock parent XXX */
1526 val = nr64(MIF_CONFIG);
1527 val |= MIF_CONFIG_INDIRECT_MODE;
1528 nw64(MIF_CONFIG, val);
1530 phy_id = phy_decode(np->parent->port_phy, np->port);
1531 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1533 /* handle different phy types */
1534 switch (phy_id & NIU_PHY_ID_MASK) {
1535 case NIU_PHY_ID_MRVL88X2011:
1536 err = xcvr_init_10g_mrvl88x2011(np);
1539 default: /* bcom 8704 */
1540 err = xcvr_init_10g_bcm8704(np);
1547 static int mii_reset(struct niu *np)
1551 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1556 while (--limit >= 0) {
1558 err = mii_read(np, np->phy_addr, MII_BMCR);
1561 if (!(err & BMCR_RESET))
1565 dev_err(np->device, PFX "Port %u MII would not reset, "
1566 "bmcr[%04x]\n", np->port, err);
1573 static int xcvr_init_1g_rgmii(struct niu *np)
1577 u16 bmcr, bmsr, estat;
1579 val = nr64(MIF_CONFIG);
1580 val &= ~MIF_CONFIG_INDIRECT_MODE;
1581 nw64(MIF_CONFIG, val);
1583 err = mii_reset(np);
1587 err = mii_read(np, np->phy_addr, MII_BMSR);
1593 if (bmsr & BMSR_ESTATEN) {
1594 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1601 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1605 if (bmsr & BMSR_ESTATEN) {
1608 if (estat & ESTATUS_1000_TFULL)
1609 ctrl1000 |= ADVERTISE_1000FULL;
1610 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1615 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1617 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1621 err = mii_read(np, np->phy_addr, MII_BMCR);
1624 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1626 err = mii_read(np, np->phy_addr, MII_BMSR);
1633 static int mii_init_common(struct niu *np)
1635 struct niu_link_config *lp = &np->link_config;
1636 u16 bmcr, bmsr, adv, estat;
1639 err = mii_reset(np);
1643 err = mii_read(np, np->phy_addr, MII_BMSR);
1649 if (bmsr & BMSR_ESTATEN) {
1650 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1657 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1661 if (lp->loopback_mode == LOOPBACK_MAC) {
1662 bmcr |= BMCR_LOOPBACK;
1663 if (lp->active_speed == SPEED_1000)
1664 bmcr |= BMCR_SPEED1000;
1665 if (lp->active_duplex == DUPLEX_FULL)
1666 bmcr |= BMCR_FULLDPLX;
1669 if (lp->loopback_mode == LOOPBACK_PHY) {
1672 aux = (BCM5464R_AUX_CTL_EXT_LB |
1673 BCM5464R_AUX_CTL_WRITE_1);
1674 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1679 /* XXX configurable XXX */
1680 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1681 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1682 if (bmsr & BMSR_10FULL)
1683 adv |= ADVERTISE_10FULL;
1684 if (bmsr & BMSR_100FULL)
1685 adv |= ADVERTISE_100FULL;
1686 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1690 if (bmsr & BMSR_ESTATEN) {
1693 if (estat & ESTATUS_1000_TFULL)
1694 ctrl1000 |= ADVERTISE_1000FULL;
1695 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1699 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1701 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1705 err = mii_read(np, np->phy_addr, MII_BMCR);
1708 err = mii_read(np, np->phy_addr, MII_BMSR);
1712 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1713 np->port, bmcr, bmsr);
1719 static int xcvr_init_1g(struct niu *np)
1723 /* XXX shared resource, lock parent XXX */
1724 val = nr64(MIF_CONFIG);
1725 val &= ~MIF_CONFIG_INDIRECT_MODE;
1726 nw64(MIF_CONFIG, val);
1728 return mii_init_common(np);
1731 static int niu_xcvr_init(struct niu *np)
1733 const struct niu_phy_ops *ops = np->phy_ops;
1738 err = ops->xcvr_init(np);
1743 static int niu_serdes_init(struct niu *np)
1745 const struct niu_phy_ops *ops = np->phy_ops;
1749 if (ops->serdes_init)
1750 err = ops->serdes_init(np);
1755 static void niu_init_xif(struct niu *);
1756 static void niu_handle_led(struct niu *, int status);
1758 static int niu_link_status_common(struct niu *np, int link_up)
1760 struct niu_link_config *lp = &np->link_config;
1761 struct net_device *dev = np->dev;
1762 unsigned long flags;
1764 if (!netif_carrier_ok(dev) && link_up) {
1765 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1767 (lp->active_speed == SPEED_10000 ?
1769 (lp->active_speed == SPEED_1000 ?
1771 (lp->active_speed == SPEED_100 ?
1772 "100Mbit/sec" : "10Mbit/sec"))),
1773 (lp->active_duplex == DUPLEX_FULL ?
1776 spin_lock_irqsave(&np->lock, flags);
1778 niu_handle_led(np, 1);
1779 spin_unlock_irqrestore(&np->lock, flags);
1781 netif_carrier_on(dev);
1782 } else if (netif_carrier_ok(dev) && !link_up) {
1783 niuwarn(LINK, "%s: Link is down\n", dev->name);
1784 spin_lock_irqsave(&np->lock, flags);
1785 niu_handle_led(np, 0);
1786 spin_unlock_irqrestore(&np->lock, flags);
1787 netif_carrier_off(dev);
1793 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1795 int err, link_up, pma_status, pcs_status;
1799 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1800 MRVL88X2011_10G_PMD_STATUS_2);
1804 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1805 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1806 MRVL88X2011_PMA_PMD_STATUS_1);
1810 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1812 /* Check PMC Register : 3.0001.2 == 1: read twice */
1813 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1814 MRVL88X2011_PMA_PMD_STATUS_1);
1818 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1819 MRVL88X2011_PMA_PMD_STATUS_1);
1823 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1825 /* Check XGXS Register : 4.0018.[0-3,12] */
1826 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1827 MRVL88X2011_10G_XGXS_LANE_STAT);
1831 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1832 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1833 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1835 link_up = (pma_status && pcs_status) ? 1 : 0;
1837 np->link_config.active_speed = SPEED_10000;
1838 np->link_config.active_duplex = DUPLEX_FULL;
1841 mrvl88x2011_act_led(np, (link_up ?
1842 MRVL88X2011_LED_CTL_PCS_ACT :
1843 MRVL88X2011_LED_CTL_OFF));
1845 *link_up_p = link_up;
1849 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1854 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1855 BCM8704_PMD_RCV_SIGDET);
1858 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1863 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1864 BCM8704_PCS_10G_R_STATUS);
1868 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1873 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1874 BCM8704_PHYXS_XGXS_LANE_STAT);
1877 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1878 PHYXS_XGXS_LANE_STAT_MAGIC |
1879 PHYXS_XGXS_LANE_STAT_PATTEST |
1880 PHYXS_XGXS_LANE_STAT_LANE3 |
1881 PHYXS_XGXS_LANE_STAT_LANE2 |
1882 PHYXS_XGXS_LANE_STAT_LANE1 |
1883 PHYXS_XGXS_LANE_STAT_LANE0)) {
1885 np->link_config.active_speed = SPEED_INVALID;
1886 np->link_config.active_duplex = DUPLEX_INVALID;
1891 np->link_config.active_speed = SPEED_10000;
1892 np->link_config.active_duplex = DUPLEX_FULL;
1896 *link_up_p = link_up;
1897 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1902 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1908 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1909 BCM8704_PMD_RCV_SIGDET);
1912 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1917 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1918 BCM8704_PCS_10G_R_STATUS);
1921 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1926 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1927 BCM8704_PHYXS_XGXS_LANE_STAT);
1931 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1932 PHYXS_XGXS_LANE_STAT_MAGIC |
1933 PHYXS_XGXS_LANE_STAT_LANE3 |
1934 PHYXS_XGXS_LANE_STAT_LANE2 |
1935 PHYXS_XGXS_LANE_STAT_LANE1 |
1936 PHYXS_XGXS_LANE_STAT_LANE0)) {
1942 np->link_config.active_speed = SPEED_10000;
1943 np->link_config.active_duplex = DUPLEX_FULL;
1947 *link_up_p = link_up;
1951 static int link_status_10g(struct niu *np, int *link_up_p)
1953 unsigned long flags;
1956 spin_lock_irqsave(&np->lock, flags);
1958 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1961 phy_id = phy_decode(np->parent->port_phy, np->port);
1962 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1964 /* handle different phy types */
1965 switch (phy_id & NIU_PHY_ID_MASK) {
1966 case NIU_PHY_ID_MRVL88X2011:
1967 err = link_status_10g_mrvl(np, link_up_p);
1970 default: /* bcom 8704 */
1971 err = link_status_10g_bcom(np, link_up_p);
1976 spin_unlock_irqrestore(&np->lock, flags);
1981 static int niu_10g_phy_present(struct niu *np)
1985 sig = nr64(ESR_INT_SIGNALS);
1988 mask = ESR_INT_SIGNALS_P0_BITS;
1989 val = (ESR_INT_SRDY0_P0 |
1992 ESR_INT_XDP_P0_CH3 |
1993 ESR_INT_XDP_P0_CH2 |
1994 ESR_INT_XDP_P0_CH1 |
1995 ESR_INT_XDP_P0_CH0);
1999 mask = ESR_INT_SIGNALS_P1_BITS;
2000 val = (ESR_INT_SRDY0_P1 |
2003 ESR_INT_XDP_P1_CH3 |
2004 ESR_INT_XDP_P1_CH2 |
2005 ESR_INT_XDP_P1_CH1 |
2006 ESR_INT_XDP_P1_CH0);
2013 if ((sig & mask) != val)
2018 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2020 unsigned long flags;
2023 int phy_present_prev;
2025 spin_lock_irqsave(&np->lock, flags);
2027 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2028 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2030 phy_present = niu_10g_phy_present(np);
2031 if (phy_present != phy_present_prev) {
2034 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2035 if (np->phy_ops->xcvr_init)
2036 err = np->phy_ops->xcvr_init(np);
2039 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2042 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2044 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2048 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2049 err = link_status_10g_bcm8706(np, link_up_p);
2052 spin_unlock_irqrestore(&np->lock, flags);
2057 static int link_status_1g(struct niu *np, int *link_up_p)
2059 struct niu_link_config *lp = &np->link_config;
2060 u16 current_speed, bmsr;
2061 unsigned long flags;
2066 current_speed = SPEED_INVALID;
2067 current_duplex = DUPLEX_INVALID;
2069 spin_lock_irqsave(&np->lock, flags);
2072 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
2075 err = mii_read(np, np->phy_addr, MII_BMSR);
2080 if (bmsr & BMSR_LSTATUS) {
2081 u16 adv, lpa, common, estat;
2083 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
2088 err = mii_read(np, np->phy_addr, MII_LPA);
2095 err = mii_read(np, np->phy_addr, MII_ESTATUS);
2101 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
2102 current_speed = SPEED_1000;
2103 if (estat & ESTATUS_1000_TFULL)
2104 current_duplex = DUPLEX_FULL;
2106 current_duplex = DUPLEX_HALF;
2108 if (common & ADVERTISE_100BASE4) {
2109 current_speed = SPEED_100;
2110 current_duplex = DUPLEX_HALF;
2111 } else if (common & ADVERTISE_100FULL) {
2112 current_speed = SPEED_100;
2113 current_duplex = DUPLEX_FULL;
2114 } else if (common & ADVERTISE_100HALF) {
2115 current_speed = SPEED_100;
2116 current_duplex = DUPLEX_HALF;
2117 } else if (common & ADVERTISE_10FULL) {
2118 current_speed = SPEED_10;
2119 current_duplex = DUPLEX_FULL;
2120 } else if (common & ADVERTISE_10HALF) {
2121 current_speed = SPEED_10;
2122 current_duplex = DUPLEX_HALF;
2127 lp->active_speed = current_speed;
2128 lp->active_duplex = current_duplex;
2132 spin_unlock_irqrestore(&np->lock, flags);
2134 *link_up_p = link_up;
2138 static int niu_link_status(struct niu *np, int *link_up_p)
2140 const struct niu_phy_ops *ops = np->phy_ops;
2144 if (ops->link_status)
2145 err = ops->link_status(np, link_up_p);
2150 static void niu_timer(unsigned long __opaque)
2152 struct niu *np = (struct niu *) __opaque;
2156 err = niu_link_status(np, &link_up);
2158 niu_link_status_common(np, link_up);
2160 if (netif_carrier_ok(np->dev))
2164 np->timer.expires = jiffies + off;
2166 add_timer(&np->timer);
2169 static const struct niu_phy_ops phy_ops_10g_serdes = {
2170 .serdes_init = serdes_init_10g_serdes,
2171 .link_status = link_status_10g_serdes,
2174 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2175 .serdes_init = serdes_init_niu_10g_serdes,
2176 .link_status = link_status_10g_serdes,
2179 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2180 .serdes_init = serdes_init_niu_1g_serdes,
2181 .link_status = link_status_1g_serdes,
2184 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2185 .xcvr_init = xcvr_init_1g_rgmii,
2186 .link_status = link_status_1g_rgmii,
2189 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2190 .serdes_init = serdes_init_niu_10g_fiber,
2191 .xcvr_init = xcvr_init_10g,
2192 .link_status = link_status_10g,
2195 static const struct niu_phy_ops phy_ops_10g_fiber = {
2196 .serdes_init = serdes_init_10g,
2197 .xcvr_init = xcvr_init_10g,
2198 .link_status = link_status_10g,
2201 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2202 .serdes_init = serdes_init_10g,
2203 .xcvr_init = xcvr_init_10g_bcm8706,
2204 .link_status = link_status_10g_hotplug,
2207 static const struct niu_phy_ops phy_ops_10g_copper = {
2208 .serdes_init = serdes_init_10g,
2209 .link_status = link_status_10g, /* XXX */
2212 static const struct niu_phy_ops phy_ops_1g_fiber = {
2213 .serdes_init = serdes_init_1g,
2214 .xcvr_init = xcvr_init_1g,
2215 .link_status = link_status_1g,
2218 static const struct niu_phy_ops phy_ops_1g_copper = {
2219 .xcvr_init = xcvr_init_1g,
2220 .link_status = link_status_1g,
2223 struct niu_phy_template {
2224 const struct niu_phy_ops *ops;
2228 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2229 .ops = &phy_ops_10g_fiber_niu,
2230 .phy_addr_base = 16,
2233 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2234 .ops = &phy_ops_10g_serdes_niu,
2238 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2239 .ops = &phy_ops_1g_serdes_niu,
2243 static const struct niu_phy_template phy_template_10g_fiber = {
2244 .ops = &phy_ops_10g_fiber,
2248 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2249 .ops = &phy_ops_10g_fiber_hotplug,
2253 static const struct niu_phy_template phy_template_10g_copper = {
2254 .ops = &phy_ops_10g_copper,
2255 .phy_addr_base = 10,
2258 static const struct niu_phy_template phy_template_1g_fiber = {
2259 .ops = &phy_ops_1g_fiber,
2263 static const struct niu_phy_template phy_template_1g_copper = {
2264 .ops = &phy_ops_1g_copper,
2268 static const struct niu_phy_template phy_template_1g_rgmii = {
2269 .ops = &phy_ops_1g_rgmii,
2273 static const struct niu_phy_template phy_template_10g_serdes = {
2274 .ops = &phy_ops_10g_serdes,
2278 static int niu_atca_port_num[4] = {
2282 static int serdes_init_10g_serdes(struct niu *np)
2284 struct niu_link_config *lp = &np->link_config;
2285 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2286 u64 ctrl_val, test_cfg_val, sig, mask, val;
2292 reset_val = ENET_SERDES_RESET_0;
2293 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2294 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2295 pll_cfg = ENET_SERDES_0_PLL_CFG;
2298 reset_val = ENET_SERDES_RESET_1;
2299 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2300 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2301 pll_cfg = ENET_SERDES_1_PLL_CFG;
2307 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2308 ENET_SERDES_CTRL_SDET_1 |
2309 ENET_SERDES_CTRL_SDET_2 |
2310 ENET_SERDES_CTRL_SDET_3 |
2311 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2312 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2313 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2314 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2315 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2316 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2317 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2318 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2321 if (lp->loopback_mode == LOOPBACK_PHY) {
2322 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2323 ENET_SERDES_TEST_MD_0_SHIFT) |
2324 (ENET_TEST_MD_PAD_LOOPBACK <<
2325 ENET_SERDES_TEST_MD_1_SHIFT) |
2326 (ENET_TEST_MD_PAD_LOOPBACK <<
2327 ENET_SERDES_TEST_MD_2_SHIFT) |
2328 (ENET_TEST_MD_PAD_LOOPBACK <<
2329 ENET_SERDES_TEST_MD_3_SHIFT));
2333 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2334 nw64(ctrl_reg, ctrl_val);
2335 nw64(test_cfg_reg, test_cfg_val);
2337 /* Initialize all 4 lanes of the SERDES. */
2338 for (i = 0; i < 4; i++) {
2339 u32 rxtx_ctrl, glue0;
2341 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2344 err = esr_read_glue0(np, i, &glue0);
2348 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2349 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2350 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2352 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2353 ESR_GLUE_CTRL0_THCNT |
2354 ESR_GLUE_CTRL0_BLTIME);
2355 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2356 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2357 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2358 (BLTIME_300_CYCLES <<
2359 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2361 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2364 err = esr_write_glue0(np, i, glue0);
2370 sig = nr64(ESR_INT_SIGNALS);
2373 mask = ESR_INT_SIGNALS_P0_BITS;
2374 val = (ESR_INT_SRDY0_P0 |
2377 ESR_INT_XDP_P0_CH3 |
2378 ESR_INT_XDP_P0_CH2 |
2379 ESR_INT_XDP_P0_CH1 |
2380 ESR_INT_XDP_P0_CH0);
2384 mask = ESR_INT_SIGNALS_P1_BITS;
2385 val = (ESR_INT_SRDY0_P1 |
2388 ESR_INT_XDP_P1_CH3 |
2389 ESR_INT_XDP_P1_CH2 |
2390 ESR_INT_XDP_P1_CH1 |
2391 ESR_INT_XDP_P1_CH0);
2398 if ((sig & mask) != val) {
2400 err = serdes_init_1g_serdes(np);
2402 np->flags &= ~NIU_FLAGS_10G;
2403 np->mac_xcvr = MAC_XCVR_PCS;
2405 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2414 static int niu_determine_phy_disposition(struct niu *np)
2416 struct niu_parent *parent = np->parent;
2417 u8 plat_type = parent->plat_type;
2418 const struct niu_phy_template *tp;
2419 u32 phy_addr_off = 0;
2421 if (plat_type == PLAT_TYPE_NIU) {
2425 NIU_FLAGS_XCVR_SERDES)) {
2426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2428 tp = &phy_template_niu_10g_serdes;
2430 case NIU_FLAGS_XCVR_SERDES:
2432 tp = &phy_template_niu_1g_serdes;
2434 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2437 tp = &phy_template_niu_10g_fiber;
2438 phy_addr_off += np->port;
2445 NIU_FLAGS_XCVR_SERDES)) {
2448 tp = &phy_template_1g_copper;
2449 if (plat_type == PLAT_TYPE_VF_P0)
2451 else if (plat_type == PLAT_TYPE_VF_P1)
2454 phy_addr_off += (np->port ^ 0x3);
2459 tp = &phy_template_1g_copper;
2462 case NIU_FLAGS_FIBER:
2464 tp = &phy_template_1g_fiber;
2467 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2469 tp = &phy_template_10g_fiber;
2470 if (plat_type == PLAT_TYPE_VF_P0 ||
2471 plat_type == PLAT_TYPE_VF_P1)
2473 phy_addr_off += np->port;
2474 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2475 tp = &phy_template_10g_fiber_hotplug;
2483 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2484 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2485 case NIU_FLAGS_XCVR_SERDES:
2489 tp = &phy_template_10g_serdes;
2493 tp = &phy_template_1g_rgmii;
2499 phy_addr_off = niu_atca_port_num[np->port];
2507 np->phy_ops = tp->ops;
2508 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2513 static int niu_init_link(struct niu *np)
2515 struct niu_parent *parent = np->parent;
2518 if (parent->plat_type == PLAT_TYPE_NIU) {
2519 err = niu_xcvr_init(np);
2524 err = niu_serdes_init(np);
2528 err = niu_xcvr_init(np);
2530 niu_link_status(np, &ignore);
2534 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2536 u16 reg0 = addr[4] << 8 | addr[5];
2537 u16 reg1 = addr[2] << 8 | addr[3];
2538 u16 reg2 = addr[0] << 8 | addr[1];
2540 if (np->flags & NIU_FLAGS_XMAC) {
2541 nw64_mac(XMAC_ADDR0, reg0);
2542 nw64_mac(XMAC_ADDR1, reg1);
2543 nw64_mac(XMAC_ADDR2, reg2);
2545 nw64_mac(BMAC_ADDR0, reg0);
2546 nw64_mac(BMAC_ADDR1, reg1);
2547 nw64_mac(BMAC_ADDR2, reg2);
2551 static int niu_num_alt_addr(struct niu *np)
2553 if (np->flags & NIU_FLAGS_XMAC)
2554 return XMAC_NUM_ALT_ADDR;
2556 return BMAC_NUM_ALT_ADDR;
2559 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2561 u16 reg0 = addr[4] << 8 | addr[5];
2562 u16 reg1 = addr[2] << 8 | addr[3];
2563 u16 reg2 = addr[0] << 8 | addr[1];
2565 if (index >= niu_num_alt_addr(np))
2568 if (np->flags & NIU_FLAGS_XMAC) {
2569 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2570 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2571 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2573 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2574 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2575 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2581 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2586 if (index >= niu_num_alt_addr(np))
2589 if (np->flags & NIU_FLAGS_XMAC) {
2590 reg = XMAC_ADDR_CMPEN;
2593 reg = BMAC_ADDR_CMPEN;
2594 mask = 1 << (index + 1);
2597 val = nr64_mac(reg);
2607 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2608 int num, int mac_pref)
2610 u64 val = nr64_mac(reg);
2611 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2614 val |= HOST_INFO_MPR;
2618 static int __set_rdc_table_num(struct niu *np,
2619 int xmac_index, int bmac_index,
2620 int rdc_table_num, int mac_pref)
2624 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2626 if (np->flags & NIU_FLAGS_XMAC)
2627 reg = XMAC_HOST_INFO(xmac_index);
2629 reg = BMAC_HOST_INFO(bmac_index);
2630 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2634 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2637 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2640 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2643 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2646 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2647 int table_num, int mac_pref)
2649 if (idx >= niu_num_alt_addr(np))
2651 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2654 static u64 vlan_entry_set_parity(u64 reg_val)
2659 port01_mask = 0x00ff;
2660 port23_mask = 0xff00;
2662 if (hweight64(reg_val & port01_mask) & 1)
2663 reg_val |= ENET_VLAN_TBL_PARITY0;
2665 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2667 if (hweight64(reg_val & port23_mask) & 1)
2668 reg_val |= ENET_VLAN_TBL_PARITY1;
2670 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2675 static void vlan_tbl_write(struct niu *np, unsigned long index,
2676 int port, int vpr, int rdc_table)
2678 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2680 reg_val &= ~((ENET_VLAN_TBL_VPR |
2681 ENET_VLAN_TBL_VLANRDCTBLN) <<
2682 ENET_VLAN_TBL_SHIFT(port));
2684 reg_val |= (ENET_VLAN_TBL_VPR <<
2685 ENET_VLAN_TBL_SHIFT(port));
2686 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2688 reg_val = vlan_entry_set_parity(reg_val);
2690 nw64(ENET_VLAN_TBL(index), reg_val);
2693 static void vlan_tbl_clear(struct niu *np)
2697 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2698 nw64(ENET_VLAN_TBL(i), 0);
2701 static int tcam_wait_bit(struct niu *np, u64 bit)
2705 while (--limit > 0) {
2706 if (nr64(TCAM_CTL) & bit)
2716 static int tcam_flush(struct niu *np, int index)
2718 nw64(TCAM_KEY_0, 0x00);
2719 nw64(TCAM_KEY_MASK_0, 0xff);
2720 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2722 return tcam_wait_bit(np, TCAM_CTL_STAT);
2726 static int tcam_read(struct niu *np, int index,
2727 u64 *key, u64 *mask)
2731 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2732 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2734 key[0] = nr64(TCAM_KEY_0);
2735 key[1] = nr64(TCAM_KEY_1);
2736 key[2] = nr64(TCAM_KEY_2);
2737 key[3] = nr64(TCAM_KEY_3);
2738 mask[0] = nr64(TCAM_KEY_MASK_0);
2739 mask[1] = nr64(TCAM_KEY_MASK_1);
2740 mask[2] = nr64(TCAM_KEY_MASK_2);
2741 mask[3] = nr64(TCAM_KEY_MASK_3);
2747 static int tcam_write(struct niu *np, int index,
2748 u64 *key, u64 *mask)
2750 nw64(TCAM_KEY_0, key[0]);
2751 nw64(TCAM_KEY_1, key[1]);
2752 nw64(TCAM_KEY_2, key[2]);
2753 nw64(TCAM_KEY_3, key[3]);
2754 nw64(TCAM_KEY_MASK_0, mask[0]);
2755 nw64(TCAM_KEY_MASK_1, mask[1]);
2756 nw64(TCAM_KEY_MASK_2, mask[2]);
2757 nw64(TCAM_KEY_MASK_3, mask[3]);
2758 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2760 return tcam_wait_bit(np, TCAM_CTL_STAT);
2764 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2768 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2769 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2771 *data = nr64(TCAM_KEY_1);
2777 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2779 nw64(TCAM_KEY_1, assoc_data);
2780 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2782 return tcam_wait_bit(np, TCAM_CTL_STAT);
2785 static void tcam_enable(struct niu *np, int on)
2787 u64 val = nr64(FFLP_CFG_1);
2790 val &= ~FFLP_CFG_1_TCAM_DIS;
2792 val |= FFLP_CFG_1_TCAM_DIS;
2793 nw64(FFLP_CFG_1, val);
2796 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2798 u64 val = nr64(FFLP_CFG_1);
2800 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2802 FFLP_CFG_1_CAMRATIO);
2803 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2804 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2805 nw64(FFLP_CFG_1, val);
2807 val = nr64(FFLP_CFG_1);
2808 val |= FFLP_CFG_1_FFLPINITDONE;
2809 nw64(FFLP_CFG_1, val);
2812 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2818 if (class < CLASS_CODE_ETHERTYPE1 ||
2819 class > CLASS_CODE_ETHERTYPE2)
2822 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2834 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2840 if (class < CLASS_CODE_ETHERTYPE1 ||
2841 class > CLASS_CODE_ETHERTYPE2 ||
2842 (ether_type & ~(u64)0xffff) != 0)
2845 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2847 val &= ~L2_CLS_ETYPE;
2848 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2855 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2861 if (class < CLASS_CODE_USER_PROG1 ||
2862 class > CLASS_CODE_USER_PROG4)
2865 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2868 val |= L3_CLS_VALID;
2870 val &= ~L3_CLS_VALID;
2877 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2878 int ipv6, u64 protocol_id,
2879 u64 tos_mask, u64 tos_val)
2884 if (class < CLASS_CODE_USER_PROG1 ||
2885 class > CLASS_CODE_USER_PROG4 ||
2886 (protocol_id & ~(u64)0xff) != 0 ||
2887 (tos_mask & ~(u64)0xff) != 0 ||
2888 (tos_val & ~(u64)0xff) != 0)
2891 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2893 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2894 L3_CLS_TOSMASK | L3_CLS_TOS);
2896 val |= L3_CLS_IPVER;
2897 val |= (protocol_id << L3_CLS_PID_SHIFT);
2898 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2899 val |= (tos_val << L3_CLS_TOS_SHIFT);
2906 static int tcam_early_init(struct niu *np)
2912 tcam_set_lat_and_ratio(np,
2913 DEFAULT_TCAM_LATENCY,
2914 DEFAULT_TCAM_ACCESS_RATIO);
2915 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2916 err = tcam_user_eth_class_enable(np, i, 0);
2920 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2921 err = tcam_user_ip_class_enable(np, i, 0);
2929 static int tcam_flush_all(struct niu *np)
2933 for (i = 0; i < np->parent->tcam_num_entries; i++) {
2934 int err = tcam_flush(np, i);
2941 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2943 return ((u64)index | (num_entries == 1 ?
2944 HASH_TBL_ADDR_AUTOINC : 0));
2948 static int hash_read(struct niu *np, unsigned long partition,
2949 unsigned long index, unsigned long num_entries,
2952 u64 val = hash_addr_regval(index, num_entries);
2955 if (partition >= FCRAM_NUM_PARTITIONS ||
2956 index + num_entries > FCRAM_SIZE)
2959 nw64(HASH_TBL_ADDR(partition), val);
2960 for (i = 0; i < num_entries; i++)
2961 data[i] = nr64(HASH_TBL_DATA(partition));
2967 static int hash_write(struct niu *np, unsigned long partition,
2968 unsigned long index, unsigned long num_entries,
2971 u64 val = hash_addr_regval(index, num_entries);
2974 if (partition >= FCRAM_NUM_PARTITIONS ||
2975 index + (num_entries * 8) > FCRAM_SIZE)
2978 nw64(HASH_TBL_ADDR(partition), val);
2979 for (i = 0; i < num_entries; i++)
2980 nw64(HASH_TBL_DATA(partition), data[i]);
2985 static void fflp_reset(struct niu *np)
2989 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2991 nw64(FFLP_CFG_1, 0);
2993 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2994 nw64(FFLP_CFG_1, val);
2997 static void fflp_set_timings(struct niu *np)
2999 u64 val = nr64(FFLP_CFG_1);
3001 val &= ~FFLP_CFG_1_FFLPINITDONE;
3002 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3003 nw64(FFLP_CFG_1, val);
3005 val = nr64(FFLP_CFG_1);
3006 val |= FFLP_CFG_1_FFLPINITDONE;
3007 nw64(FFLP_CFG_1, val);
3009 val = nr64(FCRAM_REF_TMR);
3010 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3011 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3012 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3013 nw64(FCRAM_REF_TMR, val);
3016 static int fflp_set_partition(struct niu *np, u64 partition,
3017 u64 mask, u64 base, int enable)
3022 if (partition >= FCRAM_NUM_PARTITIONS ||
3023 (mask & ~(u64)0x1f) != 0 ||
3024 (base & ~(u64)0x1f) != 0)
3027 reg = FLW_PRT_SEL(partition);
3030 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3031 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3032 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3034 val |= FLW_PRT_SEL_EXT;
3040 static int fflp_disable_all_partitions(struct niu *np)
3044 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3045 int err = fflp_set_partition(np, 0, 0, 0, 0);
3052 static void fflp_llcsnap_enable(struct niu *np, int on)
3054 u64 val = nr64(FFLP_CFG_1);
3057 val |= FFLP_CFG_1_LLCSNAP;
3059 val &= ~FFLP_CFG_1_LLCSNAP;
3060 nw64(FFLP_CFG_1, val);
3063 static void fflp_errors_enable(struct niu *np, int on)
3065 u64 val = nr64(FFLP_CFG_1);
3068 val &= ~FFLP_CFG_1_ERRORDIS;
3070 val |= FFLP_CFG_1_ERRORDIS;
3071 nw64(FFLP_CFG_1, val);
3074 static int fflp_hash_clear(struct niu *np)
3076 struct fcram_hash_ipv4 ent;
3079 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3080 memset(&ent, 0, sizeof(ent));
3081 ent.header = HASH_HEADER_EXT;
3083 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3084 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3091 static int fflp_early_init(struct niu *np)
3093 struct niu_parent *parent;
3094 unsigned long flags;
3097 niu_lock_parent(np, flags);
3099 parent = np->parent;
3101 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3102 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3104 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3106 fflp_set_timings(np);
3107 err = fflp_disable_all_partitions(np);
3109 niudbg(PROBE, "fflp_disable_all_partitions "
3110 "failed, err=%d\n", err);
3115 err = tcam_early_init(np);
3117 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3121 fflp_llcsnap_enable(np, 1);
3122 fflp_errors_enable(np, 0);
3126 err = tcam_flush_all(np);
3128 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3132 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3133 err = fflp_hash_clear(np);
3135 niudbg(PROBE, "fflp_hash_clear failed, "
3143 niudbg(PROBE, "fflp_early_init: Success\n");
3144 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3147 niu_unlock_parent(np, flags);
3151 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3153 if (class_code < CLASS_CODE_USER_PROG1 ||
3154 class_code > CLASS_CODE_SCTP_IPV6)
3157 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3161 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3163 if (class_code < CLASS_CODE_USER_PROG1 ||
3164 class_code > CLASS_CODE_SCTP_IPV6)
3167 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3171 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3172 u32 offset, u32 size)
3174 int i = skb_shinfo(skb)->nr_frags;
3175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3178 frag->page_offset = offset;
3182 skb->data_len += size;
3183 skb->truesize += size;
3185 skb_shinfo(skb)->nr_frags = i + 1;
3188 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3191 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3193 return (a & (MAX_RBR_RING_SIZE - 1));
3196 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3197 struct page ***link)
3199 unsigned int h = niu_hash_rxaddr(rp, addr);
3200 struct page *p, **pp;
3203 pp = &rp->rxhash[h];
3204 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3205 if (p->index == addr) {
3214 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3216 unsigned int h = niu_hash_rxaddr(rp, base);
3219 page->mapping = (struct address_space *) rp->rxhash[h];
3220 rp->rxhash[h] = page;
3223 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3224 gfp_t mask, int start_index)
3230 page = alloc_page(mask);
3234 addr = np->ops->map_page(np->device, page, 0,
3235 PAGE_SIZE, DMA_FROM_DEVICE);
3237 niu_hash_page(rp, page, addr);
3238 if (rp->rbr_blocks_per_page > 1)
3239 atomic_add(rp->rbr_blocks_per_page - 1,
3240 &compound_head(page)->_count);
3242 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3243 __le32 *rbr = &rp->rbr[start_index + i];
3245 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3246 addr += rp->rbr_block_size;
3252 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3254 int index = rp->rbr_index;
3257 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3258 int err = niu_rbr_add_page(np, rp, mask, index);
3260 if (unlikely(err)) {
3265 rp->rbr_index += rp->rbr_blocks_per_page;
3266 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3267 if (rp->rbr_index == rp->rbr_table_size)
3270 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3271 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3272 rp->rbr_pending = 0;
3277 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3279 unsigned int index = rp->rcr_index;
3284 struct page *page, **link;
3290 val = le64_to_cpup(&rp->rcr[index]);
3291 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3292 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3293 page = niu_find_rxpage(rp, addr, &link);
3295 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3296 RCR_ENTRY_PKTBUFSZ_SHIFT];
3297 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3298 *link = (struct page *) page->mapping;
3299 np->ops->unmap_page(np->device, page->index,
3300 PAGE_SIZE, DMA_FROM_DEVICE);
3302 page->mapping = NULL;
3304 rp->rbr_refill_pending++;
3307 index = NEXT_RCR(rp, index);
3308 if (!(val & RCR_ENTRY_MULTI))
3312 rp->rcr_index = index;
3317 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3319 unsigned int index = rp->rcr_index;
3320 struct sk_buff *skb;
3323 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3325 return niu_rx_pkt_ignore(np, rp);
3329 struct page *page, **link;
3330 u32 rcr_size, append_size;
3335 val = le64_to_cpup(&rp->rcr[index]);
3337 len = (val & RCR_ENTRY_L2_LEN) >>
3338 RCR_ENTRY_L2_LEN_SHIFT;
3341 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3342 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3343 page = niu_find_rxpage(rp, addr, &link);
3345 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3346 RCR_ENTRY_PKTBUFSZ_SHIFT];
3348 off = addr & ~PAGE_MASK;
3349 append_size = rcr_size;
3356 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3357 if ((ptype == RCR_PKT_TYPE_TCP ||
3358 ptype == RCR_PKT_TYPE_UDP) &&
3359 !(val & (RCR_ENTRY_NOPORT |
3361 skb->ip_summed = CHECKSUM_UNNECESSARY;
3363 skb->ip_summed = CHECKSUM_NONE;
3365 if (!(val & RCR_ENTRY_MULTI))
3366 append_size = len - skb->len;
3368 niu_rx_skb_append(skb, page, off, append_size);
3369 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3370 *link = (struct page *) page->mapping;
3371 np->ops->unmap_page(np->device, page->index,
3372 PAGE_SIZE, DMA_FROM_DEVICE);
3374 page->mapping = NULL;
3375 rp->rbr_refill_pending++;
3379 index = NEXT_RCR(rp, index);
3380 if (!(val & RCR_ENTRY_MULTI))
3384 rp->rcr_index = index;
3386 skb_reserve(skb, NET_IP_ALIGN);
3387 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3390 rp->rx_bytes += skb->len;
3392 skb->protocol = eth_type_trans(skb, np->dev);
3393 netif_receive_skb(skb);
3398 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3400 int blocks_per_page = rp->rbr_blocks_per_page;
3401 int err, index = rp->rbr_index;
3404 while (index < (rp->rbr_table_size - blocks_per_page)) {
3405 err = niu_rbr_add_page(np, rp, mask, index);
3409 index += blocks_per_page;
3412 rp->rbr_index = index;
3416 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3420 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3423 page = rp->rxhash[i];
3425 struct page *next = (struct page *) page->mapping;
3426 u64 base = page->index;
3428 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3431 page->mapping = NULL;
3439 for (i = 0; i < rp->rbr_table_size; i++)
3440 rp->rbr[i] = cpu_to_le32(0);
3444 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3446 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3447 struct sk_buff *skb = tb->skb;
3448 struct tx_pkt_hdr *tp;
3452 tp = (struct tx_pkt_hdr *) skb->data;
3453 tx_flags = le64_to_cpup(&tp->flags);
3456 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3457 ((tx_flags & TXHDR_PAD) / 2));
3459 len = skb_headlen(skb);
3460 np->ops->unmap_single(np->device, tb->mapping,
3461 len, DMA_TO_DEVICE);
3463 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3468 idx = NEXT_TX(rp, idx);
3469 len -= MAX_TX_DESC_LEN;
3472 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3473 tb = &rp->tx_buffs[idx];
3474 BUG_ON(tb->skb != NULL);
3475 np->ops->unmap_page(np->device, tb->mapping,
3476 skb_shinfo(skb)->frags[i].size,
3478 idx = NEXT_TX(rp, idx);
3486 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3488 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3490 struct netdev_queue *txq;
3495 index = (rp - np->tx_rings);
3496 txq = netdev_get_tx_queue(np->dev, index);
3499 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3502 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3503 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3504 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3506 rp->last_pkt_cnt = tmp;
3510 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3511 np->dev->name, pkt_cnt, cons);
3514 cons = release_tx_packet(np, rp, cons);
3520 if (unlikely(netif_tx_queue_stopped(txq) &&
3521 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3522 __netif_tx_lock(txq, smp_processor_id());
3523 if (netif_tx_queue_stopped(txq) &&
3524 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3525 netif_tx_wake_queue(txq);
3526 __netif_tx_unlock(txq);
3530 static inline void niu_sync_rx_discard_stats(struct niu *np,
3531 struct rx_ring_info *rp,
3534 /* This elaborate scheme is needed for reading the RX discard
3535 * counters, as they are only 16-bit and can overflow quickly,
3536 * and because the overflow indication bit is not usable as
3537 * the counter value does not wrap, but remains at max value
3540 * In theory and in practice counters can be lost in between
3541 * reading nr64() and clearing the counter nw64(). For this
3542 * reason, the number of counter clearings nw64() is
3543 * limited/reduced though the limit parameter.
3545 int rx_channel = rp->rx_channel;
3548 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3549 * following discard events: IPP (Input Port Process),
3550 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3551 * Block Ring) prefetch buffer is empty.
3553 misc = nr64(RXMISC(rx_channel));
3554 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3555 nw64(RXMISC(rx_channel), 0);
3556 rp->rx_errors += misc & RXMISC_COUNT;
3558 if (unlikely(misc & RXMISC_OFLOW))
3559 dev_err(np->device, "rx-%d: Counter overflow "
3560 "RXMISC discard\n", rx_channel);
3562 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3563 np->dev->name, rx_channel, misc, misc-limit);
3566 /* WRED (Weighted Random Early Discard) by hardware */
3567 wred = nr64(RED_DIS_CNT(rx_channel));
3568 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3569 nw64(RED_DIS_CNT(rx_channel), 0);
3570 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3572 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3573 dev_err(np->device, "rx-%d: Counter overflow "
3574 "WRED discard\n", rx_channel);
3576 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3577 np->dev->name, rx_channel, wred, wred-limit);
3581 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3583 int qlen, rcr_done = 0, work_done = 0;
3584 struct rxdma_mailbox *mbox = rp->mbox;
3588 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3589 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3591 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3592 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3594 mbox->rx_dma_ctl_stat = 0;
3595 mbox->rcrstat_a = 0;
3597 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3598 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3600 rcr_done = work_done = 0;
3601 qlen = min(qlen, budget);
3602 while (work_done < qlen) {
3603 rcr_done += niu_process_rx_pkt(np, rp);
3607 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3610 for (i = 0; i < rp->rbr_refill_pending; i++)
3611 niu_rbr_refill(np, rp, GFP_ATOMIC);
3612 rp->rbr_refill_pending = 0;
3615 stat = (RX_DMA_CTL_STAT_MEX |
3616 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3617 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3619 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3621 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3626 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3629 u32 tx_vec = (v0 >> 32);
3630 u32 rx_vec = (v0 & 0xffffffff);
3631 int i, work_done = 0;
3633 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3634 np->dev->name, (unsigned long long) v0);
3636 for (i = 0; i < np->num_tx_rings; i++) {
3637 struct tx_ring_info *rp = &np->tx_rings[i];
3638 if (tx_vec & (1 << rp->tx_channel))
3639 niu_tx_work(np, rp);
3640 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3643 for (i = 0; i < np->num_rx_rings; i++) {
3644 struct rx_ring_info *rp = &np->rx_rings[i];
3646 if (rx_vec & (1 << rp->rx_channel)) {
3649 this_work_done = niu_rx_work(np, rp,
3652 budget -= this_work_done;
3653 work_done += this_work_done;
3655 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3661 static int niu_poll(struct napi_struct *napi, int budget)
3663 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3664 struct niu *np = lp->np;
3667 work_done = niu_poll_core(np, lp, budget);
3669 if (work_done < budget) {
3670 netif_rx_complete(np->dev, napi);
3671 niu_ldg_rearm(np, lp, 1);
3676 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3679 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3680 np->dev->name, rp->rx_channel);
3682 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3683 printk("RBR_TMOUT ");
3684 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3686 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3687 printk("BYTE_EN_BUS ");
3688 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3690 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3692 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3693 printk("RCR_SHA_PAR ");
3694 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3695 printk("RBR_PRE_PAR ");
3696 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3698 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3699 printk("RCRINCON ");
3700 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3702 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3704 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3705 printk("RBRLOGPAGE ");
3706 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3707 printk("CFIGLOGPAGE ");
3708 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3714 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3716 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3720 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3721 RX_DMA_CTL_STAT_PORT_FATAL))
3725 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3726 np->dev->name, rp->rx_channel,
3727 (unsigned long long) stat);
3729 niu_log_rxchan_errors(np, rp, stat);
3732 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3733 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3738 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3741 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3742 np->dev->name, rp->tx_channel);
3744 if (cs & TX_CS_MBOX_ERR)
3746 if (cs & TX_CS_PKT_SIZE_ERR)
3747 printk("PKT_SIZE ");
3748 if (cs & TX_CS_TX_RING_OFLOW)
3749 printk("TX_RING_OFLOW ");
3750 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3751 printk("PREF_BUF_PAR ");
3752 if (cs & TX_CS_NACK_PREF)
3753 printk("NACK_PREF ");
3754 if (cs & TX_CS_NACK_PKT_RD)
3755 printk("NACK_PKT_RD ");
3756 if (cs & TX_CS_CONF_PART_ERR)
3757 printk("CONF_PART ");
3758 if (cs & TX_CS_PKT_PRT_ERR)
3764 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3768 cs = nr64(TX_CS(rp->tx_channel));
3769 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3770 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3772 dev_err(np->device, PFX "%s: TX channel %u error, "
3773 "cs[%llx] logh[%llx] logl[%llx]\n",
3774 np->dev->name, rp->tx_channel,
3775 (unsigned long long) cs,
3776 (unsigned long long) logh,
3777 (unsigned long long) logl);
3779 niu_log_txchan_errors(np, rp, cs);
3784 static int niu_mif_interrupt(struct niu *np)
3786 u64 mif_status = nr64(MIF_STATUS);
3789 if (np->flags & NIU_FLAGS_XMAC) {
3790 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3792 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3796 dev_err(np->device, PFX "%s: MIF interrupt, "
3797 "stat[%llx] phy_mdint(%d)\n",
3798 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3803 static void niu_xmac_interrupt(struct niu *np)
3805 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3808 val = nr64_mac(XTXMAC_STATUS);
3809 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3810 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3811 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3812 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3813 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3814 mp->tx_fifo_errors++;
3815 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3816 mp->tx_overflow_errors++;
3817 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3818 mp->tx_max_pkt_size_errors++;
3819 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3820 mp->tx_underflow_errors++;
3822 val = nr64_mac(XRXMAC_STATUS);
3823 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3824 mp->rx_local_faults++;
3825 if (val & XRXMAC_STATUS_RFLT_DET)
3826 mp->rx_remote_faults++;
3827 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3828 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3829 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3830 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3831 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3832 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3833 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3834 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3835 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3836 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3837 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3838 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3839 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3840 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3841 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3842 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3843 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3844 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3845 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3846 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3847 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3848 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3849 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3850 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3851 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3852 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3853 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3854 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3855 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3856 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3857 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3858 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3859 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3860 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3861 if (val & XRXMAC_STATUS_RXUFLOW)
3862 mp->rx_underflows++;
3863 if (val & XRXMAC_STATUS_RXOFLOW)
3866 val = nr64_mac(XMAC_FC_STAT);
3867 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3868 mp->pause_off_state++;
3869 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3870 mp->pause_on_state++;
3871 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3872 mp->pause_received++;
3875 static void niu_bmac_interrupt(struct niu *np)
3877 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3880 val = nr64_mac(BTXMAC_STATUS);
3881 if (val & BTXMAC_STATUS_UNDERRUN)
3882 mp->tx_underflow_errors++;
3883 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3884 mp->tx_max_pkt_size_errors++;
3885 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3886 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3887 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3888 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3890 val = nr64_mac(BRXMAC_STATUS);
3891 if (val & BRXMAC_STATUS_OVERFLOW)
3893 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3894 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3895 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3896 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3897 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3898 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3899 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3900 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3902 val = nr64_mac(BMAC_CTRL_STATUS);
3903 if (val & BMAC_CTRL_STATUS_NOPAUSE)
3904 mp->pause_off_state++;
3905 if (val & BMAC_CTRL_STATUS_PAUSE)
3906 mp->pause_on_state++;
3907 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3908 mp->pause_received++;
3911 static int niu_mac_interrupt(struct niu *np)
3913 if (np->flags & NIU_FLAGS_XMAC)
3914 niu_xmac_interrupt(np);
3916 niu_bmac_interrupt(np);
3921 static void niu_log_device_error(struct niu *np, u64 stat)
3923 dev_err(np->device, PFX "%s: Core device errors ( ",
3926 if (stat & SYS_ERR_MASK_META2)
3928 if (stat & SYS_ERR_MASK_META1)
3930 if (stat & SYS_ERR_MASK_PEU)
3932 if (stat & SYS_ERR_MASK_TXC)
3934 if (stat & SYS_ERR_MASK_RDMC)
3936 if (stat & SYS_ERR_MASK_TDMC)
3938 if (stat & SYS_ERR_MASK_ZCP)
3940 if (stat & SYS_ERR_MASK_FFLP)
3942 if (stat & SYS_ERR_MASK_IPP)
3944 if (stat & SYS_ERR_MASK_MAC)
3946 if (stat & SYS_ERR_MASK_SMX)
3952 static int niu_device_error(struct niu *np)
3954 u64 stat = nr64(SYS_ERR_STAT);
3956 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3957 np->dev->name, (unsigned long long) stat);
3959 niu_log_device_error(np, stat);
3964 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3965 u64 v0, u64 v1, u64 v2)
3974 if (v1 & 0x00000000ffffffffULL) {
3975 u32 rx_vec = (v1 & 0xffffffff);
3977 for (i = 0; i < np->num_rx_rings; i++) {
3978 struct rx_ring_info *rp = &np->rx_rings[i];
3980 if (rx_vec & (1 << rp->rx_channel)) {
3981 int r = niu_rx_error(np, rp);
3986 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3987 RX_DMA_CTL_STAT_MEX);
3992 if (v1 & 0x7fffffff00000000ULL) {
3993 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3995 for (i = 0; i < np->num_tx_rings; i++) {
3996 struct tx_ring_info *rp = &np->tx_rings[i];
3998 if (tx_vec & (1 << rp->tx_channel)) {
3999 int r = niu_tx_error(np, rp);
4005 if ((v0 | v1) & 0x8000000000000000ULL) {
4006 int r = niu_mif_interrupt(np);
4012 int r = niu_mac_interrupt(np);
4017 int r = niu_device_error(np);
4024 niu_enable_interrupts(np, 0);
4029 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4032 struct rxdma_mailbox *mbox = rp->mbox;
4033 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4035 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4036 RX_DMA_CTL_STAT_RCRTO);
4037 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4039 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4040 np->dev->name, (unsigned long long) stat);
4043 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4046 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4048 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4049 np->dev->name, (unsigned long long) rp->tx_cs);
4052 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4054 struct niu_parent *parent = np->parent;
4058 tx_vec = (v0 >> 32);
4059 rx_vec = (v0 & 0xffffffff);
4061 for (i = 0; i < np->num_rx_rings; i++) {
4062 struct rx_ring_info *rp = &np->rx_rings[i];
4063 int ldn = LDN_RXDMA(rp->rx_channel);
4065 if (parent->ldg_map[ldn] != ldg)
4068 nw64(LD_IM0(ldn), LD_IM0_MASK);
4069 if (rx_vec & (1 << rp->rx_channel))
4070 niu_rxchan_intr(np, rp, ldn);
4073 for (i = 0; i < np->num_tx_rings; i++) {
4074 struct tx_ring_info *rp = &np->tx_rings[i];
4075 int ldn = LDN_TXDMA(rp->tx_channel);
4077 if (parent->ldg_map[ldn] != ldg)
4080 nw64(LD_IM0(ldn), LD_IM0_MASK);
4081 if (tx_vec & (1 << rp->tx_channel))
4082 niu_txchan_intr(np, rp, ldn);
4086 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4087 u64 v0, u64 v1, u64 v2)
4089 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
4093 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4094 __netif_rx_schedule(np->dev, &lp->napi);
4098 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4100 struct niu_ldg *lp = dev_id;
4101 struct niu *np = lp->np;
4102 int ldg = lp->ldg_num;
4103 unsigned long flags;
4106 if (netif_msg_intr(np))
4107 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4110 spin_lock_irqsave(&np->lock, flags);
4112 v0 = nr64(LDSV0(ldg));
4113 v1 = nr64(LDSV1(ldg));
4114 v2 = nr64(LDSV2(ldg));
4116 if (netif_msg_intr(np))
4117 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4118 (unsigned long long) v0,
4119 (unsigned long long) v1,
4120 (unsigned long long) v2);
4122 if (unlikely(!v0 && !v1 && !v2)) {
4123 spin_unlock_irqrestore(&np->lock, flags);
4127 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4128 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4132 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4133 niu_schedule_napi(np, lp, v0, v1, v2);
4135 niu_ldg_rearm(np, lp, 1);
4137 spin_unlock_irqrestore(&np->lock, flags);
4142 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4145 np->ops->free_coherent(np->device,
4146 sizeof(struct rxdma_mailbox),
4147 rp->mbox, rp->mbox_dma);
4151 np->ops->free_coherent(np->device,
4152 MAX_RCR_RING_SIZE * sizeof(__le64),
4153 rp->rcr, rp->rcr_dma);
4155 rp->rcr_table_size = 0;
4159 niu_rbr_free(np, rp);
4161 np->ops->free_coherent(np->device,
4162 MAX_RBR_RING_SIZE * sizeof(__le32),
4163 rp->rbr, rp->rbr_dma);
4165 rp->rbr_table_size = 0;
4172 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4175 np->ops->free_coherent(np->device,
4176 sizeof(struct txdma_mailbox),
4177 rp->mbox, rp->mbox_dma);
4183 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4184 if (rp->tx_buffs[i].skb)
4185 (void) release_tx_packet(np, rp, i);
4188 np->ops->free_coherent(np->device,
4189 MAX_TX_RING_SIZE * sizeof(__le64),
4190 rp->descr, rp->descr_dma);
4199 static void niu_free_channels(struct niu *np)
4204 for (i = 0; i < np->num_rx_rings; i++) {
4205 struct rx_ring_info *rp = &np->rx_rings[i];
4207 niu_free_rx_ring_info(np, rp);
4209 kfree(np->rx_rings);
4210 np->rx_rings = NULL;
4211 np->num_rx_rings = 0;
4215 for (i = 0; i < np->num_tx_rings; i++) {
4216 struct tx_ring_info *rp = &np->tx_rings[i];
4218 niu_free_tx_ring_info(np, rp);
4220 kfree(np->tx_rings);
4221 np->tx_rings = NULL;
4222 np->num_tx_rings = 0;
4226 static int niu_alloc_rx_ring_info(struct niu *np,
4227 struct rx_ring_info *rp)
4229 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4231 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4236 rp->mbox = np->ops->alloc_coherent(np->device,
4237 sizeof(struct rxdma_mailbox),
4238 &rp->mbox_dma, GFP_KERNEL);
4241 if ((unsigned long)rp->mbox & (64UL - 1)) {
4242 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4243 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4247 rp->rcr = np->ops->alloc_coherent(np->device,
4248 MAX_RCR_RING_SIZE * sizeof(__le64),
4249 &rp->rcr_dma, GFP_KERNEL);
4252 if ((unsigned long)rp->rcr & (64UL - 1)) {
4253 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4254 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4257 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4260 rp->rbr = np->ops->alloc_coherent(np->device,
4261 MAX_RBR_RING_SIZE * sizeof(__le32),
4262 &rp->rbr_dma, GFP_KERNEL);
4265 if ((unsigned long)rp->rbr & (64UL - 1)) {
4266 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4267 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4270 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4272 rp->rbr_pending = 0;
4277 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4279 int mtu = np->dev->mtu;
4281 /* These values are recommended by the HW designers for fair
4282 * utilization of DRR amongst the rings.
4284 rp->max_burst = mtu + 32;
4285 if (rp->max_burst > 4096)
4286 rp->max_burst = 4096;
4289 static int niu_alloc_tx_ring_info(struct niu *np,
4290 struct tx_ring_info *rp)
4292 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4294 rp->mbox = np->ops->alloc_coherent(np->device,
4295 sizeof(struct txdma_mailbox),
4296 &rp->mbox_dma, GFP_KERNEL);
4299 if ((unsigned long)rp->mbox & (64UL - 1)) {
4300 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4301 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4305 rp->descr = np->ops->alloc_coherent(np->device,
4306 MAX_TX_RING_SIZE * sizeof(__le64),
4307 &rp->descr_dma, GFP_KERNEL);
4310 if ((unsigned long)rp->descr & (64UL - 1)) {
4311 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4312 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4316 rp->pending = MAX_TX_RING_SIZE;
4321 /* XXX make these configurable... XXX */
4322 rp->mark_freq = rp->pending / 4;
4324 niu_set_max_burst(np, rp);
4329 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4333 bss = min(PAGE_SHIFT, 15);
4335 rp->rbr_block_size = 1 << bss;
4336 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4338 rp->rbr_sizes[0] = 256;
4339 rp->rbr_sizes[1] = 1024;
4340 if (np->dev->mtu > ETH_DATA_LEN) {
4341 switch (PAGE_SIZE) {
4343 rp->rbr_sizes[2] = 4096;
4347 rp->rbr_sizes[2] = 8192;
4351 rp->rbr_sizes[2] = 2048;
4353 rp->rbr_sizes[3] = rp->rbr_block_size;
4356 static int niu_alloc_channels(struct niu *np)
4358 struct niu_parent *parent = np->parent;
4359 int first_rx_channel, first_tx_channel;
4363 first_rx_channel = first_tx_channel = 0;
4364 for (i = 0; i < port; i++) {
4365 first_rx_channel += parent->rxchan_per_port[i];
4366 first_tx_channel += parent->txchan_per_port[i];
4369 np->num_rx_rings = parent->rxchan_per_port[port];
4370 np->num_tx_rings = parent->txchan_per_port[port];
4372 np->dev->real_num_tx_queues = np->num_tx_rings;
4374 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4380 for (i = 0; i < np->num_rx_rings; i++) {
4381 struct rx_ring_info *rp = &np->rx_rings[i];
4384 rp->rx_channel = first_rx_channel + i;
4386 err = niu_alloc_rx_ring_info(np, rp);
4390 niu_size_rbr(np, rp);
4392 /* XXX better defaults, configurable, etc... XXX */
4393 rp->nonsyn_window = 64;
4394 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4395 rp->syn_window = 64;
4396 rp->syn_threshold = rp->rcr_table_size - 64;
4397 rp->rcr_pkt_threshold = 16;
4398 rp->rcr_timeout = 8;
4399 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4400 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4401 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4403 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4408 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4414 for (i = 0; i < np->num_tx_rings; i++) {
4415 struct tx_ring_info *rp = &np->tx_rings[i];
4418 rp->tx_channel = first_tx_channel + i;
4420 err = niu_alloc_tx_ring_info(np, rp);
4428 niu_free_channels(np);
4432 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4436 while (--limit > 0) {
4437 u64 val = nr64(TX_CS(channel));
4438 if (val & TX_CS_SNG_STATE)
4444 static int niu_tx_channel_stop(struct niu *np, int channel)
4446 u64 val = nr64(TX_CS(channel));
4448 val |= TX_CS_STOP_N_GO;
4449 nw64(TX_CS(channel), val);
4451 return niu_tx_cs_sng_poll(np, channel);
4454 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4458 while (--limit > 0) {
4459 u64 val = nr64(TX_CS(channel));
4460 if (!(val & TX_CS_RST))
4466 static int niu_tx_channel_reset(struct niu *np, int channel)
4468 u64 val = nr64(TX_CS(channel));
4472 nw64(TX_CS(channel), val);
4474 err = niu_tx_cs_reset_poll(np, channel);
4476 nw64(TX_RING_KICK(channel), 0);
4481 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4485 nw64(TX_LOG_MASK1(channel), 0);
4486 nw64(TX_LOG_VAL1(channel), 0);
4487 nw64(TX_LOG_MASK2(channel), 0);
4488 nw64(TX_LOG_VAL2(channel), 0);
4489 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4490 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4491 nw64(TX_LOG_PAGE_HDL(channel), 0);
4493 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4494 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4495 nw64(TX_LOG_PAGE_VLD(channel), val);
4497 /* XXX TXDMA 32bit mode? XXX */
4502 static void niu_txc_enable_port(struct niu *np, int on)
4504 unsigned long flags;
4507 niu_lock_parent(np, flags);
4508 val = nr64(TXC_CONTROL);
4509 mask = (u64)1 << np->port;
4511 val |= TXC_CONTROL_ENABLE | mask;
4514 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4515 val &= ~TXC_CONTROL_ENABLE;
4517 nw64(TXC_CONTROL, val);
4518 niu_unlock_parent(np, flags);
4521 static void niu_txc_set_imask(struct niu *np, u64 imask)
4523 unsigned long flags;
4526 niu_lock_parent(np, flags);
4527 val = nr64(TXC_INT_MASK);
4528 val &= ~TXC_INT_MASK_VAL(np->port);
4529 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4530 niu_unlock_parent(np, flags);
4533 static void niu_txc_port_dma_enable(struct niu *np, int on)
4540 for (i = 0; i < np->num_tx_rings; i++)
4541 val |= (1 << np->tx_rings[i].tx_channel);
4543 nw64(TXC_PORT_DMA(np->port), val);
4546 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4548 int err, channel = rp->tx_channel;
4551 err = niu_tx_channel_stop(np, channel);
4555 err = niu_tx_channel_reset(np, channel);
4559 err = niu_tx_channel_lpage_init(np, channel);
4563 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4564 nw64(TX_ENT_MSK(channel), 0);
4566 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4567 TX_RNG_CFIG_STADDR)) {
4568 dev_err(np->device, PFX "%s: TX ring channel %d "
4569 "DMA addr (%llx) is not aligned.\n",
4570 np->dev->name, channel,
4571 (unsigned long long) rp->descr_dma);
4575 /* The length field in TX_RNG_CFIG is measured in 64-byte
4576 * blocks. rp->pending is the number of TX descriptors in
4577 * our ring, 8 bytes each, thus we divide by 8 bytes more
4578 * to get the proper value the chip wants.
4580 ring_len = (rp->pending / 8);
4582 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4584 nw64(TX_RNG_CFIG(channel), val);
4586 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4587 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4588 dev_err(np->device, PFX "%s: TX ring channel %d "
4589 "MBOX addr (%llx) is has illegal bits.\n",
4590 np->dev->name, channel,
4591 (unsigned long long) rp->mbox_dma);
4594 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4595 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4597 nw64(TX_CS(channel), 0);
4599 rp->last_pkt_cnt = 0;
4604 static void niu_init_rdc_groups(struct niu *np)
4606 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4607 int i, first_table_num = tp->first_table_num;
4609 for (i = 0; i < tp->num_tables; i++) {
4610 struct rdc_table *tbl = &tp->tables[i];
4611 int this_table = first_table_num + i;
4614 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4615 nw64(RDC_TBL(this_table, slot),
4616 tbl->rxdma_channel[slot]);
4619 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4622 static void niu_init_drr_weight(struct niu *np)
4624 int type = phy_decode(np->parent->port_phy, np->port);
4629 val = PT_DRR_WEIGHT_DEFAULT_10G;
4634 val = PT_DRR_WEIGHT_DEFAULT_1G;
4637 nw64(PT_DRR_WT(np->port), val);
4640 static int niu_init_hostinfo(struct niu *np)
4642 struct niu_parent *parent = np->parent;
4643 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4644 int i, err, num_alt = niu_num_alt_addr(np);
4645 int first_rdc_table = tp->first_table_num;
4647 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4651 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4655 for (i = 0; i < num_alt; i++) {
4656 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4664 static int niu_rx_channel_reset(struct niu *np, int channel)
4666 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4667 RXDMA_CFIG1_RST, 1000, 10,
4671 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4675 nw64(RX_LOG_MASK1(channel), 0);
4676 nw64(RX_LOG_VAL1(channel), 0);
4677 nw64(RX_LOG_MASK2(channel), 0);
4678 nw64(RX_LOG_VAL2(channel), 0);
4679 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4680 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4681 nw64(RX_LOG_PAGE_HDL(channel), 0);
4683 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4684 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4685 nw64(RX_LOG_PAGE_VLD(channel), val);
4690 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4694 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4695 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4696 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4697 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4698 nw64(RDC_RED_PARA(rp->rx_channel), val);
4701 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4705 switch (rp->rbr_block_size) {
4707 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4710 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4713 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4716 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4721 val |= RBR_CFIG_B_VLD2;
4722 switch (rp->rbr_sizes[2]) {
4724 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4727 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4730 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4733 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4739 val |= RBR_CFIG_B_VLD1;
4740 switch (rp->rbr_sizes[1]) {
4742 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4745 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4748 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4751 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4757 val |= RBR_CFIG_B_VLD0;
4758 switch (rp->rbr_sizes[0]) {
4760 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4763 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4766 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4769 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4780 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4782 u64 val = nr64(RXDMA_CFIG1(channel));
4786 val |= RXDMA_CFIG1_EN;
4788 val &= ~RXDMA_CFIG1_EN;
4789 nw64(RXDMA_CFIG1(channel), val);
4792 while (--limit > 0) {
4793 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4802 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4804 int err, channel = rp->rx_channel;
4807 err = niu_rx_channel_reset(np, channel);
4811 err = niu_rx_channel_lpage_init(np, channel);
4815 niu_rx_channel_wred_init(np, rp);
4817 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4818 nw64(RX_DMA_CTL_STAT(channel),
4819 (RX_DMA_CTL_STAT_MEX |
4820 RX_DMA_CTL_STAT_RCRTHRES |
4821 RX_DMA_CTL_STAT_RCRTO |
4822 RX_DMA_CTL_STAT_RBR_EMPTY));
4823 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4824 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4825 nw64(RBR_CFIG_A(channel),
4826 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4827 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4828 err = niu_compute_rbr_cfig_b(rp, &val);
4831 nw64(RBR_CFIG_B(channel), val);
4832 nw64(RCRCFIG_A(channel),
4833 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4834 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4835 nw64(RCRCFIG_B(channel),
4836 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4838 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4840 err = niu_enable_rx_channel(np, channel, 1);
4844 nw64(RBR_KICK(channel), rp->rbr_index);
4846 val = nr64(RX_DMA_CTL_STAT(channel));
4847 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4848 nw64(RX_DMA_CTL_STAT(channel), val);
4853 static int niu_init_rx_channels(struct niu *np)
4855 unsigned long flags;
4856 u64 seed = jiffies_64;
4859 niu_lock_parent(np, flags);
4860 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4861 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4862 niu_unlock_parent(np, flags);
4864 /* XXX RXDMA 32bit mode? XXX */
4866 niu_init_rdc_groups(np);
4867 niu_init_drr_weight(np);
4869 err = niu_init_hostinfo(np);
4873 for (i = 0; i < np->num_rx_rings; i++) {
4874 struct rx_ring_info *rp = &np->rx_rings[i];
4876 err = niu_init_one_rx_channel(np, rp);
4884 static int niu_set_ip_frag_rule(struct niu *np)
4886 struct niu_parent *parent = np->parent;
4887 struct niu_classifier *cp = &np->clas;
4888 struct niu_tcam_entry *tp;
4891 /* XXX fix this allocation scheme XXX */
4892 index = cp->tcam_index;
4893 tp = &parent->tcam[index];
4895 /* Note that the noport bit is the same in both ipv4 and
4896 * ipv6 format TCAM entries.
4898 memset(tp, 0, sizeof(*tp));
4899 tp->key[1] = TCAM_V4KEY1_NOPORT;
4900 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4901 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4902 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4903 err = tcam_write(np, index, tp->key, tp->key_mask);
4906 err = tcam_assoc_write(np, index, tp->assoc_data);
4913 static int niu_init_classifier_hw(struct niu *np)
4915 struct niu_parent *parent = np->parent;
4916 struct niu_classifier *cp = &np->clas;
4919 nw64(H1POLY, cp->h1_init);
4920 nw64(H2POLY, cp->h2_init);
4922 err = niu_init_hostinfo(np);
4926 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4927 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4929 vlan_tbl_write(np, i, np->port,
4930 vp->vlan_pref, vp->rdc_num);
4933 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4934 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4936 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4937 ap->rdc_num, ap->mac_pref);
4942 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4943 int index = i - CLASS_CODE_USER_PROG1;
4945 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4948 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4953 err = niu_set_ip_frag_rule(np);
4962 static int niu_zcp_write(struct niu *np, int index, u64 *data)
4964 nw64(ZCP_RAM_DATA0, data[0]);
4965 nw64(ZCP_RAM_DATA1, data[1]);
4966 nw64(ZCP_RAM_DATA2, data[2]);
4967 nw64(ZCP_RAM_DATA3, data[3]);
4968 nw64(ZCP_RAM_DATA4, data[4]);
4969 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4971 (ZCP_RAM_ACC_WRITE |
4972 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4973 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4975 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4979 static int niu_zcp_read(struct niu *np, int index, u64 *data)
4983 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4986 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4987 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4988 (unsigned long long) nr64(ZCP_RAM_ACC));
4994 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4995 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4997 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5000 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5001 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5002 (unsigned long long) nr64(ZCP_RAM_ACC));
5006 data[0] = nr64(ZCP_RAM_DATA0);
5007 data[1] = nr64(ZCP_RAM_DATA1);
5008 data[2] = nr64(ZCP_RAM_DATA2);
5009 data[3] = nr64(ZCP_RAM_DATA3);
5010 data[4] = nr64(ZCP_RAM_DATA4);
5015 static void niu_zcp_cfifo_reset(struct niu *np)
5017 u64 val = nr64(RESET_CFIFO);
5019 val |= RESET_CFIFO_RST(np->port);
5020 nw64(RESET_CFIFO, val);
5023 val &= ~RESET_CFIFO_RST(np->port);
5024 nw64(RESET_CFIFO, val);
5027 static int niu_init_zcp(struct niu *np)
5029 u64 data[5], rbuf[5];
5032 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5033 if (np->port == 0 || np->port == 1)
5034 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5036 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5038 max = NIU_CFIFO_ENTRIES;
5046 for (i = 0; i < max; i++) {
5047 err = niu_zcp_write(np, i, data);
5050 err = niu_zcp_read(np, i, rbuf);
5055 niu_zcp_cfifo_reset(np);
5056 nw64(CFIFO_ECC(np->port), 0);
5057 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5058 (void) nr64(ZCP_INT_STAT);
5059 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5064 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5066 u64 val = nr64_ipp(IPP_CFIG);
5068 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5069 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5070 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5071 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5072 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5073 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5074 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5075 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5078 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5080 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5081 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5082 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5083 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5084 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5085 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5088 static int niu_ipp_reset(struct niu *np)
5090 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5091 1000, 100, "IPP_CFIG");
5094 static int niu_init_ipp(struct niu *np)
5096 u64 data[5], rbuf[5], val;
5099 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5100 if (np->port == 0 || np->port == 1)
5101 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5103 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5105 max = NIU_DFIFO_ENTRIES;
5113 for (i = 0; i < max; i++) {
5114 niu_ipp_write(np, i, data);
5115 niu_ipp_read(np, i, rbuf);
5118 (void) nr64_ipp(IPP_INT_STAT);
5119 (void) nr64_ipp(IPP_INT_STAT);
5121 err = niu_ipp_reset(np);
5125 (void) nr64_ipp(IPP_PKT_DIS);
5126 (void) nr64_ipp(IPP_BAD_CS_CNT);
5127 (void) nr64_ipp(IPP_ECC);
5129 (void) nr64_ipp(IPP_INT_STAT);
5131 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5133 val = nr64_ipp(IPP_CFIG);
5134 val &= ~IPP_CFIG_IP_MAX_PKT;
5135 val |= (IPP_CFIG_IPP_ENABLE |
5136 IPP_CFIG_DFIFO_ECC_EN |
5137 IPP_CFIG_DROP_BAD_CRC |
5139 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5140 nw64_ipp(IPP_CFIG, val);
5145 static void niu_handle_led(struct niu *np, int status)
5148 val = nr64_mac(XMAC_CONFIG);
5150 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5151 (np->flags & NIU_FLAGS_FIBER) != 0) {
5153 val |= XMAC_CONFIG_LED_POLARITY;
5154 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5156 val |= XMAC_CONFIG_FORCE_LED_ON;
5157 val &= ~XMAC_CONFIG_LED_POLARITY;
5161 nw64_mac(XMAC_CONFIG, val);
5164 static void niu_init_xif_xmac(struct niu *np)
5166 struct niu_link_config *lp = &np->link_config;
5169 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5170 val = nr64(MIF_CONFIG);
5171 val |= MIF_CONFIG_ATCA_GE;
5172 nw64(MIF_CONFIG, val);
5175 val = nr64_mac(XMAC_CONFIG);
5176 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5178 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5180 if (lp->loopback_mode == LOOPBACK_MAC) {
5181 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5182 val |= XMAC_CONFIG_LOOPBACK;
5184 val &= ~XMAC_CONFIG_LOOPBACK;
5187 if (np->flags & NIU_FLAGS_10G) {
5188 val &= ~XMAC_CONFIG_LFS_DISABLE;
5190 val |= XMAC_CONFIG_LFS_DISABLE;
5191 if (!(np->flags & NIU_FLAGS_FIBER) &&
5192 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5193 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5195 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5198 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5200 if (lp->active_speed == SPEED_100)
5201 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5203 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5205 nw64_mac(XMAC_CONFIG, val);
5207 val = nr64_mac(XMAC_CONFIG);
5208 val &= ~XMAC_CONFIG_MODE_MASK;
5209 if (np->flags & NIU_FLAGS_10G) {
5210 val |= XMAC_CONFIG_MODE_XGMII;
5212 if (lp->active_speed == SPEED_100)
5213 val |= XMAC_CONFIG_MODE_MII;
5215 val |= XMAC_CONFIG_MODE_GMII;
5218 nw64_mac(XMAC_CONFIG, val);
5221 static void niu_init_xif_bmac(struct niu *np)
5223 struct niu_link_config *lp = &np->link_config;
5226 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5228 if (lp->loopback_mode == LOOPBACK_MAC)
5229 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5231 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5233 if (lp->active_speed == SPEED_1000)
5234 val |= BMAC_XIF_CONFIG_GMII_MODE;
5236 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5238 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5239 BMAC_XIF_CONFIG_LED_POLARITY);
5241 if (!(np->flags & NIU_FLAGS_10G) &&
5242 !(np->flags & NIU_FLAGS_FIBER) &&
5243 lp->active_speed == SPEED_100)
5244 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5246 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5248 nw64_mac(BMAC_XIF_CONFIG, val);
5251 static void niu_init_xif(struct niu *np)
5253 if (np->flags & NIU_FLAGS_XMAC)
5254 niu_init_xif_xmac(np);
5256 niu_init_xif_bmac(np);
5259 static void niu_pcs_mii_reset(struct niu *np)
5262 u64 val = nr64_pcs(PCS_MII_CTL);
5263 val |= PCS_MII_CTL_RST;
5264 nw64_pcs(PCS_MII_CTL, val);
5265 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5267 val = nr64_pcs(PCS_MII_CTL);
5271 static void niu_xpcs_reset(struct niu *np)
5274 u64 val = nr64_xpcs(XPCS_CONTROL1);
5275 val |= XPCS_CONTROL1_RESET;
5276 nw64_xpcs(XPCS_CONTROL1, val);
5277 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5279 val = nr64_xpcs(XPCS_CONTROL1);
5283 static int niu_init_pcs(struct niu *np)
5285 struct niu_link_config *lp = &np->link_config;
5288 switch (np->flags & (NIU_FLAGS_10G |
5290 NIU_FLAGS_XCVR_SERDES)) {
5291 case NIU_FLAGS_FIBER:
5293 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5294 nw64_pcs(PCS_DPATH_MODE, 0);
5295 niu_pcs_mii_reset(np);
5299 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5300 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5302 if (!(np->flags & NIU_FLAGS_XMAC))
5305 /* 10G copper or fiber */
5306 val = nr64_mac(XMAC_CONFIG);
5307 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5308 nw64_mac(XMAC_CONFIG, val);
5312 val = nr64_xpcs(XPCS_CONTROL1);
5313 if (lp->loopback_mode == LOOPBACK_PHY)
5314 val |= XPCS_CONTROL1_LOOPBACK;
5316 val &= ~XPCS_CONTROL1_LOOPBACK;
5317 nw64_xpcs(XPCS_CONTROL1, val);
5319 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5320 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5321 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5325 case NIU_FLAGS_XCVR_SERDES:
5327 niu_pcs_mii_reset(np);
5328 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5329 nw64_pcs(PCS_DPATH_MODE, 0);
5334 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5335 /* 1G RGMII FIBER */
5336 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5337 niu_pcs_mii_reset(np);
5347 static int niu_reset_tx_xmac(struct niu *np)
5349 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5350 (XTXMAC_SW_RST_REG_RS |
5351 XTXMAC_SW_RST_SOFT_RST),
5352 1000, 100, "XTXMAC_SW_RST");
5355 static int niu_reset_tx_bmac(struct niu *np)
5359 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5361 while (--limit >= 0) {
5362 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5367 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5368 "BTXMAC_SW_RST[%llx]\n",
5370 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5377 static int niu_reset_tx_mac(struct niu *np)
5379 if (np->flags & NIU_FLAGS_XMAC)
5380 return niu_reset_tx_xmac(np);
5382 return niu_reset_tx_bmac(np);
5385 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5389 val = nr64_mac(XMAC_MIN);
5390 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5391 XMAC_MIN_RX_MIN_PKT_SIZE);
5392 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5393 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5394 nw64_mac(XMAC_MIN, val);
5396 nw64_mac(XMAC_MAX, max);
5398 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5400 val = nr64_mac(XMAC_IPG);
5401 if (np->flags & NIU_FLAGS_10G) {
5402 val &= ~XMAC_IPG_IPG_XGMII;
5403 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5405 val &= ~XMAC_IPG_IPG_MII_GMII;
5406 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5408 nw64_mac(XMAC_IPG, val);
5410 val = nr64_mac(XMAC_CONFIG);
5411 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5412 XMAC_CONFIG_STRETCH_MODE |
5413 XMAC_CONFIG_VAR_MIN_IPG_EN |
5414 XMAC_CONFIG_TX_ENABLE);
5415 nw64_mac(XMAC_CONFIG, val);
5417 nw64_mac(TXMAC_FRM_CNT, 0);
5418 nw64_mac(TXMAC_BYTE_CNT, 0);
5421 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5425 nw64_mac(BMAC_MIN_FRAME, min);
5426 nw64_mac(BMAC_MAX_FRAME, max);
5428 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5429 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5430 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5432 val = nr64_mac(BTXMAC_CONFIG);
5433 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5434 BTXMAC_CONFIG_ENABLE);
5435 nw64_mac(BTXMAC_CONFIG, val);
5438 static void niu_init_tx_mac(struct niu *np)
5443 if (np->dev->mtu > ETH_DATA_LEN)
5448 /* The XMAC_MIN register only accepts values for TX min which
5449 * have the low 3 bits cleared.
5451 BUILD_BUG_ON(min & 0x7);
5453 if (np->flags & NIU_FLAGS_XMAC)
5454 niu_init_tx_xmac(np, min, max);
5456 niu_init_tx_bmac(np, min, max);
5459 static int niu_reset_rx_xmac(struct niu *np)
5463 nw64_mac(XRXMAC_SW_RST,
5464 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5466 while (--limit >= 0) {
5467 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5468 XRXMAC_SW_RST_SOFT_RST)))
5473 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5474 "XRXMAC_SW_RST[%llx]\n",
5476 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5483 static int niu_reset_rx_bmac(struct niu *np)
5487 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5489 while (--limit >= 0) {
5490 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5495 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5496 "BRXMAC_SW_RST[%llx]\n",
5498 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5505 static int niu_reset_rx_mac(struct niu *np)
5507 if (np->flags & NIU_FLAGS_XMAC)
5508 return niu_reset_rx_xmac(np);
5510 return niu_reset_rx_bmac(np);
5513 static void niu_init_rx_xmac(struct niu *np)
5515 struct niu_parent *parent = np->parent;
5516 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5517 int first_rdc_table = tp->first_table_num;
5521 nw64_mac(XMAC_ADD_FILT0, 0);
5522 nw64_mac(XMAC_ADD_FILT1, 0);
5523 nw64_mac(XMAC_ADD_FILT2, 0);
5524 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5525 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5526 for (i = 0; i < MAC_NUM_HASH; i++)
5527 nw64_mac(XMAC_HASH_TBL(i), 0);
5528 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5529 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5530 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5532 val = nr64_mac(XMAC_CONFIG);
5533 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5534 XMAC_CONFIG_PROMISCUOUS |
5535 XMAC_CONFIG_PROMISC_GROUP |
5536 XMAC_CONFIG_ERR_CHK_DIS |
5537 XMAC_CONFIG_RX_CRC_CHK_DIS |
5538 XMAC_CONFIG_RESERVED_MULTICAST |
5539 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5540 XMAC_CONFIG_ADDR_FILTER_EN |
5541 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5542 XMAC_CONFIG_STRIP_CRC |
5543 XMAC_CONFIG_PASS_FLOW_CTRL |
5544 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5545 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5546 nw64_mac(XMAC_CONFIG, val);
5548 nw64_mac(RXMAC_BT_CNT, 0);
5549 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5550 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5551 nw64_mac(RXMAC_FRAG_CNT, 0);
5552 nw64_mac(RXMAC_HIST_CNT1, 0);
5553 nw64_mac(RXMAC_HIST_CNT2, 0);
5554 nw64_mac(RXMAC_HIST_CNT3, 0);
5555 nw64_mac(RXMAC_HIST_CNT4, 0);
5556 nw64_mac(RXMAC_HIST_CNT5, 0);
5557 nw64_mac(RXMAC_HIST_CNT6, 0);
5558 nw64_mac(RXMAC_HIST_CNT7, 0);
5559 nw64_mac(RXMAC_MPSZER_CNT, 0);
5560 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5561 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5562 nw64_mac(LINK_FAULT_CNT, 0);
5565 static void niu_init_rx_bmac(struct niu *np)
5567 struct niu_parent *parent = np->parent;
5568 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5569 int first_rdc_table = tp->first_table_num;
5573 nw64_mac(BMAC_ADD_FILT0, 0);
5574 nw64_mac(BMAC_ADD_FILT1, 0);
5575 nw64_mac(BMAC_ADD_FILT2, 0);
5576 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5577 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5578 for (i = 0; i < MAC_NUM_HASH; i++)
5579 nw64_mac(BMAC_HASH_TBL(i), 0);
5580 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5581 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5582 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5584 val = nr64_mac(BRXMAC_CONFIG);
5585 val &= ~(BRXMAC_CONFIG_ENABLE |
5586 BRXMAC_CONFIG_STRIP_PAD |
5587 BRXMAC_CONFIG_STRIP_FCS |
5588 BRXMAC_CONFIG_PROMISC |
5589 BRXMAC_CONFIG_PROMISC_GRP |
5590 BRXMAC_CONFIG_ADDR_FILT_EN |
5591 BRXMAC_CONFIG_DISCARD_DIS);
5592 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5593 nw64_mac(BRXMAC_CONFIG, val);
5595 val = nr64_mac(BMAC_ADDR_CMPEN);
5596 val |= BMAC_ADDR_CMPEN_EN0;
5597 nw64_mac(BMAC_ADDR_CMPEN, val);
5600 static void niu_init_rx_mac(struct niu *np)
5602 niu_set_primary_mac(np, np->dev->dev_addr);
5604 if (np->flags & NIU_FLAGS_XMAC)
5605 niu_init_rx_xmac(np);
5607 niu_init_rx_bmac(np);
5610 static void niu_enable_tx_xmac(struct niu *np, int on)
5612 u64 val = nr64_mac(XMAC_CONFIG);
5615 val |= XMAC_CONFIG_TX_ENABLE;
5617 val &= ~XMAC_CONFIG_TX_ENABLE;
5618 nw64_mac(XMAC_CONFIG, val);
5621 static void niu_enable_tx_bmac(struct niu *np, int on)
5623 u64 val = nr64_mac(BTXMAC_CONFIG);
5626 val |= BTXMAC_CONFIG_ENABLE;
5628 val &= ~BTXMAC_CONFIG_ENABLE;
5629 nw64_mac(BTXMAC_CONFIG, val);
5632 static void niu_enable_tx_mac(struct niu *np, int on)
5634 if (np->flags & NIU_FLAGS_XMAC)
5635 niu_enable_tx_xmac(np, on);
5637 niu_enable_tx_bmac(np, on);
5640 static void niu_enable_rx_xmac(struct niu *np, int on)
5642 u64 val = nr64_mac(XMAC_CONFIG);
5644 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5645 XMAC_CONFIG_PROMISCUOUS);
5647 if (np->flags & NIU_FLAGS_MCAST)
5648 val |= XMAC_CONFIG_HASH_FILTER_EN;
5649 if (np->flags & NIU_FLAGS_PROMISC)
5650 val |= XMAC_CONFIG_PROMISCUOUS;
5653 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5655 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5656 nw64_mac(XMAC_CONFIG, val);
5659 static void niu_enable_rx_bmac(struct niu *np, int on)
5661 u64 val = nr64_mac(BRXMAC_CONFIG);
5663 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5664 BRXMAC_CONFIG_PROMISC);
5666 if (np->flags & NIU_FLAGS_MCAST)
5667 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5668 if (np->flags & NIU_FLAGS_PROMISC)
5669 val |= BRXMAC_CONFIG_PROMISC;
5672 val |= BRXMAC_CONFIG_ENABLE;
5674 val &= ~BRXMAC_CONFIG_ENABLE;
5675 nw64_mac(BRXMAC_CONFIG, val);
5678 static void niu_enable_rx_mac(struct niu *np, int on)
5680 if (np->flags & NIU_FLAGS_XMAC)
5681 niu_enable_rx_xmac(np, on);
5683 niu_enable_rx_bmac(np, on);
5686 static int niu_init_mac(struct niu *np)
5691 err = niu_init_pcs(np);
5695 err = niu_reset_tx_mac(np);
5698 niu_init_tx_mac(np);
5699 err = niu_reset_rx_mac(np);
5702 niu_init_rx_mac(np);
5704 /* This looks hookey but the RX MAC reset we just did will
5705 * undo some of the state we setup in niu_init_tx_mac() so we
5706 * have to call it again. In particular, the RX MAC reset will
5707 * set the XMAC_MAX register back to it's default value.
5709 niu_init_tx_mac(np);
5710 niu_enable_tx_mac(np, 1);
5712 niu_enable_rx_mac(np, 1);
5717 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5719 (void) niu_tx_channel_stop(np, rp->tx_channel);
5722 static void niu_stop_tx_channels(struct niu *np)
5726 for (i = 0; i < np->num_tx_rings; i++) {
5727 struct tx_ring_info *rp = &np->tx_rings[i];
5729 niu_stop_one_tx_channel(np, rp);
5733 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5735 (void) niu_tx_channel_reset(np, rp->tx_channel);
5738 static void niu_reset_tx_channels(struct niu *np)
5742 for (i = 0; i < np->num_tx_rings; i++) {
5743 struct tx_ring_info *rp = &np->tx_rings[i];
5745 niu_reset_one_tx_channel(np, rp);
5749 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5751 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5754 static void niu_stop_rx_channels(struct niu *np)
5758 for (i = 0; i < np->num_rx_rings; i++) {
5759 struct rx_ring_info *rp = &np->rx_rings[i];
5761 niu_stop_one_rx_channel(np, rp);
5765 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5767 int channel = rp->rx_channel;
5769 (void) niu_rx_channel_reset(np, channel);
5770 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5771 nw64(RX_DMA_CTL_STAT(channel), 0);
5772 (void) niu_enable_rx_channel(np, channel, 0);
5775 static void niu_reset_rx_channels(struct niu *np)
5779 for (i = 0; i < np->num_rx_rings; i++) {
5780 struct rx_ring_info *rp = &np->rx_rings[i];
5782 niu_reset_one_rx_channel(np, rp);
5786 static void niu_disable_ipp(struct niu *np)
5791 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5792 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5794 while (--limit >= 0 && (rd != wr)) {
5795 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5796 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5799 (rd != 0 && wr != 1)) {
5800 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5801 "rd_ptr[%llx] wr_ptr[%llx]\n",
5803 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5804 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5807 val = nr64_ipp(IPP_CFIG);
5808 val &= ~(IPP_CFIG_IPP_ENABLE |
5809 IPP_CFIG_DFIFO_ECC_EN |
5810 IPP_CFIG_DROP_BAD_CRC |
5812 nw64_ipp(IPP_CFIG, val);
5814 (void) niu_ipp_reset(np);
5817 static int niu_init_hw(struct niu *np)
5821 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5822 niu_txc_enable_port(np, 1);
5823 niu_txc_port_dma_enable(np, 1);
5824 niu_txc_set_imask(np, 0);
5826 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5827 for (i = 0; i < np->num_tx_rings; i++) {
5828 struct tx_ring_info *rp = &np->tx_rings[i];
5830 err = niu_init_one_tx_channel(np, rp);
5835 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5836 err = niu_init_rx_channels(np);
5838 goto out_uninit_tx_channels;
5840 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5841 err = niu_init_classifier_hw(np);
5843 goto out_uninit_rx_channels;
5845 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5846 err = niu_init_zcp(np);
5848 goto out_uninit_rx_channels;
5850 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5851 err = niu_init_ipp(np);
5853 goto out_uninit_rx_channels;
5855 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5856 err = niu_init_mac(np);
5858 goto out_uninit_ipp;
5863 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5864 niu_disable_ipp(np);
5866 out_uninit_rx_channels:
5867 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5868 niu_stop_rx_channels(np);
5869 niu_reset_rx_channels(np);
5871 out_uninit_tx_channels:
5872 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5873 niu_stop_tx_channels(np);
5874 niu_reset_tx_channels(np);
5879 static void niu_stop_hw(struct niu *np)
5881 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5882 niu_enable_interrupts(np, 0);
5884 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5885 niu_enable_rx_mac(np, 0);
5887 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5888 niu_disable_ipp(np);
5890 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5891 niu_stop_tx_channels(np);
5893 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5894 niu_stop_rx_channels(np);
5896 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5897 niu_reset_tx_channels(np);
5899 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5900 niu_reset_rx_channels(np);
5903 static void niu_set_irq_name(struct niu *np)
5905 int port = np->port;
5908 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
5911 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
5912 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
5916 for (i = 0; i < np->num_ldg - j; i++) {
5917 if (i < np->num_rx_rings)
5918 sprintf(np->irq_name[i+j], "%s-rx-%d",
5920 else if (i < np->num_tx_rings + np->num_rx_rings)
5921 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
5922 i - np->num_rx_rings);
5926 static int niu_request_irq(struct niu *np)
5930 niu_set_irq_name(np);
5933 for (i = 0; i < np->num_ldg; i++) {
5934 struct niu_ldg *lp = &np->ldg[i];
5936 err = request_irq(lp->irq, niu_interrupt,
5937 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5938 np->irq_name[i], lp);
5947 for (j = 0; j < i; j++) {
5948 struct niu_ldg *lp = &np->ldg[j];
5950 free_irq(lp->irq, lp);
5955 static void niu_free_irq(struct niu *np)
5959 for (i = 0; i < np->num_ldg; i++) {
5960 struct niu_ldg *lp = &np->ldg[i];
5962 free_irq(lp->irq, lp);
5966 static void niu_enable_napi(struct niu *np)
5970 for (i = 0; i < np->num_ldg; i++)
5971 napi_enable(&np->ldg[i].napi);
5974 static void niu_disable_napi(struct niu *np)
5978 for (i = 0; i < np->num_ldg; i++)
5979 napi_disable(&np->ldg[i].napi);
5982 static int niu_open(struct net_device *dev)
5984 struct niu *np = netdev_priv(dev);
5987 netif_carrier_off(dev);
5989 err = niu_alloc_channels(np);
5993 err = niu_enable_interrupts(np, 0);
5995 goto out_free_channels;
5997 err = niu_request_irq(np);
5999 goto out_free_channels;
6001 niu_enable_napi(np);
6003 spin_lock_irq(&np->lock);
6005 err = niu_init_hw(np);
6007 init_timer(&np->timer);
6008 np->timer.expires = jiffies + HZ;
6009 np->timer.data = (unsigned long) np;
6010 np->timer.function = niu_timer;
6012 err = niu_enable_interrupts(np, 1);
6017 spin_unlock_irq(&np->lock);
6020 niu_disable_napi(np);
6024 netif_tx_start_all_queues(dev);
6026 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6027 netif_carrier_on(dev);
6029 add_timer(&np->timer);
6037 niu_free_channels(np);
6043 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6045 cancel_work_sync(&np->reset_task);
6047 niu_disable_napi(np);
6048 netif_tx_stop_all_queues(dev);
6050 del_timer_sync(&np->timer);
6052 spin_lock_irq(&np->lock);
6056 spin_unlock_irq(&np->lock);
6059 static int niu_close(struct net_device *dev)
6061 struct niu *np = netdev_priv(dev);
6063 niu_full_shutdown(np, dev);
6067 niu_free_channels(np);
6069 niu_handle_led(np, 0);
6074 static void niu_sync_xmac_stats(struct niu *np)
6076 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6078 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6079 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6081 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6082 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6083 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6084 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6085 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6086 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6087 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6088 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6089 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6090 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6091 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6092 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6093 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6094 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6095 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6096 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6099 static void niu_sync_bmac_stats(struct niu *np)
6101 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6103 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6104 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6106 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6107 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6108 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6109 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6112 static void niu_sync_mac_stats(struct niu *np)
6114 if (np->flags & NIU_FLAGS_XMAC)
6115 niu_sync_xmac_stats(np);
6117 niu_sync_bmac_stats(np);
6120 static void niu_get_rx_stats(struct niu *np)
6122 unsigned long pkts, dropped, errors, bytes;
6125 pkts = dropped = errors = bytes = 0;
6126 for (i = 0; i < np->num_rx_rings; i++) {
6127 struct rx_ring_info *rp = &np->rx_rings[i];
6129 niu_sync_rx_discard_stats(np, rp, 0);
6131 pkts += rp->rx_packets;
6132 bytes += rp->rx_bytes;
6133 dropped += rp->rx_dropped;
6134 errors += rp->rx_errors;
6136 np->dev->stats.rx_packets = pkts;
6137 np->dev->stats.rx_bytes = bytes;
6138 np->dev->stats.rx_dropped = dropped;
6139 np->dev->stats.rx_errors = errors;
6142 static void niu_get_tx_stats(struct niu *np)
6144 unsigned long pkts, errors, bytes;
6147 pkts = errors = bytes = 0;
6148 for (i = 0; i < np->num_tx_rings; i++) {
6149 struct tx_ring_info *rp = &np->tx_rings[i];
6151 pkts += rp->tx_packets;
6152 bytes += rp->tx_bytes;
6153 errors += rp->tx_errors;
6155 np->dev->stats.tx_packets = pkts;
6156 np->dev->stats.tx_bytes = bytes;
6157 np->dev->stats.tx_errors = errors;
6160 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6162 struct niu *np = netdev_priv(dev);
6164 niu_get_rx_stats(np);
6165 niu_get_tx_stats(np);
6170 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6174 for (i = 0; i < 16; i++)
6175 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6178 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6182 for (i = 0; i < 16; i++)
6183 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6186 static void niu_load_hash(struct niu *np, u16 *hash)
6188 if (np->flags & NIU_FLAGS_XMAC)
6189 niu_load_hash_xmac(np, hash);
6191 niu_load_hash_bmac(np, hash);
6194 static void niu_set_rx_mode(struct net_device *dev)
6196 struct niu *np = netdev_priv(dev);
6197 int i, alt_cnt, err;
6198 struct dev_addr_list *addr;
6199 unsigned long flags;
6200 u16 hash[16] = { 0, };
6202 spin_lock_irqsave(&np->lock, flags);
6203 niu_enable_rx_mac(np, 0);
6205 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6206 if (dev->flags & IFF_PROMISC)
6207 np->flags |= NIU_FLAGS_PROMISC;
6208 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6209 np->flags |= NIU_FLAGS_MCAST;
6211 alt_cnt = dev->uc_count;
6212 if (alt_cnt > niu_num_alt_addr(np)) {
6214 np->flags |= NIU_FLAGS_PROMISC;
6220 for (addr = dev->uc_list; addr; addr = addr->next) {
6221 err = niu_set_alt_mac(np, index,
6224 printk(KERN_WARNING PFX "%s: Error %d "
6225 "adding alt mac %d\n",
6226 dev->name, err, index);
6227 err = niu_enable_alt_mac(np, index, 1);
6229 printk(KERN_WARNING PFX "%s: Error %d "
6230 "enabling alt mac %d\n",
6231 dev->name, err, index);
6237 if (np->flags & NIU_FLAGS_XMAC)
6241 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6242 err = niu_enable_alt_mac(np, i, 0);
6244 printk(KERN_WARNING PFX "%s: Error %d "
6245 "disabling alt mac %d\n",
6249 if (dev->flags & IFF_ALLMULTI) {
6250 for (i = 0; i < 16; i++)
6252 } else if (dev->mc_count > 0) {
6253 for (addr = dev->mc_list; addr; addr = addr->next) {
6254 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6257 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6261 if (np->flags & NIU_FLAGS_MCAST)
6262 niu_load_hash(np, hash);
6264 niu_enable_rx_mac(np, 1);
6265 spin_unlock_irqrestore(&np->lock, flags);
6268 static int niu_set_mac_addr(struct net_device *dev, void *p)
6270 struct niu *np = netdev_priv(dev);
6271 struct sockaddr *addr = p;
6272 unsigned long flags;
6274 if (!is_valid_ether_addr(addr->sa_data))
6277 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6279 if (!netif_running(dev))
6282 spin_lock_irqsave(&np->lock, flags);
6283 niu_enable_rx_mac(np, 0);
6284 niu_set_primary_mac(np, dev->dev_addr);
6285 niu_enable_rx_mac(np, 1);
6286 spin_unlock_irqrestore(&np->lock, flags);
6291 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6296 static void niu_netif_stop(struct niu *np)
6298 np->dev->trans_start = jiffies; /* prevent tx timeout */
6300 niu_disable_napi(np);
6302 netif_tx_disable(np->dev);
6305 static void niu_netif_start(struct niu *np)
6307 /* NOTE: unconditional netif_wake_queue is only appropriate
6308 * so long as all callers are assured to have free tx slots
6309 * (such as after niu_init_hw).
6311 netif_tx_wake_all_queues(np->dev);
6313 niu_enable_napi(np);
6315 niu_enable_interrupts(np, 1);
6318 static void niu_reset_buffers(struct niu *np)
6323 for (i = 0; i < np->num_rx_rings; i++) {
6324 struct rx_ring_info *rp = &np->rx_rings[i];
6326 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6329 page = rp->rxhash[j];
6332 (struct page *) page->mapping;
6333 u64 base = page->index;
6334 base = base >> RBR_DESCR_ADDR_SHIFT;
6335 rp->rbr[k++] = cpu_to_le32(base);
6339 for (; k < MAX_RBR_RING_SIZE; k++) {
6340 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6345 rp->rbr_index = rp->rbr_table_size - 1;
6347 rp->rbr_pending = 0;
6348 rp->rbr_refill_pending = 0;
6352 for (i = 0; i < np->num_tx_rings; i++) {
6353 struct tx_ring_info *rp = &np->tx_rings[i];
6355 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6356 if (rp->tx_buffs[j].skb)
6357 (void) release_tx_packet(np, rp, j);
6360 rp->pending = MAX_TX_RING_SIZE;
6368 static void niu_reset_task(struct work_struct *work)
6370 struct niu *np = container_of(work, struct niu, reset_task);
6371 unsigned long flags;
6374 spin_lock_irqsave(&np->lock, flags);
6375 if (!netif_running(np->dev)) {
6376 spin_unlock_irqrestore(&np->lock, flags);
6380 spin_unlock_irqrestore(&np->lock, flags);
6382 del_timer_sync(&np->timer);
6386 spin_lock_irqsave(&np->lock, flags);
6390 spin_unlock_irqrestore(&np->lock, flags);
6392 niu_reset_buffers(np);
6394 spin_lock_irqsave(&np->lock, flags);
6396 err = niu_init_hw(np);
6398 np->timer.expires = jiffies + HZ;
6399 add_timer(&np->timer);
6400 niu_netif_start(np);
6403 spin_unlock_irqrestore(&np->lock, flags);
6406 static void niu_tx_timeout(struct net_device *dev)
6408 struct niu *np = netdev_priv(dev);
6410 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6413 schedule_work(&np->reset_task);
6416 static void niu_set_txd(struct tx_ring_info *rp, int index,
6417 u64 mapping, u64 len, u64 mark,
6420 __le64 *desc = &rp->descr[index];
6422 *desc = cpu_to_le64(mark |
6423 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6424 (len << TX_DESC_TR_LEN_SHIFT) |
6425 (mapping & TX_DESC_SAD));
6428 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6429 u64 pad_bytes, u64 len)
6431 u16 eth_proto, eth_proto_inner;
6432 u64 csum_bits, l3off, ihl, ret;
6436 eth_proto = be16_to_cpu(ehdr->h_proto);
6437 eth_proto_inner = eth_proto;
6438 if (eth_proto == ETH_P_8021Q) {
6439 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6440 __be16 val = vp->h_vlan_encapsulated_proto;
6442 eth_proto_inner = be16_to_cpu(val);
6446 switch (skb->protocol) {
6447 case __constant_htons(ETH_P_IP):
6448 ip_proto = ip_hdr(skb)->protocol;
6449 ihl = ip_hdr(skb)->ihl;
6451 case __constant_htons(ETH_P_IPV6):
6452 ip_proto = ipv6_hdr(skb)->nexthdr;
6461 csum_bits = TXHDR_CSUM_NONE;
6462 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6465 csum_bits = (ip_proto == IPPROTO_TCP ?
6467 (ip_proto == IPPROTO_UDP ?
6468 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6470 start = skb_transport_offset(skb) -
6471 (pad_bytes + sizeof(struct tx_pkt_hdr));
6472 stuff = start + skb->csum_offset;
6474 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6475 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6478 l3off = skb_network_offset(skb) -
6479 (pad_bytes + sizeof(struct tx_pkt_hdr));
6481 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6482 (len << TXHDR_LEN_SHIFT) |
6483 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6484 (ihl << TXHDR_IHL_SHIFT) |
6485 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6486 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6487 (ipv6 ? TXHDR_IP_VER : 0) |
6493 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6495 struct niu *np = netdev_priv(dev);
6496 unsigned long align, headroom;
6497 struct netdev_queue *txq;
6498 struct tx_ring_info *rp;
6499 struct tx_pkt_hdr *tp;
6500 unsigned int len, nfg;
6501 struct ethhdr *ehdr;
6505 i = skb_get_queue_mapping(skb);
6506 rp = &np->tx_rings[i];
6507 txq = netdev_get_tx_queue(dev, i);
6509 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6510 netif_tx_stop_queue(txq);
6511 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6512 "queue awake!\n", dev->name);
6514 return NETDEV_TX_BUSY;
6517 if (skb->len < ETH_ZLEN) {
6518 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6520 if (skb_pad(skb, pad_bytes))
6522 skb_put(skb, pad_bytes);
6525 len = sizeof(struct tx_pkt_hdr) + 15;
6526 if (skb_headroom(skb) < len) {
6527 struct sk_buff *skb_new;
6529 skb_new = skb_realloc_headroom(skb, len);
6539 align = ((unsigned long) skb->data & (16 - 1));
6540 headroom = align + sizeof(struct tx_pkt_hdr);
6542 ehdr = (struct ethhdr *) skb->data;
6543 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6545 len = skb->len - sizeof(struct tx_pkt_hdr);
6546 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6549 len = skb_headlen(skb);
6550 mapping = np->ops->map_single(np->device, skb->data,
6551 len, DMA_TO_DEVICE);
6555 rp->tx_buffs[prod].skb = skb;
6556 rp->tx_buffs[prod].mapping = mapping;
6559 if (++rp->mark_counter == rp->mark_freq) {
6560 rp->mark_counter = 0;
6561 mrk |= TX_DESC_MARK;
6566 nfg = skb_shinfo(skb)->nr_frags;
6568 tlen -= MAX_TX_DESC_LEN;
6573 unsigned int this_len = len;
6575 if (this_len > MAX_TX_DESC_LEN)
6576 this_len = MAX_TX_DESC_LEN;
6578 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6581 prod = NEXT_TX(rp, prod);
6582 mapping += this_len;
6586 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6587 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6590 mapping = np->ops->map_page(np->device, frag->page,
6591 frag->page_offset, len,
6594 rp->tx_buffs[prod].skb = NULL;
6595 rp->tx_buffs[prod].mapping = mapping;
6597 niu_set_txd(rp, prod, mapping, len, 0, 0);
6599 prod = NEXT_TX(rp, prod);
6602 if (prod < rp->prod)
6603 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6606 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6608 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6609 netif_tx_stop_queue(txq);
6610 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6611 netif_tx_wake_queue(txq);
6614 dev->trans_start = jiffies;
6617 return NETDEV_TX_OK;
6625 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6627 struct niu *np = netdev_priv(dev);
6628 int err, orig_jumbo, new_jumbo;
6630 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6633 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6634 new_jumbo = (new_mtu > ETH_DATA_LEN);
6638 if (!netif_running(dev) ||
6639 (orig_jumbo == new_jumbo))
6642 niu_full_shutdown(np, dev);
6644 niu_free_channels(np);
6646 niu_enable_napi(np);
6648 err = niu_alloc_channels(np);
6652 spin_lock_irq(&np->lock);
6654 err = niu_init_hw(np);
6656 init_timer(&np->timer);
6657 np->timer.expires = jiffies + HZ;
6658 np->timer.data = (unsigned long) np;
6659 np->timer.function = niu_timer;
6661 err = niu_enable_interrupts(np, 1);
6666 spin_unlock_irq(&np->lock);
6669 netif_tx_start_all_queues(dev);
6670 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6671 netif_carrier_on(dev);
6673 add_timer(&np->timer);
6679 static void niu_get_drvinfo(struct net_device *dev,
6680 struct ethtool_drvinfo *info)
6682 struct niu *np = netdev_priv(dev);
6683 struct niu_vpd *vpd = &np->vpd;
6685 strcpy(info->driver, DRV_MODULE_NAME);
6686 strcpy(info->version, DRV_MODULE_VERSION);
6687 sprintf(info->fw_version, "%d.%d",
6688 vpd->fcode_major, vpd->fcode_minor);
6689 if (np->parent->plat_type != PLAT_TYPE_NIU)
6690 strcpy(info->bus_info, pci_name(np->pdev));
6693 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6695 struct niu *np = netdev_priv(dev);
6696 struct niu_link_config *lp;
6698 lp = &np->link_config;
6700 memset(cmd, 0, sizeof(*cmd));
6701 cmd->phy_address = np->phy_addr;
6702 cmd->supported = lp->supported;
6703 cmd->advertising = lp->advertising;
6704 cmd->autoneg = lp->autoneg;
6705 cmd->speed = lp->active_speed;
6706 cmd->duplex = lp->active_duplex;
6711 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6716 static u32 niu_get_msglevel(struct net_device *dev)
6718 struct niu *np = netdev_priv(dev);
6719 return np->msg_enable;
6722 static void niu_set_msglevel(struct net_device *dev, u32 value)
6724 struct niu *np = netdev_priv(dev);
6725 np->msg_enable = value;
6728 static int niu_get_eeprom_len(struct net_device *dev)
6730 struct niu *np = netdev_priv(dev);
6732 return np->eeprom_len;
6735 static int niu_get_eeprom(struct net_device *dev,
6736 struct ethtool_eeprom *eeprom, u8 *data)
6738 struct niu *np = netdev_priv(dev);
6739 u32 offset, len, val;
6741 offset = eeprom->offset;
6744 if (offset + len < offset)
6746 if (offset >= np->eeprom_len)
6748 if (offset + len > np->eeprom_len)
6749 len = eeprom->len = np->eeprom_len - offset;
6752 u32 b_offset, b_count;
6754 b_offset = offset & 3;
6755 b_count = 4 - b_offset;
6759 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6760 memcpy(data, ((char *)&val) + b_offset, b_count);
6766 val = nr64(ESPC_NCR(offset / 4));
6767 memcpy(data, &val, 4);
6773 val = nr64(ESPC_NCR(offset / 4));
6774 memcpy(data, &val, len);
6779 static int niu_ethflow_to_class(int flow_type, u64 *class)
6781 switch (flow_type) {
6783 *class = CLASS_CODE_TCP_IPV4;
6786 *class = CLASS_CODE_UDP_IPV4;
6788 case AH_ESP_V4_FLOW:
6789 *class = CLASS_CODE_AH_ESP_IPV4;
6792 *class = CLASS_CODE_SCTP_IPV4;
6795 *class = CLASS_CODE_TCP_IPV6;
6798 *class = CLASS_CODE_UDP_IPV6;
6800 case AH_ESP_V6_FLOW:
6801 *class = CLASS_CODE_AH_ESP_IPV6;
6804 *class = CLASS_CODE_SCTP_IPV6;
6813 static u64 niu_flowkey_to_ethflow(u64 flow_key)
6817 if (flow_key & FLOW_KEY_PORT)
6818 ethflow |= RXH_DEV_PORT;
6819 if (flow_key & FLOW_KEY_L2DA)
6820 ethflow |= RXH_L2DA;
6821 if (flow_key & FLOW_KEY_VLAN)
6822 ethflow |= RXH_VLAN;
6823 if (flow_key & FLOW_KEY_IPSA)
6824 ethflow |= RXH_IP_SRC;
6825 if (flow_key & FLOW_KEY_IPDA)
6826 ethflow |= RXH_IP_DST;
6827 if (flow_key & FLOW_KEY_PROTO)
6828 ethflow |= RXH_L3_PROTO;
6829 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6830 ethflow |= RXH_L4_B_0_1;
6831 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6832 ethflow |= RXH_L4_B_2_3;
6838 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6842 if (ethflow & RXH_DEV_PORT)
6843 key |= FLOW_KEY_PORT;
6844 if (ethflow & RXH_L2DA)
6845 key |= FLOW_KEY_L2DA;
6846 if (ethflow & RXH_VLAN)
6847 key |= FLOW_KEY_VLAN;
6848 if (ethflow & RXH_IP_SRC)
6849 key |= FLOW_KEY_IPSA;
6850 if (ethflow & RXH_IP_DST)
6851 key |= FLOW_KEY_IPDA;
6852 if (ethflow & RXH_L3_PROTO)
6853 key |= FLOW_KEY_PROTO;
6854 if (ethflow & RXH_L4_B_0_1)
6855 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6856 if (ethflow & RXH_L4_B_2_3)
6857 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6865 static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6867 struct niu *np = netdev_priv(dev);
6872 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6875 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6877 cmd->data = RXH_DISCARD;
6880 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6881 CLASS_CODE_USER_PROG1]);
6885 static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6887 struct niu *np = netdev_priv(dev);
6890 unsigned long flags;
6892 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6895 if (class < CLASS_CODE_USER_PROG1 ||
6896 class > CLASS_CODE_SCTP_IPV6)
6899 if (cmd->data & RXH_DISCARD) {
6900 niu_lock_parent(np, flags);
6901 flow_key = np->parent->tcam_key[class -
6902 CLASS_CODE_USER_PROG1];
6903 flow_key |= TCAM_KEY_DISC;
6904 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6905 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6906 niu_unlock_parent(np, flags);
6909 /* Discard was set before, but is not set now */
6910 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6912 niu_lock_parent(np, flags);
6913 flow_key = np->parent->tcam_key[class -
6914 CLASS_CODE_USER_PROG1];
6915 flow_key &= ~TCAM_KEY_DISC;
6916 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6918 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6920 niu_unlock_parent(np, flags);
6924 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6927 niu_lock_parent(np, flags);
6928 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6929 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6930 niu_unlock_parent(np, flags);
6935 static const struct {
6936 const char string[ETH_GSTRING_LEN];
6937 } niu_xmac_stat_keys[] = {
6940 { "tx_fifo_errors" },
6941 { "tx_overflow_errors" },
6942 { "tx_max_pkt_size_errors" },
6943 { "tx_underflow_errors" },
6944 { "rx_local_faults" },
6945 { "rx_remote_faults" },
6946 { "rx_link_faults" },
6947 { "rx_align_errors" },
6959 { "rx_code_violations" },
6960 { "rx_len_errors" },
6961 { "rx_crc_errors" },
6962 { "rx_underflows" },
6964 { "pause_off_state" },
6965 { "pause_on_state" },
6966 { "pause_received" },
6969 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6971 static const struct {
6972 const char string[ETH_GSTRING_LEN];
6973 } niu_bmac_stat_keys[] = {
6974 { "tx_underflow_errors" },
6975 { "tx_max_pkt_size_errors" },
6980 { "rx_align_errors" },
6981 { "rx_crc_errors" },
6982 { "rx_len_errors" },
6983 { "pause_off_state" },
6984 { "pause_on_state" },
6985 { "pause_received" },
6988 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6990 static const struct {
6991 const char string[ETH_GSTRING_LEN];
6992 } niu_rxchan_stat_keys[] = {
7000 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7002 static const struct {
7003 const char string[ETH_GSTRING_LEN];
7004 } niu_txchan_stat_keys[] = {
7011 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7013 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7015 struct niu *np = netdev_priv(dev);
7018 if (stringset != ETH_SS_STATS)
7021 if (np->flags & NIU_FLAGS_XMAC) {
7022 memcpy(data, niu_xmac_stat_keys,
7023 sizeof(niu_xmac_stat_keys));
7024 data += sizeof(niu_xmac_stat_keys);
7026 memcpy(data, niu_bmac_stat_keys,
7027 sizeof(niu_bmac_stat_keys));
7028 data += sizeof(niu_bmac_stat_keys);
7030 for (i = 0; i < np->num_rx_rings; i++) {
7031 memcpy(data, niu_rxchan_stat_keys,
7032 sizeof(niu_rxchan_stat_keys));
7033 data += sizeof(niu_rxchan_stat_keys);
7035 for (i = 0; i < np->num_tx_rings; i++) {
7036 memcpy(data, niu_txchan_stat_keys,
7037 sizeof(niu_txchan_stat_keys));
7038 data += sizeof(niu_txchan_stat_keys);
7042 static int niu_get_stats_count(struct net_device *dev)
7044 struct niu *np = netdev_priv(dev);
7046 return ((np->flags & NIU_FLAGS_XMAC ?
7047 NUM_XMAC_STAT_KEYS :
7048 NUM_BMAC_STAT_KEYS) +
7049 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7050 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7053 static void niu_get_ethtool_stats(struct net_device *dev,
7054 struct ethtool_stats *stats, u64 *data)
7056 struct niu *np = netdev_priv(dev);
7059 niu_sync_mac_stats(np);
7060 if (np->flags & NIU_FLAGS_XMAC) {
7061 memcpy(data, &np->mac_stats.xmac,
7062 sizeof(struct niu_xmac_stats));
7063 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7065 memcpy(data, &np->mac_stats.bmac,
7066 sizeof(struct niu_bmac_stats));
7067 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7069 for (i = 0; i < np->num_rx_rings; i++) {
7070 struct rx_ring_info *rp = &np->rx_rings[i];
7072 niu_sync_rx_discard_stats(np, rp, 0);
7074 data[0] = rp->rx_channel;
7075 data[1] = rp->rx_packets;
7076 data[2] = rp->rx_bytes;
7077 data[3] = rp->rx_dropped;
7078 data[4] = rp->rx_errors;
7081 for (i = 0; i < np->num_tx_rings; i++) {
7082 struct tx_ring_info *rp = &np->tx_rings[i];
7084 data[0] = rp->tx_channel;
7085 data[1] = rp->tx_packets;
7086 data[2] = rp->tx_bytes;
7087 data[3] = rp->tx_errors;
7092 static u64 niu_led_state_save(struct niu *np)
7094 if (np->flags & NIU_FLAGS_XMAC)
7095 return nr64_mac(XMAC_CONFIG);
7097 return nr64_mac(BMAC_XIF_CONFIG);
7100 static void niu_led_state_restore(struct niu *np, u64 val)
7102 if (np->flags & NIU_FLAGS_XMAC)
7103 nw64_mac(XMAC_CONFIG, val);
7105 nw64_mac(BMAC_XIF_CONFIG, val);
7108 static void niu_force_led(struct niu *np, int on)
7112 if (np->flags & NIU_FLAGS_XMAC) {
7114 bit = XMAC_CONFIG_FORCE_LED_ON;
7116 reg = BMAC_XIF_CONFIG;
7117 bit = BMAC_XIF_CONFIG_LINK_LED;
7120 val = nr64_mac(reg);
7128 static int niu_phys_id(struct net_device *dev, u32 data)
7130 struct niu *np = netdev_priv(dev);
7134 if (!netif_running(dev))
7140 orig_led_state = niu_led_state_save(np);
7141 for (i = 0; i < (data * 2); i++) {
7142 int on = ((i % 2) == 0);
7144 niu_force_led(np, on);
7146 if (msleep_interruptible(500))
7149 niu_led_state_restore(np, orig_led_state);
7154 static const struct ethtool_ops niu_ethtool_ops = {
7155 .get_drvinfo = niu_get_drvinfo,
7156 .get_link = ethtool_op_get_link,
7157 .get_msglevel = niu_get_msglevel,
7158 .set_msglevel = niu_set_msglevel,
7159 .get_eeprom_len = niu_get_eeprom_len,
7160 .get_eeprom = niu_get_eeprom,
7161 .get_settings = niu_get_settings,
7162 .set_settings = niu_set_settings,
7163 .get_strings = niu_get_strings,
7164 .get_stats_count = niu_get_stats_count,
7165 .get_ethtool_stats = niu_get_ethtool_stats,
7166 .phys_id = niu_phys_id,
7167 .get_rxhash = niu_get_hash_opts,
7168 .set_rxhash = niu_set_hash_opts,
7171 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7174 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7176 if (ldn < 0 || ldn > LDN_MAX)
7179 parent->ldg_map[ldn] = ldg;
7181 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7182 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7183 * the firmware, and we're not supposed to change them.
7184 * Validate the mapping, because if it's wrong we probably
7185 * won't get any interrupts and that's painful to debug.
7187 if (nr64(LDG_NUM(ldn)) != ldg) {
7188 dev_err(np->device, PFX "Port %u, mis-matched "
7190 "for ldn %d, should be %d is %llu\n",
7192 (unsigned long long) nr64(LDG_NUM(ldn)));
7196 nw64(LDG_NUM(ldn), ldg);
7201 static int niu_set_ldg_timer_res(struct niu *np, int res)
7203 if (res < 0 || res > LDG_TIMER_RES_VAL)
7207 nw64(LDG_TIMER_RES, res);
7212 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7214 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7215 (func < 0 || func > 3) ||
7216 (vector < 0 || vector > 0x1f))
7219 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7224 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7226 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7227 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7230 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7234 nw64(ESPC_PIO_STAT, frame);
7238 frame = nr64(ESPC_PIO_STAT);
7239 if (frame & ESPC_PIO_STAT_READ_END)
7242 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7243 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7244 (unsigned long long) frame);
7249 nw64(ESPC_PIO_STAT, frame);
7253 frame = nr64(ESPC_PIO_STAT);
7254 if (frame & ESPC_PIO_STAT_READ_END)
7257 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7258 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7259 (unsigned long long) frame);
7263 frame = nr64(ESPC_PIO_STAT);
7264 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7267 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7269 int err = niu_pci_eeprom_read(np, off);
7275 err = niu_pci_eeprom_read(np, off + 1);
7278 val |= (err & 0xff);
7283 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7285 int err = niu_pci_eeprom_read(np, off);
7292 err = niu_pci_eeprom_read(np, off + 1);
7296 val |= (err & 0xff) << 8;
7301 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7308 for (i = 0; i < namebuf_len; i++) {
7309 int err = niu_pci_eeprom_read(np, off + i);
7316 if (i >= namebuf_len)
7322 static void __devinit niu_vpd_parse_version(struct niu *np)
7324 struct niu_vpd *vpd = &np->vpd;
7325 int len = strlen(vpd->version) + 1;
7326 const char *s = vpd->version;
7329 for (i = 0; i < len - 5; i++) {
7330 if (!strncmp(s + i, "FCode ", 5))
7337 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7339 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7340 vpd->fcode_major, vpd->fcode_minor);
7341 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7342 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7343 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7344 np->flags |= NIU_FLAGS_VPD_VALID;
7347 /* ESPC_PIO_EN_ENABLE must be set */
7348 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7351 unsigned int found_mask = 0;
7352 #define FOUND_MASK_MODEL 0x00000001
7353 #define FOUND_MASK_BMODEL 0x00000002
7354 #define FOUND_MASK_VERS 0x00000004
7355 #define FOUND_MASK_MAC 0x00000008
7356 #define FOUND_MASK_NMAC 0x00000010
7357 #define FOUND_MASK_PHY 0x00000020
7358 #define FOUND_MASK_ALL 0x0000003f
7360 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7362 while (start < end) {
7363 int len, err, instance, type, prop_len;
7368 if (found_mask == FOUND_MASK_ALL) {
7369 niu_vpd_parse_version(np);
7373 err = niu_pci_eeprom_read(np, start + 2);
7379 instance = niu_pci_eeprom_read(np, start);
7380 type = niu_pci_eeprom_read(np, start + 3);
7381 prop_len = niu_pci_eeprom_read(np, start + 4);
7382 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7388 if (!strcmp(namebuf, "model")) {
7389 prop_buf = np->vpd.model;
7390 max_len = NIU_VPD_MODEL_MAX;
7391 found_mask |= FOUND_MASK_MODEL;
7392 } else if (!strcmp(namebuf, "board-model")) {
7393 prop_buf = np->vpd.board_model;
7394 max_len = NIU_VPD_BD_MODEL_MAX;
7395 found_mask |= FOUND_MASK_BMODEL;
7396 } else if (!strcmp(namebuf, "version")) {
7397 prop_buf = np->vpd.version;
7398 max_len = NIU_VPD_VERSION_MAX;
7399 found_mask |= FOUND_MASK_VERS;
7400 } else if (!strcmp(namebuf, "local-mac-address")) {
7401 prop_buf = np->vpd.local_mac;
7403 found_mask |= FOUND_MASK_MAC;
7404 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7405 prop_buf = &np->vpd.mac_num;
7407 found_mask |= FOUND_MASK_NMAC;
7408 } else if (!strcmp(namebuf, "phy-type")) {
7409 prop_buf = np->vpd.phy_type;
7410 max_len = NIU_VPD_PHY_TYPE_MAX;
7411 found_mask |= FOUND_MASK_PHY;
7414 if (max_len && prop_len > max_len) {
7415 dev_err(np->device, PFX "Property '%s' length (%d) is "
7416 "too long.\n", namebuf, prop_len);
7421 u32 off = start + 5 + err;
7424 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7425 "len[%d]\n", namebuf, prop_len);
7426 for (i = 0; i < prop_len; i++)
7427 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7436 /* ESPC_PIO_EN_ENABLE must be set */
7437 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7442 err = niu_pci_eeprom_read16_swp(np, start + 1);
7448 while (start + offset < ESPC_EEPROM_SIZE) {
7449 u32 here = start + offset;
7452 err = niu_pci_eeprom_read(np, here);
7456 err = niu_pci_eeprom_read16_swp(np, here + 1);
7460 here = start + offset + 3;
7461 end = start + offset + err;
7465 err = niu_pci_vpd_scan_props(np, here, end);
7466 if (err < 0 || err == 1)
7471 /* ESPC_PIO_EN_ENABLE must be set */
7472 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7474 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7477 while (start < end) {
7480 /* ROM header signature? */
7481 err = niu_pci_eeprom_read16(np, start + 0);
7485 /* Apply offset to PCI data structure. */
7486 err = niu_pci_eeprom_read16(np, start + 23);
7491 /* Check for "PCIR" signature. */
7492 err = niu_pci_eeprom_read16(np, start + 0);
7495 err = niu_pci_eeprom_read16(np, start + 2);
7499 /* Check for OBP image type. */
7500 err = niu_pci_eeprom_read(np, start + 20);
7504 err = niu_pci_eeprom_read(np, ret + 2);
7508 start = ret + (err * 512);
7512 err = niu_pci_eeprom_read16_swp(np, start + 8);
7517 err = niu_pci_eeprom_read(np, ret + 0);
7527 static int __devinit niu_phy_type_prop_decode(struct niu *np,
7528 const char *phy_prop)
7530 if (!strcmp(phy_prop, "mif")) {
7531 /* 1G copper, MII */
7532 np->flags &= ~(NIU_FLAGS_FIBER |
7534 np->mac_xcvr = MAC_XCVR_MII;
7535 } else if (!strcmp(phy_prop, "xgf")) {
7536 /* 10G fiber, XPCS */
7537 np->flags |= (NIU_FLAGS_10G |
7539 np->mac_xcvr = MAC_XCVR_XPCS;
7540 } else if (!strcmp(phy_prop, "pcs")) {
7542 np->flags &= ~NIU_FLAGS_10G;
7543 np->flags |= NIU_FLAGS_FIBER;
7544 np->mac_xcvr = MAC_XCVR_PCS;
7545 } else if (!strcmp(phy_prop, "xgc")) {
7546 /* 10G copper, XPCS */
7547 np->flags |= NIU_FLAGS_10G;
7548 np->flags &= ~NIU_FLAGS_FIBER;
7549 np->mac_xcvr = MAC_XCVR_XPCS;
7550 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7551 /* 10G Serdes or 1G Serdes, default to 10G */
7552 np->flags |= NIU_FLAGS_10G;
7553 np->flags &= ~NIU_FLAGS_FIBER;
7554 np->flags |= NIU_FLAGS_XCVR_SERDES;
7555 np->mac_xcvr = MAC_XCVR_XPCS;
7562 static int niu_pci_vpd_get_nports(struct niu *np)
7566 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7567 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7568 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7569 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7570 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7572 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7573 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7574 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7575 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7582 static void __devinit niu_pci_vpd_validate(struct niu *np)
7584 struct net_device *dev = np->dev;
7585 struct niu_vpd *vpd = &np->vpd;
7588 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7589 dev_err(np->device, PFX "VPD MAC invalid, "
7590 "falling back to SPROM.\n");
7592 np->flags &= ~NIU_FLAGS_VPD_VALID;
7596 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7597 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7598 np->flags |= NIU_FLAGS_10G;
7599 np->flags &= ~NIU_FLAGS_FIBER;
7600 np->flags |= NIU_FLAGS_XCVR_SERDES;
7601 np->mac_xcvr = MAC_XCVR_PCS;
7603 np->flags |= NIU_FLAGS_FIBER;
7604 np->flags &= ~NIU_FLAGS_10G;
7606 if (np->flags & NIU_FLAGS_10G)
7607 np->mac_xcvr = MAC_XCVR_XPCS;
7608 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7609 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7610 NIU_FLAGS_HOTPLUG_PHY);
7611 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7612 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7614 dev_err(np->device, PFX "Falling back to SPROM.\n");
7615 np->flags &= ~NIU_FLAGS_VPD_VALID;
7619 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7621 val8 = dev->perm_addr[5];
7622 dev->perm_addr[5] += np->port;
7623 if (dev->perm_addr[5] < val8)
7624 dev->perm_addr[4]++;
7626 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7629 static int __devinit niu_pci_probe_sprom(struct niu *np)
7631 struct net_device *dev = np->dev;
7636 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7637 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7640 np->eeprom_len = len;
7642 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7645 for (i = 0; i < len; i++) {
7646 val = nr64(ESPC_NCR(i));
7647 sum += (val >> 0) & 0xff;
7648 sum += (val >> 8) & 0xff;
7649 sum += (val >> 16) & 0xff;
7650 sum += (val >> 24) & 0xff;
7652 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7653 if ((sum & 0xff) != 0xab) {
7654 dev_err(np->device, PFX "Bad SPROM checksum "
7655 "(%x, should be 0xab)\n", (int) (sum & 0xff));
7659 val = nr64(ESPC_PHY_TYPE);
7662 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7663 ESPC_PHY_TYPE_PORT0_SHIFT;
7666 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7667 ESPC_PHY_TYPE_PORT1_SHIFT;
7670 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7671 ESPC_PHY_TYPE_PORT2_SHIFT;
7674 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7675 ESPC_PHY_TYPE_PORT3_SHIFT;
7678 dev_err(np->device, PFX "Bogus port number %u\n",
7682 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7685 case ESPC_PHY_TYPE_1G_COPPER:
7686 /* 1G copper, MII */
7687 np->flags &= ~(NIU_FLAGS_FIBER |
7689 np->mac_xcvr = MAC_XCVR_MII;
7692 case ESPC_PHY_TYPE_1G_FIBER:
7694 np->flags &= ~NIU_FLAGS_10G;
7695 np->flags |= NIU_FLAGS_FIBER;
7696 np->mac_xcvr = MAC_XCVR_PCS;
7699 case ESPC_PHY_TYPE_10G_COPPER:
7700 /* 10G copper, XPCS */
7701 np->flags |= NIU_FLAGS_10G;
7702 np->flags &= ~NIU_FLAGS_FIBER;
7703 np->mac_xcvr = MAC_XCVR_XPCS;
7706 case ESPC_PHY_TYPE_10G_FIBER:
7707 /* 10G fiber, XPCS */
7708 np->flags |= (NIU_FLAGS_10G |
7710 np->mac_xcvr = MAC_XCVR_XPCS;
7714 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7718 val = nr64(ESPC_MAC_ADDR0);
7719 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7720 (unsigned long long) val);
7721 dev->perm_addr[0] = (val >> 0) & 0xff;
7722 dev->perm_addr[1] = (val >> 8) & 0xff;
7723 dev->perm_addr[2] = (val >> 16) & 0xff;
7724 dev->perm_addr[3] = (val >> 24) & 0xff;
7726 val = nr64(ESPC_MAC_ADDR1);
7727 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7728 (unsigned long long) val);
7729 dev->perm_addr[4] = (val >> 0) & 0xff;
7730 dev->perm_addr[5] = (val >> 8) & 0xff;
7732 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7733 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7734 dev_err(np->device, PFX "[ \n");
7735 for (i = 0; i < 6; i++)
7736 printk("%02x ", dev->perm_addr[i]);
7741 val8 = dev->perm_addr[5];
7742 dev->perm_addr[5] += np->port;
7743 if (dev->perm_addr[5] < val8)
7744 dev->perm_addr[4]++;
7746 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7748 val = nr64(ESPC_MOD_STR_LEN);
7749 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7750 (unsigned long long) val);
7754 for (i = 0; i < val; i += 4) {
7755 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7757 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
7758 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
7759 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7760 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7762 np->vpd.model[val] = '\0';
7764 val = nr64(ESPC_BD_MOD_STR_LEN);
7765 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7766 (unsigned long long) val);
7770 for (i = 0; i < val; i += 4) {
7771 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7773 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
7774 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
7775 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7776 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7778 np->vpd.board_model[val] = '\0';
7781 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7782 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7788 static int __devinit niu_get_and_validate_port(struct niu *np)
7790 struct niu_parent *parent = np->parent;
7793 np->flags |= NIU_FLAGS_XMAC;
7795 if (!parent->num_ports) {
7796 if (parent->plat_type == PLAT_TYPE_NIU) {
7797 parent->num_ports = 2;
7799 parent->num_ports = niu_pci_vpd_get_nports(np);
7800 if (!parent->num_ports) {
7801 /* Fall back to SPROM as last resort.
7802 * This will fail on most cards.
7804 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7805 ESPC_NUM_PORTS_MACS_VAL;
7807 /* All of the current probing methods fail on
7808 * Maramba on-board parts.
7810 if (!parent->num_ports)
7811 parent->num_ports = 4;
7816 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7817 np->port, parent->num_ports);
7818 if (np->port >= parent->num_ports)
7824 static int __devinit phy_record(struct niu_parent *parent,
7825 struct phy_probe_info *p,
7826 int dev_id_1, int dev_id_2, u8 phy_port,
7829 u32 id = (dev_id_1 << 16) | dev_id_2;
7832 if (dev_id_1 < 0 || dev_id_2 < 0)
7834 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7835 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7836 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7837 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7840 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7844 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7846 (type == PHY_TYPE_PMA_PMD ?
7848 (type == PHY_TYPE_PCS ?
7852 if (p->cur[type] >= NIU_MAX_PORTS) {
7853 printk(KERN_ERR PFX "Too many PHY ports.\n");
7857 p->phy_id[type][idx] = id;
7858 p->phy_port[type][idx] = phy_port;
7859 p->cur[type] = idx + 1;
7863 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7867 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7868 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7871 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7872 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7879 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7885 for (port = 8; port < 32; port++) {
7886 if (port_has_10g(p, port)) {
7896 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7899 if (p->cur[PHY_TYPE_MII])
7900 *lowest = p->phy_port[PHY_TYPE_MII][0];
7902 return p->cur[PHY_TYPE_MII];
7905 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7907 int num_ports = parent->num_ports;
7910 for (i = 0; i < num_ports; i++) {
7911 parent->rxchan_per_port[i] = (16 / num_ports);
7912 parent->txchan_per_port[i] = (16 / num_ports);
7914 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7917 parent->rxchan_per_port[i],
7918 parent->txchan_per_port[i]);
7922 static void __devinit niu_divide_channels(struct niu_parent *parent,
7923 int num_10g, int num_1g)
7925 int num_ports = parent->num_ports;
7926 int rx_chans_per_10g, rx_chans_per_1g;
7927 int tx_chans_per_10g, tx_chans_per_1g;
7928 int i, tot_rx, tot_tx;
7930 if (!num_10g || !num_1g) {
7931 rx_chans_per_10g = rx_chans_per_1g =
7932 (NIU_NUM_RXCHAN / num_ports);
7933 tx_chans_per_10g = tx_chans_per_1g =
7934 (NIU_NUM_TXCHAN / num_ports);
7936 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7937 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7938 (rx_chans_per_1g * num_1g)) /
7941 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7942 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7943 (tx_chans_per_1g * num_1g)) /
7947 tot_rx = tot_tx = 0;
7948 for (i = 0; i < num_ports; i++) {
7949 int type = phy_decode(parent->port_phy, i);
7951 if (type == PORT_TYPE_10G) {
7952 parent->rxchan_per_port[i] = rx_chans_per_10g;
7953 parent->txchan_per_port[i] = tx_chans_per_10g;
7955 parent->rxchan_per_port[i] = rx_chans_per_1g;
7956 parent->txchan_per_port[i] = tx_chans_per_1g;
7958 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7961 parent->rxchan_per_port[i],
7962 parent->txchan_per_port[i]);
7963 tot_rx += parent->rxchan_per_port[i];
7964 tot_tx += parent->txchan_per_port[i];
7967 if (tot_rx > NIU_NUM_RXCHAN) {
7968 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7969 "resetting to one per port.\n",
7970 parent->index, tot_rx);
7971 for (i = 0; i < num_ports; i++)
7972 parent->rxchan_per_port[i] = 1;
7974 if (tot_tx > NIU_NUM_TXCHAN) {
7975 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7976 "resetting to one per port.\n",
7977 parent->index, tot_tx);
7978 for (i = 0; i < num_ports; i++)
7979 parent->txchan_per_port[i] = 1;
7981 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7982 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7984 parent->index, tot_rx, tot_tx);
7988 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7989 int num_10g, int num_1g)
7991 int i, num_ports = parent->num_ports;
7992 int rdc_group, rdc_groups_per_port;
7993 int rdc_channel_base;
7996 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7998 rdc_channel_base = 0;
8000 for (i = 0; i < num_ports; i++) {
8001 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8002 int grp, num_channels = parent->rxchan_per_port[i];
8003 int this_channel_offset;
8005 tp->first_table_num = rdc_group;
8006 tp->num_tables = rdc_groups_per_port;
8007 this_channel_offset = 0;
8008 for (grp = 0; grp < tp->num_tables; grp++) {
8009 struct rdc_table *rt = &tp->tables[grp];
8012 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8013 parent->index, i, tp->first_table_num + grp);
8014 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8015 rt->rxdma_channel[slot] =
8016 rdc_channel_base + this_channel_offset;
8018 printk("%d ", rt->rxdma_channel[slot]);
8020 if (++this_channel_offset == num_channels)
8021 this_channel_offset = 0;
8026 parent->rdc_default[i] = rdc_channel_base;
8028 rdc_channel_base += num_channels;
8029 rdc_group += rdc_groups_per_port;
8033 static int __devinit fill_phy_probe_info(struct niu *np,
8034 struct niu_parent *parent,
8035 struct phy_probe_info *info)
8037 unsigned long flags;
8040 memset(info, 0, sizeof(*info));
8042 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8043 niu_lock_parent(np, flags);
8045 for (port = 8; port < 32; port++) {
8046 int dev_id_1, dev_id_2;
8048 dev_id_1 = mdio_read(np, port,
8049 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8050 dev_id_2 = mdio_read(np, port,
8051 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8052 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8056 dev_id_1 = mdio_read(np, port,
8057 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8058 dev_id_2 = mdio_read(np, port,
8059 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8060 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8064 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8065 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8066 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8071 niu_unlock_parent(np, flags);
8076 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8078 struct phy_probe_info *info = &parent->phy_probe_info;
8079 int lowest_10g, lowest_1g;
8080 int num_10g, num_1g;
8084 num_10g = num_1g = 0;
8086 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8087 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8090 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8091 parent->num_ports = 4;
8092 val = (phy_encode(PORT_TYPE_1G, 0) |
8093 phy_encode(PORT_TYPE_1G, 1) |
8094 phy_encode(PORT_TYPE_1G, 2) |
8095 phy_encode(PORT_TYPE_1G, 3));
8096 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8099 parent->num_ports = 2;
8100 val = (phy_encode(PORT_TYPE_10G, 0) |
8101 phy_encode(PORT_TYPE_10G, 1));
8102 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8103 (parent->plat_type == PLAT_TYPE_NIU)) {
8104 /* this is the Monza case */
8105 if (np->flags & NIU_FLAGS_10G) {
8106 val = (phy_encode(PORT_TYPE_10G, 0) |
8107 phy_encode(PORT_TYPE_10G, 1));
8109 val = (phy_encode(PORT_TYPE_1G, 0) |
8110 phy_encode(PORT_TYPE_1G, 1));
8113 err = fill_phy_probe_info(np, parent, info);
8117 num_10g = count_10g_ports(info, &lowest_10g);
8118 num_1g = count_1g_ports(info, &lowest_1g);
8120 switch ((num_10g << 4) | num_1g) {
8122 if (lowest_1g == 10)
8123 parent->plat_type = PLAT_TYPE_VF_P0;
8124 else if (lowest_1g == 26)
8125 parent->plat_type = PLAT_TYPE_VF_P1;
8127 goto unknown_vg_1g_port;
8131 val = (phy_encode(PORT_TYPE_10G, 0) |
8132 phy_encode(PORT_TYPE_10G, 1) |
8133 phy_encode(PORT_TYPE_1G, 2) |
8134 phy_encode(PORT_TYPE_1G, 3));
8138 val = (phy_encode(PORT_TYPE_10G, 0) |
8139 phy_encode(PORT_TYPE_10G, 1));
8143 val = phy_encode(PORT_TYPE_10G, np->port);
8147 if (lowest_1g == 10)
8148 parent->plat_type = PLAT_TYPE_VF_P0;
8149 else if (lowest_1g == 26)
8150 parent->plat_type = PLAT_TYPE_VF_P1;
8152 goto unknown_vg_1g_port;
8156 if ((lowest_10g & 0x7) == 0)
8157 val = (phy_encode(PORT_TYPE_10G, 0) |
8158 phy_encode(PORT_TYPE_1G, 1) |
8159 phy_encode(PORT_TYPE_1G, 2) |
8160 phy_encode(PORT_TYPE_1G, 3));
8162 val = (phy_encode(PORT_TYPE_1G, 0) |
8163 phy_encode(PORT_TYPE_10G, 1) |
8164 phy_encode(PORT_TYPE_1G, 2) |
8165 phy_encode(PORT_TYPE_1G, 3));
8169 if (lowest_1g == 10)
8170 parent->plat_type = PLAT_TYPE_VF_P0;
8171 else if (lowest_1g == 26)
8172 parent->plat_type = PLAT_TYPE_VF_P1;
8174 goto unknown_vg_1g_port;
8176 val = (phy_encode(PORT_TYPE_1G, 0) |
8177 phy_encode(PORT_TYPE_1G, 1) |
8178 phy_encode(PORT_TYPE_1G, 2) |
8179 phy_encode(PORT_TYPE_1G, 3));
8183 printk(KERN_ERR PFX "Unsupported port config "
8190 parent->port_phy = val;
8192 if (parent->plat_type == PLAT_TYPE_NIU)
8193 niu_n2_divide_channels(parent);
8195 niu_divide_channels(parent, num_10g, num_1g);
8197 niu_divide_rdc_groups(parent, num_10g, num_1g);
8202 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8207 static int __devinit niu_probe_ports(struct niu *np)
8209 struct niu_parent *parent = np->parent;
8212 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8215 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8216 err = walk_phys(np, parent);
8220 niu_set_ldg_timer_res(np, 2);
8221 for (i = 0; i <= LDN_MAX; i++)
8222 niu_ldn_irq_enable(np, i, 0);
8225 if (parent->port_phy == PORT_PHY_INVALID)
8231 static int __devinit niu_classifier_swstate_init(struct niu *np)
8233 struct niu_classifier *cp = &np->clas;
8235 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8236 np->parent->tcam_num_entries);
8238 cp->tcam_index = (u16) np->port;
8239 cp->h1_init = 0xffffffff;
8240 cp->h2_init = 0xffff;
8242 return fflp_early_init(np);
8245 static void __devinit niu_link_config_init(struct niu *np)
8247 struct niu_link_config *lp = &np->link_config;
8249 lp->advertising = (ADVERTISED_10baseT_Half |
8250 ADVERTISED_10baseT_Full |
8251 ADVERTISED_100baseT_Half |
8252 ADVERTISED_100baseT_Full |
8253 ADVERTISED_1000baseT_Half |
8254 ADVERTISED_1000baseT_Full |
8255 ADVERTISED_10000baseT_Full |
8256 ADVERTISED_Autoneg);
8257 lp->speed = lp->active_speed = SPEED_INVALID;
8258 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
8260 lp->loopback_mode = LOOPBACK_MAC;
8261 lp->active_speed = SPEED_10000;
8262 lp->active_duplex = DUPLEX_FULL;
8264 lp->loopback_mode = LOOPBACK_DISABLED;
8268 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8272 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8273 np->ipp_off = 0x00000;
8274 np->pcs_off = 0x04000;
8275 np->xpcs_off = 0x02000;
8279 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8280 np->ipp_off = 0x08000;
8281 np->pcs_off = 0x0a000;
8282 np->xpcs_off = 0x08000;
8286 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8287 np->ipp_off = 0x04000;
8288 np->pcs_off = 0x0e000;
8289 np->xpcs_off = ~0UL;
8293 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8294 np->ipp_off = 0x0c000;
8295 np->pcs_off = 0x12000;
8296 np->xpcs_off = ~0UL;
8300 dev_err(np->device, PFX "Port %u is invalid, cannot "
8301 "compute MAC block offset.\n", np->port);
8308 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8310 struct msix_entry msi_vec[NIU_NUM_LDG];
8311 struct niu_parent *parent = np->parent;
8312 struct pci_dev *pdev = np->pdev;
8313 int i, num_irqs, err;
8316 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8317 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8318 ldg_num_map[i] = first_ldg + i;
8320 num_irqs = (parent->rxchan_per_port[np->port] +
8321 parent->txchan_per_port[np->port] +
8322 (np->port == 0 ? 3 : 1));
8323 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8326 for (i = 0; i < num_irqs; i++) {
8327 msi_vec[i].vector = 0;
8328 msi_vec[i].entry = i;
8331 err = pci_enable_msix(pdev, msi_vec, num_irqs);
8333 np->flags &= ~NIU_FLAGS_MSIX;
8341 np->flags |= NIU_FLAGS_MSIX;
8342 for (i = 0; i < num_irqs; i++)
8343 np->ldg[i].irq = msi_vec[i].vector;
8344 np->num_ldg = num_irqs;
8347 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8349 #ifdef CONFIG_SPARC64
8350 struct of_device *op = np->op;
8351 const u32 *int_prop;
8354 int_prop = of_get_property(op->node, "interrupts", NULL);
8358 for (i = 0; i < op->num_irqs; i++) {
8359 ldg_num_map[i] = int_prop[i];
8360 np->ldg[i].irq = op->irqs[i];
8363 np->num_ldg = op->num_irqs;
8371 static int __devinit niu_ldg_init(struct niu *np)
8373 struct niu_parent *parent = np->parent;
8374 u8 ldg_num_map[NIU_NUM_LDG];
8375 int first_chan, num_chan;
8376 int i, err, ldg_rotor;
8380 np->ldg[0].irq = np->dev->irq;
8381 if (parent->plat_type == PLAT_TYPE_NIU) {
8382 err = niu_n2_irq_init(np, ldg_num_map);
8386 niu_try_msix(np, ldg_num_map);
8389 for (i = 0; i < np->num_ldg; i++) {
8390 struct niu_ldg *lp = &np->ldg[i];
8392 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8395 lp->ldg_num = ldg_num_map[i];
8396 lp->timer = 2; /* XXX */
8398 /* On N2 NIU the firmware has setup the SID mappings so they go
8399 * to the correct values that will route the LDG to the proper
8400 * interrupt in the NCU interrupt table.
8402 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8403 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8409 /* We adopt the LDG assignment ordering used by the N2 NIU
8410 * 'interrupt' properties because that simplifies a lot of
8411 * things. This ordering is:
8414 * MIF (if port zero)
8415 * SYSERR (if port zero)
8422 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8428 if (ldg_rotor == np->num_ldg)
8432 err = niu_ldg_assign_ldn(np, parent,
8433 ldg_num_map[ldg_rotor],
8439 if (ldg_rotor == np->num_ldg)
8442 err = niu_ldg_assign_ldn(np, parent,
8443 ldg_num_map[ldg_rotor],
8449 if (ldg_rotor == np->num_ldg)
8455 for (i = 0; i < port; i++)
8456 first_chan += parent->rxchan_per_port[port];
8457 num_chan = parent->rxchan_per_port[port];
8459 for (i = first_chan; i < (first_chan + num_chan); i++) {
8460 err = niu_ldg_assign_ldn(np, parent,
8461 ldg_num_map[ldg_rotor],
8466 if (ldg_rotor == np->num_ldg)
8471 for (i = 0; i < port; i++)
8472 first_chan += parent->txchan_per_port[port];
8473 num_chan = parent->txchan_per_port[port];
8474 for (i = first_chan; i < (first_chan + num_chan); i++) {
8475 err = niu_ldg_assign_ldn(np, parent,
8476 ldg_num_map[ldg_rotor],
8481 if (ldg_rotor == np->num_ldg)
8488 static void __devexit niu_ldg_free(struct niu *np)
8490 if (np->flags & NIU_FLAGS_MSIX)
8491 pci_disable_msix(np->pdev);
8494 static int __devinit niu_get_of_props(struct niu *np)
8496 #ifdef CONFIG_SPARC64
8497 struct net_device *dev = np->dev;
8498 struct device_node *dp;
8499 const char *phy_type;
8504 if (np->parent->plat_type == PLAT_TYPE_NIU)
8507 dp = pci_device_to_OF_node(np->pdev);
8509 phy_type = of_get_property(dp, "phy-type", &prop_len);
8511 dev_err(np->device, PFX "%s: OF node lacks "
8512 "phy-type property\n",
8517 if (!strcmp(phy_type, "none"))
8520 strcpy(np->vpd.phy_type, phy_type);
8522 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8523 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8524 dp->full_name, np->vpd.phy_type);
8528 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8530 dev_err(np->device, PFX "%s: OF node lacks "
8531 "local-mac-address property\n",
8535 if (prop_len != dev->addr_len) {
8536 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8538 dp->full_name, prop_len);
8540 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8541 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8544 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8546 dev_err(np->device, PFX "%s: [ \n",
8548 for (i = 0; i < 6; i++)
8549 printk("%02x ", dev->perm_addr[i]);
8554 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8556 model = of_get_property(dp, "model", &prop_len);
8559 strcpy(np->vpd.model, model);
8567 static int __devinit niu_get_invariants(struct niu *np)
8569 int err, have_props;
8572 err = niu_get_of_props(np);
8578 err = niu_init_mac_ipp_pcs_base(np);
8583 err = niu_get_and_validate_port(np);
8588 if (np->parent->plat_type == PLAT_TYPE_NIU)
8591 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8592 offset = niu_pci_vpd_offset(np);
8593 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8596 niu_pci_vpd_fetch(np, offset);
8597 nw64(ESPC_PIO_EN, 0);
8599 if (np->flags & NIU_FLAGS_VPD_VALID) {
8600 niu_pci_vpd_validate(np);
8601 err = niu_get_and_validate_port(np);
8606 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8607 err = niu_get_and_validate_port(np);
8610 err = niu_pci_probe_sprom(np);
8616 err = niu_probe_ports(np);
8622 niu_classifier_swstate_init(np);
8623 niu_link_config_init(np);
8625 err = niu_determine_phy_disposition(np);
8627 err = niu_init_link(np);
8632 static LIST_HEAD(niu_parent_list);
8633 static DEFINE_MUTEX(niu_parent_lock);
8634 static int niu_parent_index;
8636 static ssize_t show_port_phy(struct device *dev,
8637 struct device_attribute *attr, char *buf)
8639 struct platform_device *plat_dev = to_platform_device(dev);
8640 struct niu_parent *p = plat_dev->dev.platform_data;
8641 u32 port_phy = p->port_phy;
8642 char *orig_buf = buf;
8645 if (port_phy == PORT_PHY_UNKNOWN ||
8646 port_phy == PORT_PHY_INVALID)
8649 for (i = 0; i < p->num_ports; i++) {
8650 const char *type_str;
8653 type = phy_decode(port_phy, i);
8654 if (type == PORT_TYPE_10G)
8659 (i == 0) ? "%s" : " %s",
8662 buf += sprintf(buf, "\n");
8663 return buf - orig_buf;
8666 static ssize_t show_plat_type(struct device *dev,
8667 struct device_attribute *attr, char *buf)
8669 struct platform_device *plat_dev = to_platform_device(dev);
8670 struct niu_parent *p = plat_dev->dev.platform_data;
8671 const char *type_str;
8673 switch (p->plat_type) {
8674 case PLAT_TYPE_ATLAS:
8680 case PLAT_TYPE_VF_P0:
8683 case PLAT_TYPE_VF_P1:
8687 type_str = "unknown";
8691 return sprintf(buf, "%s\n", type_str);
8694 static ssize_t __show_chan_per_port(struct device *dev,
8695 struct device_attribute *attr, char *buf,
8698 struct platform_device *plat_dev = to_platform_device(dev);
8699 struct niu_parent *p = plat_dev->dev.platform_data;
8700 char *orig_buf = buf;
8704 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8706 for (i = 0; i < p->num_ports; i++) {
8708 (i == 0) ? "%d" : " %d",
8711 buf += sprintf(buf, "\n");
8713 return buf - orig_buf;
8716 static ssize_t show_rxchan_per_port(struct device *dev,
8717 struct device_attribute *attr, char *buf)
8719 return __show_chan_per_port(dev, attr, buf, 1);
8722 static ssize_t show_txchan_per_port(struct device *dev,
8723 struct device_attribute *attr, char *buf)
8725 return __show_chan_per_port(dev, attr, buf, 1);
8728 static ssize_t show_num_ports(struct device *dev,
8729 struct device_attribute *attr, char *buf)
8731 struct platform_device *plat_dev = to_platform_device(dev);
8732 struct niu_parent *p = plat_dev->dev.platform_data;
8734 return sprintf(buf, "%d\n", p->num_ports);
8737 static struct device_attribute niu_parent_attributes[] = {
8738 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8739 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8740 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8741 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8742 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8746 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8747 union niu_parent_id *id,
8750 struct platform_device *plat_dev;
8751 struct niu_parent *p;
8754 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8756 plat_dev = platform_device_register_simple("niu", niu_parent_index,
8761 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8762 int err = device_create_file(&plat_dev->dev,
8763 &niu_parent_attributes[i]);
8765 goto fail_unregister;
8768 p = kzalloc(sizeof(*p), GFP_KERNEL);
8770 goto fail_unregister;
8772 p->index = niu_parent_index++;
8774 plat_dev->dev.platform_data = p;
8775 p->plat_dev = plat_dev;
8777 memcpy(&p->id, id, sizeof(*id));
8778 p->plat_type = ptype;
8779 INIT_LIST_HEAD(&p->list);
8780 atomic_set(&p->refcnt, 0);
8781 list_add(&p->list, &niu_parent_list);
8782 spin_lock_init(&p->lock);
8784 p->rxdma_clock_divider = 7500;
8786 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8787 if (p->plat_type == PLAT_TYPE_NIU)
8788 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8790 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8791 int index = i - CLASS_CODE_USER_PROG1;
8793 p->tcam_key[index] = TCAM_KEY_TSEL;
8794 p->flow_key[index] = (FLOW_KEY_IPSA |
8797 (FLOW_KEY_L4_BYTE12 <<
8798 FLOW_KEY_L4_0_SHIFT) |
8799 (FLOW_KEY_L4_BYTE12 <<
8800 FLOW_KEY_L4_1_SHIFT));
8803 for (i = 0; i < LDN_MAX + 1; i++)
8804 p->ldg_map[i] = LDG_INVALID;
8809 platform_device_unregister(plat_dev);
8813 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8814 union niu_parent_id *id,
8817 struct niu_parent *p, *tmp;
8818 int port = np->port;
8820 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8823 mutex_lock(&niu_parent_lock);
8825 list_for_each_entry(tmp, &niu_parent_list, list) {
8826 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8832 p = niu_new_parent(np, id, ptype);
8838 sprintf(port_name, "port%d", port);
8839 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8843 p->ports[port] = np;
8844 atomic_inc(&p->refcnt);
8847 mutex_unlock(&niu_parent_lock);
8852 static void niu_put_parent(struct niu *np)
8854 struct niu_parent *p = np->parent;
8858 BUG_ON(!p || p->ports[port] != np);
8860 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8862 sprintf(port_name, "port%d", port);
8864 mutex_lock(&niu_parent_lock);
8866 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8868 p->ports[port] = NULL;
8871 if (atomic_dec_and_test(&p->refcnt)) {
8873 platform_device_unregister(p->plat_dev);
8876 mutex_unlock(&niu_parent_lock);
8879 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8880 u64 *handle, gfp_t flag)
8885 ret = dma_alloc_coherent(dev, size, &dh, flag);
8891 static void niu_pci_free_coherent(struct device *dev, size_t size,
8892 void *cpu_addr, u64 handle)
8894 dma_free_coherent(dev, size, cpu_addr, handle);
8897 static u64 niu_pci_map_page(struct device *dev, struct page *page,
8898 unsigned long offset, size_t size,
8899 enum dma_data_direction direction)
8901 return dma_map_page(dev, page, offset, size, direction);
8904 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8905 size_t size, enum dma_data_direction direction)
8907 return dma_unmap_page(dev, dma_address, size, direction);
8910 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8912 enum dma_data_direction direction)
8914 return dma_map_single(dev, cpu_addr, size, direction);
8917 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8919 enum dma_data_direction direction)
8921 dma_unmap_single(dev, dma_address, size, direction);
8924 static const struct niu_ops niu_pci_ops = {
8925 .alloc_coherent = niu_pci_alloc_coherent,
8926 .free_coherent = niu_pci_free_coherent,
8927 .map_page = niu_pci_map_page,
8928 .unmap_page = niu_pci_unmap_page,
8929 .map_single = niu_pci_map_single,
8930 .unmap_single = niu_pci_unmap_single,
8933 static void __devinit niu_driver_version(void)
8935 static int niu_version_printed;
8937 if (niu_version_printed++ == 0)
8938 pr_info("%s", version);
8941 static struct net_device * __devinit niu_alloc_and_init(
8942 struct device *gen_dev, struct pci_dev *pdev,
8943 struct of_device *op, const struct niu_ops *ops,
8946 struct net_device *dev;
8949 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
8951 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8955 SET_NETDEV_DEV(dev, gen_dev);
8957 np = netdev_priv(dev);
8961 np->device = gen_dev;
8964 np->msg_enable = niu_debug;
8966 spin_lock_init(&np->lock);
8967 INIT_WORK(&np->reset_task, niu_reset_task);
8974 static const struct net_device_ops niu_netdev_ops = {
8975 .ndo_open = niu_open,
8976 .ndo_stop = niu_close,
8977 .ndo_start_xmit = niu_start_xmit,
8978 .ndo_get_stats = niu_get_stats,
8979 .ndo_set_multicast_list = niu_set_rx_mode,
8980 .ndo_validate_addr = eth_validate_addr,
8981 .ndo_set_mac_address = niu_set_mac_addr,
8982 .ndo_do_ioctl = niu_ioctl,
8983 .ndo_tx_timeout = niu_tx_timeout,
8984 .ndo_change_mtu = niu_change_mtu,
8987 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8989 dev->netdev_ops = &niu_netdev_ops;
8990 dev->ethtool_ops = &niu_ethtool_ops;
8991 dev->watchdog_timeo = NIU_TX_TIMEOUT;
8994 static void __devinit niu_device_announce(struct niu *np)
8996 struct net_device *dev = np->dev;
8998 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9000 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9001 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9003 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9004 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9005 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9006 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9007 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9010 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9012 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9013 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9014 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9015 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9017 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9018 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9023 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9024 const struct pci_device_id *ent)
9026 union niu_parent_id parent_id;
9027 struct net_device *dev;
9033 niu_driver_version();
9035 err = pci_enable_device(pdev);
9037 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9042 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9043 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9044 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9045 "base addresses, aborting.\n");
9047 goto err_out_disable_pdev;
9050 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9052 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9054 goto err_out_disable_pdev;
9057 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9059 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9061 goto err_out_free_res;
9064 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9065 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9068 goto err_out_free_res;
9070 np = netdev_priv(dev);
9072 memset(&parent_id, 0, sizeof(parent_id));
9073 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9074 parent_id.pci.bus = pdev->bus->number;
9075 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9077 np->parent = niu_get_parent(np, &parent_id,
9081 goto err_out_free_dev;
9084 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9085 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9086 val16 |= (PCI_EXP_DEVCTL_CERE |
9087 PCI_EXP_DEVCTL_NFERE |
9088 PCI_EXP_DEVCTL_FERE |
9089 PCI_EXP_DEVCTL_URRE |
9090 PCI_EXP_DEVCTL_RELAX_EN);
9091 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9093 dma_mask = DMA_44BIT_MASK;
9094 err = pci_set_dma_mask(pdev, dma_mask);
9096 dev->features |= NETIF_F_HIGHDMA;
9097 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9099 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9100 "DMA for consistent allocations, "
9102 goto err_out_release_parent;
9105 if (err || dma_mask == DMA_32BIT_MASK) {
9106 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9108 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9110 goto err_out_release_parent;
9114 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9116 np->regs = pci_ioremap_bar(pdev, 0);
9118 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9121 goto err_out_release_parent;
9124 pci_set_master(pdev);
9125 pci_save_state(pdev);
9127 dev->irq = pdev->irq;
9129 niu_assign_netdev_ops(dev);
9131 err = niu_get_invariants(np);
9134 dev_err(&pdev->dev, PFX "Problem fetching invariants "
9135 "of chip, aborting.\n");
9136 goto err_out_iounmap;
9139 err = register_netdev(dev);
9141 dev_err(&pdev->dev, PFX "Cannot register net device, "
9143 goto err_out_iounmap;
9146 pci_set_drvdata(pdev, dev);
9148 niu_device_announce(np);
9158 err_out_release_parent:
9165 pci_release_regions(pdev);
9167 err_out_disable_pdev:
9168 pci_disable_device(pdev);
9169 pci_set_drvdata(pdev, NULL);
9174 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9176 struct net_device *dev = pci_get_drvdata(pdev);
9179 struct niu *np = netdev_priv(dev);
9181 unregister_netdev(dev);
9192 pci_release_regions(pdev);
9193 pci_disable_device(pdev);
9194 pci_set_drvdata(pdev, NULL);
9198 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9200 struct net_device *dev = pci_get_drvdata(pdev);
9201 struct niu *np = netdev_priv(dev);
9202 unsigned long flags;
9204 if (!netif_running(dev))
9207 flush_scheduled_work();
9210 del_timer_sync(&np->timer);
9212 spin_lock_irqsave(&np->lock, flags);
9213 niu_enable_interrupts(np, 0);
9214 spin_unlock_irqrestore(&np->lock, flags);
9216 netif_device_detach(dev);
9218 spin_lock_irqsave(&np->lock, flags);
9220 spin_unlock_irqrestore(&np->lock, flags);
9222 pci_save_state(pdev);
9227 static int niu_resume(struct pci_dev *pdev)
9229 struct net_device *dev = pci_get_drvdata(pdev);
9230 struct niu *np = netdev_priv(dev);
9231 unsigned long flags;
9234 if (!netif_running(dev))
9237 pci_restore_state(pdev);
9239 netif_device_attach(dev);
9241 spin_lock_irqsave(&np->lock, flags);
9243 err = niu_init_hw(np);
9245 np->timer.expires = jiffies + HZ;
9246 add_timer(&np->timer);
9247 niu_netif_start(np);
9250 spin_unlock_irqrestore(&np->lock, flags);
9255 static struct pci_driver niu_pci_driver = {
9256 .name = DRV_MODULE_NAME,
9257 .id_table = niu_pci_tbl,
9258 .probe = niu_pci_init_one,
9259 .remove = __devexit_p(niu_pci_remove_one),
9260 .suspend = niu_suspend,
9261 .resume = niu_resume,
9264 #ifdef CONFIG_SPARC64
9265 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9266 u64 *dma_addr, gfp_t flag)
9268 unsigned long order = get_order(size);
9269 unsigned long page = __get_free_pages(flag, order);
9273 memset((char *)page, 0, PAGE_SIZE << order);
9274 *dma_addr = __pa(page);
9276 return (void *) page;
9279 static void niu_phys_free_coherent(struct device *dev, size_t size,
9280 void *cpu_addr, u64 handle)
9282 unsigned long order = get_order(size);
9284 free_pages((unsigned long) cpu_addr, order);
9287 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9288 unsigned long offset, size_t size,
9289 enum dma_data_direction direction)
9291 return page_to_phys(page) + offset;
9294 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9295 size_t size, enum dma_data_direction direction)
9297 /* Nothing to do. */
9300 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9302 enum dma_data_direction direction)
9304 return __pa(cpu_addr);
9307 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9309 enum dma_data_direction direction)
9311 /* Nothing to do. */
9314 static const struct niu_ops niu_phys_ops = {
9315 .alloc_coherent = niu_phys_alloc_coherent,
9316 .free_coherent = niu_phys_free_coherent,
9317 .map_page = niu_phys_map_page,
9318 .unmap_page = niu_phys_unmap_page,
9319 .map_single = niu_phys_map_single,
9320 .unmap_single = niu_phys_unmap_single,
9323 static unsigned long res_size(struct resource *r)
9325 return r->end - r->start + 1UL;
9328 static int __devinit niu_of_probe(struct of_device *op,
9329 const struct of_device_id *match)
9331 union niu_parent_id parent_id;
9332 struct net_device *dev;
9337 niu_driver_version();
9339 reg = of_get_property(op->node, "reg", NULL);
9341 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9342 op->node->full_name);
9346 dev = niu_alloc_and_init(&op->dev, NULL, op,
9347 &niu_phys_ops, reg[0] & 0x1);
9352 np = netdev_priv(dev);
9354 memset(&parent_id, 0, sizeof(parent_id));
9355 parent_id.of = of_get_parent(op->node);
9357 np->parent = niu_get_parent(np, &parent_id,
9361 goto err_out_free_dev;
9364 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9366 np->regs = of_ioremap(&op->resource[1], 0,
9367 res_size(&op->resource[1]),
9370 dev_err(&op->dev, PFX "Cannot map device registers, "
9373 goto err_out_release_parent;
9376 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9377 res_size(&op->resource[2]),
9379 if (!np->vir_regs_1) {
9380 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9383 goto err_out_iounmap;
9386 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9387 res_size(&op->resource[3]),
9389 if (!np->vir_regs_2) {
9390 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9393 goto err_out_iounmap;
9396 niu_assign_netdev_ops(dev);
9398 err = niu_get_invariants(np);
9401 dev_err(&op->dev, PFX "Problem fetching invariants "
9402 "of chip, aborting.\n");
9403 goto err_out_iounmap;
9406 err = register_netdev(dev);
9408 dev_err(&op->dev, PFX "Cannot register net device, "
9410 goto err_out_iounmap;
9413 dev_set_drvdata(&op->dev, dev);
9415 niu_device_announce(np);
9420 if (np->vir_regs_1) {
9421 of_iounmap(&op->resource[2], np->vir_regs_1,
9422 res_size(&op->resource[2]));
9423 np->vir_regs_1 = NULL;
9426 if (np->vir_regs_2) {
9427 of_iounmap(&op->resource[3], np->vir_regs_2,
9428 res_size(&op->resource[3]));
9429 np->vir_regs_2 = NULL;
9433 of_iounmap(&op->resource[1], np->regs,
9434 res_size(&op->resource[1]));
9438 err_out_release_parent:
9448 static int __devexit niu_of_remove(struct of_device *op)
9450 struct net_device *dev = dev_get_drvdata(&op->dev);
9453 struct niu *np = netdev_priv(dev);
9455 unregister_netdev(dev);
9457 if (np->vir_regs_1) {
9458 of_iounmap(&op->resource[2], np->vir_regs_1,
9459 res_size(&op->resource[2]));
9460 np->vir_regs_1 = NULL;
9463 if (np->vir_regs_2) {
9464 of_iounmap(&op->resource[3], np->vir_regs_2,
9465 res_size(&op->resource[3]));
9466 np->vir_regs_2 = NULL;
9470 of_iounmap(&op->resource[1], np->regs,
9471 res_size(&op->resource[1]));
9480 dev_set_drvdata(&op->dev, NULL);
9485 static const struct of_device_id niu_match[] = {
9488 .compatible = "SUNW,niusl",
9492 MODULE_DEVICE_TABLE(of, niu_match);
9494 static struct of_platform_driver niu_of_driver = {
9496 .match_table = niu_match,
9497 .probe = niu_of_probe,
9498 .remove = __devexit_p(niu_of_remove),
9501 #endif /* CONFIG_SPARC64 */
9503 static int __init niu_init(void)
9507 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
9509 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9511 #ifdef CONFIG_SPARC64
9512 err = of_register_driver(&niu_of_driver, &of_bus_type);
9516 err = pci_register_driver(&niu_pci_driver);
9517 #ifdef CONFIG_SPARC64
9519 of_unregister_driver(&niu_of_driver);
9526 static void __exit niu_exit(void)
9528 pci_unregister_driver(&niu_pci_driver);
9529 #ifdef CONFIG_SPARC64
9530 of_unregister_driver(&niu_of_driver);
9534 module_init(niu_init);
9535 module_exit(niu_exit);