4 * @author Intel Corporation
7 * @brief Internal Header file for IXP425 Ethernet Access component.
13 * IXP400 SW Release version 2.0
15 * -- Copyright Notice --
18 * Copyright 2001-2005, Intel Corporation.
19 * All rights reserved.
22 * SPDX-License-Identifier: BSD-3-Clause
24 * -- End of Copyright Notice --
28 * @addtogroup IxEthAccPri
36 * Os/System dependancies.
41 * Intermodule dependancies
49 * Intra module dependancies
52 #include "IxEthAccDataPlane_p.h"
53 #include "IxEthAccMac_p.h"
56 #define INLINE __inline__
60 #define IX_ETH_ACC_PRIVATE static
64 #define IX_ETH_ACC_PRIVATE
66 #endif /* ndef NDEBUG */
68 #define IX_ETH_ACC_PUBLIC
71 #define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false )
76 #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
77 #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
78 #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
80 #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
81 #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
82 #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
85 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
86 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
87 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
88 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
89 IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
91 /* prototypes for the private control plane functions (used by the control interface wrapper) */
92 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
93 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
94 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
95 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
96 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
97 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
98 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
99 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
100 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
101 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
102 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
103 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
104 IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
105 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
106 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
107 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
108 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
109 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
110 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
111 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
112 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
113 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
114 IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
117 * @struct ixEthAccRxDataStats
118 * @brief Stats data structures for data path. - Not obtained from h/w
123 UINT32 rxFrameClientCallback;
125 UINT32 rxFreeRepDelayed;
126 UINT32 rxFreeRepFromSwQOK;
127 UINT32 rxFreeRepFromSwQDelayed;
128 UINT32 rxFreeLateNotificationEnabled;
129 UINT32 rxFreeLowCallback;
130 UINT32 rxFreeOverflow;
132 UINT32 rxDuringDisable;
133 UINT32 rxSwQDuringDisable;
134 UINT32 rxUnlearnedMacAddress;
135 UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
136 UINT32 rxUnexpectedError;
138 } IxEthAccRxDataStats;
141 * @struct IxEthAccTxDataStats
142 * @brief Stats data structures for data path. - Not obtained from h/w
150 UINT32 txFromSwQDelayed;
151 UINT32 txLowThreshCallback;
152 UINT32 txDoneClientCallback;
153 UINT32 txDoneClientCallbackDisable;
156 UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
157 UINT32 txLateNotificationEnabled;
158 UINT32 txDoneDuringDisable;
159 UINT32 txDoneSwQDuringDisable;
160 UINT32 txUnexpectedError;
161 } IxEthAccTxDataStats;
163 /* port Disable state machine : list of states */
166 /* general port states */
170 /* particular Tx/Rx states */
175 } IxEthAccPortDisableState;
186 IxOsalMutex ackMIBStatsLock;
187 IxOsalMutex ackMIBStatsResetLock;
188 IxOsalMutex MIBStatsGetAccessLock;
189 IxOsalMutex MIBStatsGetResetAccessLock;
190 IxOsalMutex npeLoopbackMessageLock;
191 IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
192 UINT32 mcastAddrIndex;
193 IX_OSAL_MBUF *portDisableTxMbufPtr;
194 IX_OSAL_MBUF *portDisableRxMbufPtr;
196 volatile IxEthAccPortDisableState portDisableState;
197 volatile IxEthAccPortDisableState rxState;
198 volatile IxEthAccPortDisableState txState;
205 * @struct IxEthAccRxInfo
206 * @brief System-wide data structures associated with the data plane.
211 IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
212 IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
216 * @struct IxEthAccRxDataInfo
217 * @brief Per Port data structures associated with the receive data plane.
222 IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
223 IxEthAccPortRxCallback rxCallbackFn;
224 UINT32 rxCallbackTag;
225 IxEthAccDataPlaneQList freeBufferList;
226 IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
227 UINT32 rxMultiBufferCallbackTag;
228 BOOL rxMultiBufferCallbackInUse;
229 IxEthAccRxDataStats stats; /**< Receive s/w stats */
230 } IxEthAccRxDataInfo;
233 * @struct IxEthAccTxDataInfo
234 * @brief Per Port data structures associated with the transmit data plane.
239 IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
240 UINT32 txCallbackTag;
241 IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
242 IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
243 IxQMgrQId txQueue; /**< txQueue for this port */
244 IxEthAccTxDataStats stats; /**< Transmit s/w stats */
245 } IxEthAccTxDataInfo;
249 * @struct IxEthAccPortDataInfo
250 * @brief Per Port data structures associated with the port data plane.
255 BOOL portInitialized;
256 UINT32 npeId; /**< NpeId for this port */
257 IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
258 IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
259 } IxEthAccPortDataInfo;
261 extern IxEthAccPortDataInfo ixEthAccPortData[];
262 #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
264 extern BOOL ixEthAccServiceInit;
265 #define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true )
268 * Maximum number of frames to consume from the Rx Frame Q.
271 #define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
274 * Max number of times to load the Rx Free Q from callback.
276 #define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
279 * Max number of times to read from the Tx Done Q in one sitting.
282 #define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
285 * Max number of times to take buffers from S/w queues and write them to the H/w Tx
286 * queues on receipt of a Tx low threshold callback
289 #define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
292 #define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
293 #define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
296 #define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
298 #endif /* ndef IxEthAcc_p_H */