2 /* ns83820.c by Benjamin LaHaise with contributions.
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
6 * $Revision: 1.34.2.23 $
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
11 * Mmmm, chocolate vanilla mocha...
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
63 * - fix missed txok introduced during performance
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
86 * Cameo SOHO-GA2000T SOHO-GA2500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
92 * Special thanks to SMC for providing hardware to test this driver on.
94 * Reports of success or failure would be greatly appreciated.
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/interrupt.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/sched.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118 #include <linux/rtnetlink.h>
119 #include <linux/jiffies.h>
120 #include <linux/slab.h>
123 #include <asm/uaccess.h>
124 #include <asm/system.h>
126 #define DRV_NAME "ns83820"
128 /* Global parameters. See module_param near the bottom. */
130 static int reset_phy = 0;
131 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
133 /* Dprintk is used for more interesting debug events */
135 #define Dprintk dprintk
138 #define RX_BUF_SIZE 1500 /* 8192 */
139 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
140 #define NS83820_VLAN_ACCEL_SUPPORT
143 /* Must not exceed ~65000. */
144 #define NR_RX_DESC 64
145 #define NR_TX_DESC 128
148 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
150 #define MIN_TX_DESC_FREE 8
152 /* register defines */
155 #define CR_TXE 0x00000001
156 #define CR_TXD 0x00000002
157 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
158 * The Receive engine skips one descriptor and moves
159 * onto the next one!! */
160 #define CR_RXE 0x00000004
161 #define CR_RXD 0x00000008
162 #define CR_TXR 0x00000010
163 #define CR_RXR 0x00000020
164 #define CR_SWI 0x00000080
165 #define CR_RST 0x00000100
167 #define PTSCR_EEBIST_FAIL 0x00000001
168 #define PTSCR_EEBIST_EN 0x00000002
169 #define PTSCR_EELOAD_EN 0x00000004
170 #define PTSCR_RBIST_FAIL 0x000001b8
171 #define PTSCR_RBIST_DONE 0x00000200
172 #define PTSCR_RBIST_EN 0x00000400
173 #define PTSCR_RBIST_RST 0x00002000
175 #define MEAR_EEDI 0x00000001
176 #define MEAR_EEDO 0x00000002
177 #define MEAR_EECLK 0x00000004
178 #define MEAR_EESEL 0x00000008
179 #define MEAR_MDIO 0x00000010
180 #define MEAR_MDDIR 0x00000020
181 #define MEAR_MDC 0x00000040
183 #define ISR_TXDESC3 0x40000000
184 #define ISR_TXDESC2 0x20000000
185 #define ISR_TXDESC1 0x10000000
186 #define ISR_TXDESC0 0x08000000
187 #define ISR_RXDESC3 0x04000000
188 #define ISR_RXDESC2 0x02000000
189 #define ISR_RXDESC1 0x01000000
190 #define ISR_RXDESC0 0x00800000
191 #define ISR_TXRCMP 0x00400000
192 #define ISR_RXRCMP 0x00200000
193 #define ISR_DPERR 0x00100000
194 #define ISR_SSERR 0x00080000
195 #define ISR_RMABT 0x00040000
196 #define ISR_RTABT 0x00020000
197 #define ISR_RXSOVR 0x00010000
198 #define ISR_HIBINT 0x00008000
199 #define ISR_PHY 0x00004000
200 #define ISR_PME 0x00002000
201 #define ISR_SWI 0x00001000
202 #define ISR_MIB 0x00000800
203 #define ISR_TXURN 0x00000400
204 #define ISR_TXIDLE 0x00000200
205 #define ISR_TXERR 0x00000100
206 #define ISR_TXDESC 0x00000080
207 #define ISR_TXOK 0x00000040
208 #define ISR_RXORN 0x00000020
209 #define ISR_RXIDLE 0x00000010
210 #define ISR_RXEARLY 0x00000008
211 #define ISR_RXERR 0x00000004
212 #define ISR_RXDESC 0x00000002
213 #define ISR_RXOK 0x00000001
215 #define TXCFG_CSI 0x80000000
216 #define TXCFG_HBI 0x40000000
217 #define TXCFG_MLB 0x20000000
218 #define TXCFG_ATP 0x10000000
219 #define TXCFG_ECRETRY 0x00800000
220 #define TXCFG_BRST_DIS 0x00080000
221 #define TXCFG_MXDMA1024 0x00000000
222 #define TXCFG_MXDMA512 0x00700000
223 #define TXCFG_MXDMA256 0x00600000
224 #define TXCFG_MXDMA128 0x00500000
225 #define TXCFG_MXDMA64 0x00400000
226 #define TXCFG_MXDMA32 0x00300000
227 #define TXCFG_MXDMA16 0x00200000
228 #define TXCFG_MXDMA8 0x00100000
230 #define CFG_LNKSTS 0x80000000
231 #define CFG_SPDSTS 0x60000000
232 #define CFG_SPDSTS1 0x40000000
233 #define CFG_SPDSTS0 0x20000000
234 #define CFG_DUPSTS 0x10000000
235 #define CFG_TBI_EN 0x01000000
236 #define CFG_MODE_1000 0x00400000
237 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
238 * Read the Phy response and then configure the MAC accordingly */
239 #define CFG_AUTO_1000 0x00200000
240 #define CFG_PINT_CTL 0x001c0000
241 #define CFG_PINT_DUPSTS 0x00100000
242 #define CFG_PINT_LNKSTS 0x00080000
243 #define CFG_PINT_SPDSTS 0x00040000
244 #define CFG_TMRTEST 0x00020000
245 #define CFG_MRM_DIS 0x00010000
246 #define CFG_MWI_DIS 0x00008000
247 #define CFG_T64ADDR 0x00004000
248 #define CFG_PCI64_DET 0x00002000
249 #define CFG_DATA64_EN 0x00001000
250 #define CFG_M64ADDR 0x00000800
251 #define CFG_PHY_RST 0x00000400
252 #define CFG_PHY_DIS 0x00000200
253 #define CFG_EXTSTS_EN 0x00000100
254 #define CFG_REQALG 0x00000080
255 #define CFG_SB 0x00000040
256 #define CFG_POW 0x00000020
257 #define CFG_EXD 0x00000010
258 #define CFG_PESEL 0x00000008
259 #define CFG_BROM_DIS 0x00000004
260 #define CFG_EXT_125 0x00000002
261 #define CFG_BEM 0x00000001
263 #define EXTSTS_UDPPKT 0x00200000
264 #define EXTSTS_TCPPKT 0x00080000
265 #define EXTSTS_IPPKT 0x00020000
266 #define EXTSTS_VPKT 0x00010000
267 #define EXTSTS_VTG_MASK 0x0000ffff
269 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
271 #define MIBC_MIBS 0x00000008
272 #define MIBC_ACLR 0x00000004
273 #define MIBC_FRZ 0x00000002
274 #define MIBC_WRN 0x00000001
276 #define PCR_PSEN (1 << 31)
277 #define PCR_PS_MCAST (1 << 30)
278 #define PCR_PS_DA (1 << 29)
279 #define PCR_STHI_8 (3 << 23)
280 #define PCR_STLO_4 (1 << 23)
281 #define PCR_FFHI_8K (3 << 21)
282 #define PCR_FFLO_4K (1 << 21)
283 #define PCR_PAUSE_CNT 0xFFFE
285 #define RXCFG_AEP 0x80000000
286 #define RXCFG_ARP 0x40000000
287 #define RXCFG_STRIPCRC 0x20000000
288 #define RXCFG_RX_FD 0x10000000
289 #define RXCFG_ALP 0x08000000
290 #define RXCFG_AIRL 0x04000000
291 #define RXCFG_MXDMA512 0x00700000
292 #define RXCFG_DRTH 0x0000003e
293 #define RXCFG_DRTH0 0x00000002
295 #define RFCR_RFEN 0x80000000
296 #define RFCR_AAB 0x40000000
297 #define RFCR_AAM 0x20000000
298 #define RFCR_AAU 0x10000000
299 #define RFCR_APM 0x08000000
300 #define RFCR_APAT 0x07800000
301 #define RFCR_APAT3 0x04000000
302 #define RFCR_APAT2 0x02000000
303 #define RFCR_APAT1 0x01000000
304 #define RFCR_APAT0 0x00800000
305 #define RFCR_AARP 0x00400000
306 #define RFCR_MHEN 0x00200000
307 #define RFCR_UHEN 0x00100000
308 #define RFCR_ULM 0x00080000
310 #define VRCR_RUDPE 0x00000080
311 #define VRCR_RTCPE 0x00000040
312 #define VRCR_RIPE 0x00000020
313 #define VRCR_IPEN 0x00000010
314 #define VRCR_DUTF 0x00000008
315 #define VRCR_DVTF 0x00000004
316 #define VRCR_VTREN 0x00000002
317 #define VRCR_VTDEN 0x00000001
319 #define VTCR_PPCHK 0x00000008
320 #define VTCR_GCHK 0x00000004
321 #define VTCR_VPPTI 0x00000002
322 #define VTCR_VGTI 0x00000001
359 #define TBICR_MR_AN_ENABLE 0x00001000
360 #define TBICR_MR_RESTART_AN 0x00000200
362 #define TBISR_MR_LINK_STATUS 0x00000020
363 #define TBISR_MR_AN_COMPLETE 0x00000004
365 #define TANAR_PS2 0x00000100
366 #define TANAR_PS1 0x00000080
367 #define TANAR_HALF_DUP 0x00000040
368 #define TANAR_FULL_DUP 0x00000020
370 #define GPIOR_GP5_OE 0x00000200
371 #define GPIOR_GP4_OE 0x00000100
372 #define GPIOR_GP3_OE 0x00000080
373 #define GPIOR_GP2_OE 0x00000040
374 #define GPIOR_GP1_OE 0x00000020
375 #define GPIOR_GP3_OUT 0x00000004
376 #define GPIOR_GP1_OUT 0x00000001
378 #define LINK_AUTONEGOTIATE 0x01
379 #define LINK_DOWN 0x02
382 #define HW_ADDR_LEN sizeof(dma_addr_t)
383 #define desc_addr_set(desc, addr) \
385 ((desc)[0] = cpu_to_le32(addr)); \
386 if (HW_ADDR_LEN == 8) \
387 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
389 #define desc_addr_get(desc) \
390 (le32_to_cpu((desc)[0]) | \
391 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
394 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
395 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
396 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
398 #define CMDSTS_OWN 0x80000000
399 #define CMDSTS_MORE 0x40000000
400 #define CMDSTS_INTR 0x20000000
401 #define CMDSTS_ERR 0x10000000
402 #define CMDSTS_OK 0x08000000
403 #define CMDSTS_RUNT 0x00200000
404 #define CMDSTS_LEN_MASK 0x0000ffff
406 #define CMDSTS_DEST_MASK 0x01800000
407 #define CMDSTS_DEST_SELF 0x00800000
408 #define CMDSTS_DEST_MULTI 0x01000000
410 #define DESC_SIZE 8 /* Should be cache line sized */
417 struct sk_buff *skbs[NR_RX_DESC];
419 __le32 *next_rx_desc;
420 u16 next_rx, next_empty;
423 dma_addr_t phy_descs;
430 struct pci_dev *pci_dev;
431 struct net_device *ndev;
433 #ifdef NS83820_VLAN_ACCEL_SUPPORT
434 struct vlan_group *vlgrp;
437 struct rx_info rx_info;
438 struct tasklet_struct rx_tasklet;
441 struct work_struct tq_refill;
443 /* protects everything below. irqsave when using. */
444 spinlock_t misc_lock;
457 volatile u16 tx_free_idx; /* idx of free desc chain */
461 struct sk_buff *tx_skbs[NR_TX_DESC];
463 char pad[16] __attribute__((aligned(16)));
465 dma_addr_t tx_phy_descs;
467 struct timer_list tx_watchdog;
470 static inline struct ns83820 *PRIV(struct net_device *dev)
472 return netdev_priv(dev);
475 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
477 static inline void kick_rx(struct net_device *ndev)
479 struct ns83820 *dev = PRIV(ndev);
480 dprintk("kick_rx: maybe kicking\n");
481 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
482 dprintk("actually kicking\n");
483 writel(dev->rx_info.phy_descs +
484 (4 * DESC_SIZE * dev->rx_info.next_rx),
486 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
487 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
493 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
494 #define start_tx_okay(dev) \
495 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
498 #ifdef NS83820_VLAN_ACCEL_SUPPORT
499 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
501 struct ns83820 *dev = PRIV(ndev);
503 spin_lock_irq(&dev->misc_lock);
504 spin_lock(&dev->tx_lock);
508 spin_unlock(&dev->tx_lock);
509 spin_unlock_irq(&dev->misc_lock);
515 * The hardware supports linked lists of receive descriptors for
516 * which ownership is transferred back and forth by means of an
517 * ownership bit. While the hardware does support the use of a
518 * ring for receive descriptors, we only make use of a chain in
519 * an attempt to reduce bus traffic under heavy load scenarios.
520 * This will also make bugs a bit more obvious. The current code
521 * only makes use of a single rx chain; I hope to implement
522 * priority based rx for version 1.0. Goal: even under overload
523 * conditions, still route realtime traffic with as low jitter as
526 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
528 desc_addr_set(desc + DESC_LINK, link);
529 desc_addr_set(desc + DESC_BUFPTR, buf);
530 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
532 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
535 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
536 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
543 next_empty = dev->rx_info.next_empty;
545 /* don't overrun last rx marker */
546 if (unlikely(nr_rx_empty(dev) <= 2)) {
552 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
553 dev->rx_info.next_empty,
554 dev->rx_info.nr_used,
559 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
560 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
561 dev->rx_info.skbs[next_empty] = skb;
563 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
564 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
565 buf = pci_map_single(dev->pci_dev, skb->data,
566 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
567 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
568 /* update link of previous rx */
569 if (likely(next_empty != dev->rx_info.next_rx))
570 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
575 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
577 struct ns83820 *dev = PRIV(ndev);
579 unsigned long flags = 0;
581 if (unlikely(nr_rx_empty(dev) <= 2))
584 dprintk("rx_refill(%p)\n", ndev);
585 if (gfp == GFP_ATOMIC)
586 spin_lock_irqsave(&dev->rx_info.lock, flags);
587 for (i=0; i<NR_RX_DESC; i++) {
591 /* extra 16 bytes for alignment */
592 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
596 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
597 if (gfp != GFP_ATOMIC)
598 spin_lock_irqsave(&dev->rx_info.lock, flags);
599 res = ns83820_add_rx_skb(dev, skb);
600 if (gfp != GFP_ATOMIC)
601 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
607 if (gfp == GFP_ATOMIC)
608 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
610 return i ? 0 : -ENOMEM;
613 static void rx_refill_atomic(struct net_device *ndev)
615 rx_refill(ndev, GFP_ATOMIC);
619 static inline void queue_refill(struct work_struct *work)
621 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
622 struct net_device *ndev = dev->ndev;
624 rx_refill(ndev, GFP_KERNEL);
629 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
631 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
634 static void phy_intr(struct net_device *ndev)
636 struct ns83820 *dev = PRIV(ndev);
637 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
639 u32 tbisr, tanar, tanlpar;
640 int speed, fullduplex, newlinkstate;
642 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
644 if (dev->CFG_cache & CFG_TBI_EN) {
645 /* we have an optical transceiver */
646 tbisr = readl(dev->base + TBISR);
647 tanar = readl(dev->base + TANAR);
648 tanlpar = readl(dev->base + TANLPAR);
649 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
650 tbisr, tanar, tanlpar);
652 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
653 (tanar & TANAR_FULL_DUP)) ) {
655 /* both of us are full duplex */
656 writel(readl(dev->base + TXCFG)
657 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
659 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
661 /* Light up full duplex LED */
662 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
665 } else if (((tanlpar & TANAR_HALF_DUP) &&
666 (tanar & TANAR_HALF_DUP)) ||
667 ((tanlpar & TANAR_FULL_DUP) &&
668 (tanar & TANAR_HALF_DUP)) ||
669 ((tanlpar & TANAR_HALF_DUP) &&
670 (tanar & TANAR_FULL_DUP))) {
672 /* one or both of us are half duplex */
673 writel((readl(dev->base + TXCFG)
674 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
676 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
678 /* Turn off full duplex LED */
679 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
683 speed = 4; /* 1000F */
686 /* we have a copper transceiver */
687 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
689 if (cfg & CFG_SPDSTS1)
690 new_cfg |= CFG_MODE_1000;
692 new_cfg &= ~CFG_MODE_1000;
694 speed = ((cfg / CFG_SPDSTS0) & 3);
695 fullduplex = (cfg & CFG_DUPSTS);
699 writel(readl(dev->base + TXCFG)
700 | TXCFG_CSI | TXCFG_HBI,
702 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
705 writel(readl(dev->base + TXCFG)
706 & ~(TXCFG_CSI | TXCFG_HBI),
708 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
712 if ((cfg & CFG_LNKSTS) &&
713 ((new_cfg ^ dev->CFG_cache) != 0)) {
714 writel(new_cfg, dev->base + CFG);
715 dev->CFG_cache = new_cfg;
718 dev->CFG_cache &= ~CFG_SPDSTS;
719 dev->CFG_cache |= cfg & CFG_SPDSTS;
722 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
724 if (newlinkstate & LINK_UP &&
725 dev->linkstate != newlinkstate) {
726 netif_start_queue(ndev);
727 netif_wake_queue(ndev);
728 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
731 fullduplex ? "full" : "half");
732 } else if (newlinkstate & LINK_DOWN &&
733 dev->linkstate != newlinkstate) {
734 netif_stop_queue(ndev);
735 printk(KERN_INFO "%s: link now down.\n", ndev->name);
738 dev->linkstate = newlinkstate;
741 static int ns83820_setup_rx(struct net_device *ndev)
743 struct ns83820 *dev = PRIV(ndev);
747 dprintk("ns83820_setup_rx(%p)\n", ndev);
749 dev->rx_info.idle = 1;
750 dev->rx_info.next_rx = 0;
751 dev->rx_info.next_rx_desc = dev->rx_info.descs;
752 dev->rx_info.next_empty = 0;
754 for (i=0; i<NR_RX_DESC; i++)
755 clear_rx_desc(dev, i);
757 writel(0, dev->base + RXDP_HI);
758 writel(dev->rx_info.phy_descs, dev->base + RXDP);
760 ret = rx_refill(ndev, GFP_KERNEL);
762 dprintk("starting receiver\n");
763 /* prevent the interrupt handler from stomping on us */
764 spin_lock_irq(&dev->rx_info.lock);
766 writel(0x0001, dev->base + CCSR);
767 writel(0, dev->base + RFCR);
768 writel(0x7fc00000, dev->base + RFCR);
769 writel(0xffc00000, dev->base + RFCR);
775 /* Okay, let it rip */
776 spin_lock(&dev->misc_lock);
777 dev->IMR_cache |= ISR_PHY;
778 dev->IMR_cache |= ISR_RXRCMP;
779 //dev->IMR_cache |= ISR_RXERR;
780 //dev->IMR_cache |= ISR_RXOK;
781 dev->IMR_cache |= ISR_RXORN;
782 dev->IMR_cache |= ISR_RXSOVR;
783 dev->IMR_cache |= ISR_RXDESC;
784 dev->IMR_cache |= ISR_RXIDLE;
785 dev->IMR_cache |= ISR_TXDESC;
786 dev->IMR_cache |= ISR_TXIDLE;
788 writel(dev->IMR_cache, dev->base + IMR);
789 writel(1, dev->base + IER);
790 spin_unlock(&dev->misc_lock);
794 spin_unlock_irq(&dev->rx_info.lock);
799 static void ns83820_cleanup_rx(struct ns83820 *dev)
804 dprintk("ns83820_cleanup_rx(%p)\n", dev);
806 /* disable receive interrupts */
807 spin_lock_irqsave(&dev->misc_lock, flags);
808 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
809 writel(dev->IMR_cache, dev->base + IMR);
810 spin_unlock_irqrestore(&dev->misc_lock, flags);
812 /* synchronize with the interrupt handler and kill it */
814 synchronize_irq(dev->pci_dev->irq);
816 /* touch the pci bus... */
817 readl(dev->base + IMR);
819 /* assumes the transmitter is already disabled and reset */
820 writel(0, dev->base + RXDP_HI);
821 writel(0, dev->base + RXDP);
823 for (i=0; i<NR_RX_DESC; i++) {
824 struct sk_buff *skb = dev->rx_info.skbs[i];
825 dev->rx_info.skbs[i] = NULL;
826 clear_rx_desc(dev, i);
831 static void ns83820_rx_kick(struct net_device *ndev)
833 struct ns83820 *dev = PRIV(ndev);
834 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
835 if (dev->rx_info.up) {
836 rx_refill_atomic(ndev);
841 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
842 schedule_work(&dev->tq_refill);
845 if (dev->rx_info.idle)
846 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
852 static void rx_irq(struct net_device *ndev)
854 struct ns83820 *dev = PRIV(ndev);
855 struct rx_info *info = &dev->rx_info;
863 dprintk("rx_irq(%p)\n", ndev);
864 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
865 readl(dev->base + RXDP),
866 (long)(dev->rx_info.phy_descs),
867 (int)dev->rx_info.next_rx,
868 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
869 (int)dev->rx_info.next_empty,
870 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
873 spin_lock_irqsave(&info->lock, flags);
877 dprintk("walking descs\n");
878 next_rx = info->next_rx;
879 desc = info->next_rx_desc;
880 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
881 (cmdsts != CMDSTS_OWN)) {
883 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
884 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
886 dprintk("cmdsts: %08x\n", cmdsts);
887 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
888 dprintk("extsts: %08x\n", extsts);
890 skb = info->skbs[next_rx];
891 info->skbs[next_rx] = NULL;
892 info->next_rx = (next_rx + 1) % NR_RX_DESC;
895 clear_rx_desc(dev, next_rx);
897 pci_unmap_single(dev->pci_dev, bufptr,
898 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
899 len = cmdsts & CMDSTS_LEN_MASK;
900 #ifdef NS83820_VLAN_ACCEL_SUPPORT
901 /* NH: As was mentioned below, this chip is kinda
902 * brain dead about vlan tag stripping. Frames
903 * that are 64 bytes with a vlan header appended
904 * like arp frames, or pings, are flagged as Runts
905 * when the tag is stripped and hardware. This
906 * also means that the OK bit in the descriptor
907 * is cleared when the frame comes in so we have
908 * to do a specific length check here to make sure
909 * the frame would have been ok, had we not stripped
912 if (likely((CMDSTS_OK & cmdsts) ||
913 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
915 if (likely(CMDSTS_OK & cmdsts)) {
919 goto netdev_mangle_me_harder_failed;
920 if (cmdsts & CMDSTS_DEST_MULTI)
921 ndev->stats.multicast++;
922 ndev->stats.rx_packets++;
923 ndev->stats.rx_bytes += len;
924 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
925 skb->ip_summed = CHECKSUM_UNNECESSARY;
927 skb_checksum_none_assert(skb);
929 skb->protocol = eth_type_trans(skb, ndev);
930 #ifdef NS83820_VLAN_ACCEL_SUPPORT
931 if(extsts & EXTSTS_VPKT) {
933 tag = ntohs(extsts & EXTSTS_VTG_MASK);
934 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
936 rx_rc = netif_rx(skb);
939 rx_rc = netif_rx(skb);
941 if (NET_RX_DROP == rx_rc) {
942 netdev_mangle_me_harder_failed:
943 ndev->stats.rx_dropped++;
950 next_rx = info->next_rx;
951 desc = info->descs + (DESC_SIZE * next_rx);
953 info->next_rx = next_rx;
954 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
958 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
961 spin_unlock_irqrestore(&info->lock, flags);
964 static void rx_action(unsigned long _dev)
966 struct net_device *ndev = (void *)_dev;
967 struct ns83820 *dev = PRIV(ndev);
969 writel(ihr, dev->base + IHR);
971 spin_lock_irq(&dev->misc_lock);
972 dev->IMR_cache |= ISR_RXDESC;
973 writel(dev->IMR_cache, dev->base + IMR);
974 spin_unlock_irq(&dev->misc_lock);
977 ns83820_rx_kick(ndev);
980 /* Packet Transmit code
982 static inline void kick_tx(struct ns83820 *dev)
984 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
985 dev, dev->tx_idx, dev->tx_free_idx);
986 writel(CR_TXE, dev->base + CR);
989 /* No spinlock needed on the transmit irq path as the interrupt handler is
992 static void do_tx_done(struct net_device *ndev)
994 struct ns83820 *dev = PRIV(ndev);
995 u32 cmdsts, tx_done_idx;
998 dprintk("do_tx_done(%p)\n", ndev);
999 tx_done_idx = dev->tx_done_idx;
1000 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1002 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1003 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1004 while ((tx_done_idx != dev->tx_free_idx) &&
1005 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1006 struct sk_buff *skb;
1010 if (cmdsts & CMDSTS_ERR)
1011 ndev->stats.tx_errors++;
1012 if (cmdsts & CMDSTS_OK)
1013 ndev->stats.tx_packets++;
1014 if (cmdsts & CMDSTS_OK)
1015 ndev->stats.tx_bytes += cmdsts & 0xffff;
1017 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1018 tx_done_idx, dev->tx_free_idx, cmdsts);
1019 skb = dev->tx_skbs[tx_done_idx];
1020 dev->tx_skbs[tx_done_idx] = NULL;
1021 dprintk("done(%p)\n", skb);
1023 len = cmdsts & CMDSTS_LEN_MASK;
1024 addr = desc_addr_get(desc + DESC_BUFPTR);
1026 pci_unmap_single(dev->pci_dev,
1030 dev_kfree_skb_irq(skb);
1031 atomic_dec(&dev->nr_tx_skbs);
1033 pci_unmap_page(dev->pci_dev,
1038 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1039 dev->tx_done_idx = tx_done_idx;
1040 desc[DESC_CMDSTS] = cpu_to_le32(0);
1042 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1045 /* Allow network stack to resume queueing packets after we've
1046 * finished transmitting at least 1/4 of the packets in the queue.
1048 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1049 dprintk("start_queue(%p)\n", ndev);
1050 netif_start_queue(ndev);
1051 netif_wake_queue(ndev);
1055 static void ns83820_cleanup_tx(struct ns83820 *dev)
1059 for (i=0; i<NR_TX_DESC; i++) {
1060 struct sk_buff *skb = dev->tx_skbs[i];
1061 dev->tx_skbs[i] = NULL;
1063 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1064 pci_unmap_single(dev->pci_dev,
1065 desc_addr_get(desc + DESC_BUFPTR),
1066 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1068 dev_kfree_skb_irq(skb);
1069 atomic_dec(&dev->nr_tx_skbs);
1073 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1076 /* transmit routine. This code relies on the network layer serializing
1077 * its calls in, but will run happily in parallel with the interrupt
1078 * handler. This code currently has provisions for fragmenting tx buffers
1079 * while trying to track down a bug in either the zero copy code or
1080 * the tx fifo (hence the MAX_FRAG_LEN).
1082 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1083 struct net_device *ndev)
1085 struct ns83820 *dev = PRIV(ndev);
1086 u32 free_idx, cmdsts, extsts;
1087 int nr_free, nr_frags;
1088 unsigned tx_done_idx, last_idx;
1094 volatile __le32 *first_desc;
1096 dprintk("ns83820_hard_start_xmit\n");
1098 nr_frags = skb_shinfo(skb)->nr_frags;
1100 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1101 netif_stop_queue(ndev);
1102 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1103 return NETDEV_TX_BUSY;
1104 netif_start_queue(ndev);
1107 last_idx = free_idx = dev->tx_free_idx;
1108 tx_done_idx = dev->tx_done_idx;
1109 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1111 if (nr_free <= nr_frags) {
1112 dprintk("stop_queue - not enough(%p)\n", ndev);
1113 netif_stop_queue(ndev);
1115 /* Check again: we may have raced with a tx done irq */
1116 if (dev->tx_done_idx != tx_done_idx) {
1117 dprintk("restart queue(%p)\n", ndev);
1118 netif_start_queue(ndev);
1121 return NETDEV_TX_BUSY;
1124 if (free_idx == dev->tx_intr_idx) {
1126 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1129 nr_free -= nr_frags;
1130 if (nr_free < MIN_TX_DESC_FREE) {
1131 dprintk("stop_queue - last entry(%p)\n", ndev);
1132 netif_stop_queue(ndev);
1136 frag = skb_shinfo(skb)->frags;
1140 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1141 extsts |= EXTSTS_IPPKT;
1142 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1143 extsts |= EXTSTS_TCPPKT;
1144 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1145 extsts |= EXTSTS_UDPPKT;
1148 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1149 if(vlan_tx_tag_present(skb)) {
1150 /* fetch the vlan tag info out of the
1151 * ancillary data if the vlan code
1152 * is using hw vlan acceleration
1154 short tag = vlan_tx_tag_get(skb);
1155 extsts |= (EXTSTS_VPKT | htons(tag));
1161 len -= skb->data_len;
1162 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1164 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1167 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1169 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1170 (unsigned long long)buf);
1171 last_idx = free_idx;
1172 free_idx = (free_idx + 1) % NR_TX_DESC;
1173 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1174 desc_addr_set(desc + DESC_BUFPTR, buf);
1175 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1177 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1178 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1180 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1185 buf = pci_map_page(dev->pci_dev, frag->page,
1187 frag->size, PCI_DMA_TODEVICE);
1188 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1189 (long long)buf, (long) page_to_pfn(frag->page),
1195 dprintk("done pkt\n");
1197 spin_lock_irq(&dev->tx_lock);
1198 dev->tx_skbs[last_idx] = skb;
1199 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1200 dev->tx_free_idx = free_idx;
1201 atomic_inc(&dev->nr_tx_skbs);
1202 spin_unlock_irq(&dev->tx_lock);
1206 /* Check again: we may have raced with a tx done irq */
1207 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1208 netif_start_queue(ndev);
1210 return NETDEV_TX_OK;
1213 static void ns83820_update_stats(struct ns83820 *dev)
1215 struct net_device *ndev = dev->ndev;
1216 u8 __iomem *base = dev->base;
1218 /* the DP83820 will freeze counters, so we need to read all of them */
1219 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1220 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1221 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1222 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1223 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1224 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1225 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1226 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1227 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1228 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1229 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1232 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1234 struct ns83820 *dev = PRIV(ndev);
1236 /* somewhat overkill */
1237 spin_lock_irq(&dev->misc_lock);
1238 ns83820_update_stats(dev);
1239 spin_unlock_irq(&dev->misc_lock);
1241 return &ndev->stats;
1244 /* Let ethtool retrieve info */
1245 static int ns83820_get_settings(struct net_device *ndev,
1246 struct ethtool_cmd *cmd)
1248 struct ns83820 *dev = PRIV(ndev);
1249 u32 cfg, tanar, tbicr;
1253 * Here's the list of available ethtool commands from other drivers:
1254 * cmd->advertising =
1255 * ethtool_cmd_speed_set(cmd, ...)
1258 * cmd->phy_address =
1259 * cmd->transceiver = 0;
1261 * cmd->maxtxpkt = 0;
1262 * cmd->maxrxpkt = 0;
1265 /* read current configuration */
1266 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1267 tanar = readl(dev->base + TANAR);
1268 tbicr = readl(dev->base + TBICR);
1270 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1272 cmd->supported = SUPPORTED_Autoneg;
1274 if (dev->CFG_cache & CFG_TBI_EN) {
1275 /* we have optical interface */
1276 cmd->supported |= SUPPORTED_1000baseT_Half |
1277 SUPPORTED_1000baseT_Full |
1279 cmd->port = PORT_FIBRE;
1281 /* we have copper */
1282 cmd->supported |= SUPPORTED_10baseT_Half |
1283 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1284 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1285 SUPPORTED_1000baseT_Full |
1287 cmd->port = PORT_MII;
1290 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1291 switch (cfg / CFG_SPDSTS0 & 3) {
1293 ethtool_cmd_speed_set(cmd, SPEED_1000);
1296 ethtool_cmd_speed_set(cmd, SPEED_100);
1299 ethtool_cmd_speed_set(cmd, SPEED_10);
1302 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1303 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1307 /* Let ethool change settings*/
1308 static int ns83820_set_settings(struct net_device *ndev,
1309 struct ethtool_cmd *cmd)
1311 struct ns83820 *dev = PRIV(ndev);
1313 int have_optical = 0;
1316 /* read current configuration */
1317 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1318 tanar = readl(dev->base + TANAR);
1320 if (dev->CFG_cache & CFG_TBI_EN) {
1321 /* we have optical */
1323 fullduplex = (tanar & TANAR_FULL_DUP);
1326 /* we have copper */
1327 fullduplex = cfg & CFG_DUPSTS;
1330 spin_lock_irq(&dev->misc_lock);
1331 spin_lock(&dev->tx_lock);
1334 if (cmd->duplex != fullduplex) {
1337 if (cmd->duplex == DUPLEX_FULL) {
1338 /* force full duplex */
1339 writel(readl(dev->base + TXCFG)
1340 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1342 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1344 /* Light up full duplex LED */
1345 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1348 /*TODO: set half duplex */
1353 /* TODO: Set duplex for copper cards */
1355 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1359 /* Set autonegotiation */
1361 if (cmd->autoneg == AUTONEG_ENABLE) {
1362 /* restart auto negotiation */
1363 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1365 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1366 dev->linkstate = LINK_AUTONEGOTIATE;
1368 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1371 /* disable auto negotiation */
1372 writel(0x00000000, dev->base + TBICR);
1375 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1376 cmd->autoneg ? "ENABLED" : "DISABLED");
1380 spin_unlock(&dev->tx_lock);
1381 spin_unlock_irq(&dev->misc_lock);
1385 /* end ethtool get/set support -df */
1387 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1389 struct ns83820 *dev = PRIV(ndev);
1390 strcpy(info->driver, "ns83820");
1391 strcpy(info->version, VERSION);
1392 strcpy(info->bus_info, pci_name(dev->pci_dev));
1395 static u32 ns83820_get_link(struct net_device *ndev)
1397 struct ns83820 *dev = PRIV(ndev);
1398 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1399 return cfg & CFG_LNKSTS ? 1 : 0;
1402 static const struct ethtool_ops ops = {
1403 .get_settings = ns83820_get_settings,
1404 .set_settings = ns83820_set_settings,
1405 .get_drvinfo = ns83820_get_drvinfo,
1406 .get_link = ns83820_get_link
1409 static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1411 writel(0, dev->base + IMR);
1412 writel(0, dev->base + IER);
1413 readl(dev->base + IER);
1416 /* this function is called in irq context from the ISR */
1417 static void ns83820_mib_isr(struct ns83820 *dev)
1419 unsigned long flags;
1420 spin_lock_irqsave(&dev->misc_lock, flags);
1421 ns83820_update_stats(dev);
1422 spin_unlock_irqrestore(&dev->misc_lock, flags);
1425 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1426 static irqreturn_t ns83820_irq(int foo, void *data)
1428 struct net_device *ndev = data;
1429 struct ns83820 *dev = PRIV(ndev);
1431 dprintk("ns83820_irq(%p)\n", ndev);
1435 isr = readl(dev->base + ISR);
1436 dprintk("irq: %08x\n", isr);
1437 ns83820_do_isr(ndev, isr);
1441 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1443 struct ns83820 *dev = PRIV(ndev);
1444 unsigned long flags;
1447 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1448 Dprintk("odd isr? 0x%08x\n", isr);
1451 if (ISR_RXIDLE & isr) {
1452 dev->rx_info.idle = 1;
1453 Dprintk("oh dear, we are idle\n");
1454 ns83820_rx_kick(ndev);
1457 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1458 prefetch(dev->rx_info.next_rx_desc);
1460 spin_lock_irqsave(&dev->misc_lock, flags);
1461 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1462 writel(dev->IMR_cache, dev->base + IMR);
1463 spin_unlock_irqrestore(&dev->misc_lock, flags);
1465 tasklet_schedule(&dev->rx_tasklet);
1467 //writel(4, dev->base + IHR);
1470 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1471 ns83820_rx_kick(ndev);
1473 if (unlikely(ISR_RXSOVR & isr)) {
1474 //printk("overrun: rxsovr\n");
1475 ndev->stats.rx_fifo_errors++;
1478 if (unlikely(ISR_RXORN & isr)) {
1479 //printk("overrun: rxorn\n");
1480 ndev->stats.rx_fifo_errors++;
1483 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1484 writel(CR_RXE, dev->base + CR);
1486 if (ISR_TXIDLE & isr) {
1488 txdp = readl(dev->base + TXDP);
1489 dprintk("txdp: %08x\n", txdp);
1490 txdp -= dev->tx_phy_descs;
1491 dev->tx_idx = txdp / (DESC_SIZE * 4);
1492 if (dev->tx_idx >= NR_TX_DESC) {
1493 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1496 /* The may have been a race between a pci originated read
1497 * and the descriptor update from the cpu. Just in case,
1498 * kick the transmitter if the hardware thinks it is on a
1499 * different descriptor than we are.
1501 if (dev->tx_idx != dev->tx_free_idx)
1505 /* Defer tx ring processing until more than a minimum amount of
1506 * work has accumulated
1508 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1509 spin_lock_irqsave(&dev->tx_lock, flags);
1511 spin_unlock_irqrestore(&dev->tx_lock, flags);
1513 /* Disable TxOk if there are no outstanding tx packets.
1515 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1516 (dev->IMR_cache & ISR_TXOK)) {
1517 spin_lock_irqsave(&dev->misc_lock, flags);
1518 dev->IMR_cache &= ~ISR_TXOK;
1519 writel(dev->IMR_cache, dev->base + IMR);
1520 spin_unlock_irqrestore(&dev->misc_lock, flags);
1524 /* The TxIdle interrupt can come in before the transmit has
1525 * completed. Normally we reap packets off of the combination
1526 * of TxDesc and TxIdle and leave TxOk disabled (since it
1527 * occurs on every packet), but when no further irqs of this
1528 * nature are expected, we must enable TxOk.
1530 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1531 spin_lock_irqsave(&dev->misc_lock, flags);
1532 dev->IMR_cache |= ISR_TXOK;
1533 writel(dev->IMR_cache, dev->base + IMR);
1534 spin_unlock_irqrestore(&dev->misc_lock, flags);
1537 /* MIB interrupt: one of the statistics counters is about to overflow */
1538 if (unlikely(ISR_MIB & isr))
1539 ns83820_mib_isr(dev);
1541 /* PHY: Link up/down/negotiation state change */
1542 if (unlikely(ISR_PHY & isr))
1545 #if 0 /* Still working on the interrupt mitigation strategy */
1547 writel(dev->ihr, dev->base + IHR);
1551 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1553 Dprintk("resetting chip...\n");
1554 writel(which, dev->base + CR);
1557 } while (readl(dev->base + CR) & which);
1561 static int ns83820_stop(struct net_device *ndev)
1563 struct ns83820 *dev = PRIV(ndev);
1565 /* FIXME: protect against interrupt handler? */
1566 del_timer_sync(&dev->tx_watchdog);
1568 ns83820_disable_interrupts(dev);
1570 dev->rx_info.up = 0;
1571 synchronize_irq(dev->pci_dev->irq);
1573 ns83820_do_reset(dev, CR_RST);
1575 synchronize_irq(dev->pci_dev->irq);
1577 spin_lock_irq(&dev->misc_lock);
1578 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1579 spin_unlock_irq(&dev->misc_lock);
1581 ns83820_cleanup_rx(dev);
1582 ns83820_cleanup_tx(dev);
1587 static void ns83820_tx_timeout(struct net_device *ndev)
1589 struct ns83820 *dev = PRIV(ndev);
1592 unsigned long flags;
1594 spin_lock_irqsave(&dev->tx_lock, flags);
1596 tx_done_idx = dev->tx_done_idx;
1597 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1599 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1601 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1606 isr = readl(dev->base + ISR);
1607 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1608 ns83820_do_isr(ndev, isr);
1614 tx_done_idx = dev->tx_done_idx;
1615 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1617 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1619 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1621 spin_unlock_irqrestore(&dev->tx_lock, flags);
1624 static void ns83820_tx_watch(unsigned long data)
1626 struct net_device *ndev = (void *)data;
1627 struct ns83820 *dev = PRIV(ndev);
1630 printk("ns83820_tx_watch: %u %u %d\n",
1631 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1635 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1636 dev->tx_done_idx != dev->tx_free_idx) {
1637 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1639 dev->tx_done_idx, dev->tx_free_idx,
1640 atomic_read(&dev->nr_tx_skbs));
1641 ns83820_tx_timeout(ndev);
1644 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1647 static int ns83820_open(struct net_device *ndev)
1649 struct ns83820 *dev = PRIV(ndev);
1654 dprintk("ns83820_open\n");
1656 writel(0, dev->base + PQCR);
1658 ret = ns83820_setup_rx(ndev);
1662 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1663 for (i=0; i<NR_TX_DESC; i++) {
1664 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1667 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1671 dev->tx_done_idx = 0;
1672 desc = dev->tx_phy_descs;
1673 writel(0, dev->base + TXDP_HI);
1674 writel(desc, dev->base + TXDP);
1676 init_timer(&dev->tx_watchdog);
1677 dev->tx_watchdog.data = (unsigned long)ndev;
1678 dev->tx_watchdog.function = ns83820_tx_watch;
1679 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1681 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1690 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1693 for (i=0; i<3; i++) {
1696 /* Read from the perfect match memory: this is loaded by
1697 * the chip from the EEPROM via the EELOAD self test.
1699 writel(i*2, dev->base + RFCR);
1700 data = readl(dev->base + RFDR);
1707 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1709 if (new_mtu > RX_BUF_SIZE)
1711 ndev->mtu = new_mtu;
1715 static void ns83820_set_multicast(struct net_device *ndev)
1717 struct ns83820 *dev = PRIV(ndev);
1718 u8 __iomem *rfcr = dev->base + RFCR;
1719 u32 and_mask = 0xffffffff;
1723 if (ndev->flags & IFF_PROMISC)
1724 or_mask |= RFCR_AAU | RFCR_AAM;
1726 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1728 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1729 or_mask |= RFCR_AAM;
1731 and_mask &= ~RFCR_AAM;
1733 spin_lock_irq(&dev->misc_lock);
1734 val = (readl(rfcr) & and_mask) | or_mask;
1735 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1736 writel(val & ~RFCR_RFEN, rfcr);
1738 spin_unlock_irq(&dev->misc_lock);
1741 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1743 struct ns83820 *dev = PRIV(ndev);
1745 unsigned long start;
1749 dprintk("%s: start %s\n", ndev->name, name);
1753 writel(enable, dev->base + PTSCR);
1756 status = readl(dev->base + PTSCR);
1757 if (!(status & enable))
1763 if (time_after_eq(jiffies, start + HZ)) {
1767 schedule_timeout_uninterruptible(1);
1771 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1772 ndev->name, name, status, fail);
1774 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1775 ndev->name, name, status);
1777 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1780 #ifdef PHY_CODE_IS_FINISHED
1781 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1784 dev->MEAR_cache &= ~MEAR_MDC;
1785 writel(dev->MEAR_cache, dev->base + MEAR);
1786 readl(dev->base + MEAR);
1788 /* enable output, set bit */
1789 dev->MEAR_cache |= MEAR_MDDIR;
1791 dev->MEAR_cache |= MEAR_MDIO;
1793 dev->MEAR_cache &= ~MEAR_MDIO;
1795 /* set the output bit */
1796 writel(dev->MEAR_cache, dev->base + MEAR);
1797 readl(dev->base + MEAR);
1799 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1802 /* drive MDC high causing the data bit to be latched */
1803 dev->MEAR_cache |= MEAR_MDC;
1804 writel(dev->MEAR_cache, dev->base + MEAR);
1805 readl(dev->base + MEAR);
1811 static int ns83820_mii_read_bit(struct ns83820 *dev)
1815 /* drive MDC low, disable output */
1816 dev->MEAR_cache &= ~MEAR_MDC;
1817 dev->MEAR_cache &= ~MEAR_MDDIR;
1818 writel(dev->MEAR_cache, dev->base + MEAR);
1819 readl(dev->base + MEAR);
1821 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1824 /* drive MDC high causing the data bit to be latched */
1825 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1826 dev->MEAR_cache |= MEAR_MDC;
1827 writel(dev->MEAR_cache, dev->base + MEAR);
1835 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1840 /* read some garbage so that we eventually sync up */
1841 for (i=0; i<64; i++)
1842 ns83820_mii_read_bit(dev);
1844 ns83820_mii_write_bit(dev, 0); /* start */
1845 ns83820_mii_write_bit(dev, 1);
1846 ns83820_mii_write_bit(dev, 1); /* opcode read */
1847 ns83820_mii_write_bit(dev, 0);
1849 /* write out the phy address: 5 bits, msb first */
1851 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1853 /* write out the register address, 5 bits, msb first */
1855 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1857 ns83820_mii_read_bit(dev); /* turn around cycles */
1858 ns83820_mii_read_bit(dev);
1860 /* read in the register data, 16 bits msb first */
1861 for (i=0; i<16; i++) {
1863 data |= ns83820_mii_read_bit(dev);
1869 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1873 /* read some garbage so that we eventually sync up */
1874 for (i=0; i<64; i++)
1875 ns83820_mii_read_bit(dev);
1877 ns83820_mii_write_bit(dev, 0); /* start */
1878 ns83820_mii_write_bit(dev, 1);
1879 ns83820_mii_write_bit(dev, 0); /* opcode read */
1880 ns83820_mii_write_bit(dev, 1);
1882 /* write out the phy address: 5 bits, msb first */
1884 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1886 /* write out the register address, 5 bits, msb first */
1888 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1890 ns83820_mii_read_bit(dev); /* turn around cycles */
1891 ns83820_mii_read_bit(dev);
1893 /* read in the register data, 16 bits msb first */
1894 for (i=0; i<16; i++)
1895 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1900 static void ns83820_probe_phy(struct net_device *ndev)
1902 struct ns83820 *dev = PRIV(ndev);
1905 #define MII_PHYIDR1 0x02
1906 #define MII_PHYIDR2 0x03
1911 ns83820_mii_read_reg(dev, 1, 0x09);
1912 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1914 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1915 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1917 ns83820_mii_read_reg(dev, 1, 0x09);
1922 for (i=1; i<2; i++) {
1925 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1926 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1928 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1929 // ndev->name, i, a, b);
1931 for (j=0; j<0x16; j+=4) {
1932 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1934 ns83820_mii_read_reg(dev, i, 0 + j),
1935 ns83820_mii_read_reg(dev, i, 1 + j),
1936 ns83820_mii_read_reg(dev, i, 2 + j),
1937 ns83820_mii_read_reg(dev, i, 3 + j)
1943 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1944 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1945 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1946 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1948 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1949 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1950 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1951 dprintk("version: 0x%04x 0x%04x\n", a, b);
1956 static const struct net_device_ops netdev_ops = {
1957 .ndo_open = ns83820_open,
1958 .ndo_stop = ns83820_stop,
1959 .ndo_start_xmit = ns83820_hard_start_xmit,
1960 .ndo_get_stats = ns83820_get_stats,
1961 .ndo_change_mtu = ns83820_change_mtu,
1962 .ndo_set_multicast_list = ns83820_set_multicast,
1963 .ndo_validate_addr = eth_validate_addr,
1964 .ndo_set_mac_address = eth_mac_addr,
1965 .ndo_tx_timeout = ns83820_tx_timeout,
1966 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1967 .ndo_vlan_rx_register = ns83820_vlan_rx_register,
1971 static int __devinit ns83820_init_one(struct pci_dev *pci_dev,
1972 const struct pci_device_id *id)
1974 struct net_device *ndev;
1975 struct ns83820 *dev;
1980 /* See if we can set the dma mask early on; failure is fatal. */
1981 if (sizeof(dma_addr_t) == 8 &&
1982 !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
1984 } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
1987 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1991 ndev = alloc_etherdev(sizeof(struct ns83820));
1999 spin_lock_init(&dev->rx_info.lock);
2000 spin_lock_init(&dev->tx_lock);
2001 spin_lock_init(&dev->misc_lock);
2002 dev->pci_dev = pci_dev;
2004 SET_NETDEV_DEV(ndev, &pci_dev->dev);
2006 INIT_WORK(&dev->tq_refill, queue_refill);
2007 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
2009 err = pci_enable_device(pci_dev);
2011 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
2015 pci_set_master(pci_dev);
2016 addr = pci_resource_start(pci_dev, 1);
2017 dev->base = ioremap_nocache(addr, PAGE_SIZE);
2018 dev->tx_descs = pci_alloc_consistent(pci_dev,
2019 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
2020 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
2021 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2023 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2026 dprintk("%p: %08lx %p: %08lx\n",
2027 dev->tx_descs, (long)dev->tx_phy_descs,
2028 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2030 ns83820_disable_interrupts(dev);
2034 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2037 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2043 * FIXME: we are holding rtnl_lock() over obscenely long area only
2044 * because some of the setup code uses dev->name. It's Wrong(tm) -
2045 * we should be using driver-specific names for all that stuff.
2046 * For now that will do, but we really need to come back and kill
2047 * most of the dev_alloc_name() users later.
2050 err = dev_alloc_name(ndev, ndev->name);
2052 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2056 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2057 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2058 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2060 ndev->netdev_ops = &netdev_ops;
2061 SET_ETHTOOL_OPS(ndev, &ops);
2062 ndev->watchdog_timeo = 5 * HZ;
2063 pci_set_drvdata(pci_dev, ndev);
2065 ns83820_do_reset(dev, CR_RST);
2067 /* Must reset the ram bist before running it */
2068 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2069 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2070 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2071 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2073 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2075 /* I love config registers */
2076 dev->CFG_cache = readl(dev->base + CFG);
2078 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2079 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2081 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2082 if (!(dev->CFG_cache & CFG_DATA64_EN))
2083 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2086 dev->CFG_cache &= ~(CFG_DATA64_EN);
2088 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2089 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2091 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2092 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2093 dev->CFG_cache |= CFG_REQALG;
2094 dev->CFG_cache |= CFG_POW;
2095 dev->CFG_cache |= CFG_TMRTEST;
2097 /* When compiled with 64 bit addressing, we must always enable
2098 * the 64 bit descriptor format.
2100 if (sizeof(dma_addr_t) == 8)
2101 dev->CFG_cache |= CFG_M64ADDR;
2103 dev->CFG_cache |= CFG_T64ADDR;
2105 /* Big endian mode does not seem to do what the docs suggest */
2106 dev->CFG_cache &= ~CFG_BEM;
2108 /* setup optical transceiver if we have one */
2109 if (dev->CFG_cache & CFG_TBI_EN) {
2110 printk(KERN_INFO "%s: enabling optical transceiver\n",
2112 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2114 /* setup auto negotiation feature advertisement */
2115 writel(readl(dev->base + TANAR)
2116 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2119 /* start auto negotiation */
2120 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2122 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2123 dev->linkstate = LINK_AUTONEGOTIATE;
2125 dev->CFG_cache |= CFG_MODE_1000;
2128 writel(dev->CFG_cache, dev->base + CFG);
2129 dprintk("CFG: %08x\n", dev->CFG_cache);
2132 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2133 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2135 writel(dev->CFG_cache, dev->base + CFG);
2138 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2139 * the PCI layer. FIXME.
2141 if (readl(dev->base + SRR))
2142 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2145 /* Note! The DMA burst size interacts with packet
2146 * transmission, such that the largest packet that
2147 * can be transmitted is 8192 - FLTH - burst size.
2148 * If only the transmit fifo was larger...
2150 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2151 * some DELL and COMPAQ SMP systems */
2152 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2153 | ((1600 / 32) * 0x100),
2156 /* Flush the interrupt holdoff timer */
2157 writel(0x000, dev->base + IHR);
2158 writel(0x100, dev->base + IHR);
2159 writel(0x000, dev->base + IHR);
2161 /* Set Rx to full duplex, don't accept runt, errored, long or length
2162 * range errored packets. Use 512 byte DMA.
2164 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2165 * some DELL and COMPAQ SMP systems
2166 * Turn on ALP, only we are accpeting Jumbo Packets */
2167 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2170 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2172 /* Disable priority queueing */
2173 writel(0, dev->base + PQCR);
2175 /* Enable IP checksum validation and detetion of VLAN headers.
2176 * Note: do not set the reject options as at least the 0x102
2177 * revision of the chip does not properly accept IP fragments
2180 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2181 * the MAC it calculates the packetsize AFTER stripping the VLAN
2182 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2183 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2184 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2185 * it discrards it!. These guys......
2186 * also turn on tag stripping if hardware acceleration is enabled
2188 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2189 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2191 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2193 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2195 /* Enable per-packet TCP/UDP/IP checksumming
2196 * and per packet vlan tag insertion if
2197 * vlan hardware acceleration is enabled
2199 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2200 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2202 #define VTCR_INIT_VALUE VTCR_PPCHK
2204 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2206 /* Ramit : Enable async and sync pause frames */
2207 /* writel(0, dev->base + PCR); */
2208 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2209 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2212 /* Disable Wake On Lan */
2213 writel(0, dev->base + WCSR);
2215 ns83820_getmac(dev, ndev->dev_addr);
2217 /* Yes, we support dumb IP checksum on transmit */
2218 ndev->features |= NETIF_F_SG;
2219 ndev->features |= NETIF_F_IP_CSUM;
2221 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2222 /* We also support hardware vlan acceleration */
2223 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2227 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2229 ndev->features |= NETIF_F_HIGHDMA;
2232 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2234 (unsigned)readl(dev->base + SRR) >> 8,
2235 (unsigned)readl(dev->base + SRR) & 0xff,
2236 ndev->dev_addr, addr, pci_dev->irq,
2237 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2240 #ifdef PHY_CODE_IS_FINISHED
2241 ns83820_probe_phy(ndev);
2244 err = register_netdevice(ndev);
2246 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2254 ns83820_disable_interrupts(dev); /* paranoia */
2257 free_irq(pci_dev->irq, ndev);
2261 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2262 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2263 pci_disable_device(pci_dev);
2266 pci_set_drvdata(pci_dev, NULL);
2271 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2273 struct net_device *ndev = pci_get_drvdata(pci_dev);
2274 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2276 if (!ndev) /* paranoia */
2279 ns83820_disable_interrupts(dev); /* paranoia */
2281 unregister_netdev(ndev);
2282 free_irq(dev->pci_dev->irq, ndev);
2284 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2285 dev->tx_descs, dev->tx_phy_descs);
2286 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2287 dev->rx_info.descs, dev->rx_info.phy_descs);
2288 pci_disable_device(dev->pci_dev);
2290 pci_set_drvdata(pci_dev, NULL);
2293 static DEFINE_PCI_DEVICE_TABLE(ns83820_pci_tbl) = {
2294 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2298 static struct pci_driver driver = {
2300 .id_table = ns83820_pci_tbl,
2301 .probe = ns83820_init_one,
2302 .remove = __devexit_p(ns83820_remove_one),
2303 #if 0 /* FIXME: implement */
2310 static int __init ns83820_init(void)
2312 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2313 return pci_register_driver(&driver);
2316 static void __exit ns83820_exit(void)
2318 pci_unregister_driver(&driver);
2321 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2322 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2323 MODULE_LICENSE("GPL");
2325 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2327 module_param(lnksts, int, 0);
2328 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2330 module_param(ihr, int, 0);
2331 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2333 module_param(reset_phy, int, 0);
2334 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2336 module_init(ns83820_init);
2337 module_exit(ns83820_exit);