drivers/net/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  19  */
  20
  21 #include "pch_gbe.h"
  22 #include "pch_gbe_api.h"
  23
  24 #define DRV_VERSION     "1.00"
  25 const char pch_driver_version[] = DRV_VERSION;
  26
  27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  28 #define PCH_GBE_MAR_ENTRIES             16
  29 #define PCH_GBE_SHORT_PKT               64
  30 #define DSC_INIT16                      0xC000
  31 #define PCH_GBE_DMA_ALIGN               0
  32 #define PCH_GBE_DMA_PADDING             2
  33 #define PCH_GBE_WATCHDOG_PERIOD         (1 * HZ)        /* watchdog time */
  34 #define PCH_GBE_COPYBREAK_DEFAULT       256
  35 #define PCH_GBE_PCI_BAR                 1
  36
  37 #define PCH_GBE_TX_WEIGHT         64
  38 #define PCH_GBE_RX_WEIGHT         64
  39 #define PCH_GBE_RX_BUFFER_WRITE   16
  40
  41 /* Initialize the wake-on-LAN settings */
  42 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  43
  44 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  45         PCH_GBE_CHIP_TYPE_INTERNAL | \
  46         PCH_GBE_RGMII_MODE_RGMII     \
  47         )
  48
  49 /* Ethertype field values */
  50 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  51 #define PCH_GBE_FRAME_SIZE_2048         2048
  52 #define PCH_GBE_FRAME_SIZE_4096         4096
  53 #define PCH_GBE_FRAME_SIZE_8192         8192
  54
  55 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  56 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  57 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  58 #define PCH_GBE_DESC_UNUSED(R) \
  59         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  60         (R)->next_to_clean - (R)->next_to_use - 1)
  61
  62 /* Pause packet value */
  63 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  64 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  65 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  66 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  67
  68 #define PCH_GBE_ETH_ALEN            6
  69
  70 /* This defines the bits that are set in the Interrupt Mask
  71  * Set/Read Register.  Each bit is documented below:
  72  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  73  *   o TXDW   = Transmit Descriptor Written Back
  74  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  75  *   o RXSEQ  = Receive Sequence Error
  76  *   o LSC    = Link Status Change
  77  */
  78 #define PCH_GBE_INT_ENABLE_MASK ( \
  79         PCH_GBE_INT_RX_DMA_CMPLT |    \
  80         PCH_GBE_INT_RX_DSC_EMP   |    \
  81         PCH_GBE_INT_WOL_DET      |    \
  82         PCH_GBE_INT_TX_CMPLT          \
  83         )
  84
  85
  86 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
  87
  88 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
  89 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
  90                                int data);
  91
  92 inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
  93 {
  94         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
  95 }
  96
  97 /**
  98  * pch_gbe_mac_read_mac_addr - Read MAC address
  99  * @hw:             Pointer to the HW structure
 100  * Returns
 101  *      0:                      Successful.
 102  */
 103 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 104 {
 105         u32  adr1a, adr1b;
 106
 107         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 108         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 109
 110         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 111         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 112         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 113         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 114         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 115         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 116
 117         pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
 118         return 0;
 119 }
 120
 121 /**
 122  * pch_gbe_wait_clr_bit - Wait to clear a bit
 123  * @reg:        Pointer of register
 124  * @busy:       Busy bit
 125  */
 126 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 127 {
 128         u32 tmp;
 129         /* wait busy */
 130         tmp = 1000;
 131         while ((ioread32(reg) & bit) && --tmp)
 132                 cpu_relax();
 133         if (!tmp)
 134                 pr_err("Error: busy bit is not cleared\n");
 135 }
 136 /**
 137  * pch_gbe_mac_mar_set - Set MAC address register
 138  * @hw:     Pointer to the HW structure
 139  * @addr:   Pointer to the MAC address
 140  * @index:  MAC address array register
 141  */
 142 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 143 {
 144         u32 mar_low, mar_high, adrmask;
 145
 146         pr_debug("index : 0x%x\n", index);
 147
 148         /*
 149          * HW expects these in little endian so we reverse the byte order
 150          * from network order (big endian) to little endian
 151          */
 152         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 153                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 154         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 155         /* Stop the MAC Address of index. */
 156         adrmask = ioread32(&hw->reg->ADDR_MASK);
 157         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 158         /* wait busy */
 159         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 160         /* Set the MAC address to the MAC address 1A/1B register */
 161         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 162         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 163         /* Start the MAC address of index */
 164         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 165         /* wait busy */
 166         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 167 }
 168
 169 /**
 170  * pch_gbe_mac_reset_hw - Reset hardware
 171  * @hw: Pointer to the HW structure
 172  */
 173 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 174 {
 175         /* Read the MAC address. and store to the private data */
 176         pch_gbe_mac_read_mac_addr(hw);
 177         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 178 #ifdef PCH_GBE_MAC_IFOP_RGMII
 179         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 180 #endif
 181         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 182         /* Setup the receive address */
 183         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 184         return;
 185 }
 186
 187 /**
 188  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 189  * @hw: Pointer to the HW structure
 190  * @mar_count: Receive address registers
 191  */
 192 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 193 {
 194         u32 i;
 195
 196         /* Setup the receive address */
 197         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 198
 199         /* Zero out the other receive addresses */
 200         for (i = 1; i < mar_count; i++) {
 201                 iowrite32(0, &hw->reg->mac_adr[i].high);
 202                 iowrite32(0, &hw->reg->mac_adr[i].low);
 203         }
 204         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 205         /* wait busy */
 206         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 207 }
 208
 209
 210 /**
 211  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 212  * @hw:             Pointer to the HW structure
 213  * @mc_addr_list:   Array of multicast addresses to program
 214  * @mc_addr_count:  Number of multicast addresses to program
 215  * @mar_used_count: The first MAC Address register free to program
 216  * @mar_total_num:  Total number of supported MAC Address Registers
 217  */
 218 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 219                                             u8 *mc_addr_list, u32 mc_addr_count,
 220                                             u32 mar_used_count, u32 mar_total_num)
 221 {
 222         u32 i, adrmask;
 223
 224         /* Load the first set of multicast addresses into the exact
 225          * filters (RAR).  If there are not enough to fill the RAR
 226          * array, clear the filters.
 227          */
 228         for (i = mar_used_count; i < mar_total_num; i++) {
 229                 if (mc_addr_count) {
 230                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 231                         mc_addr_count--;
 232                         mc_addr_list += PCH_GBE_ETH_ALEN;
 233                 } else {
 234                         /* Clear MAC address mask */
 235                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 236                         iowrite32((adrmask | (0x0001 << i)),
 237                                         &hw->reg->ADDR_MASK);
 238                         /* wait busy */
 239                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 240                         /* Clear MAC address */
 241                         iowrite32(0, &hw->reg->mac_adr[i].high);
 242                         iowrite32(0, &hw->reg->mac_adr[i].low);
 243                 }
 244         }
 245 }
 246
 247 /**
 248  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 249  * @hw:             Pointer to the HW structure
 250  * Returns
 251  *      0:                      Successful.
 252  *      Negative value:         Failed.
 253  */
 254 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 255 {
 256         struct pch_gbe_mac_info *mac = &hw->mac;
 257         u32 rx_fctrl;
 258
 259         pr_debug("mac->fc = %u\n", mac->fc);
 260
 261         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 262
 263         switch (mac->fc) {
 264         case PCH_GBE_FC_NONE:
 265                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 266                 mac->tx_fc_enable = false;
 267                 break;
 268         case PCH_GBE_FC_RX_PAUSE:
 269                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 270                 mac->tx_fc_enable = false;
 271                 break;
 272         case PCH_GBE_FC_TX_PAUSE:
 273                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 274                 mac->tx_fc_enable = true;
 275                 break;
 276         case PCH_GBE_FC_FULL:
 277                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 278                 mac->tx_fc_enable = true;
 279                 break;
 280         default:
 281                 pr_err("Flow control param set incorrectly\n");
 282                 return -EINVAL;
 283         }
 284         if (mac->link_duplex == DUPLEX_HALF)
 285                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 286         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 287         pr_debug("RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 288                  ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 289         return 0;
 290 }
 291
 292 /**
 293  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 294  * @hw:     Pointer to the HW structure
 295  * @wu_evt: Wake up event
 296  */
 297 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 298 {
 299         u32 addr_mask;
 300
 301         pr_debug("wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 302                  wu_evt, ioread32(&hw->reg->ADDR_MASK));
 303
 304         if (wu_evt) {
 305                 /* Set Wake-On-Lan address mask */
 306                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 307                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 308                 /* wait busy */
 309                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 310                 iowrite32(0, &hw->reg->WOL_ST);
 311                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 312                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 313                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 314         } else {
 315                 iowrite32(0, &hw->reg->WOL_CTRL);
 316                 iowrite32(0, &hw->reg->WOL_ST);
 317         }
 318         return;
 319 }
 320
 321 /**
 322  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 323  * @hw:   Pointer to the HW structure
 324  * @addr: Address of PHY
 325  * @dir:  Operetion. (Write or Read)
 326  * @reg:  Access register of PHY
 327  * @data: Write data.
 328  *
 329  * Returns: Read date.
 330  */
 331 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 332                         u16 data)
 333 {
 334         u32 data_out = 0;
 335         unsigned int i;
 336         unsigned long flags;
 337
 338         spin_lock_irqsave(&hw->miim_lock, flags);
 339
 340         for (i = 100; i; --i) {
 341                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 342                         break;
 343                 udelay(20);
 344         }
 345         if (i == 0) {
 346                 pr_err("pch-gbe.miim won't go Ready\n");
 347                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 348                 return 0;       /* No way to indicate timeout error */
 349         }
 350         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 351                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 352                   dir | data), &hw->reg->MIIM);
 353         for (i = 0; i < 100; i++) {
 354                 udelay(20);
 355                 data_out = ioread32(&hw->reg->MIIM);
 356                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 357                         break;
 358         }
 359         spin_unlock_irqrestore(&hw->miim_lock, flags);
 360
 361         pr_debug("PHY %s: reg=%d, data=0x%04X\n",
 362                  dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 363                  dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 364         return (u16) data_out;
 365 }
 366
 367 /**
 368  * pch_gbe_mac_set_pause_packet - Set pause packet
 369  * @hw:   Pointer to the HW structure
 370  */
 371 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 372 {
 373         unsigned long tmp2, tmp3;
 374
 375         /* Set Pause packet */
 376         tmp2 = hw->mac.addr[1];
 377         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 378         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 379
 380         tmp3 = hw->mac.addr[5];
 381         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 382         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 383         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 384
 385         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 386         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 387         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 388         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 389         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 390
 391         /* Transmit Pause Packet */
 392         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 393
 394         pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 395                  ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
 396                  ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
 397                  ioread32(&hw->reg->PAUSE_PKT5));
 398
 399         return;
 400 }
 401
 402
 403 /**
 404  * pch_gbe_alloc_queues - Allocate memory for all rings
 405  * @adapter:  Board private structure to initialize
 406  * Returns
 407  *      0:      Successfully
 408  *      Negative value: Failed
 409  */
 410 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 411 {
 412         int size;
 413
 414         size = (int)sizeof(struct pch_gbe_tx_ring);
 415         adapter->tx_ring = kzalloc(size, GFP_KERNEL);
 416         if (!adapter->tx_ring)
 417                 return -ENOMEM;
 418         size = (int)sizeof(struct pch_gbe_rx_ring);
 419         adapter->rx_ring = kzalloc(size, GFP_KERNEL);
 420         if (!adapter->rx_ring) {
 421                 kfree(adapter->tx_ring);
 422                 return -ENOMEM;
 423         }
 424         return 0;
 425 }
 426
 427 /**
 428  * pch_gbe_init_stats - Initialize status
 429  * @adapter:  Board private structure to initialize
 430  */
 431 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 432 {
 433         memset(&adapter->stats, 0, sizeof(adapter->stats));
 434         return;
 435 }
 436
 437 /**
 438  * pch_gbe_init_phy - Initialize PHY
 439  * @adapter:  Board private structure to initialize
 440  * Returns
 441  *      0:      Successfully
 442  *      Negative value: Failed
 443  */
 444 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 445 {
 446         struct net_device *netdev = adapter->netdev;
 447         u32 addr;
 448         u16 bmcr, stat;
 449
 450         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 451         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 452                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 453                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 454                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 455                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 456                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 457                         break;
 458         }
 459         adapter->hw.phy.addr = adapter->mii.phy_id;
 460         pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
 461         if (addr == 32)
 462                 return -EAGAIN;
 463         /* Selected the phy and isolate the rest */
 464         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 465                 if (addr != adapter->mii.phy_id) {
 466                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 467                                            BMCR_ISOLATE);
 468                 } else {
 469                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 470                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 471                                            bmcr & ~BMCR_ISOLATE);
 472                 }
 473         }
 474
 475         /* MII setup */
 476         adapter->mii.phy_id_mask = 0x1F;
 477         adapter->mii.reg_num_mask = 0x1F;
 478         adapter->mii.dev = adapter->netdev;
 479         adapter->mii.mdio_read = pch_gbe_mdio_read;
 480         adapter->mii.mdio_write = pch_gbe_mdio_write;
 481         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 482         return 0;
 483 }
 484
 485 /**
 486  * pch_gbe_mdio_read - The read function for mii
 487  * @netdev: Network interface device structure
 488  * @addr:   Phy ID
 489  * @reg:    Access location
 490  * Returns
 491  *      0:      Successfully
 492  *      Negative value: Failed
 493  */
 494 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 495 {
 496         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 497         struct pch_gbe_hw *hw = &adapter->hw;
 498
 499         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 500                                      (u16) 0);
 501 }
 502
 503 /**
 504  * pch_gbe_mdio_write - The write function for mii
 505  * @netdev: Network interface device structure
 506  * @addr:   Phy ID (not used)
 507  * @reg:    Access location
 508  * @data:   Write data
 509  */
 510 static void pch_gbe_mdio_write(struct net_device *netdev,
 511                                int addr, int reg, int data)
 512 {
 513         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 514         struct pch_gbe_hw *hw = &adapter->hw;
 515
 516         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 517 }
 518
 519 /**
 520  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 521  * @work:  Pointer of board private structure
 522  */
 523 static void pch_gbe_reset_task(struct work_struct *work)
 524 {
 525         struct pch_gbe_adapter *adapter;
 526         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 527
 528         rtnl_lock();
 529         pch_gbe_reinit_locked(adapter);
 530         rtnl_unlock();
 531 }
 532
 533 /**
 534  * pch_gbe_reinit_locked- Re-initialization
 535  * @adapter:  Board private structure
 536  */
 537 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 538 {
 539         pch_gbe_down(adapter);
 540         pch_gbe_up(adapter);
 541 }
 542
 543 /**
 544  * pch_gbe_reset - Reset GbE
 545  * @adapter:  Board private structure
 546  */
 547 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 548 {
 549         pch_gbe_mac_reset_hw(&adapter->hw);
 550         /* Setup the receive address. */
 551         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 552         if (pch_gbe_hal_init_hw(&adapter->hw))
 553                 pr_err("Hardware Error\n");
 554 }
 555
 556 /**
 557  * pch_gbe_free_irq - Free an interrupt
 558  * @adapter:  Board private structure
 559  */
 560 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 561 {
 562         struct net_device *netdev = adapter->netdev;
 563
 564         free_irq(adapter->pdev->irq, netdev);
 565         if (adapter->have_msi) {
 566                 pci_disable_msi(adapter->pdev);
 567                 pr_debug("call pci_disable_msi\n");
 568         }
 569 }
 570
 571 /**
 572  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 573  * @adapter:  Board private structure
 574  */
 575 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 576 {
 577         struct pch_gbe_hw *hw = &adapter->hw;
 578
 579         atomic_inc(&adapter->irq_sem);
 580         iowrite32(0, &hw->reg->INT_EN);
 581         ioread32(&hw->reg->INT_ST);
 582         synchronize_irq(adapter->pdev->irq);
 583
 584         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
 585 }
 586
 587 /**
 588  * pch_gbe_irq_enable - Enable default interrupt generation settings
 589  * @adapter:  Board private structure
 590  */
 591 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 592 {
 593         struct pch_gbe_hw *hw = &adapter->hw;
 594
 595         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 596                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 597         ioread32(&hw->reg->INT_ST);
 598         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
 599 }
 600
 601
 602
 603 /**
 604  * pch_gbe_setup_tctl - configure the Transmit control registers
 605  * @adapter:  Board private structure
 606  */
 607 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 608 {
 609         struct pch_gbe_hw *hw = &adapter->hw;
 610         u32 tx_mode, tcpip;
 611
 612         tx_mode = PCH_GBE_TM_LONG_PKT |
 613                 PCH_GBE_TM_ST_AND_FD |
 614                 PCH_GBE_TM_SHORT_PKT |
 615                 PCH_GBE_TM_TH_TX_STRT_8 |
 616                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 617
 618         iowrite32(tx_mode, &hw->reg->TX_MODE);
 619
 620         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 621         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 622         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 623         return;
 624 }
 625
 626 /**
 627  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 628  * @adapter:  Board private structure
 629  */
 630 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 631 {
 632         struct pch_gbe_hw *hw = &adapter->hw;
 633         u32 tdba, tdlen, dctrl;
 634
 635         pr_debug("dma addr = 0x%08llx  size = 0x%08x\n",
 636                  (unsigned long long)adapter->tx_ring->dma,
 637                  adapter->tx_ring->size);
 638
 639         /* Setup the HW Tx Head and Tail descriptor pointers */
 640         tdba = adapter->tx_ring->dma;
 641         tdlen = adapter->tx_ring->size - 0x10;
 642         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 643         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 644         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 645
 646         /* Enables Transmission DMA */
 647         dctrl = ioread32(&hw->reg->DMA_CTRL);
 648         dctrl |= PCH_GBE_TX_DMA_EN;
 649         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 650 }
 651
 652 /**
 653  * pch_gbe_setup_rctl - Configure the receive control registers
 654  * @adapter:  Board private structure
 655  */
 656 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 657 {
 658         struct pch_gbe_hw *hw = &adapter->hw;
 659         u32 rx_mode, tcpip;
 660
 661         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 662         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 663
 664         iowrite32(rx_mode, &hw->reg->RX_MODE);
 665
 666         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 667
 668         if (adapter->rx_csum) {
 669                 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
 670                 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
 671         } else {
 672                 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 673                 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 674         }
 675         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 676         return;
 677 }
 678
 679 /**
 680  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 681  * @adapter:  Board private structure
 682  */
 683 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 684 {
 685         struct pch_gbe_hw *hw = &adapter->hw;
 686         u32 rdba, rdlen, rctl, rxdma;
 687
 688         pr_debug("dma adr = 0x%08llx  size = 0x%08x\n",
 689                  (unsigned long long)adapter->rx_ring->dma,
 690                  adapter->rx_ring->size);
 691
 692         pch_gbe_mac_force_mac_fc(hw);
 693
 694         /* Disables Receive MAC */
 695         rctl = ioread32(&hw->reg->MAC_RX_EN);
 696         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 697
 698         /* Disables Receive DMA */
 699         rxdma = ioread32(&hw->reg->DMA_CTRL);
 700         rxdma &= ~PCH_GBE_RX_DMA_EN;
 701         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 702
 703         pr_debug("MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 704                  ioread32(&hw->reg->MAC_RX_EN),
 705                  ioread32(&hw->reg->DMA_CTRL));
 706
 707         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 708          * the Base and Length of the Rx Descriptor Ring */
 709         rdba = adapter->rx_ring->dma;
 710         rdlen = adapter->rx_ring->size - 0x10;
 711         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 712         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 713         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 714
 715         /* Enables Receive DMA */
 716         rxdma = ioread32(&hw->reg->DMA_CTRL);
 717         rxdma |= PCH_GBE_RX_DMA_EN;
 718         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 719         /* Enables Receive */
 720         iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
 721 }
 722
 723 /**
 724  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 725  * @adapter:     Board private structure
 726  * @buffer_info: Buffer information structure
 727  */
 728 static void pch_gbe_unmap_and_free_tx_resource(
 729         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 730 {
 731         if (buffer_info->mapped) {
 732                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 733                                  buffer_info->length, DMA_TO_DEVICE);
 734                 buffer_info->mapped = false;
 735         }
 736         if (buffer_info->skb) {
 737                 dev_kfree_skb_any(buffer_info->skb);
 738                 buffer_info->skb = NULL;
 739         }
 740 }
 741
 742 /**
 743  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 744  * @adapter:      Board private structure
 745  * @buffer_info:  Buffer information structure
 746  */
 747 static void pch_gbe_unmap_and_free_rx_resource(
 748                                         struct pch_gbe_adapter *adapter,
 749                                         struct pch_gbe_buffer *buffer_info)
 750 {
 751         if (buffer_info->mapped) {
 752                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 753                                  buffer_info->length, DMA_FROM_DEVICE);
 754                 buffer_info->mapped = false;
 755         }
 756         if (buffer_info->skb) {
 757                 dev_kfree_skb_any(buffer_info->skb);
 758                 buffer_info->skb = NULL;
 759         }
 760 }
 761
 762 /**
 763  * pch_gbe_clean_tx_ring - Free Tx Buffers
 764  * @adapter:  Board private structure
 765  * @tx_ring:  Ring to be cleaned
 766  */
 767 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 768                                    struct pch_gbe_tx_ring *tx_ring)
 769 {
 770         struct pch_gbe_hw *hw = &adapter->hw;
 771         struct pch_gbe_buffer *buffer_info;
 772         unsigned long size;
 773         unsigned int i;
 774
 775         /* Free all the Tx ring sk_buffs */
 776         for (i = 0; i < tx_ring->count; i++) {
 777                 buffer_info = &tx_ring->buffer_info[i];
 778                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 779         }
 780         pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 781
 782         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 783         memset(tx_ring->buffer_info, 0, size);
 784
 785         /* Zero out the descriptor ring */
 786         memset(tx_ring->desc, 0, tx_ring->size);
 787         tx_ring->next_to_use = 0;
 788         tx_ring->next_to_clean = 0;
 789         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
 790         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
 791 }
 792
 793 /**
 794  * pch_gbe_clean_rx_ring - Free Rx Buffers
 795  * @adapter:  Board private structure
 796  * @rx_ring:  Ring to free buffers from
 797  */
 798 static void
 799 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
 800                       struct pch_gbe_rx_ring *rx_ring)
 801 {
 802         struct pch_gbe_hw *hw = &adapter->hw;
 803         struct pch_gbe_buffer *buffer_info;
 804         unsigned long size;
 805         unsigned int i;
 806
 807         /* Free all the Rx ring sk_buffs */
 808         for (i = 0; i < rx_ring->count; i++) {
 809                 buffer_info = &rx_ring->buffer_info[i];
 810                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
 811         }
 812         pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
 813         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
 814         memset(rx_ring->buffer_info, 0, size);
 815
 816         /* Zero out the descriptor ring */
 817         memset(rx_ring->desc, 0, rx_ring->size);
 818         rx_ring->next_to_clean = 0;
 819         rx_ring->next_to_use = 0;
 820         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
 821         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
 822 }
 823
 824 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
 825                                     u16 duplex)
 826 {
 827         struct pch_gbe_hw *hw = &adapter->hw;
 828         unsigned long rgmii = 0;
 829
 830         /* Set the RGMII control. */
 831 #ifdef PCH_GBE_MAC_IFOP_RGMII
 832         switch (speed) {
 833         case SPEED_10:
 834                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
 835                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 836                 break;
 837         case SPEED_100:
 838                 rgmii = (PCH_GBE_RGMII_RATE_25M |
 839                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 840                 break;
 841         case SPEED_1000:
 842                 rgmii = (PCH_GBE_RGMII_RATE_125M |
 843                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 844                 break;
 845         }
 846         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
 847 #else   /* GMII */
 848         rgmii = 0;
 849         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
 850 #endif
 851 }
 852 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
 853                               u16 duplex)
 854 {
 855         struct net_device *netdev = adapter->netdev;
 856         struct pch_gbe_hw *hw = &adapter->hw;
 857         unsigned long mode = 0;
 858
 859         /* Set the communication mode */
 860         switch (speed) {
 861         case SPEED_10:
 862                 mode = PCH_GBE_MODE_MII_ETHER;
 863                 netdev->tx_queue_len = 10;
 864                 break;
 865         case SPEED_100:
 866                 mode = PCH_GBE_MODE_MII_ETHER;
 867                 netdev->tx_queue_len = 100;
 868                 break;
 869         case SPEED_1000:
 870                 mode = PCH_GBE_MODE_GMII_ETHER;
 871                 break;
 872         }
 873         if (duplex == DUPLEX_FULL)
 874                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
 875         else
 876                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
 877         iowrite32(mode, &hw->reg->MODE);
 878 }
 879
 880 /**
 881  * pch_gbe_watchdog - Watchdog process
 882  * @data:  Board private structure
 883  */
 884 static void pch_gbe_watchdog(unsigned long data)
 885 {
 886         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
 887         struct net_device *netdev = adapter->netdev;
 888         struct pch_gbe_hw *hw = &adapter->hw;
 889         struct ethtool_cmd cmd;
 890
 891         pr_debug("right now = %ld\n", jiffies);
 892
 893         pch_gbe_update_stats(adapter);
 894         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
 895                 netdev->tx_queue_len = adapter->tx_queue_len;
 896                 /* mii library handles link maintenance tasks */
 897                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
 898                         pr_err("ethtool get setting Error\n");
 899                         mod_timer(&adapter->watchdog_timer,
 900                                   round_jiffies(jiffies +
 901                                                 PCH_GBE_WATCHDOG_PERIOD));
 902                         return;
 903                 }
 904                 hw->mac.link_speed = cmd.speed;
 905                 hw->mac.link_duplex = cmd.duplex;
 906                 /* Set the RGMII control. */
 907                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
 908                                                 hw->mac.link_duplex);
 909                 /* Set the communication mode */
 910                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
 911                                  hw->mac.link_duplex);
 912                 netdev_dbg(netdev,
 913                            "Link is Up %d Mbps %s-Duplex\n",
 914                            cmd.speed,
 915                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
 916                 netif_carrier_on(netdev);
 917                 netif_wake_queue(netdev);
 918         } else if ((!mii_link_ok(&adapter->mii)) &&
 919                    (netif_carrier_ok(netdev))) {
 920                 netdev_dbg(netdev, "NIC Link is Down\n");
 921                 hw->mac.link_speed = SPEED_10;
 922                 hw->mac.link_duplex = DUPLEX_HALF;
 923                 netif_carrier_off(netdev);
 924                 netif_stop_queue(netdev);
 925         }
 926         mod_timer(&adapter->watchdog_timer,
 927                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
 928 }
 929
 930 /**
 931  * pch_gbe_tx_queue - Carry out queuing of the transmission data
 932  * @adapter:  Board private structure
 933  * @tx_ring:  Tx descriptor ring structure
 934  * @skb:      Sockt buffer structure
 935  */
 936 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
 937                               struct pch_gbe_tx_ring *tx_ring,
 938                               struct sk_buff *skb)
 939 {
 940         struct pch_gbe_hw *hw = &adapter->hw;
 941         struct pch_gbe_tx_desc *tx_desc;
 942         struct pch_gbe_buffer *buffer_info;
 943         struct sk_buff *tmp_skb;
 944         unsigned int frame_ctrl;
 945         unsigned int ring_num;
 946         unsigned long flags;
 947
 948         /*-- Set frame control --*/
 949         frame_ctrl = 0;
 950         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
 951                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
 952         if (unlikely(!adapter->tx_csum))
 953                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
 954
 955         /* Performs checksum processing */
 956         /*
 957          * It is because the hardware accelerator does not support a checksum,
 958          * when the received data size is less than 64 bytes.
 959          */
 960         if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
 961                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
 962                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
 963                 if (skb->protocol == htons(ETH_P_IP)) {
 964                         struct iphdr *iph = ip_hdr(skb);
 965                         unsigned int offset;
 966                         iph->check = 0;
 967                         iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
 968                         offset = skb_transport_offset(skb);
 969                         if (iph->protocol == IPPROTO_TCP) {
 970                                 skb->csum = 0;
 971                                 tcp_hdr(skb)->check = 0;
 972                                 skb->csum = skb_checksum(skb, offset,
 973                                                          skb->len - offset, 0);
 974                                 tcp_hdr(skb)->check =
 975                                         csum_tcpudp_magic(iph->saddr,
 976                                                           iph->daddr,
 977                                                           skb->len - offset,
 978                                                           IPPROTO_TCP,
 979                                                           skb->csum);
 980                         } else if (iph->protocol == IPPROTO_UDP) {
 981                                 skb->csum = 0;
 982                                 udp_hdr(skb)->check = 0;
 983                                 skb->csum =
 984                                         skb_checksum(skb, offset,
 985                                                      skb->len - offset, 0);
 986                                 udp_hdr(skb)->check =
 987                                         csum_tcpudp_magic(iph->saddr,
 988                                                           iph->daddr,
 989                                                           skb->len - offset,
 990                                                           IPPROTO_UDP,
 991                                                           skb->csum);
 992                         }
 993                 }
 994         }
 995         spin_lock_irqsave(&tx_ring->tx_lock, flags);
 996         ring_num = tx_ring->next_to_use;
 997         if (unlikely((ring_num + 1) == tx_ring->count))
 998                 tx_ring->next_to_use = 0;
 999         else
1000                 tx_ring->next_to_use = ring_num + 1;
1001
1002         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1003         buffer_info = &tx_ring->buffer_info[ring_num];
1004         tmp_skb = buffer_info->skb;
1005
1006         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1007         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1008         tmp_skb->data[ETH_HLEN] = 0x00;
1009         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1010         tmp_skb->len = skb->len;
1011         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1012                (skb->len - ETH_HLEN));
1013         /*-- Set Buffer information --*/
1014         buffer_info->length = tmp_skb->len;
1015         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1016                                           buffer_info->length,
1017                                           DMA_TO_DEVICE);
1018         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1019                 pr_err("TX DMA map failed\n");
1020                 buffer_info->dma = 0;
1021                 buffer_info->time_stamp = 0;
1022                 tx_ring->next_to_use = ring_num;
1023                 return;
1024         }
1025         buffer_info->mapped = true;
1026         buffer_info->time_stamp = jiffies;
1027
1028         /*-- Set Tx descriptor --*/
1029         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1030         tx_desc->buffer_addr = (buffer_info->dma);
1031         tx_desc->length = (tmp_skb->len);
1032         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1033         tx_desc->tx_frame_ctrl = (frame_ctrl);
1034         tx_desc->gbec_status = (DSC_INIT16);
1035
1036         if (unlikely(++ring_num == tx_ring->count))
1037                 ring_num = 0;
1038
1039         /* Update software pointer of TX descriptor */
1040         iowrite32(tx_ring->dma +
1041                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1042                   &hw->reg->TX_DSC_SW_P);
1043         dev_kfree_skb_any(skb);
1044 }
1045
1046 /**
1047  * pch_gbe_update_stats - Update the board statistics counters
1048  * @adapter:  Board private structure
1049  */
1050 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1051 {
1052         struct net_device *netdev = adapter->netdev;
1053         struct pci_dev *pdev = adapter->pdev;
1054         struct pch_gbe_hw_stats *stats = &adapter->stats;
1055         unsigned long flags;
1056
1057         /*
1058          * Prevent stats update while adapter is being reset, or if the pci
1059          * connection is down.
1060          */
1061         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1062                 return;
1063
1064         spin_lock_irqsave(&adapter->stats_lock, flags);
1065
1066         /* Update device status "adapter->stats" */
1067         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1068         stats->tx_errors = stats->tx_length_errors +
1069             stats->tx_aborted_errors +
1070             stats->tx_carrier_errors + stats->tx_timeout_count;
1071
1072         /* Update network device status "adapter->net_stats" */
1073         netdev->stats.rx_packets = stats->rx_packets;
1074         netdev->stats.rx_bytes = stats->rx_bytes;
1075         netdev->stats.rx_dropped = stats->rx_dropped;
1076         netdev->stats.tx_packets = stats->tx_packets;
1077         netdev->stats.tx_bytes = stats->tx_bytes;
1078         netdev->stats.tx_dropped = stats->tx_dropped;
1079         /* Fill out the OS statistics structure */
1080         netdev->stats.multicast = stats->multicast;
1081         netdev->stats.collisions = stats->collisions;
1082         /* Rx Errors */
1083         netdev->stats.rx_errors = stats->rx_errors;
1084         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1085         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1086         /* Tx Errors */
1087         netdev->stats.tx_errors = stats->tx_errors;
1088         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1089         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1090
1091         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1092 }
1093
1094 /**
1095  * pch_gbe_intr - Interrupt Handler
1096  * @irq:   Interrupt number
1097  * @data:  Pointer to a network interface device structure
1098  * Returns
1099  *      - IRQ_HANDLED:  Our interrupt
1100  *      - IRQ_NONE:     Not our interrupt
1101  */
1102 static irqreturn_t pch_gbe_intr(int irq, void *data)
1103 {
1104         struct net_device *netdev = data;
1105         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1106         struct pch_gbe_hw *hw = &adapter->hw;
1107         u32 int_st;
1108         u32 int_en;
1109
1110         /* Check request status */
1111         int_st = ioread32(&hw->reg->INT_ST);
1112         int_st = int_st & ioread32(&hw->reg->INT_EN);
1113         /* When request status is no interruption factor */
1114         if (unlikely(!int_st))
1115                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1116         pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1117         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1118                 adapter->stats.intr_rx_frame_err_count++;
1119         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1120                 adapter->stats.intr_rx_fifo_err_count++;
1121         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1122                 adapter->stats.intr_rx_dma_err_count++;
1123         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1124                 adapter->stats.intr_tx_fifo_err_count++;
1125         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1126                 adapter->stats.intr_tx_dma_err_count++;
1127         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1128                 adapter->stats.intr_tcpip_err_count++;
1129         /* When Rx descriptor is empty  */
1130         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1131                 adapter->stats.intr_rx_dsc_empty_count++;
1132                 pr_err("Rx descriptor is empty\n");
1133                 int_en = ioread32(&hw->reg->INT_EN);
1134                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1135                 if (hw->mac.tx_fc_enable) {
1136                         /* Set Pause packet */
1137                         pch_gbe_mac_set_pause_packet(hw);
1138                 }
1139                 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1140                     == 0) {
1141                         return IRQ_HANDLED;
1142                 }
1143         }
1144
1145         /* When request status is Receive interruption */
1146         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1147                 if (likely(napi_schedule_prep(&adapter->napi))) {
1148                         /* Enable only Rx Descriptor empty */
1149                         atomic_inc(&adapter->irq_sem);
1150                         int_en = ioread32(&hw->reg->INT_EN);
1151                         int_en &=
1152                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1153                         iowrite32(int_en, &hw->reg->INT_EN);
1154                         /* Start polling for NAPI */
1155                         __napi_schedule(&adapter->napi);
1156                 }
1157         }
1158         pr_debug("return = 0x%08x  INT_EN reg = 0x%08x\n",
1159                  IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1160         return IRQ_HANDLED;
1161 }
1162
1163 /**
1164  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1165  * @adapter:       Board private structure
1166  * @rx_ring:       Rx descriptor ring
1167  * @cleaned_count: Cleaned count
1168  */
1169 static void
1170 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1171                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1172 {
1173         struct net_device *netdev = adapter->netdev;
1174         struct pci_dev *pdev = adapter->pdev;
1175         struct pch_gbe_hw *hw = &adapter->hw;
1176         struct pch_gbe_rx_desc *rx_desc;
1177         struct pch_gbe_buffer *buffer_info;
1178         struct sk_buff *skb;
1179         unsigned int i;
1180         unsigned int bufsz;
1181
1182         bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1183         i = rx_ring->next_to_use;
1184
1185         while ((cleaned_count--)) {
1186                 buffer_info = &rx_ring->buffer_info[i];
1187                 skb = buffer_info->skb;
1188                 if (skb) {
1189                         skb_trim(skb, 0);
1190                 } else {
1191                         skb = netdev_alloc_skb(netdev, bufsz);
1192                         if (unlikely(!skb)) {
1193                                 /* Better luck next round */
1194                                 adapter->stats.rx_alloc_buff_failed++;
1195                                 break;
1196                         }
1197                         /* 64byte align */
1198                         skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1199
1200                         buffer_info->skb = skb;
1201                         buffer_info->length = adapter->rx_buffer_len;
1202                 }
1203                 buffer_info->dma = dma_map_single(&pdev->dev,
1204                                                   skb->data,
1205                                                   buffer_info->length,
1206                                                   DMA_FROM_DEVICE);
1207                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1208                         dev_kfree_skb(skb);
1209                         buffer_info->skb = NULL;
1210                         buffer_info->dma = 0;
1211                         adapter->stats.rx_alloc_buff_failed++;
1212                         break; /* while !buffer_info->skb */
1213                 }
1214                 buffer_info->mapped = true;
1215                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1216                 rx_desc->buffer_addr = (buffer_info->dma);
1217                 rx_desc->gbec_status = DSC_INIT16;
1218
1219                 pr_debug("i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1220                          i, (unsigned long long)buffer_info->dma,
1221                          buffer_info->length);
1222
1223                 if (unlikely(++i == rx_ring->count))
1224                         i = 0;
1225         }
1226         if (likely(rx_ring->next_to_use != i)) {
1227                 rx_ring->next_to_use = i;
1228                 if (unlikely(i-- == 0))
1229                         i = (rx_ring->count - 1);
1230                 iowrite32(rx_ring->dma +
1231                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1232                           &hw->reg->RX_DSC_SW_P);
1233         }
1234         return;
1235 }
1236
1237 /**
1238  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1239  * @adapter:   Board private structure
1240  * @tx_ring:   Tx descriptor ring
1241  */
1242 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1243                                         struct pch_gbe_tx_ring *tx_ring)
1244 {
1245         struct pch_gbe_buffer *buffer_info;
1246         struct sk_buff *skb;
1247         unsigned int i;
1248         unsigned int bufsz;
1249         struct pch_gbe_tx_desc *tx_desc;
1250
1251         bufsz =
1252             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1253
1254         for (i = 0; i < tx_ring->count; i++) {
1255                 buffer_info = &tx_ring->buffer_info[i];
1256                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1257                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1258                 buffer_info->skb = skb;
1259                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1260                 tx_desc->gbec_status = (DSC_INIT16);
1261         }
1262         return;
1263 }
1264
1265 /**
1266  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1267  * @adapter:   Board private structure
1268  * @tx_ring:   Tx descriptor ring
1269  * Returns
1270  *      true:  Cleaned the descriptor
1271  *      false: Not cleaned the descriptor
1272  */
1273 static bool
1274 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1275                  struct pch_gbe_tx_ring *tx_ring)
1276 {
1277         struct pch_gbe_tx_desc *tx_desc;
1278         struct pch_gbe_buffer *buffer_info;
1279         struct sk_buff *skb;
1280         unsigned int i;
1281         unsigned int cleaned_count = 0;
1282         bool cleaned = false;
1283
1284         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1285
1286         i = tx_ring->next_to_clean;
1287         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1288         pr_debug("gbec_status:0x%04x  dma_status:0x%04x\n",
1289                  tx_desc->gbec_status, tx_desc->dma_status);
1290
1291         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1292                 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1293                 cleaned = true;
1294                 buffer_info = &tx_ring->buffer_info[i];
1295                 skb = buffer_info->skb;
1296
1297                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1298                         adapter->stats.tx_aborted_errors++;
1299                         pr_err("Transfer Abort Error\n");
1300                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1301                           ) {
1302                         adapter->stats.tx_carrier_errors++;
1303                         pr_err("Transfer Carrier Sense Error\n");
1304                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1305                           ) {
1306                         adapter->stats.tx_aborted_errors++;
1307                         pr_err("Transfer Collision Abort Error\n");
1308                 } else if ((tx_desc->gbec_status &
1309                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1310                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1311                         adapter->stats.collisions++;
1312                         adapter->stats.tx_packets++;
1313                         adapter->stats.tx_bytes += skb->len;
1314                         pr_debug("Transfer Collision\n");
1315                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1316                           ) {
1317                         adapter->stats.tx_packets++;
1318                         adapter->stats.tx_bytes += skb->len;
1319                 }
1320                 if (buffer_info->mapped) {
1321                         pr_debug("unmap buffer_info->dma : %d\n", i);
1322                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1323                                          buffer_info->length, DMA_TO_DEVICE);
1324                         buffer_info->mapped = false;
1325                 }
1326                 if (buffer_info->skb) {
1327                         pr_debug("trim buffer_info->skb : %d\n", i);
1328                         skb_trim(buffer_info->skb, 0);
1329                 }
1330                 tx_desc->gbec_status = DSC_INIT16;
1331                 if (unlikely(++i == tx_ring->count))
1332                         i = 0;
1333                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1334
1335                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1336                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1337                         break;
1338         }
1339         pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1340                  cleaned_count);
1341         /* Recover from running out of Tx resources in xmit_frame */
1342         if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1343                 netif_wake_queue(adapter->netdev);
1344                 adapter->stats.tx_restart_count++;
1345                 pr_debug("Tx wake queue\n");
1346         }
1347         spin_lock(&adapter->tx_queue_lock);
1348         tx_ring->next_to_clean = i;
1349         spin_unlock(&adapter->tx_queue_lock);
1350         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1351         return cleaned;
1352 }
1353
1354 /**
1355  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1356  * @adapter:     Board private structure
1357  * @rx_ring:     Rx descriptor ring
1358  * @work_done:   Completed count
1359  * @work_to_do:  Request count
1360  * Returns
1361  *      true:  Cleaned the descriptor
1362  *      false: Not cleaned the descriptor
1363  */
1364 static bool
1365 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1366                  struct pch_gbe_rx_ring *rx_ring,
1367                  int *work_done, int work_to_do)
1368 {
1369         struct net_device *netdev = adapter->netdev;
1370         struct pci_dev *pdev = adapter->pdev;
1371         struct pch_gbe_buffer *buffer_info;
1372         struct pch_gbe_rx_desc *rx_desc;
1373         u32 length;
1374         unsigned int i;
1375         unsigned int cleaned_count = 0;
1376         bool cleaned = false;
1377         struct sk_buff *skb, *new_skb;
1378         u8 dma_status;
1379         u16 gbec_status;
1380         u32 tcp_ip_status;
1381
1382         i = rx_ring->next_to_clean;
1383
1384         while (*work_done < work_to_do) {
1385                 /* Check Rx descriptor status */
1386                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1387                 if (rx_desc->gbec_status == DSC_INIT16)
1388                         break;
1389                 cleaned = true;
1390                 cleaned_count++;
1391
1392                 dma_status = rx_desc->dma_status;
1393                 gbec_status = rx_desc->gbec_status;
1394                 tcp_ip_status = rx_desc->tcp_ip_status;
1395                 rx_desc->gbec_status = DSC_INIT16;
1396                 buffer_info = &rx_ring->buffer_info[i];
1397                 skb = buffer_info->skb;
1398
1399                 /* unmap dma */
1400                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1401                                    buffer_info->length, DMA_FROM_DEVICE);
1402                 buffer_info->mapped = false;
1403                 /* Prefetch the packet */
1404                 prefetch(skb->data);
1405
1406                 pr_debug("RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x "
1407                          "TCP:0x%08x]  BufInf = 0x%p\n",
1408                          i, dma_status, gbec_status, tcp_ip_status,
1409                          buffer_info);
1410                 /* Error check */
1411                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1412                         adapter->stats.rx_frame_errors++;
1413                         pr_err("Receive Not Octal Error\n");
1414                 } else if (unlikely(gbec_status &
1415                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1416                         adapter->stats.rx_frame_errors++;
1417                         pr_err("Receive Nibble Error\n");
1418                 } else if (unlikely(gbec_status &
1419                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1420                         adapter->stats.rx_crc_errors++;
1421                         pr_err("Receive CRC Error\n");
1422                 } else {
1423                         /* get receive length */
1424                         /* length convert[-3] */
1425                         length = (rx_desc->rx_words_eob) - 3;
1426
1427                         /* Decide the data conversion method */
1428                         if (!adapter->rx_csum) {
1429                                 /* [Header:14][payload] */
1430                                 if (NET_IP_ALIGN) {
1431                                         /* Because alignment differs,
1432                                          * the new_skb is newly allocated,
1433                                          * and data is copied to new_skb.*/
1434                                         new_skb = netdev_alloc_skb(netdev,
1435                                                          length + NET_IP_ALIGN);
1436                                         if (!new_skb) {
1437                                                 /* dorrop error */
1438                                                 pr_err("New skb allocation "
1439                                                         "Error\n");
1440                                                 goto dorrop;
1441                                         }
1442                                         skb_reserve(new_skb, NET_IP_ALIGN);
1443                                         memcpy(new_skb->data, skb->data,
1444                                                length);
1445                                         skb = new_skb;
1446                                 } else {
1447                                         /* DMA buffer is used as SKB as it is.*/
1448                                         buffer_info->skb = NULL;
1449                                 }
1450                         } else {
1451                                 /* [Header:14][padding:2][payload] */
1452                                 /* The length includes padding length */
1453                                 length = length - PCH_GBE_DMA_PADDING;
1454                                 if ((length < copybreak) ||
1455                                     (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1456                                         /* Because alignment differs,
1457                                          * the new_skb is newly allocated,
1458                                          * and data is copied to new_skb.
1459                                          * Padding data is deleted
1460                                          * at the time of a copy.*/
1461                                         new_skb = netdev_alloc_skb(netdev,
1462                                                          length + NET_IP_ALIGN);
1463                                         if (!new_skb) {
1464                                                 /* dorrop error */
1465                                                 pr_err("New skb allocation "
1466                                                         "Error\n");
1467                                                 goto dorrop;
1468                                         }
1469                                         skb_reserve(new_skb, NET_IP_ALIGN);
1470                                         memcpy(new_skb->data, skb->data,
1471                                                ETH_HLEN);
1472                                         memcpy(&new_skb->data[ETH_HLEN],
1473                                                &skb->data[ETH_HLEN +
1474                                                PCH_GBE_DMA_PADDING],
1475                                                length - ETH_HLEN);
1476                                         skb = new_skb;
1477                                 } else {
1478                                         /* Padding data is deleted
1479                                          * by moving header data.*/
1480                                         memmove(&skb->data[PCH_GBE_DMA_PADDING],
1481                                                 &skb->data[0], ETH_HLEN);
1482                                         skb_reserve(skb, NET_IP_ALIGN);
1483                                         buffer_info->skb = NULL;
1484                                 }
1485                         }
1486                         /* The length includes FCS length */
1487                         length = length - ETH_FCS_LEN;
1488                         /* update status of driver */
1489                         adapter->stats.rx_bytes += length;
1490                         adapter->stats.rx_packets++;
1491                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1492                                 adapter->stats.multicast++;
1493                         /* Write meta date of skb */
1494                         skb_put(skb, length);
1495                         skb->protocol = eth_type_trans(skb, netdev);
1496                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1497                                 skb->ip_summed = CHECKSUM_NONE;
1498                         else
1499                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1500
1501                         napi_gro_receive(&adapter->napi, skb);
1502                         (*work_done)++;
1503                         pr_debug("Receive skb->ip_summed: %d length: %d\n",
1504                                  skb->ip_summed, length);
1505                 }
1506 dorrop:
1507                 /* return some buffers to hardware, one at a time is too slow */
1508                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1509                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1510                                                  cleaned_count);
1511                         cleaned_count = 0;
1512                 }
1513                 if (++i == rx_ring->count)
1514                         i = 0;
1515         }
1516         rx_ring->next_to_clean = i;
1517         if (cleaned_count)
1518                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1519         return cleaned;
1520 }
1521
1522 /**
1523  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1524  * @adapter:  Board private structure
1525  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1526  * Returns
1527  *      0:              Successfully
1528  *      Negative value: Failed
1529  */
1530 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1531                                 struct pch_gbe_tx_ring *tx_ring)
1532 {
1533         struct pci_dev *pdev = adapter->pdev;
1534         struct pch_gbe_tx_desc *tx_desc;
1535         int size;
1536         int desNo;
1537
1538         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1539         tx_ring->buffer_info = vzalloc(size);
1540         if (!tx_ring->buffer_info) {
1541                 pr_err("Unable to allocate memory for the buffer information\n");
1542                 return -ENOMEM;
1543         }
1544
1545         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1546
1547         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1548                                            &tx_ring->dma, GFP_KERNEL);
1549         if (!tx_ring->desc) {
1550                 vfree(tx_ring->buffer_info);
1551                 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1552                 return -ENOMEM;
1553         }
1554         memset(tx_ring->desc, 0, tx_ring->size);
1555
1556         tx_ring->next_to_use = 0;
1557         tx_ring->next_to_clean = 0;
1558         spin_lock_init(&tx_ring->tx_lock);
1559
1560         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1561                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1562                 tx_desc->gbec_status = DSC_INIT16;
1563         }
1564         pr_debug("tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx\n"
1565                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1566                  tx_ring->desc, (unsigned long long)tx_ring->dma,
1567                  tx_ring->next_to_clean, tx_ring->next_to_use);
1568         return 0;
1569 }
1570
1571 /**
1572  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1573  * @adapter:  Board private structure
1574  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1575  * Returns
1576  *      0:              Successfully
1577  *      Negative value: Failed
1578  */
1579 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1580                                 struct pch_gbe_rx_ring *rx_ring)
1581 {
1582         struct pci_dev *pdev = adapter->pdev;
1583         struct pch_gbe_rx_desc *rx_desc;
1584         int size;
1585         int desNo;
1586
1587         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1588         rx_ring->buffer_info = vzalloc(size);
1589         if (!rx_ring->buffer_info) {
1590                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1591                 return -ENOMEM;
1592         }
1593         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1594         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1595                                            &rx_ring->dma, GFP_KERNEL);
1596
1597         if (!rx_ring->desc) {
1598                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1599                 vfree(rx_ring->buffer_info);
1600                 return -ENOMEM;
1601         }
1602         memset(rx_ring->desc, 0, rx_ring->size);
1603         rx_ring->next_to_clean = 0;
1604         rx_ring->next_to_use = 0;
1605         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1606                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1607                 rx_desc->gbec_status = DSC_INIT16;
1608         }
1609         pr_debug("rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx "
1610                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1611                  rx_ring->desc, (unsigned long long)rx_ring->dma,
1612                  rx_ring->next_to_clean, rx_ring->next_to_use);
1613         return 0;
1614 }
1615
1616 /**
1617  * pch_gbe_free_tx_resources - Free Tx Resources
1618  * @adapter:  Board private structure
1619  * @tx_ring:  Tx descriptor ring for a specific queue
1620  */
1621 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1622                                 struct pch_gbe_tx_ring *tx_ring)
1623 {
1624         struct pci_dev *pdev = adapter->pdev;
1625
1626         pch_gbe_clean_tx_ring(adapter, tx_ring);
1627         vfree(tx_ring->buffer_info);
1628         tx_ring->buffer_info = NULL;
1629         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1630         tx_ring->desc = NULL;
1631 }
1632
1633 /**
1634  * pch_gbe_free_rx_resources - Free Rx Resources
1635  * @adapter:  Board private structure
1636  * @rx_ring:  Ring to clean the resources from
1637  */
1638 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1639                                 struct pch_gbe_rx_ring *rx_ring)
1640 {
1641         struct pci_dev *pdev = adapter->pdev;
1642
1643         pch_gbe_clean_rx_ring(adapter, rx_ring);
1644         vfree(rx_ring->buffer_info);
1645         rx_ring->buffer_info = NULL;
1646         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1647         rx_ring->desc = NULL;
1648 }
1649
1650 /**
1651  * pch_gbe_request_irq - Allocate an interrupt line
1652  * @adapter:  Board private structure
1653  * Returns
1654  *      0:              Successfully
1655  *      Negative value: Failed
1656  */
1657 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1658 {
1659         struct net_device *netdev = adapter->netdev;
1660         int err;
1661         int flags;
1662
1663         flags = IRQF_SHARED;
1664         adapter->have_msi = false;
1665         err = pci_enable_msi(adapter->pdev);
1666         pr_debug("call pci_enable_msi\n");
1667         if (err) {
1668                 pr_debug("call pci_enable_msi - Error: %d\n", err);
1669         } else {
1670                 flags = 0;
1671                 adapter->have_msi = true;
1672         }
1673         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1674                           flags, netdev->name, netdev);
1675         if (err)
1676                 pr_err("Unable to allocate interrupt Error: %d\n", err);
1677         pr_debug("adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1678                  adapter->have_msi, flags, err);
1679         return err;
1680 }
1681
1682
1683 static void pch_gbe_set_multi(struct net_device *netdev);
1684 /**
1685  * pch_gbe_up - Up GbE network device
1686  * @adapter:  Board private structure
1687  * Returns
1688  *      0:              Successfully
1689  *      Negative value: Failed
1690  */
1691 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1692 {
1693         struct net_device *netdev = adapter->netdev;
1694         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1695         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1696         int err;
1697
1698         /* hardware has been reset, we need to reload some things */
1699         pch_gbe_set_multi(netdev);
1700
1701         pch_gbe_setup_tctl(adapter);
1702         pch_gbe_configure_tx(adapter);
1703         pch_gbe_setup_rctl(adapter);
1704         pch_gbe_configure_rx(adapter);
1705
1706         err = pch_gbe_request_irq(adapter);
1707         if (err) {
1708                 pr_err("Error: can't bring device up\n");
1709                 return err;
1710         }
1711         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1712         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1713         adapter->tx_queue_len = netdev->tx_queue_len;
1714
1715         mod_timer(&adapter->watchdog_timer, jiffies);
1716
1717         napi_enable(&adapter->napi);
1718         pch_gbe_irq_enable(adapter);
1719         netif_start_queue(adapter->netdev);
1720
1721         return 0;
1722 }
1723
1724 /**
1725  * pch_gbe_down - Down GbE network device
1726  * @adapter:  Board private structure
1727  */
1728 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1729 {
1730         struct net_device *netdev = adapter->netdev;
1731
1732         /* signal that we're down so the interrupt handler does not
1733          * reschedule our watchdog timer */
1734         napi_disable(&adapter->napi);
1735         atomic_set(&adapter->irq_sem, 0);
1736
1737         pch_gbe_irq_disable(adapter);
1738         pch_gbe_free_irq(adapter);
1739
1740         del_timer_sync(&adapter->watchdog_timer);
1741
1742         netdev->tx_queue_len = adapter->tx_queue_len;
1743         netif_carrier_off(netdev);
1744         netif_stop_queue(netdev);
1745
1746         pch_gbe_reset(adapter);
1747         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1748         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1749 }
1750
1751 /**
1752  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1753  * @adapter:  Board private structure to initialize
1754  * Returns
1755  *      0:              Successfully
1756  *      Negative value: Failed
1757  */
1758 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1759 {
1760         struct pch_gbe_hw *hw = &adapter->hw;
1761         struct net_device *netdev = adapter->netdev;
1762
1763         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1764         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1765         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1766
1767         /* Initialize the hardware-specific values */
1768         if (pch_gbe_hal_setup_init_funcs(hw)) {
1769                 pr_err("Hardware Initialization Failure\n");
1770                 return -EIO;
1771         }
1772         if (pch_gbe_alloc_queues(adapter)) {
1773                 pr_err("Unable to allocate memory for queues\n");
1774                 return -ENOMEM;
1775         }
1776         spin_lock_init(&adapter->hw.miim_lock);
1777         spin_lock_init(&adapter->tx_queue_lock);
1778         spin_lock_init(&adapter->stats_lock);
1779         spin_lock_init(&adapter->ethtool_lock);
1780         atomic_set(&adapter->irq_sem, 0);
1781         pch_gbe_irq_disable(adapter);
1782
1783         pch_gbe_init_stats(adapter);
1784
1785         pr_debug("rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
1786                  (u32) adapter->rx_buffer_len,
1787                  hw->mac.min_frame_size, hw->mac.max_frame_size);
1788         return 0;
1789 }
1790
1791 /**
1792  * pch_gbe_open - Called when a network interface is made active
1793  * @netdev:     Network interface device structure
1794  * Returns
1795  *      0:              Successfully
1796  *      Negative value: Failed
1797  */
1798 static int pch_gbe_open(struct net_device *netdev)
1799 {
1800         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1801         struct pch_gbe_hw *hw = &adapter->hw;
1802         int err;
1803
1804         /* allocate transmit descriptors */
1805         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1806         if (err)
1807                 goto err_setup_tx;
1808         /* allocate receive descriptors */
1809         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1810         if (err)
1811                 goto err_setup_rx;
1812         pch_gbe_hal_power_up_phy(hw);
1813         err = pch_gbe_up(adapter);
1814         if (err)
1815                 goto err_up;
1816         pr_debug("Success End\n");
1817         return 0;
1818
1819 err_up:
1820         if (!adapter->wake_up_evt)
1821                 pch_gbe_hal_power_down_phy(hw);
1822         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1823 err_setup_rx:
1824         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1825 err_setup_tx:
1826         pch_gbe_reset(adapter);
1827         pr_err("Error End\n");
1828         return err;
1829 }
1830
1831 /**
1832  * pch_gbe_stop - Disables a network interface
1833  * @netdev:  Network interface device structure
1834  * Returns
1835  *      0: Successfully
1836  */
1837 static int pch_gbe_stop(struct net_device *netdev)
1838 {
1839         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1840         struct pch_gbe_hw *hw = &adapter->hw;
1841
1842         pch_gbe_down(adapter);
1843         if (!adapter->wake_up_evt)
1844                 pch_gbe_hal_power_down_phy(hw);
1845         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1846         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1847         return 0;
1848 }
1849
1850 /**
1851  * pch_gbe_xmit_frame - Packet transmitting start
1852  * @skb:     Socket buffer structure
1853  * @netdev:  Network interface device structure
1854  * Returns
1855  *      - NETDEV_TX_OK:   Normal end
1856  *      - NETDEV_TX_BUSY: Error end
1857  */
1858 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1859 {
1860         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1861         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1862         unsigned long flags;
1863
1864         if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1865                 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1866                        skb->len, adapter->hw.mac.max_frame_size);
1867                 dev_kfree_skb_any(skb);
1868                 adapter->stats.tx_length_errors++;
1869                 return NETDEV_TX_OK;
1870         }
1871         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1872                 /* Collision - tell upper layer to requeue */
1873                 return NETDEV_TX_LOCKED;
1874         }
1875         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1876                 netif_stop_queue(netdev);
1877                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1878                 pr_debug("Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
1879                          tx_ring->next_to_use, tx_ring->next_to_clean);
1880                 return NETDEV_TX_BUSY;
1881         }
1882         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1883
1884         /* CRC,ITAG no support */
1885         pch_gbe_tx_queue(adapter, tx_ring, skb);
1886         return NETDEV_TX_OK;
1887 }
1888
1889 /**
1890  * pch_gbe_get_stats - Get System Network Statistics
1891  * @netdev:  Network interface device structure
1892  * Returns:  The current stats
1893  */
1894 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1895 {
1896         /* only return the current stats */
1897         return &netdev->stats;
1898 }
1899
1900 /**
1901  * pch_gbe_set_multi - Multicast and Promiscuous mode set
1902  * @netdev:   Network interface device structure
1903  */
1904 static void pch_gbe_set_multi(struct net_device *netdev)
1905 {
1906         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1907         struct pch_gbe_hw *hw = &adapter->hw;
1908         struct netdev_hw_addr *ha;
1909         u8 *mta_list;
1910         u32 rctl;
1911         int i;
1912         int mc_count;
1913
1914         pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1915
1916         /* Check for Promiscuous and All Multicast modes */
1917         rctl = ioread32(&hw->reg->RX_MODE);
1918         mc_count = netdev_mc_count(netdev);
1919         if ((netdev->flags & IFF_PROMISC)) {
1920                 rctl &= ~PCH_GBE_ADD_FIL_EN;
1921                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1922         } else if ((netdev->flags & IFF_ALLMULTI)) {
1923                 /* all the multicasting receive permissions */
1924                 rctl |= PCH_GBE_ADD_FIL_EN;
1925                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1926         } else {
1927                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1928                         /* all the multicasting receive permissions */
1929                         rctl |= PCH_GBE_ADD_FIL_EN;
1930                         rctl &= ~PCH_GBE_MLT_FIL_EN;
1931                 } else {
1932                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1933                 }
1934         }
1935         iowrite32(rctl, &hw->reg->RX_MODE);
1936
1937         if (mc_count >= PCH_GBE_MAR_ENTRIES)
1938                 return;
1939         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1940         if (!mta_list)
1941                 return;
1942
1943         /* The shared function expects a packed array of only addresses. */
1944         i = 0;
1945         netdev_for_each_mc_addr(ha, netdev) {
1946                 if (i == mc_count)
1947                         break;
1948                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1949         }
1950         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1951                                         PCH_GBE_MAR_ENTRIES);
1952         kfree(mta_list);
1953
1954         pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
1955                  ioread32(&hw->reg->RX_MODE), mc_count);
1956 }
1957
1958 /**
1959  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1960  * @netdev: Network interface device structure
1961  * @addr:   Pointer to an address structure
1962  * Returns
1963  *      0:              Successfully
1964  *      -EADDRNOTAVAIL: Failed
1965  */
1966 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1967 {
1968         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1969         struct sockaddr *skaddr = addr;
1970         int ret_val;
1971
1972         if (!is_valid_ether_addr(skaddr->sa_data)) {
1973                 ret_val = -EADDRNOTAVAIL;
1974         } else {
1975                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1976                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1977                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1978                 ret_val = 0;
1979         }
1980         pr_debug("ret_val : 0x%08x\n", ret_val);
1981         pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1982         pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1983         pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1984                  ioread32(&adapter->hw.reg->mac_adr[0].high),
1985                  ioread32(&adapter->hw.reg->mac_adr[0].low));
1986         return ret_val;
1987 }
1988
1989 /**
1990  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1991  * @netdev:   Network interface device structure
1992  * @new_mtu:  New value for maximum frame size
1993  * Returns
1994  *      0:              Successfully
1995  *      -EINVAL:        Failed
1996  */
1997 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
1998 {
1999         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2000         int max_frame;
2001
2002         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2003         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2004                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2005                 pr_err("Invalid MTU setting\n");
2006                 return -EINVAL;
2007         }
2008         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2009                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2010         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2011                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2012         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2013                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2014         else
2015                 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2016         netdev->mtu = new_mtu;
2017         adapter->hw.mac.max_frame_size = max_frame;
2018
2019         if (netif_running(netdev))
2020                 pch_gbe_reinit_locked(adapter);
2021         else
2022                 pch_gbe_reset(adapter);
2023
2024         pr_debug("max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2025                  max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2026                  adapter->hw.mac.max_frame_size);
2027         return 0;
2028 }
2029
2030 /**
2031  * pch_gbe_ioctl - Controls register through a MII interface
2032  * @netdev:   Network interface device structure
2033  * @ifr:      Pointer to ifr structure
2034  * @cmd:      Control command
2035  * Returns
2036  *      0:      Successfully
2037  *      Negative value: Failed
2038  */
2039 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2040 {
2041         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2042
2043         pr_debug("cmd : 0x%04x\n", cmd);
2044
2045         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2046 }
2047
2048 /**
2049  * pch_gbe_tx_timeout - Respond to a Tx Hang
2050  * @netdev:   Network interface device structure
2051  */
2052 static void pch_gbe_tx_timeout(struct net_device *netdev)
2053 {
2054         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2055
2056         /* Do the reset outside of interrupt context */
2057         adapter->stats.tx_timeout_count++;
2058         schedule_work(&adapter->reset_task);
2059 }
2060
2061 /**
2062  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2063  * @napi:    Pointer of polling device struct
2064  * @budget:  The maximum number of a packet
2065  * Returns
2066  *      false:  Exit the polling mode
2067  *      true:   Continue the polling mode
2068  */
2069 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2070 {
2071         struct pch_gbe_adapter *adapter =
2072             container_of(napi, struct pch_gbe_adapter, napi);
2073         struct net_device *netdev = adapter->netdev;
2074         int work_done = 0;
2075         bool poll_end_flag = false;
2076         bool cleaned = false;
2077
2078         pr_debug("budget : %d\n", budget);
2079
2080         /* Keep link state information with original netdev */
2081         if (!netif_carrier_ok(netdev)) {
2082                 poll_end_flag = true;
2083         } else {
2084                 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2085                 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2086
2087                 if (cleaned)
2088                         work_done = budget;
2089                 /* If no Tx and not enough Rx work done,
2090                  * exit the polling mode
2091                  */
2092                 if ((work_done < budget) || !netif_running(netdev))
2093                         poll_end_flag = true;
2094         }
2095
2096         if (poll_end_flag) {
2097                 napi_complete(napi);
2098                 pch_gbe_irq_enable(adapter);
2099         }
2100
2101         pr_debug("poll_end_flag : %d  work_done : %d  budget : %d\n",
2102                  poll_end_flag, work_done, budget);
2103
2104         return work_done;
2105 }
2106
2107 #ifdef CONFIG_NET_POLL_CONTROLLER
2108 /**
2109  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2110  * @netdev:  Network interface device structure
2111  */
2112 static void pch_gbe_netpoll(struct net_device *netdev)
2113 {
2114         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2115
2116         disable_irq(adapter->pdev->irq);
2117         pch_gbe_intr(adapter->pdev->irq, netdev);
2118         enable_irq(adapter->pdev->irq);
2119 }
2120 #endif
2121
2122 static const struct net_device_ops pch_gbe_netdev_ops = {
2123         .ndo_open = pch_gbe_open,
2124         .ndo_stop = pch_gbe_stop,
2125         .ndo_start_xmit = pch_gbe_xmit_frame,
2126         .ndo_get_stats = pch_gbe_get_stats,
2127         .ndo_set_mac_address = pch_gbe_set_mac,
2128         .ndo_tx_timeout = pch_gbe_tx_timeout,
2129         .ndo_change_mtu = pch_gbe_change_mtu,
2130         .ndo_do_ioctl = pch_gbe_ioctl,
2131         .ndo_set_multicast_list = &pch_gbe_set_multi,
2132 #ifdef CONFIG_NET_POLL_CONTROLLER
2133         .ndo_poll_controller = pch_gbe_netpoll,
2134 #endif
2135 };
2136
2137 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2138                                                 pci_channel_state_t state)
2139 {
2140         struct net_device *netdev = pci_get_drvdata(pdev);
2141         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2142
2143         netif_device_detach(netdev);
2144         if (netif_running(netdev))
2145                 pch_gbe_down(adapter);
2146         pci_disable_device(pdev);
2147         /* Request a slot slot reset. */
2148         return PCI_ERS_RESULT_NEED_RESET;
2149 }
2150
2151 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2152 {
2153         struct net_device *netdev = pci_get_drvdata(pdev);
2154         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2155         struct pch_gbe_hw *hw = &adapter->hw;
2156
2157         if (pci_enable_device(pdev)) {
2158                 pr_err("Cannot re-enable PCI device after reset\n");
2159                 return PCI_ERS_RESULT_DISCONNECT;
2160         }
2161         pci_set_master(pdev);
2162         pci_enable_wake(pdev, PCI_D0, 0);
2163         pch_gbe_hal_power_up_phy(hw);
2164         pch_gbe_reset(adapter);
2165         /* Clear wake up status */
2166         pch_gbe_mac_set_wol_event(hw, 0);
2167
2168         return PCI_ERS_RESULT_RECOVERED;
2169 }
2170
2171 static void pch_gbe_io_resume(struct pci_dev *pdev)
2172 {
2173         struct net_device *netdev = pci_get_drvdata(pdev);
2174         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2175
2176         if (netif_running(netdev)) {
2177                 if (pch_gbe_up(adapter)) {
2178                         pr_debug("can't bring device back up after reset\n");
2179                         return;
2180                 }
2181         }
2182         netif_device_attach(netdev);
2183 }
2184
2185 static int __pch_gbe_suspend(struct pci_dev *pdev)
2186 {
2187         struct net_device *netdev = pci_get_drvdata(pdev);
2188         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2189         struct pch_gbe_hw *hw = &adapter->hw;
2190         u32 wufc = adapter->wake_up_evt;
2191         int retval = 0;
2192
2193         netif_device_detach(netdev);
2194         if (netif_running(netdev))
2195                 pch_gbe_down(adapter);
2196         if (wufc) {
2197                 pch_gbe_set_multi(netdev);
2198                 pch_gbe_setup_rctl(adapter);
2199                 pch_gbe_configure_rx(adapter);
2200                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2201                                         hw->mac.link_duplex);
2202                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2203                                         hw->mac.link_duplex);
2204                 pch_gbe_mac_set_wol_event(hw, wufc);
2205                 pci_disable_device(pdev);
2206         } else {
2207                 pch_gbe_hal_power_down_phy(hw);
2208                 pch_gbe_mac_set_wol_event(hw, wufc);
2209                 pci_disable_device(pdev);
2210         }
2211         return retval;
2212 }
2213
2214 #ifdef CONFIG_PM
2215 static int pch_gbe_suspend(struct device *device)
2216 {
2217         struct pci_dev *pdev = to_pci_dev(device);
2218
2219         return __pch_gbe_suspend(pdev);
2220 }
2221
2222 static int pch_gbe_resume(struct device *device)
2223 {
2224         struct pci_dev *pdev = to_pci_dev(device);
2225         struct net_device *netdev = pci_get_drvdata(pdev);
2226         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2227         struct pch_gbe_hw *hw = &adapter->hw;
2228         u32 err;
2229
2230         err = pci_enable_device(pdev);
2231         if (err) {
2232                 pr_err("Cannot enable PCI device from suspend\n");
2233                 return err;
2234         }
2235         pci_set_master(pdev);
2236         pch_gbe_hal_power_up_phy(hw);
2237         pch_gbe_reset(adapter);
2238         /* Clear wake on lan control and status */
2239         pch_gbe_mac_set_wol_event(hw, 0);
2240
2241         if (netif_running(netdev))
2242                 pch_gbe_up(adapter);
2243         netif_device_attach(netdev);
2244
2245         return 0;
2246 }
2247 #endif /* CONFIG_PM */
2248
2249 static void pch_gbe_shutdown(struct pci_dev *pdev)
2250 {
2251         __pch_gbe_suspend(pdev);
2252         if (system_state == SYSTEM_POWER_OFF) {
2253                 pci_wake_from_d3(pdev, true);
2254                 pci_set_power_state(pdev, PCI_D3hot);
2255         }
2256 }
2257
2258 static void pch_gbe_remove(struct pci_dev *pdev)
2259 {
2260         struct net_device *netdev = pci_get_drvdata(pdev);
2261         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2262
2263         cancel_work_sync(&adapter->reset_task);
2264         unregister_netdev(netdev);
2265
2266         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2267
2268         kfree(adapter->tx_ring);
2269         kfree(adapter->rx_ring);
2270
2271         iounmap(adapter->hw.reg);
2272         pci_release_regions(pdev);
2273         free_netdev(netdev);
2274         pci_disable_device(pdev);
2275 }
2276
2277 static int pch_gbe_probe(struct pci_dev *pdev,
2278                           const struct pci_device_id *pci_id)
2279 {
2280         struct net_device *netdev;
2281         struct pch_gbe_adapter *adapter;
2282         int ret;
2283
2284         ret = pci_enable_device(pdev);
2285         if (ret)
2286                 return ret;
2287
2288         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2289                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2290                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2291                 if (ret) {
2292                         ret = pci_set_consistent_dma_mask(pdev,
2293                                                           DMA_BIT_MASK(32));
2294                         if (ret) {
2295                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2296                                         "configuration, aborting\n");
2297                                 goto err_disable_device;
2298                         }
2299                 }
2300         }
2301
2302         ret = pci_request_regions(pdev, KBUILD_MODNAME);
2303         if (ret) {
2304                 dev_err(&pdev->dev,
2305                         "ERR: Can't reserve PCI I/O and memory resources\n");
2306                 goto err_disable_device;
2307         }
2308         pci_set_master(pdev);
2309
2310         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2311         if (!netdev) {
2312                 ret = -ENOMEM;
2313                 dev_err(&pdev->dev,
2314                         "ERR: Can't allocate and set up an Ethernet device\n");
2315                 goto err_release_pci;
2316         }
2317         SET_NETDEV_DEV(netdev, &pdev->dev);
2318
2319         pci_set_drvdata(pdev, netdev);
2320         adapter = netdev_priv(netdev);
2321         adapter->netdev = netdev;
2322         adapter->pdev = pdev;
2323         adapter->hw.back = adapter;
2324         adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2325         if (!adapter->hw.reg) {
2326                 ret = -EIO;
2327                 dev_err(&pdev->dev, "Can't ioremap\n");
2328                 goto err_free_netdev;
2329         }
2330
2331         netdev->netdev_ops = &pch_gbe_netdev_ops;
2332         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2333         netif_napi_add(netdev, &adapter->napi,
2334                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2335         netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
2336         pch_gbe_set_ethtool_ops(netdev);
2337
2338         pch_gbe_mac_load_mac_addr(&adapter->hw);
2339         pch_gbe_mac_reset_hw(&adapter->hw);
2340
2341         /* setup the private structure */
2342         ret = pch_gbe_sw_init(adapter);
2343         if (ret)
2344                 goto err_iounmap;
2345
2346         /* Initialize PHY */
2347         ret = pch_gbe_init_phy(adapter);
2348         if (ret) {
2349                 dev_err(&pdev->dev, "PHY initialize error\n");
2350                 goto err_free_adapter;
2351         }
2352         pch_gbe_hal_get_bus_info(&adapter->hw);
2353
2354         /* Read the MAC address. and store to the private data */
2355         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2356         if (ret) {
2357                 dev_err(&pdev->dev, "MAC address Read Error\n");
2358                 goto err_free_adapter;
2359         }
2360
2361         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2362         if (!is_valid_ether_addr(netdev->dev_addr)) {
2363                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2364                 ret = -EIO;
2365                 goto err_free_adapter;
2366         }
2367         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2368                     (unsigned long)adapter);
2369
2370         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2371
2372         pch_gbe_check_options(adapter);
2373
2374         if (adapter->tx_csum)
2375                 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2376         else
2377                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2378
2379         /* initialize the wol settings based on the eeprom settings */
2380         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2381         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2382
2383         /* reset the hardware with the new settings */
2384         pch_gbe_reset(adapter);
2385
2386         ret = register_netdev(netdev);
2387         if (ret)
2388                 goto err_free_adapter;
2389         /* tell the stack to leave us alone until pch_gbe_open() is called */
2390         netif_carrier_off(netdev);
2391         netif_stop_queue(netdev);
2392
2393         dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2394
2395         device_set_wakeup_enable(&pdev->dev, 1);
2396         return 0;
2397
2398 err_free_adapter:
2399         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2400         kfree(adapter->tx_ring);
2401         kfree(adapter->rx_ring);
2402 err_iounmap:
2403         iounmap(adapter->hw.reg);
2404 err_free_netdev:
2405         free_netdev(netdev);
2406 err_release_pci:
2407         pci_release_regions(pdev);
2408 err_disable_device:
2409         pci_disable_device(pdev);
2410         return ret;
2411 }
2412
2413 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2414         {.vendor = PCI_VENDOR_ID_INTEL,
2415          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2416          .subvendor = PCI_ANY_ID,
2417          .subdevice = PCI_ANY_ID,
2418          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2419          .class_mask = (0xFFFF00)
2420          },
2421         /* required last entry */
2422         {0}
2423 };
2424
2425 #ifdef CONFIG_PM
2426 static const struct dev_pm_ops pch_gbe_pm_ops = {
2427         .suspend = pch_gbe_suspend,
2428         .resume = pch_gbe_resume,
2429         .freeze = pch_gbe_suspend,
2430         .thaw = pch_gbe_resume,
2431         .poweroff = pch_gbe_suspend,
2432         .restore = pch_gbe_resume,
2433 };
2434 #endif
2435
2436 static struct pci_error_handlers pch_gbe_err_handler = {
2437         .error_detected = pch_gbe_io_error_detected,
2438         .slot_reset = pch_gbe_io_slot_reset,
2439         .resume = pch_gbe_io_resume
2440 };
2441
2442 static struct pci_driver pch_gbe_driver = {
2443         .name = KBUILD_MODNAME,
2444         .id_table = pch_gbe_pcidev_id,
2445         .probe = pch_gbe_probe,
2446         .remove = pch_gbe_remove,
2447 #ifdef CONFIG_PM
2448         .driver.pm = &pch_gbe_pm_ops,
2449 #endif
2450         .shutdown = pch_gbe_shutdown,
2451         .err_handler = &pch_gbe_err_handler
2452 };
2453
2454
2455 static int __init pch_gbe_init_module(void)
2456 {
2457         int ret;
2458
2459         ret = pci_register_driver(&pch_gbe_driver);
2460         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2461                 if (copybreak == 0) {
2462                         pr_info("copybreak disabled\n");
2463                 } else {
2464                         pr_info("copybreak enabled for packets <= %u bytes\n",
2465                                 copybreak);
2466                 }
2467         }
2468         return ret;
2469 }
2470
2471 static void __exit pch_gbe_exit_module(void)
2472 {
2473         pci_unregister_driver(&pch_gbe_driver);
2474 }
2475
2476 module_init(pch_gbe_init_module);
2477 module_exit(pch_gbe_exit_module);
2478
2479 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2480 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2481 MODULE_LICENSE("GPL");
2482 MODULE_VERSION(DRV_VERSION);
2483 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2484
2485 module_param(copybreak, uint, 0644);
2486 MODULE_PARM_DESC(copybreak,
2487         "Maximum size of packet that is copied to a new buffer on receive");
2488
2489 /* pch_gbe_main.c */