2 * AMD 10Gb Ethernet PHY driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 * License 2: Modified BSD
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 #include <linux/kernel.h>
54 #include <linux/device.h>
55 #include <linux/platform_device.h>
56 #include <linux/string.h>
57 #include <linux/errno.h>
58 #include <linux/unistd.h>
59 #include <linux/slab.h>
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
62 #include <linux/delay.h>
63 #include <linux/netdevice.h>
64 #include <linux/etherdevice.h>
65 #include <linux/skbuff.h>
67 #include <linux/module.h>
68 #include <linux/mii.h>
69 #include <linux/ethtool.h>
70 #include <linux/phy.h>
71 #include <linux/mdio.h>
74 #include <linux/of_platform.h>
75 #include <linux/of_device.h>
76 #include <linux/uaccess.h>
78 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
79 MODULE_LICENSE("Dual BSD/GPL");
80 MODULE_VERSION("1.0.0-a");
81 MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
83 #define XGBE_PHY_ID 0x000162d0
84 #define XGBE_PHY_MASK 0xfffffff0
86 #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
88 #define XGBE_AN_INT_CMPLT 0x01
89 #define XGBE_AN_INC_LINK 0x02
90 #define XGBE_AN_PG_RCV 0x04
92 #define XNP_MCF_NULL_MESSAGE 0x001
93 #define XNP_ACK_PROCESSED (1 << 12)
94 #define XNP_MP_FORMATTED (1 << 13)
95 #define XNP_NP_EXCHANGE (1 << 15)
97 #define XGBE_PHY_RATECHANGE_COUNT 500
99 #ifndef MDIO_PMA_10GBR_PMD_CTRL
100 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
103 #ifndef MDIO_PMA_10GBR_FEC_CTRL
104 #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
108 #define MDIO_AN_XNP 0x0016
111 #ifndef MDIO_AN_INTMASK
112 #define MDIO_AN_INTMASK 0x8001
116 #define MDIO_AN_INT 0x8002
119 #ifndef MDIO_AN_KR_CTRL
120 #define MDIO_AN_KR_CTRL 0x8003
123 #ifndef MDIO_CTRL1_SPEED1G
124 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
127 #ifndef MDIO_KR_CTRL_PDETECT
128 #define MDIO_KR_CTRL_PDETECT 0x01
131 /* SerDes integration register offsets */
132 #define SIR0_KR_RT_1 0x002c
133 #define SIR0_STATUS 0x0040
134 #define SIR1_SPEED 0x0000
136 /* SerDes integration register entry bit positions and sizes */
137 #define SIR0_KR_RT_1_RESET_INDEX 11
138 #define SIR0_KR_RT_1_RESET_WIDTH 1
139 #define SIR0_STATUS_RX_READY_INDEX 0
140 #define SIR0_STATUS_RX_READY_WIDTH 1
141 #define SIR0_STATUS_TX_READY_INDEX 8
142 #define SIR0_STATUS_TX_READY_WIDTH 1
143 #define SIR1_SPEED_DATARATE_INDEX 4
144 #define SIR1_SPEED_DATARATE_WIDTH 2
145 #define SIR1_SPEED_PI_SPD_SEL_INDEX 12
146 #define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
147 #define SIR1_SPEED_PLLSEL_INDEX 3
148 #define SIR1_SPEED_PLLSEL_WIDTH 1
149 #define SIR1_SPEED_RATECHANGE_INDEX 6
150 #define SIR1_SPEED_RATECHANGE_WIDTH 1
151 #define SIR1_SPEED_TXAMP_INDEX 8
152 #define SIR1_SPEED_TXAMP_WIDTH 4
153 #define SIR1_SPEED_WORDMODE_INDEX 0
154 #define SIR1_SPEED_WORDMODE_WIDTH 3
156 #define SPEED_10000_CDR 0x7
157 #define SPEED_10000_PLL 0x1
158 #define SPEED_10000_RATE 0x0
159 #define SPEED_10000_TXAMP 0xa
160 #define SPEED_10000_WORD 0x7
162 #define SPEED_2500_CDR 0x2
163 #define SPEED_2500_PLL 0x0
164 #define SPEED_2500_RATE 0x1
165 #define SPEED_2500_TXAMP 0xf
166 #define SPEED_2500_WORD 0x1
168 #define SPEED_1000_CDR 0x2
169 #define SPEED_1000_PLL 0x0
170 #define SPEED_1000_RATE 0x3
171 #define SPEED_1000_TXAMP 0xf
172 #define SPEED_1000_WORD 0x1
174 /* SerDes RxTx register offsets */
175 #define RXTX_REG20 0x0050
176 #define RXTX_REG114 0x01c8
178 /* SerDes RxTx register entry bit positions and sizes */
179 #define RXTX_REG20_BLWC_ENA_INDEX 2
180 #define RXTX_REG20_BLWC_ENA_WIDTH 1
181 #define RXTX_REG114_PQ_REG_INDEX 9
182 #define RXTX_REG114_PQ_REG_WIDTH 7
184 #define RXTX_10000_BLWC 0
185 #define RXTX_10000_PQ 0x1e
187 #define RXTX_2500_BLWC 1
188 #define RXTX_2500_PQ 0xa
190 #define RXTX_1000_BLWC 1
191 #define RXTX_1000_PQ 0xa
193 /* Bit setting and getting macros
194 * The get macro will extract the current bit field value from within
197 * The set macro will clear the current bit field value within the
198 * variable and then set the bit field of the variable to the
201 #define GET_BITS(_var, _index, _width) \
202 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
204 #define SET_BITS(_var, _index, _width, _val) \
206 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
207 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
210 #define XSIR_GET_BITS(_var, _prefix, _field) \
212 _prefix##_##_field##_INDEX, \
213 _prefix##_##_field##_WIDTH)
215 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
217 _prefix##_##_field##_INDEX, \
218 _prefix##_##_field##_WIDTH, (_val))
220 /* Macros for reading or writing SerDes integration registers
221 * The ioread macros will get bit fields or full values using the
222 * register definitions formed using the input names
224 * The iowrite macros will set bit fields or full values using the
225 * register definitions formed using the input names
227 #define XSIR0_IOREAD(_priv, _reg) \
228 ioread16((_priv)->sir0_regs + _reg)
230 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
231 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
232 _reg##_##_field##_INDEX, \
233 _reg##_##_field##_WIDTH)
235 #define XSIR0_IOWRITE(_priv, _reg, _val) \
236 iowrite16((_val), (_priv)->sir0_regs + _reg)
238 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
240 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
242 _reg##_##_field##_INDEX, \
243 _reg##_##_field##_WIDTH, (_val)); \
244 XSIR0_IOWRITE((_priv), _reg, reg_val); \
247 #define XSIR1_IOREAD(_priv, _reg) \
248 ioread16((_priv)->sir1_regs + _reg)
250 #define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
251 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
252 _reg##_##_field##_INDEX, \
253 _reg##_##_field##_WIDTH)
255 #define XSIR1_IOWRITE(_priv, _reg, _val) \
256 iowrite16((_val), (_priv)->sir1_regs + _reg)
258 #define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
260 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
262 _reg##_##_field##_INDEX, \
263 _reg##_##_field##_WIDTH, (_val)); \
264 XSIR1_IOWRITE((_priv), _reg, reg_val); \
267 /* Macros for reading or writing SerDes RxTx registers
268 * The ioread macros will get bit fields or full values using the
269 * register definitions formed using the input names
271 * The iowrite macros will set bit fields or full values using the
272 * register definitions formed using the input names
274 #define XRXTX_IOREAD(_priv, _reg) \
275 ioread16((_priv)->rxtx_regs + _reg)
277 #define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
278 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
279 _reg##_##_field##_INDEX, \
280 _reg##_##_field##_WIDTH)
282 #define XRXTX_IOWRITE(_priv, _reg, _val) \
283 iowrite16((_val), (_priv)->rxtx_regs + _reg)
285 #define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
287 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
289 _reg##_##_field##_INDEX, \
290 _reg##_##_field##_WIDTH, (_val)); \
291 XRXTX_IOWRITE((_priv), _reg, reg_val); \
294 enum amd_xgbe_phy_an {
295 AMD_XGBE_AN_READY = 0,
298 AMD_XGBE_AN_PAGE_RECEIVED,
299 AMD_XGBE_AN_INCOMPAT_LINK,
300 AMD_XGBE_AN_COMPLETE,
306 enum amd_xgbe_phy_rx {
307 AMD_XGBE_RX_READY = 0,
310 AMD_XGBE_RX_COMPLETE,
313 enum amd_xgbe_phy_mode {
318 enum amd_xgbe_phy_speedset {
319 AMD_XGBE_PHY_SPEEDSET_1000_10000,
320 AMD_XGBE_PHY_SPEEDSET_2500_10000,
323 struct amd_xgbe_phy_priv {
324 struct platform_device *pdev;
327 struct phy_device *phydev;
329 /* SerDes related mmio resources */
330 struct resource *rxtx_res;
331 struct resource *sir0_res;
332 struct resource *sir1_res;
334 /* SerDes related mmio registers */
335 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
336 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
337 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
339 /* Maintain link status for re-starting auto-negotiation */
341 unsigned int speed_set;
343 /* Auto-negotiation state machine support */
344 struct mutex an_mutex;
345 enum amd_xgbe_phy_an an_result;
346 enum amd_xgbe_phy_an an_state;
347 enum amd_xgbe_phy_rx kr_state;
348 enum amd_xgbe_phy_rx kx_state;
349 struct work_struct an_work;
350 struct workqueue_struct *an_workqueue;
351 unsigned int parallel_detect;
354 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
358 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
363 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
368 static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
372 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
377 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
382 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
386 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
390 ret |= MDIO_CTRL1_LPOWER;
391 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
393 usleep_range(75, 100);
395 ret &= ~MDIO_CTRL1_LPOWER;
396 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
401 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
403 struct amd_xgbe_phy_priv *priv = phydev->priv;
405 /* Assert Rx and Tx ratechange */
406 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
409 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
411 struct amd_xgbe_phy_priv *priv = phydev->priv;
415 /* Release Rx and Tx ratechange */
416 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
418 /* Wait for Rx and Tx ready */
419 wait = XGBE_PHY_RATECHANGE_COUNT;
421 usleep_range(50, 75);
423 status = XSIR0_IOREAD(priv, SIR0_STATUS);
424 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
425 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
429 netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
433 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
435 struct amd_xgbe_phy_priv *priv = phydev->priv;
438 /* Enable KR training */
439 ret = amd_xgbe_an_enable_kr_training(phydev);
443 /* Set PCS to KR/10G speed */
444 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
448 ret &= ~MDIO_PCS_CTRL2_TYPE;
449 ret |= MDIO_PCS_CTRL2_10GBR;
450 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
452 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
456 ret &= ~MDIO_CTRL1_SPEEDSEL;
457 ret |= MDIO_CTRL1_SPEED10G;
458 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
460 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
464 /* Set SerDes to 10G speed */
465 amd_xgbe_phy_serdes_start_ratechange(phydev);
467 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
468 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
469 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
470 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
471 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
473 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
474 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
476 amd_xgbe_phy_serdes_complete_ratechange(phydev);
481 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
483 struct amd_xgbe_phy_priv *priv = phydev->priv;
486 /* Disable KR training */
487 ret = amd_xgbe_an_disable_kr_training(phydev);
491 /* Set PCS to KX/1G speed */
492 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
496 ret &= ~MDIO_PCS_CTRL2_TYPE;
497 ret |= MDIO_PCS_CTRL2_10GBX;
498 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
500 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
504 ret &= ~MDIO_CTRL1_SPEEDSEL;
505 ret |= MDIO_CTRL1_SPEED1G;
506 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
508 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
512 /* Set SerDes to 2.5G speed */
513 amd_xgbe_phy_serdes_start_ratechange(phydev);
515 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
516 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
517 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
518 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
519 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
521 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
522 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
524 amd_xgbe_phy_serdes_complete_ratechange(phydev);
529 static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
531 struct amd_xgbe_phy_priv *priv = phydev->priv;
534 /* Disable KR training */
535 ret = amd_xgbe_an_disable_kr_training(phydev);
539 /* Set PCS to KX/1G speed */
540 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
544 ret &= ~MDIO_PCS_CTRL2_TYPE;
545 ret |= MDIO_PCS_CTRL2_10GBX;
546 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
548 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
552 ret &= ~MDIO_CTRL1_SPEEDSEL;
553 ret |= MDIO_CTRL1_SPEED1G;
554 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
556 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
560 /* Set SerDes to 1G speed */
561 amd_xgbe_phy_serdes_start_ratechange(phydev);
563 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
564 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
565 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
566 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
567 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
569 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
570 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
572 amd_xgbe_phy_serdes_complete_ratechange(phydev);
577 static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
578 enum amd_xgbe_phy_mode *mode)
582 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
586 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
587 *mode = AMD_XGBE_MODE_KR;
589 *mode = AMD_XGBE_MODE_KX;
594 static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
596 enum amd_xgbe_phy_mode mode;
598 if (amd_xgbe_phy_cur_mode(phydev, &mode))
601 return (mode == AMD_XGBE_MODE_KR);
604 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
606 struct amd_xgbe_phy_priv *priv = phydev->priv;
609 /* If we are in KR switch to KX, and vice-versa */
610 if (amd_xgbe_phy_in_kr_mode(phydev)) {
611 if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
612 ret = amd_xgbe_phy_gmii_mode(phydev);
614 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
616 ret = amd_xgbe_phy_xgmii_mode(phydev);
622 static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
623 enum amd_xgbe_phy_mode mode)
625 enum amd_xgbe_phy_mode cur_mode;
628 ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
632 if (mode != cur_mode)
633 ret = amd_xgbe_phy_switch_mode(phydev);
638 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
639 enum amd_xgbe_phy_rx *state)
641 struct amd_xgbe_phy_priv *priv = phydev->priv;
642 int ad_reg, lp_reg, ret;
644 *state = AMD_XGBE_RX_COMPLETE;
646 /* If we're not in KR mode then we're done */
647 if (!amd_xgbe_phy_in_kr_mode(phydev))
648 return AMD_XGBE_AN_EVENT;
650 /* Enable/Disable FEC */
651 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
653 return AMD_XGBE_AN_ERROR;
655 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
657 return AMD_XGBE_AN_ERROR;
659 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
661 return AMD_XGBE_AN_ERROR;
663 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
668 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
670 /* Start KR training */
671 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
673 return AMD_XGBE_AN_ERROR;
675 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
678 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
680 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
682 return AMD_XGBE_AN_EVENT;
685 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
686 enum amd_xgbe_phy_rx *state)
690 *state = AMD_XGBE_RX_XNP;
692 msg = XNP_MCF_NULL_MESSAGE;
693 msg |= XNP_MP_FORMATTED;
695 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
696 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
697 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
699 return AMD_XGBE_AN_EVENT;
702 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
703 enum amd_xgbe_phy_rx *state)
705 unsigned int link_support;
706 int ret, ad_reg, lp_reg;
708 /* Read Base Ability register 2 first */
709 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
711 return AMD_XGBE_AN_ERROR;
713 /* Check for a supported mode, otherwise restart in a different one */
714 link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
715 if (!(ret & link_support))
716 return AMD_XGBE_AN_INCOMPAT_LINK;
718 /* Check Extended Next Page support */
719 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
721 return AMD_XGBE_AN_ERROR;
723 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
725 return AMD_XGBE_AN_ERROR;
727 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
728 amd_xgbe_an_tx_xnp(phydev, state) :
729 amd_xgbe_an_tx_training(phydev, state);
732 static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
733 enum amd_xgbe_phy_rx *state)
737 /* Check Extended Next Page support */
738 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
740 return AMD_XGBE_AN_ERROR;
742 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
744 return AMD_XGBE_AN_ERROR;
746 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
747 amd_xgbe_an_tx_xnp(phydev, state) :
748 amd_xgbe_an_tx_training(phydev, state);
751 static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
753 struct amd_xgbe_phy_priv *priv = phydev->priv;
756 /* Be sure we aren't looping trying to negotiate */
757 if (amd_xgbe_phy_in_kr_mode(phydev)) {
758 if (priv->kr_state != AMD_XGBE_RX_READY)
759 return AMD_XGBE_AN_NO_LINK;
760 priv->kr_state = AMD_XGBE_RX_BPA;
762 if (priv->kx_state != AMD_XGBE_RX_READY)
763 return AMD_XGBE_AN_NO_LINK;
764 priv->kx_state = AMD_XGBE_RX_BPA;
767 /* Set up Advertisement register 3 first */
768 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
770 return AMD_XGBE_AN_ERROR;
772 if (phydev->supported & SUPPORTED_10000baseR_FEC)
777 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
779 /* Set up Advertisement register 2 next */
780 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
782 return AMD_XGBE_AN_ERROR;
784 if (phydev->supported & SUPPORTED_10000baseKR_Full)
789 if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
790 (phydev->supported & SUPPORTED_2500baseX_Full))
795 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
797 /* Set up Advertisement register 1 last */
798 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
800 return AMD_XGBE_AN_ERROR;
802 if (phydev->supported & SUPPORTED_Pause)
807 if (phydev->supported & SUPPORTED_Asym_Pause)
812 /* We don't intend to perform XNP */
813 ret &= ~XNP_NP_EXCHANGE;
815 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
817 /* Enable and start auto-negotiation */
818 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
820 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
822 return AMD_XGBE_AN_ERROR;
824 ret |= MDIO_KR_CTRL_PDETECT;
825 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
827 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
829 return AMD_XGBE_AN_ERROR;
831 ret |= MDIO_AN_CTRL1_ENABLE;
832 ret |= MDIO_AN_CTRL1_RESTART;
833 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
835 return AMD_XGBE_AN_EVENT;
838 static enum amd_xgbe_phy_an amd_xgbe_an_event(struct phy_device *phydev)
840 enum amd_xgbe_phy_an new_state;
843 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
845 return AMD_XGBE_AN_ERROR;
847 new_state = AMD_XGBE_AN_EVENT;
848 if (ret & XGBE_AN_PG_RCV)
849 new_state = AMD_XGBE_AN_PAGE_RECEIVED;
850 else if (ret & XGBE_AN_INC_LINK)
851 new_state = AMD_XGBE_AN_INCOMPAT_LINK;
852 else if (ret & XGBE_AN_INT_CMPLT)
853 new_state = AMD_XGBE_AN_COMPLETE;
855 if (new_state != AMD_XGBE_AN_EVENT)
856 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
861 static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
863 struct amd_xgbe_phy_priv *priv = phydev->priv;
864 enum amd_xgbe_phy_rx *state;
867 state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
871 case AMD_XGBE_RX_BPA:
872 ret = amd_xgbe_an_rx_bpa(phydev, state);
875 case AMD_XGBE_RX_XNP:
876 ret = amd_xgbe_an_rx_xnp(phydev, state);
880 ret = AMD_XGBE_AN_ERROR;
886 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
890 ret = amd_xgbe_phy_switch_mode(phydev);
892 return AMD_XGBE_AN_ERROR;
894 return AMD_XGBE_AN_START;
897 static void amd_xgbe_an_state_machine(struct work_struct *work)
899 struct amd_xgbe_phy_priv *priv = container_of(work,
900 struct amd_xgbe_phy_priv,
902 struct phy_device *phydev = priv->phydev;
903 enum amd_xgbe_phy_an cur_state;
905 unsigned int an_supported = 0;
907 /* Start in KX mode */
908 if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
909 priv->an_state = AMD_XGBE_AN_ERROR;
912 mutex_lock(&priv->an_mutex);
914 cur_state = priv->an_state;
916 switch (priv->an_state) {
917 case AMD_XGBE_AN_START:
919 priv->parallel_detect = 0;
920 priv->an_state = amd_xgbe_an_start(phydev);
923 case AMD_XGBE_AN_EVENT:
924 priv->an_state = amd_xgbe_an_event(phydev);
927 case AMD_XGBE_AN_PAGE_RECEIVED:
928 priv->an_state = amd_xgbe_an_page_received(phydev);
932 case AMD_XGBE_AN_INCOMPAT_LINK:
933 priv->an_state = amd_xgbe_an_incompat_link(phydev);
936 case AMD_XGBE_AN_COMPLETE:
937 priv->parallel_detect = an_supported ? 0 : 1;
938 netdev_info(phydev->attached_dev, "%s successful\n",
939 an_supported ? "Auto negotiation"
940 : "Parallel detection");
943 case AMD_XGBE_AN_NO_LINK:
944 case AMD_XGBE_AN_EXIT:
948 priv->an_state = AMD_XGBE_AN_ERROR;
951 if (priv->an_state == AMD_XGBE_AN_ERROR) {
952 netdev_err(phydev->attached_dev,
953 "error during auto-negotiation, state=%u\n",
958 sleep = (priv->an_state == AMD_XGBE_AN_EVENT) ? 1 : 0;
960 mutex_unlock(&priv->an_mutex);
963 usleep_range(20, 50);
967 priv->an_result = priv->an_state;
968 priv->an_state = AMD_XGBE_AN_READY;
970 mutex_unlock(&priv->an_mutex);
973 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
977 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
981 ret |= MDIO_CTRL1_RESET;
982 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
987 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
990 } while ((ret & MDIO_CTRL1_RESET) && --count);
992 if (ret & MDIO_CTRL1_RESET)
995 /* Make sure the XPCS and SerDes are in compatible states */
996 return amd_xgbe_phy_xgmii_mode(phydev);
999 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
1001 struct amd_xgbe_phy_priv *priv = phydev->priv;
1003 /* Initialize supported features */
1004 phydev->supported = SUPPORTED_Autoneg;
1005 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1006 phydev->supported |= SUPPORTED_Backplane;
1007 phydev->supported |= SUPPORTED_10000baseKR_Full |
1008 SUPPORTED_10000baseR_FEC;
1009 switch (priv->speed_set) {
1010 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1011 phydev->supported |= SUPPORTED_1000baseKX_Full;
1013 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1014 phydev->supported |= SUPPORTED_2500baseX_Full;
1017 phydev->advertising = phydev->supported;
1019 /* Turn off and clear interrupts */
1020 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1021 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1026 static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
1030 /* Disable auto-negotiation */
1031 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
1035 ret &= ~MDIO_AN_CTRL1_ENABLE;
1036 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
1038 /* Validate/Set specified speed */
1039 switch (phydev->speed) {
1041 ret = amd_xgbe_phy_xgmii_mode(phydev);
1045 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
1049 ret = amd_xgbe_phy_gmii_mode(phydev);
1059 /* Validate duplex mode */
1060 if (phydev->duplex != DUPLEX_FULL)
1064 phydev->asym_pause = 0;
1069 static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
1071 struct amd_xgbe_phy_priv *priv = phydev->priv;
1072 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1074 if (phydev->autoneg != AUTONEG_ENABLE)
1075 return amd_xgbe_phy_setup_forced(phydev);
1077 /* Make sure we have the AN MMD present */
1078 if (!(mmd_mask & MDIO_DEVS_AN))
1081 /* Start/Restart the auto-negotiation state machine */
1082 mutex_lock(&priv->an_mutex);
1083 priv->an_result = AMD_XGBE_AN_READY;
1084 priv->an_state = AMD_XGBE_AN_START;
1085 priv->kr_state = AMD_XGBE_RX_READY;
1086 priv->kx_state = AMD_XGBE_RX_READY;
1087 mutex_unlock(&priv->an_mutex);
1089 queue_work(priv->an_workqueue, &priv->an_work);
1094 static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
1096 struct amd_xgbe_phy_priv *priv = phydev->priv;
1097 enum amd_xgbe_phy_an state;
1099 mutex_lock(&priv->an_mutex);
1100 state = priv->an_result;
1101 mutex_unlock(&priv->an_mutex);
1103 return (state == AMD_XGBE_AN_COMPLETE);
1106 static int amd_xgbe_phy_update_link(struct phy_device *phydev)
1108 struct amd_xgbe_phy_priv *priv = phydev->priv;
1109 enum amd_xgbe_phy_an state;
1110 unsigned int check_again, autoneg;
1113 /* If we're doing auto-negotiation don't report link down */
1114 mutex_lock(&priv->an_mutex);
1115 state = priv->an_state;
1116 mutex_unlock(&priv->an_mutex);
1118 if (state != AMD_XGBE_AN_READY) {
1123 /* Since the device can be in the wrong mode when a link is
1124 * (re-)established (cable connected after the interface is
1125 * up, etc.), the link status may report no link. If there
1126 * is no link, try switching modes and checking the status
1127 * again if auto negotiation is enabled.
1129 check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0;
1131 /* Link status is latched low, so read once to clear
1132 * and then read again to get current state
1134 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1138 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1142 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1144 if (!phydev->link) {
1146 ret = amd_xgbe_phy_switch_mode(phydev);
1154 autoneg = (phydev->link && !priv->link) ? 1 : 0;
1155 priv->link = phydev->link;
1157 /* Link is (back) up, re-start auto-negotiation */
1158 ret = amd_xgbe_phy_config_aneg(phydev);
1166 static int amd_xgbe_phy_read_status(struct phy_device *phydev)
1168 struct amd_xgbe_phy_priv *priv = phydev->priv;
1169 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1170 int ret, ad_ret, lp_ret;
1172 ret = amd_xgbe_phy_update_link(phydev);
1176 if ((phydev->autoneg == AUTONEG_ENABLE) &&
1177 !priv->parallel_detect) {
1178 if (!(mmd_mask & MDIO_DEVS_AN))
1181 if (!amd_xgbe_phy_aneg_done(phydev))
1184 /* Compare Advertisement and Link Partner register 1 */
1185 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1188 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
1193 phydev->pause = (ad_ret & 0x400) ? 1 : 0;
1194 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
1196 /* Compare Advertisement and Link Partner register 2 */
1197 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
1198 MDIO_AN_ADVERTISE + 1);
1201 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1206 if (ad_ret & 0x80) {
1207 phydev->speed = SPEED_10000;
1208 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1212 switch (priv->speed_set) {
1213 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1214 phydev->speed = SPEED_1000;
1217 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1218 phydev->speed = SPEED_2500;
1222 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1227 phydev->duplex = DUPLEX_FULL;
1229 if (amd_xgbe_phy_in_kr_mode(phydev)) {
1230 phydev->speed = SPEED_10000;
1232 switch (priv->speed_set) {
1233 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1234 phydev->speed = SPEED_1000;
1237 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1238 phydev->speed = SPEED_2500;
1242 phydev->duplex = DUPLEX_FULL;
1244 phydev->asym_pause = 0;
1250 static int amd_xgbe_phy_suspend(struct phy_device *phydev)
1254 mutex_lock(&phydev->lock);
1256 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1260 ret |= MDIO_CTRL1_LPOWER;
1261 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1266 mutex_unlock(&phydev->lock);
1271 static int amd_xgbe_phy_resume(struct phy_device *phydev)
1275 mutex_lock(&phydev->lock);
1277 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1281 ret &= ~MDIO_CTRL1_LPOWER;
1282 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1287 mutex_unlock(&phydev->lock);
1292 static int amd_xgbe_phy_probe(struct phy_device *phydev)
1294 struct amd_xgbe_phy_priv *priv;
1295 struct platform_device *pdev;
1298 const __be32 *property;
1299 unsigned int speed_set;
1302 if (!phydev->dev.of_node)
1305 pdev = of_find_device_by_node(phydev->dev.of_node);
1310 wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
1316 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1324 priv->phydev = phydev;
1326 /* Get the device mmio areas */
1327 priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1328 priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
1329 if (IS_ERR(priv->rxtx_regs)) {
1330 dev_err(dev, "rxtx ioremap failed\n");
1331 ret = PTR_ERR(priv->rxtx_regs);
1335 priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1336 priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
1337 if (IS_ERR(priv->sir0_regs)) {
1338 dev_err(dev, "sir0 ioremap failed\n");
1339 ret = PTR_ERR(priv->sir0_regs);
1343 priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1344 priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
1345 if (IS_ERR(priv->sir1_regs)) {
1346 dev_err(dev, "sir1 ioremap failed\n");
1347 ret = PTR_ERR(priv->sir1_regs);
1351 /* Get the device speed set property */
1353 property = of_get_property(dev->of_node, XGBE_PHY_SPEEDSET_PROPERTY,
1356 speed_set = be32_to_cpu(*property);
1358 switch (speed_set) {
1360 priv->speed_set = AMD_XGBE_PHY_SPEEDSET_1000_10000;
1363 priv->speed_set = AMD_XGBE_PHY_SPEEDSET_2500_10000;
1366 dev_err(dev, "invalid amd,speed-set property\n");
1373 mutex_init(&priv->an_mutex);
1374 INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
1375 priv->an_workqueue = create_singlethread_workqueue(wq_name);
1376 if (!priv->an_workqueue) {
1381 phydev->priv = priv;
1389 devm_iounmap(dev, priv->sir1_regs);
1390 devm_release_mem_region(dev, priv->sir1_res->start,
1391 resource_size(priv->sir1_res));
1394 devm_iounmap(dev, priv->sir0_regs);
1395 devm_release_mem_region(dev, priv->sir0_res->start,
1396 resource_size(priv->sir0_res));
1399 devm_iounmap(dev, priv->rxtx_regs);
1400 devm_release_mem_region(dev, priv->rxtx_res->start,
1401 resource_size(priv->rxtx_res));
1404 devm_kfree(dev, priv);
1415 static void amd_xgbe_phy_remove(struct phy_device *phydev)
1417 struct amd_xgbe_phy_priv *priv = phydev->priv;
1418 struct device *dev = priv->dev;
1420 /* Stop any in process auto-negotiation */
1421 mutex_lock(&priv->an_mutex);
1422 priv->an_state = AMD_XGBE_AN_EXIT;
1423 mutex_unlock(&priv->an_mutex);
1425 flush_workqueue(priv->an_workqueue);
1426 destroy_workqueue(priv->an_workqueue);
1428 /* Release resources */
1429 devm_iounmap(dev, priv->sir1_regs);
1430 devm_release_mem_region(dev, priv->sir1_res->start,
1431 resource_size(priv->sir1_res));
1433 devm_iounmap(dev, priv->sir0_regs);
1434 devm_release_mem_region(dev, priv->sir0_res->start,
1435 resource_size(priv->sir0_res));
1437 devm_iounmap(dev, priv->rxtx_regs);
1438 devm_release_mem_region(dev, priv->rxtx_res->start,
1439 resource_size(priv->rxtx_res));
1441 devm_kfree(dev, priv);
1444 static int amd_xgbe_match_phy_device(struct phy_device *phydev)
1446 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
1449 static struct phy_driver amd_xgbe_phy_driver[] = {
1451 .phy_id = XGBE_PHY_ID,
1452 .phy_id_mask = XGBE_PHY_MASK,
1453 .name = "AMD XGBE PHY",
1455 .probe = amd_xgbe_phy_probe,
1456 .remove = amd_xgbe_phy_remove,
1457 .soft_reset = amd_xgbe_phy_soft_reset,
1458 .config_init = amd_xgbe_phy_config_init,
1459 .suspend = amd_xgbe_phy_suspend,
1460 .resume = amd_xgbe_phy_resume,
1461 .config_aneg = amd_xgbe_phy_config_aneg,
1462 .aneg_done = amd_xgbe_phy_aneg_done,
1463 .read_status = amd_xgbe_phy_read_status,
1464 .match_phy_device = amd_xgbe_match_phy_device,
1466 .owner = THIS_MODULE,
1471 static int __init amd_xgbe_phy_init(void)
1473 return phy_drivers_register(amd_xgbe_phy_driver,
1474 ARRAY_SIZE(amd_xgbe_phy_driver));
1477 static void __exit amd_xgbe_phy_exit(void)
1479 phy_drivers_unregister(amd_xgbe_phy_driver,
1480 ARRAY_SIZE(amd_xgbe_phy_driver));
1483 module_init(amd_xgbe_phy_init);
1484 module_exit(amd_xgbe_phy_exit);
1486 static struct mdio_device_id __maybe_unused amd_xgbe_phy_ids[] = {
1487 { XGBE_PHY_ID, XGBE_PHY_MASK },
1490 MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids);