2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include "bcm-phy-lib.h"
15 #include <linux/brcmphy.h>
16 #include <linux/export.h>
17 #include <linux/mdio.h>
18 #include <linux/module.h>
19 #include <linux/phy.h>
20 #include <linux/ethtool.h>
22 #define MII_BCM_CHANNEL_WIDTH 0x2000
23 #define BCM_CL45VEN_EEE_ADV 0x3c
25 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
29 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
33 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
35 EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
37 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
41 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
45 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
47 /* Restore default value. It's O.K. if this write fails. */
48 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
52 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
54 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
56 /* The register must be written to both the Shadow Register Select and
57 * the Shadow Read Register Selector
59 phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
60 regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
61 return phy_read(phydev, MII_BCM54XX_AUX_CTL);
63 EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
65 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
67 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
69 EXPORT_SYMBOL(bcm54xx_auxctl_write);
71 int bcm_phy_write_misc(struct phy_device *phydev,
72 u16 reg, u16 chl, u16 val)
77 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
78 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
82 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
83 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
84 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
88 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
89 rc = bcm_phy_write_exp(phydev, tmp, val);
93 EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
95 int bcm_phy_read_misc(struct phy_device *phydev,
101 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
102 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
106 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
107 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
108 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
112 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
113 rc = bcm_phy_read_exp(phydev, tmp);
117 EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
119 int bcm_phy_ack_intr(struct phy_device *phydev)
123 /* Clear pending interrupts. */
124 reg = phy_read(phydev, MII_BCM54XX_ISR);
130 EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
132 int bcm_phy_config_intr(struct phy_device *phydev)
136 reg = phy_read(phydev, MII_BCM54XX_ECR);
140 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
141 reg &= ~MII_BCM54XX_ECR_IM;
143 reg |= MII_BCM54XX_ECR_IM;
145 return phy_write(phydev, MII_BCM54XX_ECR, reg);
147 EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
149 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
151 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
152 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
154 EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
156 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
159 return phy_write(phydev, MII_BCM54XX_SHD,
160 MII_BCM54XX_SHD_WRITE |
161 MII_BCM54XX_SHD_VAL(shadow) |
162 MII_BCM54XX_SHD_DATA(val));
164 EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
166 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
171 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
175 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
176 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
179 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
184 val &= BCM_APD_CLR_MASK;
186 if (phydev->autoneg == AUTONEG_ENABLE)
187 val |= BCM54XX_SHD_APD_EN;
189 val |= BCM_NO_ANEG_APD_EN;
191 /* Enable energy detect single link pulse for easy wakeup */
192 val |= BCM_APD_SINGLELP_EN;
194 /* Enable Auto Power-Down (APD) for the PHY */
195 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
197 EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
199 int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
203 /* Enable EEE at PHY level */
204 val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
210 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
212 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
214 phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
215 MDIO_MMD_AN, (u32)val);
218 val = phy_read_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,
224 val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
226 val &= ~(MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
228 phy_write_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,
229 MDIO_MMD_AN, (u32)val);
233 EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
235 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
239 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
243 /* Check if wirespeed is enabled or not */
244 if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
245 *count = DOWNSHIFT_DEV_DISABLE;
249 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
253 /* Downgrade after one link attempt */
254 if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
257 /* Downgrade after configured retry count */
258 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
259 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
260 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
265 EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
267 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
269 int val = 0, ret = 0;
271 /* Range check the number given */
272 if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
273 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
274 count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
278 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
282 /* Se the write enable bit */
283 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
285 if (count == DOWNSHIFT_DEV_DISABLE) {
286 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
287 return bcm54xx_auxctl_write(phydev,
288 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
291 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
292 ret = bcm54xx_auxctl_write(phydev,
293 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
299 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
300 val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
301 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
302 BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
306 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
308 case DOWNSHIFT_DEV_DEFAULT_COUNT:
309 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
312 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
313 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
317 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
319 EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
321 struct bcm_phy_hw_stat {
328 /* Counters freeze at either 0xffff or 0xff, better than nothing */
329 static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
330 { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
331 { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
332 { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
333 { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
334 { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
337 int bcm_phy_get_sset_count(struct phy_device *phydev)
339 return ARRAY_SIZE(bcm_phy_hw_stats);
341 EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
343 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
347 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
348 memcpy(data + i * ETH_GSTRING_LEN,
349 bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
351 EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
354 #define UINT64_MAX (u64)(~((u64)0))
357 /* Caller is supposed to provide appropriate storage for the library code to
358 * access the shadow copy
360 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
363 struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
367 val = phy_read(phydev, stat.reg);
372 val = val & ((1 << stat.bits) - 1);
380 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
381 struct ethtool_stats *stats, u64 *data)
385 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
386 data[i] = bcm_phy_get_stat(phydev, shadow, i);
388 EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
390 MODULE_DESCRIPTION("Broadcom PHY Library");
391 MODULE_LICENSE("GPL v2");
392 MODULE_AUTHOR("Broadcom Corporation");