2 * Driver for ICPlus PHYs
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/errno.h>
15 #include <linux/unistd.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/netdevice.h>
20 #include <linux/etherdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/spinlock.h>
24 #include <linux/module.h>
25 #include <linux/mii.h>
26 #include <linux/ethtool.h>
27 #include <linux/phy.h>
31 #include <asm/uaccess.h>
33 MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
34 MODULE_AUTHOR("Michael Barkowski");
35 MODULE_LICENSE("GPL");
37 /* IP101A/G - IP1001 */
38 #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
39 #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
40 #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
41 #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
42 #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
43 #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
45 static int ip175c_config_init(struct phy_device *phydev)
48 static int full_reset_performed = 0;
50 if (full_reset_performed == 0) {
53 err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
57 /* ensure no bus delays overlap reset period */
58 err = mdiobus_read(phydev->bus, 30, 0);
60 /* data sheet specifies reset period is 2 msec */
63 /* enable IP175C mode */
64 err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
68 /* Set MII0 speed and duplex (in PHY mode) */
69 err = mdiobus_write(phydev->bus, 29, 22, 0x420);
73 /* reset switch ports */
74 for (i = 0; i < 5; i++) {
75 err = mdiobus_write(phydev->bus, i,
76 MII_BMCR, BMCR_RESET);
81 for (i = 0; i < 5; i++)
82 err = mdiobus_read(phydev->bus, i, MII_BMCR);
86 full_reset_performed = 1;
89 if (phydev->addr != 4) {
90 phydev->state = PHY_RUNNING;
91 phydev->speed = SPEED_100;
92 phydev->duplex = DUPLEX_FULL;
94 netif_carrier_on(phydev->attached_dev);
100 static int ip1xx_reset(struct phy_device *phydev)
104 /* Software Reset PHY */
105 bmcr = phy_read(phydev, MII_BMCR);
109 bmcr = phy_write(phydev, MII_BMCR, bmcr);
114 bmcr = phy_read(phydev, MII_BMCR);
117 } while (bmcr & BMCR_RESET);
122 static int ip1001_config_init(struct phy_device *phydev)
126 c = ip1xx_reset(phydev);
130 /* Enable Auto Power Saving mode */
131 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
135 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
139 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
140 /* Additional delay (2ns) used to adjust RX clock phase
141 * at RGMII interface */
142 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
146 c |= IP1001_PHASE_SEL_MASK;
147 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
155 static int ip101a_g_config_init(struct phy_device *phydev)
159 c = ip1xx_reset(phydev);
163 /* Enable Auto Power Saving mode */
164 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
165 c |= IP101A_G_APS_ON;
167 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
170 static int ip175c_read_status(struct phy_device *phydev)
172 if (phydev->addr == 4) /* WAN port */
173 genphy_read_status(phydev);
175 /* Don't need to read status for switch ports */
176 phydev->irq = PHY_IGNORE_INTERRUPT;
181 static int ip175c_config_aneg(struct phy_device *phydev)
183 if (phydev->addr == 4) /* WAN port */
184 genphy_config_aneg(phydev);
189 static int ip101a_g_ack_interrupt(struct phy_device *phydev)
191 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
198 static struct phy_driver ip175c_driver = {
199 .phy_id = 0x02430d80,
200 .name = "ICPlus IP175C",
201 .phy_id_mask = 0x0ffffff0,
202 .features = PHY_BASIC_FEATURES,
203 .config_init = &ip175c_config_init,
204 .config_aneg = &ip175c_config_aneg,
205 .read_status = &ip175c_read_status,
206 .suspend = genphy_suspend,
207 .resume = genphy_resume,
208 .driver = { .owner = THIS_MODULE,},
211 static struct phy_driver ip1001_driver = {
212 .phy_id = 0x02430d90,
213 .name = "ICPlus IP1001",
214 .phy_id_mask = 0x0ffffff0,
215 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
216 SUPPORTED_Asym_Pause,
217 .config_init = &ip1001_config_init,
218 .config_aneg = &genphy_config_aneg,
219 .read_status = &genphy_read_status,
220 .suspend = genphy_suspend,
221 .resume = genphy_resume,
222 .driver = { .owner = THIS_MODULE,},
225 static struct phy_driver ip101a_g_driver = {
226 .phy_id = 0x02430c54,
227 .name = "ICPlus IP101A/G",
228 .phy_id_mask = 0x0ffffff0,
229 .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
230 SUPPORTED_Asym_Pause,
231 .flags = PHY_HAS_INTERRUPT,
232 .ack_interrupt = ip101a_g_ack_interrupt,
233 .config_init = &ip101a_g_config_init,
234 .config_aneg = &genphy_config_aneg,
235 .read_status = &genphy_read_status,
236 .suspend = genphy_suspend,
237 .resume = genphy_resume,
238 .driver = { .owner = THIS_MODULE,},
241 static int __init icplus_init(void)
245 ret = phy_driver_register(&ip1001_driver);
249 ret = phy_driver_register(&ip101a_g_driver);
253 return phy_driver_register(&ip175c_driver);
256 static void __exit icplus_exit(void)
258 phy_driver_unregister(&ip1001_driver);
259 phy_driver_unregister(&ip101a_g_driver);
260 phy_driver_unregister(&ip175c_driver);
263 module_init(icplus_init);
264 module_exit(icplus_exit);
266 static struct mdio_device_id __maybe_unused icplus_tbl[] = {
267 { 0x02430d80, 0x0ffffff0 },
268 { 0x02430d90, 0x0ffffff0 },
269 { 0x02430c54, 0x0ffffff0 },
273 MODULE_DEVICE_TABLE(mdio, icplus_tbl);