drivers/net/phy/intel-xway.c

   1 /*
   2  * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
   3  * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/mdio.h>
  17 #include <linux/module.h>
  18 #include <linux/phy.h>
  19 #include <linux/of.h>
  20
  21 #define XWAY_MDIO_IMASK                 0x19    /* interrupt mask */
  22 #define XWAY_MDIO_ISTAT                 0x1A    /* interrupt status */
  23
  24 #define XWAY_MDIO_INIT_WOL              BIT(15) /* Wake-On-LAN */
  25 #define XWAY_MDIO_INIT_MSRE             BIT(14)
  26 #define XWAY_MDIO_INIT_NPRX             BIT(13)
  27 #define XWAY_MDIO_INIT_NPTX             BIT(12)
  28 #define XWAY_MDIO_INIT_ANE              BIT(11) /* Auto-Neg error */
  29 #define XWAY_MDIO_INIT_ANC              BIT(10) /* Auto-Neg complete */
  30 #define XWAY_MDIO_INIT_ADSC             BIT(5)  /* Link auto-downspeed detect */
  31 #define XWAY_MDIO_INIT_MPIPC            BIT(4)
  32 #define XWAY_MDIO_INIT_MDIXC            BIT(3)
  33 #define XWAY_MDIO_INIT_DXMC             BIT(2)  /* Duplex mode change */
  34 #define XWAY_MDIO_INIT_LSPC             BIT(1)  /* Link speed change */
  35 #define XWAY_MDIO_INIT_LSTC             BIT(0)  /* Link state change */
  36 #define XWAY_MDIO_INIT_MASK             (XWAY_MDIO_INIT_LSTC | \
  37                                          XWAY_MDIO_INIT_ADSC)
  38
  39 #define ADVERTISED_MPD                  BIT(10) /* Multi-port device */
  40
  41 /* LED Configuration */
  42 #define XWAY_MMD_LEDCH                  0x01E0
  43 /* Inverse of SCAN Function */
  44 #define  XWAY_MMD_LEDCH_NACS_NONE       0x0000
  45 #define  XWAY_MMD_LEDCH_NACS_LINK       0x0001
  46 #define  XWAY_MMD_LEDCH_NACS_PDOWN      0x0002
  47 #define  XWAY_MMD_LEDCH_NACS_EEE        0x0003
  48 #define  XWAY_MMD_LEDCH_NACS_ANEG       0x0004
  49 #define  XWAY_MMD_LEDCH_NACS_ABIST      0x0005
  50 #define  XWAY_MMD_LEDCH_NACS_CDIAG      0x0006
  51 #define  XWAY_MMD_LEDCH_NACS_TEST       0x0007
  52 /* Slow Blink Frequency */
  53 #define  XWAY_MMD_LEDCH_SBF_F02HZ       0x0000
  54 #define  XWAY_MMD_LEDCH_SBF_F04HZ       0x0010
  55 #define  XWAY_MMD_LEDCH_SBF_F08HZ       0x0020
  56 #define  XWAY_MMD_LEDCH_SBF_F16HZ       0x0030
  57 /* Fast Blink Frequency */
  58 #define  XWAY_MMD_LEDCH_FBF_F02HZ       0x0000
  59 #define  XWAY_MMD_LEDCH_FBF_F04HZ       0x0040
  60 #define  XWAY_MMD_LEDCH_FBF_F08HZ       0x0080
  61 #define  XWAY_MMD_LEDCH_FBF_F16HZ       0x00C0
  62 /* LED Configuration */
  63 #define XWAY_MMD_LEDCL                  0x01E1
  64 /* Complex Blinking Configuration */
  65 #define  XWAY_MMD_LEDCH_CBLINK_NONE     0x0000
  66 #define  XWAY_MMD_LEDCH_CBLINK_LINK     0x0001
  67 #define  XWAY_MMD_LEDCH_CBLINK_PDOWN    0x0002
  68 #define  XWAY_MMD_LEDCH_CBLINK_EEE      0x0003
  69 #define  XWAY_MMD_LEDCH_CBLINK_ANEG     0x0004
  70 #define  XWAY_MMD_LEDCH_CBLINK_ABIST    0x0005
  71 #define  XWAY_MMD_LEDCH_CBLINK_CDIAG    0x0006
  72 #define  XWAY_MMD_LEDCH_CBLINK_TEST     0x0007
  73 /* Complex SCAN Configuration */
  74 #define  XWAY_MMD_LEDCH_SCAN_NONE       0x0000
  75 #define  XWAY_MMD_LEDCH_SCAN_LINK       0x0010
  76 #define  XWAY_MMD_LEDCH_SCAN_PDOWN      0x0020
  77 #define  XWAY_MMD_LEDCH_SCAN_EEE        0x0030
  78 #define  XWAY_MMD_LEDCH_SCAN_ANEG       0x0040
  79 #define  XWAY_MMD_LEDCH_SCAN_ABIST      0x0050
  80 #define  XWAY_MMD_LEDCH_SCAN_CDIAG      0x0060
  81 #define  XWAY_MMD_LEDCH_SCAN_TEST       0x0070
  82 /* Configuration for LED Pin x */
  83 #define XWAY_MMD_LED0H                  0x01E2
  84 /* Fast Blinking Configuration */
  85 #define  XWAY_MMD_LEDxH_BLINKF_MASK     0x000F
  86 #define  XWAY_MMD_LEDxH_BLINKF_NONE     0x0000
  87 #define  XWAY_MMD_LEDxH_BLINKF_LINK10   0x0001
  88 #define  XWAY_MMD_LEDxH_BLINKF_LINK100  0x0002
  89 #define  XWAY_MMD_LEDxH_BLINKF_LINK10X  0x0003
  90 #define  XWAY_MMD_LEDxH_BLINKF_LINK1000 0x0004
  91 #define  XWAY_MMD_LEDxH_BLINKF_LINK10_0 0x0005
  92 #define  XWAY_MMD_LEDxH_BLINKF_LINK100X 0x0006
  93 #define  XWAY_MMD_LEDxH_BLINKF_LINK10XX 0x0007
  94 #define  XWAY_MMD_LEDxH_BLINKF_PDOWN    0x0008
  95 #define  XWAY_MMD_LEDxH_BLINKF_EEE      0x0009
  96 #define  XWAY_MMD_LEDxH_BLINKF_ANEG     0x000A
  97 #define  XWAY_MMD_LEDxH_BLINKF_ABIST    0x000B
  98 #define  XWAY_MMD_LEDxH_BLINKF_CDIAG    0x000C
  99 /* Constant On Configuration */
 100 #define  XWAY_MMD_LEDxH_CON_MASK        0x00F0
 101 #define  XWAY_MMD_LEDxH_CON_NONE        0x0000
 102 #define  XWAY_MMD_LEDxH_CON_LINK10      0x0010
 103 #define  XWAY_MMD_LEDxH_CON_LINK100     0x0020
 104 #define  XWAY_MMD_LEDxH_CON_LINK10X     0x0030
 105 #define  XWAY_MMD_LEDxH_CON_LINK1000    0x0040
 106 #define  XWAY_MMD_LEDxH_CON_LINK10_0    0x0050
 107 #define  XWAY_MMD_LEDxH_CON_LINK100X    0x0060
 108 #define  XWAY_MMD_LEDxH_CON_LINK10XX    0x0070
 109 #define  XWAY_MMD_LEDxH_CON_PDOWN       0x0080
 110 #define  XWAY_MMD_LEDxH_CON_EEE         0x0090
 111 #define  XWAY_MMD_LEDxH_CON_ANEG        0x00A0
 112 #define  XWAY_MMD_LEDxH_CON_ABIST       0x00B0
 113 #define  XWAY_MMD_LEDxH_CON_CDIAG       0x00C0
 114 #define  XWAY_MMD_LEDxH_CON_COPPER      0x00D0
 115 #define  XWAY_MMD_LEDxH_CON_FIBER       0x00E0
 116 /* Configuration for LED Pin x */
 117 #define XWAY_MMD_LED0L                  0x01E3
 118 /* Pulsing Configuration */
 119 #define  XWAY_MMD_LEDxL_PULSE_MASK      0x000F
 120 #define  XWAY_MMD_LEDxL_PULSE_NONE      0x0000
 121 #define  XWAY_MMD_LEDxL_PULSE_TXACT     0x0001
 122 #define  XWAY_MMD_LEDxL_PULSE_RXACT     0x0002
 123 #define  XWAY_MMD_LEDxL_PULSE_COL       0x0004
 124 /* Slow Blinking Configuration */
 125 #define  XWAY_MMD_LEDxL_BLINKS_MASK     0x00F0
 126 #define  XWAY_MMD_LEDxL_BLINKS_NONE     0x0000
 127 #define  XWAY_MMD_LEDxL_BLINKS_LINK10   0x0010
 128 #define  XWAY_MMD_LEDxL_BLINKS_LINK100  0x0020
 129 #define  XWAY_MMD_LEDxL_BLINKS_LINK10X  0x0030
 130 #define  XWAY_MMD_LEDxL_BLINKS_LINK1000 0x0040
 131 #define  XWAY_MMD_LEDxL_BLINKS_LINK10_0 0x0050
 132 #define  XWAY_MMD_LEDxL_BLINKS_LINK100X 0x0060
 133 #define  XWAY_MMD_LEDxL_BLINKS_LINK10XX 0x0070
 134 #define  XWAY_MMD_LEDxL_BLINKS_PDOWN    0x0080
 135 #define  XWAY_MMD_LEDxL_BLINKS_EEE      0x0090
 136 #define  XWAY_MMD_LEDxL_BLINKS_ANEG     0x00A0
 137 #define  XWAY_MMD_LEDxL_BLINKS_ABIST    0x00B0
 138 #define  XWAY_MMD_LEDxL_BLINKS_CDIAG    0x00C0
 139 #define XWAY_MMD_LED1H                  0x01E4
 140 #define XWAY_MMD_LED1L                  0x01E5
 141 #define XWAY_MMD_LED2H                  0x01E6
 142 #define XWAY_MMD_LED2L                  0x01E7
 143 #define XWAY_MMD_LED3H                  0x01E8
 144 #define XWAY_MMD_LED3L                  0x01E9
 145
 146 #define PHY_ID_PHY11G_1_3               0x030260D1
 147 #define PHY_ID_PHY22F_1_3               0x030260E1
 148 #define PHY_ID_PHY11G_1_4               0xD565A400
 149 #define PHY_ID_PHY22F_1_4               0xD565A410
 150 #define PHY_ID_PHY11G_1_5               0xD565A401
 151 #define PHY_ID_PHY22F_1_5               0xD565A411
 152 #define PHY_ID_PHY11G_VR9               0xD565A409
 153 #define PHY_ID_PHY22F_VR9               0xD565A419
 154
 155 static int xway_gphy_config_init(struct phy_device *phydev)
 156 {
 157         int err;
 158         u32 ledxh;
 159         u32 ledxl;
 160
 161         /* Mask all interrupts */
 162         err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
 163         if (err)
 164                 return err;
 165
 166         /* Clear all pending interrupts */
 167         phy_read(phydev, XWAY_MDIO_ISTAT);
 168
 169         phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCH, MDIO_MMD_VEND2,
 170                                XWAY_MMD_LEDCH_NACS_NONE |
 171                                XWAY_MMD_LEDCH_SBF_F02HZ |
 172                                XWAY_MMD_LEDCH_FBF_F16HZ);
 173         phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCL, MDIO_MMD_VEND2,
 174                                XWAY_MMD_LEDCH_CBLINK_NONE |
 175                                XWAY_MMD_LEDCH_SCAN_NONE);
 176
 177         /**
 178          * In most cases only one LED is connected to this phy, so
 179          * configure them all to constant on and pulse mode. LED3 is
 180          * only available in some packages, leave it in its reset
 181          * configuration.
 182          */
 183         ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX;
 184         ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT |
 185                 XWAY_MMD_LEDxL_BLINKS_NONE;
 186         phy_write_mmd_indirect(phydev, XWAY_MMD_LED0H, MDIO_MMD_VEND2, ledxh);
 187         phy_write_mmd_indirect(phydev, XWAY_MMD_LED0L, MDIO_MMD_VEND2, ledxl);
 188         phy_write_mmd_indirect(phydev, XWAY_MMD_LED1H, MDIO_MMD_VEND2, ledxh);
 189         phy_write_mmd_indirect(phydev, XWAY_MMD_LED1L, MDIO_MMD_VEND2, ledxl);
 190         phy_write_mmd_indirect(phydev, XWAY_MMD_LED2H, MDIO_MMD_VEND2, ledxh);
 191         phy_write_mmd_indirect(phydev, XWAY_MMD_LED2L, MDIO_MMD_VEND2, ledxl);
 192
 193         return 0;
 194 }
 195
 196 static int xway_gphy14_config_aneg(struct phy_device *phydev)
 197 {
 198         int reg, err;
 199
 200         /* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */
 201         /* This is a workaround for an errata in rev < 1.5 devices */
 202         reg = phy_read(phydev, MII_CTRL1000);
 203         reg |= ADVERTISED_MPD;
 204         err = phy_write(phydev, MII_CTRL1000, reg);
 205         if (err)
 206                 return err;
 207
 208         return genphy_config_aneg(phydev);
 209 }
 210
 211 static int xway_gphy_ack_interrupt(struct phy_device *phydev)
 212 {
 213         int reg;
 214
 215         reg = phy_read(phydev, XWAY_MDIO_ISTAT);
 216         return (reg < 0) ? reg : 0;
 217 }
 218
 219 static int xway_gphy_did_interrupt(struct phy_device *phydev)
 220 {
 221         int reg;
 222
 223         reg = phy_read(phydev, XWAY_MDIO_ISTAT);
 224         return reg & XWAY_MDIO_INIT_MASK;
 225 }
 226
 227 static int xway_gphy_config_intr(struct phy_device *phydev)
 228 {
 229         u16 mask = 0;
 230
 231         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 232                 mask = XWAY_MDIO_INIT_MASK;
 233
 234         return phy_write(phydev, XWAY_MDIO_IMASK, mask);
 235 }
 236
 237 static struct phy_driver xway_gphy[] = {
 238         {
 239                 .phy_id         = PHY_ID_PHY11G_1_3,
 240                 .phy_id_mask    = 0xffffffff,
 241                 .name           = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3",
 242                 .features       = PHY_GBIT_FEATURES,
 243                 .flags          = PHY_HAS_INTERRUPT,
 244                 .config_init    = xway_gphy_config_init,
 245                 .config_aneg    = xway_gphy14_config_aneg,
 246                 .read_status    = genphy_read_status,
 247                 .ack_interrupt  = xway_gphy_ack_interrupt,
 248                 .did_interrupt  = xway_gphy_did_interrupt,
 249                 .config_intr    = xway_gphy_config_intr,
 250                 .suspend        = genphy_suspend,
 251                 .resume         = genphy_resume,
 252         }, {
 253                 .phy_id         = PHY_ID_PHY22F_1_3,
 254                 .phy_id_mask    = 0xffffffff,
 255                 .name           = "Intel XWAY PHY22F (PEF 7061) v1.3",
 256                 .features       = PHY_BASIC_FEATURES,
 257                 .flags          = PHY_HAS_INTERRUPT,
 258                 .config_init    = xway_gphy_config_init,
 259                 .config_aneg    = xway_gphy14_config_aneg,
 260                 .read_status    = genphy_read_status,
 261                 .ack_interrupt  = xway_gphy_ack_interrupt,
 262                 .did_interrupt  = xway_gphy_did_interrupt,
 263                 .config_intr    = xway_gphy_config_intr,
 264                 .suspend        = genphy_suspend,
 265                 .resume         = genphy_resume,
 266         }, {
 267                 .phy_id         = PHY_ID_PHY11G_1_4,
 268                 .phy_id_mask    = 0xffffffff,
 269                 .name           = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4",
 270                 .features       = PHY_GBIT_FEATURES,
 271                 .flags          = PHY_HAS_INTERRUPT,
 272                 .config_init    = xway_gphy_config_init,
 273                 .config_aneg    = xway_gphy14_config_aneg,
 274                 .read_status    = genphy_read_status,
 275                 .ack_interrupt  = xway_gphy_ack_interrupt,
 276                 .did_interrupt  = xway_gphy_did_interrupt,
 277                 .config_intr    = xway_gphy_config_intr,
 278                 .suspend        = genphy_suspend,
 279                 .resume         = genphy_resume,
 280         }, {
 281                 .phy_id         = PHY_ID_PHY22F_1_4,
 282                 .phy_id_mask    = 0xffffffff,
 283                 .name           = "Intel XWAY PHY22F (PEF 7061) v1.4",
 284                 .features       = PHY_BASIC_FEATURES,
 285                 .flags          = PHY_HAS_INTERRUPT,
 286                 .config_init    = xway_gphy_config_init,
 287                 .config_aneg    = xway_gphy14_config_aneg,
 288                 .read_status    = genphy_read_status,
 289                 .ack_interrupt  = xway_gphy_ack_interrupt,
 290                 .did_interrupt  = xway_gphy_did_interrupt,
 291                 .config_intr    = xway_gphy_config_intr,
 292                 .suspend        = genphy_suspend,
 293                 .resume         = genphy_resume,
 294         }, {
 295                 .phy_id         = PHY_ID_PHY11G_1_5,
 296                 .phy_id_mask    = 0xffffffff,
 297                 .name           = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6",
 298                 .features       = PHY_GBIT_FEATURES,
 299                 .flags          = PHY_HAS_INTERRUPT,
 300                 .config_init    = xway_gphy_config_init,
 301                 .config_aneg    = genphy_config_aneg,
 302                 .read_status    = genphy_read_status,
 303                 .ack_interrupt  = xway_gphy_ack_interrupt,
 304                 .did_interrupt  = xway_gphy_did_interrupt,
 305                 .config_intr    = xway_gphy_config_intr,
 306                 .suspend        = genphy_suspend,
 307                 .resume         = genphy_resume,
 308         }, {
 309                 .phy_id         = PHY_ID_PHY22F_1_5,
 310                 .phy_id_mask    = 0xffffffff,
 311                 .name           = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6",
 312                 .features       = PHY_BASIC_FEATURES,
 313                 .flags          = PHY_HAS_INTERRUPT,
 314                 .config_init    = xway_gphy_config_init,
 315                 .config_aneg    = genphy_config_aneg,
 316                 .read_status    = genphy_read_status,
 317                 .ack_interrupt  = xway_gphy_ack_interrupt,
 318                 .did_interrupt  = xway_gphy_did_interrupt,
 319                 .config_intr    = xway_gphy_config_intr,
 320                 .suspend        = genphy_suspend,
 321                 .resume         = genphy_resume,
 322         }, {
 323                 .phy_id         = PHY_ID_PHY11G_VR9,
 324                 .phy_id_mask    = 0xffffffff,
 325                 .name           = "Intel XWAY PHY11G (xRX integrated)",
 326                 .features       = PHY_GBIT_FEATURES,
 327                 .flags          = PHY_HAS_INTERRUPT,
 328                 .config_init    = xway_gphy_config_init,
 329                 .config_aneg    = genphy_config_aneg,
 330                 .read_status    = genphy_read_status,
 331                 .ack_interrupt  = xway_gphy_ack_interrupt,
 332                 .did_interrupt  = xway_gphy_did_interrupt,
 333                 .config_intr    = xway_gphy_config_intr,
 334                 .suspend        = genphy_suspend,
 335                 .resume         = genphy_resume,
 336         }, {
 337                 .phy_id         = PHY_ID_PHY22F_VR9,
 338                 .phy_id_mask    = 0xffffffff,
 339                 .name           = "Intel XWAY PHY22F (xRX integrated)",
 340                 .features       = PHY_BASIC_FEATURES,
 341                 .flags          = PHY_HAS_INTERRUPT,
 342                 .config_init    = xway_gphy_config_init,
 343                 .config_aneg    = genphy_config_aneg,
 344                 .read_status    = genphy_read_status,
 345                 .ack_interrupt  = xway_gphy_ack_interrupt,
 346                 .did_interrupt  = xway_gphy_did_interrupt,
 347                 .config_intr    = xway_gphy_config_intr,
 348                 .suspend        = genphy_suspend,
 349                 .resume         = genphy_resume,
 350         },
 351 };
 352 module_phy_driver(xway_gphy);
 353
 354 static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = {
 355         { PHY_ID_PHY11G_1_3, 0xffffffff },
 356         { PHY_ID_PHY22F_1_3, 0xffffffff },
 357         { PHY_ID_PHY11G_1_4, 0xffffffff },
 358         { PHY_ID_PHY22F_1_4, 0xffffffff },
 359         { PHY_ID_PHY11G_1_5, 0xffffffff },
 360         { PHY_ID_PHY22F_1_5, 0xffffffff },
 361         { PHY_ID_PHY11G_VR9, 0xffffffff },
 362         { PHY_ID_PHY22F_VR9, 0xffffffff },
 363         { }
 364 };
 365 MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl);
 366
 367 MODULE_DESCRIPTION("Intel XWAY PHY driver");
 368 MODULE_LICENSE("GPL");