2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/spinlock.h>
29 #include <linux/module.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/phy.h>
36 #include <asm/uaccess.h>
38 #define MII_M1011_IEVENT 0x13
39 #define MII_M1011_IEVENT_CLEAR 0x0000
41 #define MII_M1011_IMASK 0x12
42 #define MII_M1011_IMASK_INIT 0x6400
43 #define MII_M1011_IMASK_CLEAR 0x0000
45 #define MII_M1011_PHY_SCR 0x10
46 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
48 #define MII_M1145_PHY_EXT_CR 0x14
49 #define MII_M1145_RGMII_RX_DELAY 0x0080
50 #define MII_M1145_RGMII_TX_DELAY 0x0002
52 #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
54 #define MII_M1111_PHY_LED_CONTROL 0x18
55 #define MII_M1111_PHY_LED_DIRECT 0x4100
56 #define MII_M1111_PHY_LED_COMBINE 0x411c
57 #define MII_M1111_PHY_EXT_CR 0x14
58 #define MII_M1111_RX_DELAY 0x80
59 #define MII_M1111_TX_DELAY 0x2
60 #define MII_M1111_PHY_EXT_SR 0x1b
62 #define MII_M1111_HWCFG_MODE_MASK 0xf
63 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
64 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
65 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
66 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
67 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
69 #define MII_M1111_COPPER 0
70 #define MII_M1111_FIBER 1
72 #define MII_88E1121_PHY_LED_CTRL 16
73 #define MII_88E1121_PHY_LED_PAGE 3
74 #define MII_88E1121_PHY_LED_DEF 0x0030
75 #define MII_88E1121_PHY_PAGE 22
77 #define MII_M1011_PHY_STATUS 0x11
78 #define MII_M1011_PHY_STATUS_1000 0x8000
79 #define MII_M1011_PHY_STATUS_100 0x4000
80 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
81 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
82 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
83 #define MII_M1011_PHY_STATUS_LINK 0x0400
86 MODULE_DESCRIPTION("Marvell PHY driver");
87 MODULE_AUTHOR("Andy Fleming");
88 MODULE_LICENSE("GPL");
90 static int marvell_ack_interrupt(struct phy_device *phydev)
94 /* Clear the interrupts by reading the reg */
95 err = phy_read(phydev, MII_M1011_IEVENT);
103 static int marvell_config_intr(struct phy_device *phydev)
107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
108 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
110 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
115 static int marvell_config_aneg(struct phy_device *phydev)
119 /* The Marvell PHY has an errata which requires
120 * that certain registers get written in order
121 * to restart autonegotiation */
122 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
127 err = phy_write(phydev, 0x1d, 0x1f);
131 err = phy_write(phydev, 0x1e, 0x200c);
135 err = phy_write(phydev, 0x1d, 0x5);
139 err = phy_write(phydev, 0x1e, 0);
143 err = phy_write(phydev, 0x1e, 0x100);
147 err = phy_write(phydev, MII_M1011_PHY_SCR,
148 MII_M1011_PHY_SCR_AUTO_CROSS);
152 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
153 MII_M1111_PHY_LED_DIRECT);
157 err = genphy_config_aneg(phydev);
162 static int m88e1121_config_aneg(struct phy_device *phydev)
166 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
170 err = phy_write(phydev, MII_M1011_PHY_SCR,
171 MII_M1011_PHY_SCR_AUTO_CROSS);
175 temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
177 phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
178 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
179 phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
181 err = genphy_config_aneg(phydev);
186 static int m88e1111_config_init(struct phy_device *phydev)
191 /* Enable Fiber/Copper auto selection */
192 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
193 temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
194 phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
196 temp = phy_read(phydev, MII_BMCR);
198 phy_write(phydev, MII_BMCR, temp);
200 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
201 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
202 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
203 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
205 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
209 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
210 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
211 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
212 temp &= ~MII_M1111_TX_DELAY;
213 temp |= MII_M1111_RX_DELAY;
214 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
215 temp &= ~MII_M1111_RX_DELAY;
216 temp |= MII_M1111_TX_DELAY;
219 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
223 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
227 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
229 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
230 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
232 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
234 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
239 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
240 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
244 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
245 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
247 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
252 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
259 static int m88e1118_config_aneg(struct phy_device *phydev)
263 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
267 err = phy_write(phydev, MII_M1011_PHY_SCR,
268 MII_M1011_PHY_SCR_AUTO_CROSS);
272 err = genphy_config_aneg(phydev);
276 static int m88e1118_config_init(struct phy_device *phydev)
281 err = phy_write(phydev, 0x16, 0x0002);
285 /* Enable 1000 Mbit */
286 err = phy_write(phydev, 0x15, 0x1070);
291 err = phy_write(phydev, 0x16, 0x0003);
295 /* Adjust LED Control */
296 err = phy_write(phydev, 0x10, 0x021e);
301 err = phy_write(phydev, 0x16, 0x0);
305 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
312 static int m88e1145_config_init(struct phy_device *phydev)
316 /* Take care of errata E0 & E1 */
317 err = phy_write(phydev, 0x1d, 0x001b);
321 err = phy_write(phydev, 0x1e, 0x418f);
325 err = phy_write(phydev, 0x1d, 0x0016);
329 err = phy_write(phydev, 0x1e, 0xa2da);
333 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
334 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
338 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
340 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
344 if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
345 err = phy_write(phydev, 0x1d, 0x0012);
349 temp = phy_read(phydev, 0x1e);
354 temp |= 2 << 9; /* 36 ohm */
355 temp |= 2 << 6; /* 39 ohm */
357 err = phy_write(phydev, 0x1e, temp);
361 err = phy_write(phydev, 0x1d, 0x3);
365 err = phy_write(phydev, 0x1e, 0x8000);
374 /* marvell_read_status
376 * Generic status code does not detect Fiber correctly!
378 * Check the link, then figure out the current state
379 * by comparing what we advertise with what the link partner
380 * advertises. Start by checking the gigabit possibilities,
381 * then move on to 10/100.
383 static int marvell_read_status(struct phy_device *phydev)
390 /* Update the link, but return if there
392 err = genphy_update_link(phydev);
396 if (AUTONEG_ENABLE == phydev->autoneg) {
397 status = phy_read(phydev, MII_M1011_PHY_STATUS);
401 lpa = phy_read(phydev, MII_LPA);
405 adv = phy_read(phydev, MII_ADVERTISE);
411 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
412 phydev->duplex = DUPLEX_FULL;
414 phydev->duplex = DUPLEX_HALF;
416 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
417 phydev->pause = phydev->asym_pause = 0;
420 case MII_M1011_PHY_STATUS_1000:
421 phydev->speed = SPEED_1000;
424 case MII_M1011_PHY_STATUS_100:
425 phydev->speed = SPEED_100;
429 phydev->speed = SPEED_10;
433 if (phydev->duplex == DUPLEX_FULL) {
434 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
435 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
438 int bmcr = phy_read(phydev, MII_BMCR);
443 if (bmcr & BMCR_FULLDPLX)
444 phydev->duplex = DUPLEX_FULL;
446 phydev->duplex = DUPLEX_HALF;
448 if (bmcr & BMCR_SPEED1000)
449 phydev->speed = SPEED_1000;
450 else if (bmcr & BMCR_SPEED100)
451 phydev->speed = SPEED_100;
453 phydev->speed = SPEED_10;
455 phydev->pause = phydev->asym_pause = 0;
461 static int m88e1121_did_interrupt(struct phy_device *phydev)
465 imask = phy_read(phydev, MII_M1011_IEVENT);
467 if (imask & MII_M1011_IMASK_INIT)
473 static struct phy_driver marvell_drivers[] = {
475 .phy_id = 0x01410c60,
476 .phy_id_mask = 0xfffffff0,
477 .name = "Marvell 88E1101",
478 .features = PHY_GBIT_FEATURES,
479 .flags = PHY_HAS_INTERRUPT,
480 .config_aneg = &marvell_config_aneg,
481 .read_status = &genphy_read_status,
482 .ack_interrupt = &marvell_ack_interrupt,
483 .config_intr = &marvell_config_intr,
484 .driver = { .owner = THIS_MODULE },
487 .phy_id = 0x01410c90,
488 .phy_id_mask = 0xfffffff0,
489 .name = "Marvell 88E1112",
490 .features = PHY_GBIT_FEATURES,
491 .flags = PHY_HAS_INTERRUPT,
492 .config_init = &m88e1111_config_init,
493 .config_aneg = &marvell_config_aneg,
494 .read_status = &genphy_read_status,
495 .ack_interrupt = &marvell_ack_interrupt,
496 .config_intr = &marvell_config_intr,
497 .driver = { .owner = THIS_MODULE },
500 .phy_id = 0x01410cc0,
501 .phy_id_mask = 0xfffffff0,
502 .name = "Marvell 88E1111",
503 .features = PHY_GBIT_FEATURES,
504 .flags = PHY_HAS_INTERRUPT,
505 .config_init = &m88e1111_config_init,
506 .config_aneg = &marvell_config_aneg,
507 .read_status = &marvell_read_status,
508 .ack_interrupt = &marvell_ack_interrupt,
509 .config_intr = &marvell_config_intr,
510 .driver = { .owner = THIS_MODULE },
513 .phy_id = 0x01410e10,
514 .phy_id_mask = 0xfffffff0,
515 .name = "Marvell 88E1118",
516 .features = PHY_GBIT_FEATURES,
517 .flags = PHY_HAS_INTERRUPT,
518 .config_init = &m88e1118_config_init,
519 .config_aneg = &m88e1118_config_aneg,
520 .read_status = &genphy_read_status,
521 .ack_interrupt = &marvell_ack_interrupt,
522 .config_intr = &marvell_config_intr,
523 .driver = {.owner = THIS_MODULE,},
526 .phy_id = 0x01410cb0,
527 .phy_id_mask = 0xfffffff0,
528 .name = "Marvell 88E1121R",
529 .features = PHY_GBIT_FEATURES,
530 .flags = PHY_HAS_INTERRUPT,
531 .config_aneg = &m88e1121_config_aneg,
532 .read_status = &marvell_read_status,
533 .ack_interrupt = &marvell_ack_interrupt,
534 .config_intr = &marvell_config_intr,
535 .did_interrupt = &m88e1121_did_interrupt,
536 .driver = { .owner = THIS_MODULE },
539 .phy_id = 0x01410cd0,
540 .phy_id_mask = 0xfffffff0,
541 .name = "Marvell 88E1145",
542 .features = PHY_GBIT_FEATURES,
543 .flags = PHY_HAS_INTERRUPT,
544 .config_init = &m88e1145_config_init,
545 .config_aneg = &marvell_config_aneg,
546 .read_status = &genphy_read_status,
547 .ack_interrupt = &marvell_ack_interrupt,
548 .config_intr = &marvell_config_intr,
549 .driver = { .owner = THIS_MODULE },
552 .phy_id = 0x01410e30,
553 .phy_id_mask = 0xfffffff0,
554 .name = "Marvell 88E1240",
555 .features = PHY_GBIT_FEATURES,
556 .flags = PHY_HAS_INTERRUPT,
557 .config_init = &m88e1111_config_init,
558 .config_aneg = &marvell_config_aneg,
559 .read_status = &genphy_read_status,
560 .ack_interrupt = &marvell_ack_interrupt,
561 .config_intr = &marvell_config_intr,
562 .driver = { .owner = THIS_MODULE },
566 static int __init marvell_init(void)
571 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
572 ret = phy_driver_register(&marvell_drivers[i]);
576 phy_driver_unregister(&marvell_drivers[i]);
584 static void __exit marvell_exit(void)
588 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
589 phy_driver_unregister(&marvell_drivers[i]);
592 module_init(marvell_init);
593 module_exit(marvell_exit);