2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_MDI 0x0000
52 #define MII_M1011_PHY_SCR_MDI_X 0x0020
53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
56 #define MII_M1145_PHY_EXT_SR 0x1b
57 #define MII_M1145_PHY_EXT_CR 0x14
58 #define MII_M1145_RGMII_RX_DELAY 0x0080
59 #define MII_M1145_RGMII_TX_DELAY 0x0002
60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61 #define MII_M1145_HWCFG_MODE_MASK 0xf
62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1145_HWCFG_MODE_MASK 0xf
66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_RX_DELAY 0x80
73 #define MII_M1111_TX_DELAY 0x2
74 #define MII_M1111_PHY_EXT_SR 0x1b
76 #define MII_M1111_HWCFG_MODE_MASK 0xf
77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
84 #define MII_M1111_COPPER 0
85 #define MII_M1111_FIBER 1
87 #define MII_88E1121_PHY_MSCR_PAGE 2
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
93 #define MII_88E1318S_PHY_MSCR1_REG 16
94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
96 /* Copper Specific Interrupt Enable Register */
97 #define MII_88E1318S_PHY_CSIER 0x12
98 /* WOL Event Interrupt Enable */
99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
101 /* LED Timer Control Register */
102 #define MII_88E1318S_PHY_LED_PAGE 0x03
103 #define MII_88E1318S_PHY_LED_TCR 0x12
104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
108 /* Magic Packet MAC address registers */
109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
113 #define MII_88E1318S_PHY_WOL_PAGE 0x11
114 #define MII_88E1318S_PHY_WOL_CTRL 0x10
115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
118 #define MII_88E1121_PHY_LED_CTRL 16
119 #define MII_88E1121_PHY_LED_PAGE 3
120 #define MII_88E1121_PHY_LED_DEF 0x0030
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
130 #define MII_M1116R_CONTROL_REG_MAC 21
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
136 MODULE_DESCRIPTION("Marvell PHY driver");
137 MODULE_AUTHOR("Andy Fleming");
138 MODULE_LICENSE("GPL");
140 static int marvell_ack_interrupt(struct phy_device *phydev)
144 /* Clear the interrupts by reading the reg */
145 err = phy_read(phydev, MII_M1011_IEVENT);
153 static int marvell_config_intr(struct phy_device *phydev)
157 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
158 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
160 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
165 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
171 /* get the current settings */
172 reg = phy_read(phydev, MII_M1011_PHY_SCR);
177 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
180 val |= MII_M1011_PHY_SCR_MDI;
183 val |= MII_M1011_PHY_SCR_MDI_X;
185 case ETH_TP_MDI_AUTO:
186 case ETH_TP_MDI_INVALID:
188 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
193 /* Set the new polarity value in the register */
194 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
202 static int marvell_config_aneg(struct phy_device *phydev)
206 /* The Marvell PHY has an errata which requires
207 * that certain registers get written in order
208 * to restart autonegotiation */
209 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
214 err = phy_write(phydev, 0x1d, 0x1f);
218 err = phy_write(phydev, 0x1e, 0x200c);
222 err = phy_write(phydev, 0x1d, 0x5);
226 err = phy_write(phydev, 0x1e, 0);
230 err = phy_write(phydev, 0x1e, 0x100);
234 err = marvell_set_polarity(phydev, phydev->mdix);
238 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
239 MII_M1111_PHY_LED_DIRECT);
243 err = genphy_config_aneg(phydev);
247 if (phydev->autoneg != AUTONEG_ENABLE) {
251 * A write to speed/duplex bits (that is performed by
252 * genphy_config_aneg() call above) must be followed by
253 * a software reset. Otherwise, the write has no effect.
255 bmcr = phy_read(phydev, MII_BMCR);
259 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
267 #ifdef CONFIG_OF_MDIO
269 * Set and/or override some configuration registers based on the
270 * marvell,reg-init property stored in the of_node for the phydev.
272 * marvell,reg-init = <reg-page reg mask value>,...;
274 * There may be one or more sets of <reg-page reg mask value>:
276 * reg-page: which register bank to use.
278 * mask: if non-zero, ANDed with existing register value.
279 * value: ORed with the masked value and written to the regiser.
282 static int marvell_of_reg_init(struct phy_device *phydev)
285 int len, i, saved_page, current_page, page_changed, ret;
287 if (!phydev->dev.of_node)
290 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
291 if (!paddr || len < (4 * sizeof(*paddr)))
294 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
298 current_page = saved_page;
301 len /= sizeof(*paddr);
302 for (i = 0; i < len - 3; i += 4) {
303 u16 reg_page = be32_to_cpup(paddr + i);
304 u16 reg = be32_to_cpup(paddr + i + 1);
305 u16 mask = be32_to_cpup(paddr + i + 2);
306 u16 val_bits = be32_to_cpup(paddr + i + 3);
309 if (reg_page != current_page) {
310 current_page = reg_page;
312 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
319 val = phy_read(phydev, reg);
328 ret = phy_write(phydev, reg, val);
335 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
342 static int marvell_of_reg_init(struct phy_device *phydev)
346 #endif /* CONFIG_OF_MDIO */
348 static int m88e1121_config_aneg(struct phy_device *phydev)
350 int err, oldpage, mscr;
352 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
354 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
355 MII_88E1121_PHY_MSCR_PAGE);
359 if (phy_interface_is_rgmii(phydev)) {
361 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
362 MII_88E1121_PHY_MSCR_DELAY_MASK;
364 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
365 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
366 MII_88E1121_PHY_MSCR_TX_DELAY);
367 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
368 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
369 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
370 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
372 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
377 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
379 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
383 err = phy_write(phydev, MII_M1011_PHY_SCR,
384 MII_M1011_PHY_SCR_AUTO_CROSS);
388 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
390 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
391 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
392 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
394 err = genphy_config_aneg(phydev);
399 static int m88e1318_config_aneg(struct phy_device *phydev)
401 int err, oldpage, mscr;
403 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
405 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
406 MII_88E1121_PHY_MSCR_PAGE);
410 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
411 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
413 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
417 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
421 return m88e1121_config_aneg(phydev);
424 static int m88e1510_config_aneg(struct phy_device *phydev)
428 err = m88e1318_config_aneg(phydev);
432 return marvell_of_reg_init(phydev);
435 static int m88e1116r_config_init(struct phy_device *phydev)
440 temp = phy_read(phydev, MII_BMCR);
442 err = phy_write(phydev, MII_BMCR, temp);
448 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
452 temp = phy_read(phydev, MII_M1011_PHY_SCR);
453 temp |= (7 << 12); /* max number of gigabit attempts */
454 temp |= (1 << 11); /* enable downshift */
455 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
456 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
460 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
463 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
466 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
469 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
473 temp = phy_read(phydev, MII_BMCR);
475 err = phy_write(phydev, MII_BMCR, temp);
484 static int m88e3016_config_init(struct phy_device *phydev)
488 /* Enable Scrambler and Auto-Crossover */
489 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
493 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
494 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
496 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
503 static int m88e1111_config_init(struct phy_device *phydev)
508 if (phy_interface_is_rgmii(phydev)) {
510 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
514 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
515 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
516 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
517 temp &= ~MII_M1111_TX_DELAY;
518 temp |= MII_M1111_RX_DELAY;
519 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
520 temp &= ~MII_M1111_RX_DELAY;
521 temp |= MII_M1111_TX_DELAY;
524 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
528 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
532 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
534 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
535 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
537 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
539 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
544 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
545 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
549 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
550 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
551 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
553 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
557 /* make sure copper is selected */
558 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
562 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
568 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
569 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
572 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
573 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
577 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
580 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
581 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
582 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
587 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
591 temp = phy_read(phydev, MII_BMCR);
592 while (temp & BMCR_RESET);
594 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
597 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
598 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
599 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
604 err = marvell_of_reg_init(phydev);
608 return phy_write(phydev, MII_BMCR, BMCR_RESET);
611 static int m88e1118_config_aneg(struct phy_device *phydev)
615 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
619 err = phy_write(phydev, MII_M1011_PHY_SCR,
620 MII_M1011_PHY_SCR_AUTO_CROSS);
624 err = genphy_config_aneg(phydev);
628 static int m88e1118_config_init(struct phy_device *phydev)
633 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
637 /* Enable 1000 Mbit */
638 err = phy_write(phydev, 0x15, 0x1070);
643 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
647 /* Adjust LED Control */
648 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
649 err = phy_write(phydev, 0x10, 0x1100);
651 err = phy_write(phydev, 0x10, 0x021e);
655 err = marvell_of_reg_init(phydev);
660 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
664 return phy_write(phydev, MII_BMCR, BMCR_RESET);
667 static int m88e1149_config_init(struct phy_device *phydev)
672 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
676 /* Enable 1000 Mbit */
677 err = phy_write(phydev, 0x15, 0x1048);
681 err = marvell_of_reg_init(phydev);
686 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
690 return phy_write(phydev, MII_BMCR, BMCR_RESET);
693 static int m88e1145_config_init(struct phy_device *phydev)
698 /* Take care of errata E0 & E1 */
699 err = phy_write(phydev, 0x1d, 0x001b);
703 err = phy_write(phydev, 0x1e, 0x418f);
707 err = phy_write(phydev, 0x1d, 0x0016);
711 err = phy_write(phydev, 0x1e, 0xa2da);
715 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
716 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
720 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
722 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
726 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
727 err = phy_write(phydev, 0x1d, 0x0012);
731 temp = phy_read(phydev, 0x1e);
736 temp |= 2 << 9; /* 36 ohm */
737 temp |= 2 << 6; /* 39 ohm */
739 err = phy_write(phydev, 0x1e, temp);
743 err = phy_write(phydev, 0x1d, 0x3);
747 err = phy_write(phydev, 0x1e, 0x8000);
753 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
754 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
758 temp &= ~MII_M1145_HWCFG_MODE_MASK;
759 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
760 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
762 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
767 err = marvell_of_reg_init(phydev);
774 /* marvell_read_status
776 * Generic status code does not detect Fiber correctly!
778 * Check the link, then figure out the current state
779 * by comparing what we advertise with what the link partner
780 * advertises. Start by checking the gigabit possibilities,
781 * then move on to 10/100.
783 static int marvell_read_status(struct phy_device *phydev)
790 /* Update the link, but return if there
792 err = genphy_update_link(phydev);
796 if (AUTONEG_ENABLE == phydev->autoneg) {
797 status = phy_read(phydev, MII_M1011_PHY_STATUS);
801 lpa = phy_read(phydev, MII_LPA);
805 adv = phy_read(phydev, MII_ADVERTISE);
811 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
812 phydev->duplex = DUPLEX_FULL;
814 phydev->duplex = DUPLEX_HALF;
816 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
817 phydev->pause = phydev->asym_pause = 0;
820 case MII_M1011_PHY_STATUS_1000:
821 phydev->speed = SPEED_1000;
824 case MII_M1011_PHY_STATUS_100:
825 phydev->speed = SPEED_100;
829 phydev->speed = SPEED_10;
833 if (phydev->duplex == DUPLEX_FULL) {
834 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
835 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
838 int bmcr = phy_read(phydev, MII_BMCR);
843 if (bmcr & BMCR_FULLDPLX)
844 phydev->duplex = DUPLEX_FULL;
846 phydev->duplex = DUPLEX_HALF;
848 if (bmcr & BMCR_SPEED1000)
849 phydev->speed = SPEED_1000;
850 else if (bmcr & BMCR_SPEED100)
851 phydev->speed = SPEED_100;
853 phydev->speed = SPEED_10;
855 phydev->pause = phydev->asym_pause = 0;
861 static int marvell_aneg_done(struct phy_device *phydev)
863 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
864 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
867 static int m88e1121_did_interrupt(struct phy_device *phydev)
871 imask = phy_read(phydev, MII_M1011_IEVENT);
873 if (imask & MII_M1011_IMASK_INIT)
879 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
881 wol->supported = WAKE_MAGIC;
884 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
885 MII_88E1318S_PHY_WOL_PAGE) < 0)
888 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
889 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
890 wol->wolopts |= WAKE_MAGIC;
892 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
896 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
898 int err, oldpage, temp;
900 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
902 if (wol->wolopts & WAKE_MAGIC) {
903 /* Explicitly switch to page 0x00, just to be sure */
904 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
908 /* Enable the WOL interrupt */
909 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
910 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
911 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
915 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
916 MII_88E1318S_PHY_LED_PAGE);
920 /* Setup LED[2] as interrupt pin (active low) */
921 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
922 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
923 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
924 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
925 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
929 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
930 MII_88E1318S_PHY_WOL_PAGE);
934 /* Store the device address for the magic packet */
935 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
936 ((phydev->attached_dev->dev_addr[5] << 8) |
937 phydev->attached_dev->dev_addr[4]));
940 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
941 ((phydev->attached_dev->dev_addr[3] << 8) |
942 phydev->attached_dev->dev_addr[2]));
945 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
946 ((phydev->attached_dev->dev_addr[1] << 8) |
947 phydev->attached_dev->dev_addr[0]));
951 /* Clear WOL status and enable magic packet matching */
952 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
953 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
954 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
955 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
959 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
960 MII_88E1318S_PHY_WOL_PAGE);
964 /* Clear WOL status and disable magic packet matching */
965 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
966 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
967 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
968 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
973 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
980 static struct phy_driver marvell_drivers[] = {
982 .phy_id = MARVELL_PHY_ID_88E1101,
983 .phy_id_mask = MARVELL_PHY_ID_MASK,
984 .name = "Marvell 88E1101",
985 .features = PHY_GBIT_FEATURES,
986 .flags = PHY_HAS_INTERRUPT,
987 .config_aneg = &marvell_config_aneg,
988 .read_status = &genphy_read_status,
989 .ack_interrupt = &marvell_ack_interrupt,
990 .config_intr = &marvell_config_intr,
991 .resume = &genphy_resume,
992 .suspend = &genphy_suspend,
993 .driver = { .owner = THIS_MODULE },
996 .phy_id = MARVELL_PHY_ID_88E1112,
997 .phy_id_mask = MARVELL_PHY_ID_MASK,
998 .name = "Marvell 88E1112",
999 .features = PHY_GBIT_FEATURES,
1000 .flags = PHY_HAS_INTERRUPT,
1001 .config_init = &m88e1111_config_init,
1002 .config_aneg = &marvell_config_aneg,
1003 .read_status = &genphy_read_status,
1004 .ack_interrupt = &marvell_ack_interrupt,
1005 .config_intr = &marvell_config_intr,
1006 .resume = &genphy_resume,
1007 .suspend = &genphy_suspend,
1008 .driver = { .owner = THIS_MODULE },
1011 .phy_id = MARVELL_PHY_ID_88E1111,
1012 .phy_id_mask = MARVELL_PHY_ID_MASK,
1013 .name = "Marvell 88E1111",
1014 .features = PHY_GBIT_FEATURES,
1015 .flags = PHY_HAS_INTERRUPT,
1016 .config_init = &m88e1111_config_init,
1017 .config_aneg = &marvell_config_aneg,
1018 .read_status = &marvell_read_status,
1019 .ack_interrupt = &marvell_ack_interrupt,
1020 .config_intr = &marvell_config_intr,
1021 .resume = &genphy_resume,
1022 .suspend = &genphy_suspend,
1023 .driver = { .owner = THIS_MODULE },
1026 .phy_id = MARVELL_PHY_ID_88E1118,
1027 .phy_id_mask = MARVELL_PHY_ID_MASK,
1028 .name = "Marvell 88E1118",
1029 .features = PHY_GBIT_FEATURES,
1030 .flags = PHY_HAS_INTERRUPT,
1031 .config_init = &m88e1118_config_init,
1032 .config_aneg = &m88e1118_config_aneg,
1033 .read_status = &genphy_read_status,
1034 .ack_interrupt = &marvell_ack_interrupt,
1035 .config_intr = &marvell_config_intr,
1036 .resume = &genphy_resume,
1037 .suspend = &genphy_suspend,
1038 .driver = {.owner = THIS_MODULE,},
1041 .phy_id = MARVELL_PHY_ID_88E1121R,
1042 .phy_id_mask = MARVELL_PHY_ID_MASK,
1043 .name = "Marvell 88E1121R",
1044 .features = PHY_GBIT_FEATURES,
1045 .flags = PHY_HAS_INTERRUPT,
1046 .config_aneg = &m88e1121_config_aneg,
1047 .read_status = &marvell_read_status,
1048 .ack_interrupt = &marvell_ack_interrupt,
1049 .config_intr = &marvell_config_intr,
1050 .did_interrupt = &m88e1121_did_interrupt,
1051 .resume = &genphy_resume,
1052 .suspend = &genphy_suspend,
1053 .driver = { .owner = THIS_MODULE },
1056 .phy_id = MARVELL_PHY_ID_88E1318S,
1057 .phy_id_mask = MARVELL_PHY_ID_MASK,
1058 .name = "Marvell 88E1318S",
1059 .features = PHY_GBIT_FEATURES,
1060 .flags = PHY_HAS_INTERRUPT,
1061 .config_aneg = &m88e1318_config_aneg,
1062 .read_status = &marvell_read_status,
1063 .ack_interrupt = &marvell_ack_interrupt,
1064 .config_intr = &marvell_config_intr,
1065 .did_interrupt = &m88e1121_did_interrupt,
1066 .get_wol = &m88e1318_get_wol,
1067 .set_wol = &m88e1318_set_wol,
1068 .resume = &genphy_resume,
1069 .suspend = &genphy_suspend,
1070 .driver = { .owner = THIS_MODULE },
1073 .phy_id = MARVELL_PHY_ID_88E1145,
1074 .phy_id_mask = MARVELL_PHY_ID_MASK,
1075 .name = "Marvell 88E1145",
1076 .features = PHY_GBIT_FEATURES,
1077 .flags = PHY_HAS_INTERRUPT,
1078 .config_init = &m88e1145_config_init,
1079 .config_aneg = &marvell_config_aneg,
1080 .read_status = &genphy_read_status,
1081 .ack_interrupt = &marvell_ack_interrupt,
1082 .config_intr = &marvell_config_intr,
1083 .resume = &genphy_resume,
1084 .suspend = &genphy_suspend,
1085 .driver = { .owner = THIS_MODULE },
1088 .phy_id = MARVELL_PHY_ID_88E1149R,
1089 .phy_id_mask = MARVELL_PHY_ID_MASK,
1090 .name = "Marvell 88E1149R",
1091 .features = PHY_GBIT_FEATURES,
1092 .flags = PHY_HAS_INTERRUPT,
1093 .config_init = &m88e1149_config_init,
1094 .config_aneg = &m88e1118_config_aneg,
1095 .read_status = &genphy_read_status,
1096 .ack_interrupt = &marvell_ack_interrupt,
1097 .config_intr = &marvell_config_intr,
1098 .resume = &genphy_resume,
1099 .suspend = &genphy_suspend,
1100 .driver = { .owner = THIS_MODULE },
1103 .phy_id = MARVELL_PHY_ID_88E1240,
1104 .phy_id_mask = MARVELL_PHY_ID_MASK,
1105 .name = "Marvell 88E1240",
1106 .features = PHY_GBIT_FEATURES,
1107 .flags = PHY_HAS_INTERRUPT,
1108 .config_init = &m88e1111_config_init,
1109 .config_aneg = &marvell_config_aneg,
1110 .read_status = &genphy_read_status,
1111 .ack_interrupt = &marvell_ack_interrupt,
1112 .config_intr = &marvell_config_intr,
1113 .resume = &genphy_resume,
1114 .suspend = &genphy_suspend,
1115 .driver = { .owner = THIS_MODULE },
1118 .phy_id = MARVELL_PHY_ID_88E1116R,
1119 .phy_id_mask = MARVELL_PHY_ID_MASK,
1120 .name = "Marvell 88E1116R",
1121 .features = PHY_GBIT_FEATURES,
1122 .flags = PHY_HAS_INTERRUPT,
1123 .config_init = &m88e1116r_config_init,
1124 .config_aneg = &genphy_config_aneg,
1125 .read_status = &genphy_read_status,
1126 .ack_interrupt = &marvell_ack_interrupt,
1127 .config_intr = &marvell_config_intr,
1128 .resume = &genphy_resume,
1129 .suspend = &genphy_suspend,
1130 .driver = { .owner = THIS_MODULE },
1133 .phy_id = MARVELL_PHY_ID_88E1510,
1134 .phy_id_mask = MARVELL_PHY_ID_MASK,
1135 .name = "Marvell 88E1510",
1136 .features = PHY_GBIT_FEATURES,
1137 .flags = PHY_HAS_INTERRUPT,
1138 .config_aneg = &m88e1510_config_aneg,
1139 .read_status = &marvell_read_status,
1140 .ack_interrupt = &marvell_ack_interrupt,
1141 .config_intr = &marvell_config_intr,
1142 .did_interrupt = &m88e1121_did_interrupt,
1143 .resume = &genphy_resume,
1144 .suspend = &genphy_suspend,
1145 .driver = { .owner = THIS_MODULE },
1148 .phy_id = MARVELL_PHY_ID_88E3016,
1149 .phy_id_mask = MARVELL_PHY_ID_MASK,
1150 .name = "Marvell 88E3016",
1151 .features = PHY_BASIC_FEATURES,
1152 .flags = PHY_HAS_INTERRUPT,
1153 .config_aneg = &genphy_config_aneg,
1154 .config_init = &m88e3016_config_init,
1155 .aneg_done = &marvell_aneg_done,
1156 .read_status = &marvell_read_status,
1157 .ack_interrupt = &marvell_ack_interrupt,
1158 .config_intr = &marvell_config_intr,
1159 .did_interrupt = &m88e1121_did_interrupt,
1160 .resume = &genphy_resume,
1161 .suspend = &genphy_suspend,
1162 .driver = { .owner = THIS_MODULE },
1166 module_phy_driver(marvell_drivers);
1168 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1169 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1170 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1171 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1172 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1173 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1174 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1175 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1176 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1177 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1178 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1179 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1180 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1184 MODULE_DEVICE_TABLE(mdio, marvell_tbl);