2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
78 u16 interrupt_level_mask;
79 bool has_broadcast_disable;
80 bool has_nand_tree_disable;
81 bool has_rmii_ref_clk_sel;
85 const struct kszphy_type *type;
87 bool rmii_ref_clk_sel;
88 bool rmii_ref_clk_sel_val;
91 static const struct kszphy_type ksz8021_type = {
92 .led_mode_reg = MII_KSZPHY_CTRL_2,
93 .has_broadcast_disable = true,
94 .has_nand_tree_disable = true,
95 .has_rmii_ref_clk_sel = true,
98 static const struct kszphy_type ksz8041_type = {
99 .led_mode_reg = MII_KSZPHY_CTRL_1,
102 static const struct kszphy_type ksz8051_type = {
103 .led_mode_reg = MII_KSZPHY_CTRL_2,
104 .has_nand_tree_disable = true,
107 static const struct kszphy_type ksz8081_type = {
108 .led_mode_reg = MII_KSZPHY_CTRL_2,
109 .has_broadcast_disable = true,
110 .has_nand_tree_disable = true,
111 .has_rmii_ref_clk_sel = true,
114 static const struct kszphy_type ks8737_type = {
115 .interrupt_level_mask = BIT(14),
118 static const struct kszphy_type ksz9021_type = {
119 .interrupt_level_mask = BIT(14),
122 static int kszphy_extended_write(struct phy_device *phydev,
125 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
126 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
129 static int kszphy_extended_read(struct phy_device *phydev,
132 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
133 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
136 static int kszphy_ack_interrupt(struct phy_device *phydev)
138 /* bit[7..0] int status, which is a read and clear register. */
141 rc = phy_read(phydev, MII_KSZPHY_INTCS);
143 return (rc < 0) ? rc : 0;
146 static int kszphy_config_intr(struct phy_device *phydev)
148 const struct kszphy_type *type = phydev->drv->driver_data;
152 if (type && type->interrupt_level_mask)
153 mask = type->interrupt_level_mask;
155 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
157 /* set the interrupt pin active low */
158 temp = phy_read(phydev, MII_KSZPHY_CTRL);
162 phy_write(phydev, MII_KSZPHY_CTRL, temp);
164 /* enable / disable interrupts */
165 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
166 temp = KSZPHY_INTCS_ALL;
170 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
173 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
177 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
182 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
184 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
186 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
189 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
194 case MII_KSZPHY_CTRL_1:
197 case MII_KSZPHY_CTRL_2:
204 temp = phy_read(phydev, reg);
210 temp &= ~(3 << shift);
211 temp |= val << shift;
212 rc = phy_write(phydev, reg, temp);
215 dev_err(&phydev->dev, "failed to set led mode\n");
220 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
221 * unique (non-broadcast) address on a shared bus.
223 static int kszphy_broadcast_disable(struct phy_device *phydev)
227 ret = phy_read(phydev, MII_KSZPHY_OMSO);
231 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
234 dev_err(&phydev->dev, "failed to disable broadcast address\n");
239 static int kszphy_nand_tree_disable(struct phy_device *phydev)
243 ret = phy_read(phydev, MII_KSZPHY_OMSO);
247 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
250 ret = phy_write(phydev, MII_KSZPHY_OMSO,
251 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
254 dev_err(&phydev->dev, "failed to disable NAND tree mode\n");
259 static int kszphy_config_init(struct phy_device *phydev)
261 struct kszphy_priv *priv = phydev->priv;
262 const struct kszphy_type *type;
270 if (type->has_broadcast_disable)
271 kszphy_broadcast_disable(phydev);
273 if (type->has_nand_tree_disable)
274 kszphy_nand_tree_disable(phydev);
276 if (priv->rmii_ref_clk_sel) {
277 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
279 dev_err(&phydev->dev, "failed to set rmii reference clock\n");
284 if (priv->led_mode >= 0)
285 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
290 static int ksz9021_load_values_from_of(struct phy_device *phydev,
291 struct device_node *of_node, u16 reg,
292 char *field1, char *field2,
293 char *field3, char *field4)
302 if (!of_property_read_u32(of_node, field1, &val1))
305 if (!of_property_read_u32(of_node, field2, &val2))
308 if (!of_property_read_u32(of_node, field3, &val3))
311 if (!of_property_read_u32(of_node, field4, &val4))
318 newval = kszphy_extended_read(phydev, reg);
323 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
326 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
329 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
332 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
334 return kszphy_extended_write(phydev, reg, newval);
337 static int ksz9021_config_init(struct phy_device *phydev)
339 struct device *dev = &phydev->dev;
340 struct device_node *of_node = dev->of_node;
342 if (!of_node && dev->parent->of_node)
343 of_node = dev->parent->of_node;
346 ksz9021_load_values_from_of(phydev, of_node,
347 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
348 "txen-skew-ps", "txc-skew-ps",
349 "rxdv-skew-ps", "rxc-skew-ps");
350 ksz9021_load_values_from_of(phydev, of_node,
351 MII_KSZPHY_RX_DATA_PAD_SKEW,
352 "rxd0-skew-ps", "rxd1-skew-ps",
353 "rxd2-skew-ps", "rxd3-skew-ps");
354 ksz9021_load_values_from_of(phydev, of_node,
355 MII_KSZPHY_TX_DATA_PAD_SKEW,
356 "txd0-skew-ps", "txd1-skew-ps",
357 "txd2-skew-ps", "txd3-skew-ps");
362 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
363 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
365 #define KSZ9031_PS_TO_REG 60
367 /* Extended registers */
368 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
369 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
370 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
371 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
373 static int ksz9031_extended_write(struct phy_device *phydev,
374 u8 mode, u32 dev_addr, u32 regnum, u16 val)
376 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
377 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
378 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
379 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
382 static int ksz9031_extended_read(struct phy_device *phydev,
383 u8 mode, u32 dev_addr, u32 regnum)
385 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
386 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
387 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
388 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
391 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
392 struct device_node *of_node,
393 u16 reg, size_t field_sz,
394 char *field[], u8 numfields)
396 int val[4] = {-1, -2, -3, -4};
403 for (i = 0; i < numfields; i++)
404 if (!of_property_read_u32(of_node, field[i], val + i))
410 if (matches < numfields)
411 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
415 maxval = (field_sz == 4) ? 0xf : 0x1f;
416 for (i = 0; i < numfields; i++)
417 if (val[i] != -(i + 1)) {
419 mask ^= maxval << (field_sz * i);
420 newval = (newval & mask) |
421 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
425 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
428 static int ksz9031_config_init(struct phy_device *phydev)
430 struct device *dev = &phydev->dev;
431 struct device_node *of_node = dev->of_node;
432 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
433 char *rx_data_skews[4] = {
434 "rxd0-skew-ps", "rxd1-skew-ps",
435 "rxd2-skew-ps", "rxd3-skew-ps"
437 char *tx_data_skews[4] = {
438 "txd0-skew-ps", "txd1-skew-ps",
439 "txd2-skew-ps", "txd3-skew-ps"
441 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
443 if (!of_node && dev->parent->of_node)
444 of_node = dev->parent->of_node;
447 ksz9031_of_load_skew_values(phydev, of_node,
448 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
451 ksz9031_of_load_skew_values(phydev, of_node,
452 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
455 ksz9031_of_load_skew_values(phydev, of_node,
456 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
459 ksz9031_of_load_skew_values(phydev, of_node,
460 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
466 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
467 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
468 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
469 static int ksz8873mll_read_status(struct phy_device *phydev)
474 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
476 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
478 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
479 phydev->duplex = DUPLEX_HALF;
481 phydev->duplex = DUPLEX_FULL;
483 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
484 phydev->speed = SPEED_10;
486 phydev->speed = SPEED_100;
489 phydev->pause = phydev->asym_pause = 0;
494 static int ksz8873mll_config_aneg(struct phy_device *phydev)
499 /* This routine returns -1 as an indication to the caller that the
500 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
501 * MMD extended PHY registers.
504 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
510 /* This routine does nothing since the Micrel ksz9021 does not support
511 * standard IEEE MMD extended PHY registers.
514 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
519 static int kszphy_probe(struct phy_device *phydev)
521 const struct kszphy_type *type = phydev->drv->driver_data;
522 struct device_node *np = phydev->dev.of_node;
523 struct kszphy_priv *priv;
527 priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
535 if (type->led_mode_reg) {
536 ret = of_property_read_u32(np, "micrel,led-mode",
541 if (priv->led_mode > 3) {
542 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
550 clk = devm_clk_get(&phydev->dev, "rmii-ref");
552 unsigned long rate = clk_get_rate(clk);
553 bool rmii_ref_clk_sel_25_mhz;
555 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
556 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
557 "micrel,rmii-reference-clock-select-25-mhz");
559 if (rate > 24500000 && rate < 25500000) {
560 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
561 } else if (rate > 49500000 && rate < 50500000) {
562 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
564 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
569 /* Support legacy board-file configuration */
570 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
571 priv->rmii_ref_clk_sel = true;
572 priv->rmii_ref_clk_sel_val = true;
578 static struct phy_driver ksphy_driver[] = {
580 .phy_id = PHY_ID_KS8737,
581 .phy_id_mask = 0x00fffff0,
582 .name = "Micrel KS8737",
583 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
584 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
585 .driver_data = &ks8737_type,
586 .config_init = kszphy_config_init,
587 .config_aneg = genphy_config_aneg,
588 .read_status = genphy_read_status,
589 .ack_interrupt = kszphy_ack_interrupt,
590 .config_intr = kszphy_config_intr,
591 .suspend = genphy_suspend,
592 .resume = genphy_resume,
593 .driver = { .owner = THIS_MODULE,},
595 .phy_id = PHY_ID_KSZ8021,
596 .phy_id_mask = 0x00ffffff,
597 .name = "Micrel KSZ8021 or KSZ8031",
598 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
599 SUPPORTED_Asym_Pause),
600 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
601 .driver_data = &ksz8021_type,
602 .probe = kszphy_probe,
603 .config_init = kszphy_config_init,
604 .config_aneg = genphy_config_aneg,
605 .read_status = genphy_read_status,
606 .ack_interrupt = kszphy_ack_interrupt,
607 .config_intr = kszphy_config_intr,
608 .suspend = genphy_suspend,
609 .resume = genphy_resume,
610 .driver = { .owner = THIS_MODULE,},
612 .phy_id = PHY_ID_KSZ8031,
613 .phy_id_mask = 0x00ffffff,
614 .name = "Micrel KSZ8031",
615 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
616 SUPPORTED_Asym_Pause),
617 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
618 .driver_data = &ksz8021_type,
619 .probe = kszphy_probe,
620 .config_init = kszphy_config_init,
621 .config_aneg = genphy_config_aneg,
622 .read_status = genphy_read_status,
623 .ack_interrupt = kszphy_ack_interrupt,
624 .config_intr = kszphy_config_intr,
625 .suspend = genphy_suspend,
626 .resume = genphy_resume,
627 .driver = { .owner = THIS_MODULE,},
629 .phy_id = PHY_ID_KSZ8041,
630 .phy_id_mask = 0x00fffff0,
631 .name = "Micrel KSZ8041",
632 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
633 | SUPPORTED_Asym_Pause),
634 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
635 .driver_data = &ksz8041_type,
636 .probe = kszphy_probe,
637 .config_init = kszphy_config_init,
638 .config_aneg = genphy_config_aneg,
639 .read_status = genphy_read_status,
640 .ack_interrupt = kszphy_ack_interrupt,
641 .config_intr = kszphy_config_intr,
642 .suspend = genphy_suspend,
643 .resume = genphy_resume,
644 .driver = { .owner = THIS_MODULE,},
646 .phy_id = PHY_ID_KSZ8041RNLI,
647 .phy_id_mask = 0x00fffff0,
648 .name = "Micrel KSZ8041RNLI",
649 .features = PHY_BASIC_FEATURES |
650 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
651 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
652 .driver_data = &ksz8041_type,
653 .probe = kszphy_probe,
654 .config_init = kszphy_config_init,
655 .config_aneg = genphy_config_aneg,
656 .read_status = genphy_read_status,
657 .ack_interrupt = kszphy_ack_interrupt,
658 .config_intr = kszphy_config_intr,
659 .suspend = genphy_suspend,
660 .resume = genphy_resume,
661 .driver = { .owner = THIS_MODULE,},
663 .phy_id = PHY_ID_KSZ8051,
664 .phy_id_mask = 0x00fffff0,
665 .name = "Micrel KSZ8051",
666 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
667 | SUPPORTED_Asym_Pause),
668 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
669 .driver_data = &ksz8051_type,
670 .probe = kszphy_probe,
671 .config_init = kszphy_config_init,
672 .config_aneg = genphy_config_aneg,
673 .read_status = genphy_read_status,
674 .ack_interrupt = kszphy_ack_interrupt,
675 .config_intr = kszphy_config_intr,
676 .suspend = genphy_suspend,
677 .resume = genphy_resume,
678 .driver = { .owner = THIS_MODULE,},
680 .phy_id = PHY_ID_KSZ8001,
681 .name = "Micrel KSZ8001 or KS8721",
682 .phy_id_mask = 0x00ffffff,
683 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
684 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
685 .driver_data = &ksz8041_type,
686 .probe = kszphy_probe,
687 .config_init = kszphy_config_init,
688 .config_aneg = genphy_config_aneg,
689 .read_status = genphy_read_status,
690 .ack_interrupt = kszphy_ack_interrupt,
691 .config_intr = kszphy_config_intr,
692 .suspend = genphy_suspend,
693 .resume = genphy_resume,
694 .driver = { .owner = THIS_MODULE,},
696 .phy_id = PHY_ID_KSZ8081,
697 .name = "Micrel KSZ8081 or KSZ8091",
698 .phy_id_mask = 0x00fffff0,
699 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
700 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
701 .driver_data = &ksz8081_type,
702 .probe = kszphy_probe,
703 .config_init = kszphy_config_init,
704 .config_aneg = genphy_config_aneg,
705 .read_status = genphy_read_status,
706 .ack_interrupt = kszphy_ack_interrupt,
707 .config_intr = kszphy_config_intr,
708 .suspend = genphy_suspend,
709 .resume = genphy_resume,
710 .driver = { .owner = THIS_MODULE,},
712 .phy_id = PHY_ID_KSZ8061,
713 .name = "Micrel KSZ8061",
714 .phy_id_mask = 0x00fffff0,
715 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
716 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
717 .config_init = kszphy_config_init,
718 .config_aneg = genphy_config_aneg,
719 .read_status = genphy_read_status,
720 .ack_interrupt = kszphy_ack_interrupt,
721 .config_intr = kszphy_config_intr,
722 .suspend = genphy_suspend,
723 .resume = genphy_resume,
724 .driver = { .owner = THIS_MODULE,},
726 .phy_id = PHY_ID_KSZ9021,
727 .phy_id_mask = 0x000ffffe,
728 .name = "Micrel KSZ9021 Gigabit PHY",
729 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
730 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
731 .driver_data = &ksz9021_type,
732 .config_init = ksz9021_config_init,
733 .config_aneg = genphy_config_aneg,
734 .read_status = genphy_read_status,
735 .ack_interrupt = kszphy_ack_interrupt,
736 .config_intr = kszphy_config_intr,
737 .suspend = genphy_suspend,
738 .resume = genphy_resume,
739 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
740 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
741 .driver = { .owner = THIS_MODULE, },
743 .phy_id = PHY_ID_KSZ9031,
744 .phy_id_mask = 0x00fffff0,
745 .name = "Micrel KSZ9031 Gigabit PHY",
746 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
747 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
748 .driver_data = &ksz9021_type,
749 .config_init = ksz9031_config_init,
750 .config_aneg = genphy_config_aneg,
751 .read_status = genphy_read_status,
752 .ack_interrupt = kszphy_ack_interrupt,
753 .config_intr = kszphy_config_intr,
754 .suspend = genphy_suspend,
755 .resume = genphy_resume,
756 .driver = { .owner = THIS_MODULE, },
758 .phy_id = PHY_ID_KSZ8873MLL,
759 .phy_id_mask = 0x00fffff0,
760 .name = "Micrel KSZ8873MLL Switch",
761 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
762 .flags = PHY_HAS_MAGICANEG,
763 .config_init = kszphy_config_init,
764 .config_aneg = ksz8873mll_config_aneg,
765 .read_status = ksz8873mll_read_status,
766 .suspend = genphy_suspend,
767 .resume = genphy_resume,
768 .driver = { .owner = THIS_MODULE, },
770 .phy_id = PHY_ID_KSZ886X,
771 .phy_id_mask = 0x00fffff0,
772 .name = "Micrel KSZ886X Switch",
773 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
774 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
775 .config_init = kszphy_config_init,
776 .config_aneg = genphy_config_aneg,
777 .read_status = genphy_read_status,
778 .suspend = genphy_suspend,
779 .resume = genphy_resume,
780 .driver = { .owner = THIS_MODULE, },
783 module_phy_driver(ksphy_driver);
785 MODULE_DESCRIPTION("Micrel PHY driver");
786 MODULE_AUTHOR("David J. Choi");
787 MODULE_LICENSE("GPL");
789 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
790 { PHY_ID_KSZ9021, 0x000ffffe },
791 { PHY_ID_KSZ9031, 0x00fffff0 },
792 { PHY_ID_KSZ8001, 0x00ffffff },
793 { PHY_ID_KS8737, 0x00fffff0 },
794 { PHY_ID_KSZ8021, 0x00ffffff },
795 { PHY_ID_KSZ8031, 0x00ffffff },
796 { PHY_ID_KSZ8041, 0x00fffff0 },
797 { PHY_ID_KSZ8051, 0x00fffff0 },
798 { PHY_ID_KSZ8061, 0x00fffff0 },
799 { PHY_ID_KSZ8081, 0x00fffff0 },
800 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
801 { PHY_ID_KSZ886X, 0x00fffff0 },
805 MODULE_DEVICE_TABLE(mdio, micrel_tbl);