2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
21 * Switch : ksz8873, ksz886x
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/phy.h>
27 #include <linux/micrel_phy.h>
30 /* Operation Mode Strap Override */
31 #define MII_KSZPHY_OMSO 0x16
32 #define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33 #define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
34 #define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
36 /* general Interrupt control/status reg in vendor specific block. */
37 #define MII_KSZPHY_INTCS 0x1B
38 #define KSZPHY_INTCS_JABBER (1 << 15)
39 #define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
40 #define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
41 #define KSZPHY_INTCS_PARELLEL (1 << 12)
42 #define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
43 #define KSZPHY_INTCS_LINK_DOWN (1 << 10)
44 #define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
45 #define KSZPHY_INTCS_LINK_UP (1 << 8)
46 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
47 KSZPHY_INTCS_LINK_DOWN)
49 /* general PHY control reg in vendor specific block. */
50 #define MII_KSZPHY_CTRL 0x1F
51 /* bitmap of PHY register to set interrupt mode */
52 #define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
53 #define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
54 #define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
55 #define KSZ8051_RMII_50MHZ_CLK (1 << 7)
57 /* Write/read to/from extended registers */
58 #define MII_KSZPHY_EXTREG 0x0b
59 #define KSZPHY_EXTREG_WRITE 0x8000
61 #define MII_KSZPHY_EXTREG_WRITE 0x0c
62 #define MII_KSZPHY_EXTREG_READ 0x0d
64 /* Extended registers */
65 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
66 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
67 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
71 static int ksz_config_flags(struct phy_device *phydev)
75 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
76 regval = phy_read(phydev, MII_KSZPHY_CTRL);
77 regval |= KSZ8051_RMII_50MHZ_CLK;
78 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
83 static int kszphy_extended_write(struct phy_device *phydev,
86 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
87 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
90 static int kszphy_extended_read(struct phy_device *phydev,
93 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
94 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
97 static int kszphy_ack_interrupt(struct phy_device *phydev)
99 /* bit[7..0] int status, which is a read and clear register. */
102 rc = phy_read(phydev, MII_KSZPHY_INTCS);
104 return (rc < 0) ? rc : 0;
107 static int kszphy_set_interrupt(struct phy_device *phydev)
110 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
111 KSZPHY_INTCS_ALL : 0;
112 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
115 static int kszphy_config_intr(struct phy_device *phydev)
119 /* set the interrupt pin active low */
120 temp = phy_read(phydev, MII_KSZPHY_CTRL);
121 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
122 phy_write(phydev, MII_KSZPHY_CTRL, temp);
123 rc = kszphy_set_interrupt(phydev);
124 return rc < 0 ? rc : 0;
127 static int ksz9021_config_intr(struct phy_device *phydev)
131 /* set the interrupt pin active low */
132 temp = phy_read(phydev, MII_KSZPHY_CTRL);
133 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
134 phy_write(phydev, MII_KSZPHY_CTRL, temp);
135 rc = kszphy_set_interrupt(phydev);
136 return rc < 0 ? rc : 0;
139 static int ks8737_config_intr(struct phy_device *phydev)
143 /* set the interrupt pin active low */
144 temp = phy_read(phydev, MII_KSZPHY_CTRL);
145 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
146 phy_write(phydev, MII_KSZPHY_CTRL, temp);
147 rc = kszphy_set_interrupt(phydev);
148 return rc < 0 ? rc : 0;
151 static int kszphy_setup_led(struct phy_device *phydev,
152 unsigned int reg, unsigned int shift)
155 struct device *dev = &phydev->dev;
156 struct device_node *of_node = dev->of_node;
160 if (!of_node && dev->parent->of_node)
161 of_node = dev->parent->of_node;
163 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
166 temp = phy_read(phydev, reg);
170 temp &= ~(3 << shift);
171 temp |= val << shift;
172 rc = phy_write(phydev, reg, temp);
174 return rc < 0 ? rc : 0;
177 static int kszphy_config_init(struct phy_device *phydev)
182 static int kszphy_config_init_led8041(struct phy_device *phydev)
184 /* single led control, register 0x1e bits 15..14 */
185 return kszphy_setup_led(phydev, 0x1e, 14);
188 static int ksz8021_config_init(struct phy_device *phydev)
190 const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
193 rc = kszphy_setup_led(phydev, 0x1f, 4);
195 dev_err(&phydev->dev, "failed to set led mode\n");
197 phy_write(phydev, MII_KSZPHY_OMSO, val);
198 rc = ksz_config_flags(phydev);
199 return rc < 0 ? rc : 0;
202 static int ks8051_config_init(struct phy_device *phydev)
206 rc = kszphy_setup_led(phydev, 0x1f, 4);
208 dev_err(&phydev->dev, "failed to set led mode\n");
210 rc = ksz_config_flags(phydev);
211 return rc < 0 ? rc : 0;
214 static int ksz9021_load_values_from_of(struct phy_device *phydev,
215 struct device_node *of_node, u16 reg,
216 char *field1, char *field2,
217 char *field3, char *field4)
226 if (!of_property_read_u32(of_node, field1, &val1))
229 if (!of_property_read_u32(of_node, field2, &val2))
232 if (!of_property_read_u32(of_node, field3, &val3))
235 if (!of_property_read_u32(of_node, field4, &val4))
242 newval = kszphy_extended_read(phydev, reg);
247 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
250 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
253 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
256 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
258 return kszphy_extended_write(phydev, reg, newval);
261 static int ksz9021_config_init(struct phy_device *phydev)
263 struct device *dev = &phydev->dev;
264 struct device_node *of_node = dev->of_node;
266 if (!of_node && dev->parent->of_node)
267 of_node = dev->parent->of_node;
270 ksz9021_load_values_from_of(phydev, of_node,
271 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
272 "txen-skew-ps", "txc-skew-ps",
273 "rxdv-skew-ps", "rxc-skew-ps");
274 ksz9021_load_values_from_of(phydev, of_node,
275 MII_KSZPHY_RX_DATA_PAD_SKEW,
276 "rxd0-skew-ps", "rxd1-skew-ps",
277 "rxd2-skew-ps", "rxd3-skew-ps");
278 ksz9021_load_values_from_of(phydev, of_node,
279 MII_KSZPHY_TX_DATA_PAD_SKEW,
280 "txd0-skew-ps", "txd1-skew-ps",
281 "txd2-skew-ps", "txd3-skew-ps");
286 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
287 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
289 #define KSZ9031_PS_TO_REG 60
291 /* Extended registers */
292 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
293 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
294 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
295 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
297 static int ksz9031_extended_write(struct phy_device *phydev,
298 u8 mode, u32 dev_addr, u32 regnum, u16 val)
300 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
301 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
302 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
303 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
306 static int ksz9031_extended_read(struct phy_device *phydev,
307 u8 mode, u32 dev_addr, u32 regnum)
309 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
310 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
311 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
312 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
315 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
316 struct device_node *of_node,
317 u16 reg, size_t field_sz,
318 char *field[], u8 numfields)
320 int val[4] = {-1, -2, -3, -4};
327 for (i = 0; i < numfields; i++)
328 if (!of_property_read_u32(of_node, field[i], val + i))
334 if (matches < numfields)
335 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
339 maxval = (field_sz == 4) ? 0xf : 0x1f;
340 for (i = 0; i < numfields; i++)
341 if (val[i] != -(i + 1)) {
343 mask ^= maxval << (field_sz * i);
344 newval = (newval & mask) |
345 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
349 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
352 static int ksz9031_config_init(struct phy_device *phydev)
354 struct device *dev = &phydev->dev;
355 struct device_node *of_node = dev->of_node;
356 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
357 char *rx_data_skews[4] = {
358 "rxd0-skew-ps", "rxd1-skew-ps",
359 "rxd2-skew-ps", "rxd3-skew-ps"
361 char *tx_data_skews[4] = {
362 "txd0-skew-ps", "txd1-skew-ps",
363 "txd2-skew-ps", "txd3-skew-ps"
365 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
367 if (!of_node && dev->parent->of_node)
368 of_node = dev->parent->of_node;
371 ksz9031_of_load_skew_values(phydev, of_node,
372 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
375 ksz9031_of_load_skew_values(phydev, of_node,
376 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
379 ksz9031_of_load_skew_values(phydev, of_node,
380 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
383 ksz9031_of_load_skew_values(phydev, of_node,
384 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
390 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
391 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
392 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
393 static int ksz8873mll_read_status(struct phy_device *phydev)
398 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
400 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
402 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
403 phydev->duplex = DUPLEX_HALF;
405 phydev->duplex = DUPLEX_FULL;
407 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
408 phydev->speed = SPEED_10;
410 phydev->speed = SPEED_100;
413 phydev->pause = phydev->asym_pause = 0;
418 static int ksz8873mll_config_aneg(struct phy_device *phydev)
423 static struct phy_driver ksphy_driver[] = {
425 .phy_id = PHY_ID_KS8737,
426 .phy_id_mask = 0x00fffff0,
427 .name = "Micrel KS8737",
428 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
429 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
430 .config_init = kszphy_config_init,
431 .config_aneg = genphy_config_aneg,
432 .read_status = genphy_read_status,
433 .ack_interrupt = kszphy_ack_interrupt,
434 .config_intr = ks8737_config_intr,
435 .suspend = genphy_suspend,
436 .resume = genphy_resume,
437 .driver = { .owner = THIS_MODULE,},
439 .phy_id = PHY_ID_KSZ8021,
440 .phy_id_mask = 0x00ffffff,
441 .name = "Micrel KSZ8021 or KSZ8031",
442 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
443 SUPPORTED_Asym_Pause),
444 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
445 .config_init = ksz8021_config_init,
446 .config_aneg = genphy_config_aneg,
447 .read_status = genphy_read_status,
448 .ack_interrupt = kszphy_ack_interrupt,
449 .config_intr = kszphy_config_intr,
450 .suspend = genphy_suspend,
451 .resume = genphy_resume,
452 .driver = { .owner = THIS_MODULE,},
454 .phy_id = PHY_ID_KSZ8031,
455 .phy_id_mask = 0x00ffffff,
456 .name = "Micrel KSZ8031",
457 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
458 SUPPORTED_Asym_Pause),
459 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
460 .config_init = ksz8021_config_init,
461 .config_aneg = genphy_config_aneg,
462 .read_status = genphy_read_status,
463 .ack_interrupt = kszphy_ack_interrupt,
464 .config_intr = kszphy_config_intr,
465 .suspend = genphy_suspend,
466 .resume = genphy_resume,
467 .driver = { .owner = THIS_MODULE,},
469 .phy_id = PHY_ID_KSZ8041,
470 .phy_id_mask = 0x00fffff0,
471 .name = "Micrel KSZ8041",
472 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
473 | SUPPORTED_Asym_Pause),
474 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
475 .config_init = kszphy_config_init_led8041,
476 .config_aneg = genphy_config_aneg,
477 .read_status = genphy_read_status,
478 .ack_interrupt = kszphy_ack_interrupt,
479 .config_intr = kszphy_config_intr,
480 .suspend = genphy_suspend,
481 .resume = genphy_resume,
482 .driver = { .owner = THIS_MODULE,},
484 .phy_id = PHY_ID_KSZ8041RNLI,
485 .phy_id_mask = 0x00fffff0,
486 .name = "Micrel KSZ8041RNLI",
487 .features = PHY_BASIC_FEATURES |
488 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
489 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
490 .config_init = kszphy_config_init_led8041,
491 .config_aneg = genphy_config_aneg,
492 .read_status = genphy_read_status,
493 .ack_interrupt = kszphy_ack_interrupt,
494 .config_intr = kszphy_config_intr,
495 .suspend = genphy_suspend,
496 .resume = genphy_resume,
497 .driver = { .owner = THIS_MODULE,},
499 .phy_id = PHY_ID_KSZ8051,
500 .phy_id_mask = 0x00fffff0,
501 .name = "Micrel KSZ8051",
502 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
503 | SUPPORTED_Asym_Pause),
504 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
505 .config_init = ks8051_config_init,
506 .config_aneg = genphy_config_aneg,
507 .read_status = genphy_read_status,
508 .ack_interrupt = kszphy_ack_interrupt,
509 .config_intr = kszphy_config_intr,
510 .suspend = genphy_suspend,
511 .resume = genphy_resume,
512 .driver = { .owner = THIS_MODULE,},
514 .phy_id = PHY_ID_KSZ8001,
515 .name = "Micrel KSZ8001 or KS8721",
516 .phy_id_mask = 0x00ffffff,
517 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
518 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
519 .config_init = kszphy_config_init_led8041,
520 .config_aneg = genphy_config_aneg,
521 .read_status = genphy_read_status,
522 .ack_interrupt = kszphy_ack_interrupt,
523 .config_intr = kszphy_config_intr,
524 .suspend = genphy_suspend,
525 .resume = genphy_resume,
526 .driver = { .owner = THIS_MODULE,},
528 .phy_id = PHY_ID_KSZ8081,
529 .name = "Micrel KSZ8081 or KSZ8091",
530 .phy_id_mask = 0x00fffff0,
531 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
532 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
533 .config_init = kszphy_config_init,
534 .config_aneg = genphy_config_aneg,
535 .read_status = genphy_read_status,
536 .ack_interrupt = kszphy_ack_interrupt,
537 .config_intr = kszphy_config_intr,
538 .suspend = genphy_suspend,
539 .resume = genphy_resume,
540 .driver = { .owner = THIS_MODULE,},
542 .phy_id = PHY_ID_KSZ8061,
543 .name = "Micrel KSZ8061",
544 .phy_id_mask = 0x00fffff0,
545 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
546 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
547 .config_init = kszphy_config_init,
548 .config_aneg = genphy_config_aneg,
549 .read_status = genphy_read_status,
550 .ack_interrupt = kszphy_ack_interrupt,
551 .config_intr = kszphy_config_intr,
552 .suspend = genphy_suspend,
553 .resume = genphy_resume,
554 .driver = { .owner = THIS_MODULE,},
556 .phy_id = PHY_ID_KSZ9021,
557 .phy_id_mask = 0x000ffffe,
558 .name = "Micrel KSZ9021 Gigabit PHY",
559 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
560 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
561 .config_init = ksz9021_config_init,
562 .config_aneg = genphy_config_aneg,
563 .read_status = genphy_read_status,
564 .ack_interrupt = kszphy_ack_interrupt,
565 .config_intr = ksz9021_config_intr,
566 .suspend = genphy_suspend,
567 .resume = genphy_resume,
568 .driver = { .owner = THIS_MODULE, },
570 .phy_id = PHY_ID_KSZ9031,
571 .phy_id_mask = 0x00fffff0,
572 .name = "Micrel KSZ9031 Gigabit PHY",
573 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
574 | SUPPORTED_Asym_Pause),
575 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
576 .config_init = ksz9031_config_init,
577 .config_aneg = genphy_config_aneg,
578 .read_status = genphy_read_status,
579 .ack_interrupt = kszphy_ack_interrupt,
580 .config_intr = ksz9021_config_intr,
581 .suspend = genphy_suspend,
582 .resume = genphy_resume,
583 .driver = { .owner = THIS_MODULE, },
585 .phy_id = PHY_ID_KSZ8873MLL,
586 .phy_id_mask = 0x00fffff0,
587 .name = "Micrel KSZ8873MLL Switch",
588 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
589 .flags = PHY_HAS_MAGICANEG,
590 .config_init = kszphy_config_init,
591 .config_aneg = ksz8873mll_config_aneg,
592 .read_status = ksz8873mll_read_status,
593 .suspend = genphy_suspend,
594 .resume = genphy_resume,
595 .driver = { .owner = THIS_MODULE, },
597 .phy_id = PHY_ID_KSZ886X,
598 .phy_id_mask = 0x00fffff0,
599 .name = "Micrel KSZ886X Switch",
600 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
601 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
602 .config_init = kszphy_config_init,
603 .config_aneg = genphy_config_aneg,
604 .read_status = genphy_read_status,
605 .suspend = genphy_suspend,
606 .resume = genphy_resume,
607 .driver = { .owner = THIS_MODULE, },
610 static int __init ksphy_init(void)
612 return phy_drivers_register(ksphy_driver,
613 ARRAY_SIZE(ksphy_driver));
616 static void __exit ksphy_exit(void)
618 phy_drivers_unregister(ksphy_driver,
619 ARRAY_SIZE(ksphy_driver));
622 module_init(ksphy_init);
623 module_exit(ksphy_exit);
625 MODULE_DESCRIPTION("Micrel PHY driver");
626 MODULE_AUTHOR("David J. Choi");
627 MODULE_LICENSE("GPL");
629 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
630 { PHY_ID_KSZ9021, 0x000ffffe },
631 { PHY_ID_KSZ9031, 0x00fffff0 },
632 { PHY_ID_KSZ8001, 0x00ffffff },
633 { PHY_ID_KS8737, 0x00fffff0 },
634 { PHY_ID_KSZ8021, 0x00ffffff },
635 { PHY_ID_KSZ8031, 0x00ffffff },
636 { PHY_ID_KSZ8041, 0x00fffff0 },
637 { PHY_ID_KSZ8051, 0x00fffff0 },
638 { PHY_ID_KSZ8061, 0x00fffff0 },
639 { PHY_ID_KSZ8081, 0x00fffff0 },
640 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
641 { PHY_ID_KSZ886X, 0x00fffff0 },
645 MODULE_DEVICE_TABLE(mdio, micrel_tbl);