2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
76 struct kszphy_hw_stat {
82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
89 u16 interrupt_level_mask;
90 bool has_broadcast_disable;
91 bool has_nand_tree_disable;
92 bool has_rmii_ref_clk_sel;
96 const struct kszphy_type *type;
98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
103 static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
105 .has_broadcast_disable = true,
106 .has_nand_tree_disable = true,
107 .has_rmii_ref_clk_sel = true,
110 static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
114 static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
116 .has_nand_tree_disable = true,
119 static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
121 .has_broadcast_disable = true,
122 .has_nand_tree_disable = true,
123 .has_rmii_ref_clk_sel = true,
126 static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
130 static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
134 static int kszphy_extended_write(struct phy_device *phydev,
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
141 static int kszphy_extended_read(struct phy_device *phydev,
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
148 static int kszphy_ack_interrupt(struct phy_device *phydev)
150 /* bit[7..0] int status, which is a read and clear register. */
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
155 return (rc < 0) ? rc : 0;
158 static int kszphy_config_intr(struct phy_device *phydev)
160 const struct kszphy_type *type = phydev->drv->driver_data;
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
206 case MII_KSZPHY_CTRL_1:
209 case MII_KSZPHY_CTRL_2:
216 temp = phy_read(phydev, reg);
222 temp &= ~(3 << shift);
223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
227 phydev_err(phydev, "failed to set led mode\n");
232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
235 static int kszphy_broadcast_disable(struct phy_device *phydev)
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
246 phydev_err(phydev, "failed to disable broadcast address\n");
251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
266 phydev_err(phydev, "failed to disable NAND tree mode\n");
271 /* Some config bits need to be set again on resume, handle them here. */
272 static int kszphy_config_reset(struct phy_device *phydev)
274 struct kszphy_priv *priv = phydev->priv;
277 if (priv->rmii_ref_clk_sel) {
278 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
281 "failed to set rmii reference clock\n");
286 if (priv->led_mode >= 0)
287 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
292 static int kszphy_config_init(struct phy_device *phydev)
294 struct kszphy_priv *priv = phydev->priv;
295 const struct kszphy_type *type;
302 if (type->has_broadcast_disable)
303 kszphy_broadcast_disable(phydev);
305 if (type->has_nand_tree_disable)
306 kszphy_nand_tree_disable(phydev);
308 return kszphy_config_reset(phydev);
311 static int ksz8041_config_init(struct phy_device *phydev)
313 struct device_node *of_node = phydev->mdio.dev.of_node;
315 /* Limit supported and advertised modes in fiber mode */
316 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
317 phydev->dev_flags |= MICREL_PHY_FXEN;
318 phydev->supported &= SUPPORTED_100baseT_Full |
319 SUPPORTED_100baseT_Half;
320 phydev->supported |= SUPPORTED_FIBRE;
321 phydev->advertising &= ADVERTISED_100baseT_Full |
322 ADVERTISED_100baseT_Half;
323 phydev->advertising |= ADVERTISED_FIBRE;
324 phydev->autoneg = AUTONEG_DISABLE;
327 return kszphy_config_init(phydev);
330 static int ksz8041_config_aneg(struct phy_device *phydev)
332 /* Skip auto-negotiation in fiber mode */
333 if (phydev->dev_flags & MICREL_PHY_FXEN) {
334 phydev->speed = SPEED_100;
338 return genphy_config_aneg(phydev);
341 static int ksz9021_load_values_from_of(struct phy_device *phydev,
342 const struct device_node *of_node,
344 const char *field1, const char *field2,
345 const char *field3, const char *field4)
354 if (!of_property_read_u32(of_node, field1, &val1))
357 if (!of_property_read_u32(of_node, field2, &val2))
360 if (!of_property_read_u32(of_node, field3, &val3))
363 if (!of_property_read_u32(of_node, field4, &val4))
370 newval = kszphy_extended_read(phydev, reg);
375 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
378 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
381 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
384 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
386 return kszphy_extended_write(phydev, reg, newval);
389 static int ksz9021_config_init(struct phy_device *phydev)
391 const struct device *dev = &phydev->mdio.dev;
392 const struct device_node *of_node = dev->of_node;
393 const struct device *dev_walker;
395 /* The Micrel driver has a deprecated option to place phy OF
396 * properties in the MAC node. Walk up the tree of devices to
397 * find a device with an OF node.
399 dev_walker = &phydev->mdio.dev;
401 of_node = dev_walker->of_node;
402 dev_walker = dev_walker->parent;
404 } while (!of_node && dev_walker);
407 ksz9021_load_values_from_of(phydev, of_node,
408 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
409 "txen-skew-ps", "txc-skew-ps",
410 "rxdv-skew-ps", "rxc-skew-ps");
411 ksz9021_load_values_from_of(phydev, of_node,
412 MII_KSZPHY_RX_DATA_PAD_SKEW,
413 "rxd0-skew-ps", "rxd1-skew-ps",
414 "rxd2-skew-ps", "rxd3-skew-ps");
415 ksz9021_load_values_from_of(phydev, of_node,
416 MII_KSZPHY_TX_DATA_PAD_SKEW,
417 "txd0-skew-ps", "txd1-skew-ps",
418 "txd2-skew-ps", "txd3-skew-ps");
423 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
424 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
426 #define KSZ9031_PS_TO_REG 60
428 /* Extended registers */
429 /* MMD Address 0x0 */
430 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
431 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
433 /* MMD Address 0x2 */
434 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
435 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
436 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
437 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
439 /* MMD Address 0x1C */
440 #define MII_KSZ9031RN_EDPD 0x23
441 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
443 static int ksz9031_extended_write(struct phy_device *phydev,
444 u8 mode, u32 dev_addr, u32 regnum, u16 val)
446 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
447 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
448 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
449 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
452 static int ksz9031_extended_read(struct phy_device *phydev,
453 u8 mode, u32 dev_addr, u32 regnum)
455 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
456 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
457 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
458 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
461 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
462 const struct device_node *of_node,
463 u16 reg, size_t field_sz,
464 const char *field[], u8 numfields)
466 int val[4] = {-1, -2, -3, -4};
473 for (i = 0; i < numfields; i++)
474 if (!of_property_read_u32(of_node, field[i], val + i))
480 if (matches < numfields)
481 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
485 maxval = (field_sz == 4) ? 0xf : 0x1f;
486 for (i = 0; i < numfields; i++)
487 if (val[i] != -(i + 1)) {
489 mask ^= maxval << (field_sz * i);
490 newval = (newval & mask) |
491 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
495 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
498 static int ksz9031_center_flp_timing(struct phy_device *phydev)
502 /* Center KSZ9031RNX FLP timing at 16ms. */
503 result = ksz9031_extended_write(phydev, OP_DATA, 0,
504 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
505 result = ksz9031_extended_write(phydev, OP_DATA, 0,
506 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
511 return genphy_restart_aneg(phydev);
514 /* Enable energy-detect power-down mode */
515 static int ksz9031_enable_edpd(struct phy_device *phydev)
519 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
522 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
523 reg | MII_KSZ9031RN_EDPD_ENABLE);
526 static int ksz9031_config_init(struct phy_device *phydev)
528 const struct device *dev = &phydev->mdio.dev;
529 const struct device_node *of_node = dev->of_node;
530 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
531 static const char *rx_data_skews[4] = {
532 "rxd0-skew-ps", "rxd1-skew-ps",
533 "rxd2-skew-ps", "rxd3-skew-ps"
535 static const char *tx_data_skews[4] = {
536 "txd0-skew-ps", "txd1-skew-ps",
537 "txd2-skew-ps", "txd3-skew-ps"
539 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
540 const struct device *dev_walker;
543 result = ksz9031_enable_edpd(phydev);
547 /* The Micrel driver has a deprecated option to place phy OF
548 * properties in the MAC node. Walk up the tree of devices to
549 * find a device with an OF node.
551 dev_walker = &phydev->mdio.dev;
553 of_node = dev_walker->of_node;
554 dev_walker = dev_walker->parent;
555 } while (!of_node && dev_walker);
558 ksz9031_of_load_skew_values(phydev, of_node,
559 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
562 ksz9031_of_load_skew_values(phydev, of_node,
563 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
566 ksz9031_of_load_skew_values(phydev, of_node,
567 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
570 ksz9031_of_load_skew_values(phydev, of_node,
571 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
575 return ksz9031_center_flp_timing(phydev);
578 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
579 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
580 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
581 static int ksz8873mll_read_status(struct phy_device *phydev)
586 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
588 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
590 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
591 phydev->duplex = DUPLEX_HALF;
593 phydev->duplex = DUPLEX_FULL;
595 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
596 phydev->speed = SPEED_10;
598 phydev->speed = SPEED_100;
601 phydev->pause = phydev->asym_pause = 0;
606 static int ksz9031_read_status(struct phy_device *phydev)
611 err = genphy_read_status(phydev);
615 /* Make sure the PHY is not broken. Read idle error count,
616 * and reset the PHY if it is maxed out.
618 regval = phy_read(phydev, MII_STAT1000);
619 if ((regval & 0xFF) == 0xFF) {
627 static int ksz8873mll_config_aneg(struct phy_device *phydev)
632 /* This routine returns -1 as an indication to the caller that the
633 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
634 * MMD extended PHY registers.
637 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
642 /* This routine does nothing since the Micrel ksz9021 does not support
643 * standard IEEE MMD extended PHY registers.
646 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
651 static int kszphy_get_sset_count(struct phy_device *phydev)
653 return ARRAY_SIZE(kszphy_hw_stats);
656 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
660 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
661 memcpy(data + i * ETH_GSTRING_LEN,
662 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
667 #define UINT64_MAX (u64)(~((u64)0))
669 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
671 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
672 struct kszphy_priv *priv = phydev->priv;
676 val = phy_read(phydev, stat.reg);
680 val = val & ((1 << stat.bits) - 1);
681 priv->stats[i] += val;
682 ret = priv->stats[i];
688 static void kszphy_get_stats(struct phy_device *phydev,
689 struct ethtool_stats *stats, u64 *data)
693 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
694 data[i] = kszphy_get_stat(phydev, i);
697 static int kszphy_suspend(struct phy_device *phydev)
699 /* Disable PHY Interrupts */
700 if (phy_interrupt_is_valid(phydev)) {
701 phydev->interrupts = PHY_INTERRUPT_DISABLED;
702 if (phydev->drv->config_intr)
703 phydev->drv->config_intr(phydev);
706 return genphy_suspend(phydev);
709 static int kszphy_resume(struct phy_device *phydev)
713 genphy_resume(phydev);
715 ret = kszphy_config_reset(phydev);
719 /* Enable PHY Interrupts */
720 if (phy_interrupt_is_valid(phydev)) {
721 phydev->interrupts = PHY_INTERRUPT_ENABLED;
722 if (phydev->drv->config_intr)
723 phydev->drv->config_intr(phydev);
729 static int kszphy_probe(struct phy_device *phydev)
731 const struct kszphy_type *type = phydev->drv->driver_data;
732 const struct device_node *np = phydev->mdio.dev.of_node;
733 struct kszphy_priv *priv;
737 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
745 if (type->led_mode_reg) {
746 ret = of_property_read_u32(np, "micrel,led-mode",
751 if (priv->led_mode > 3) {
752 phydev_err(phydev, "invalid led mode: 0x%02x\n",
760 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
761 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
762 if (!IS_ERR_OR_NULL(clk)) {
763 unsigned long rate = clk_get_rate(clk);
764 bool rmii_ref_clk_sel_25_mhz;
766 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
767 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
768 "micrel,rmii-reference-clock-select-25-mhz");
770 if (rate > 24500000 && rate < 25500000) {
771 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
772 } else if (rate > 49500000 && rate < 50500000) {
773 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
775 phydev_err(phydev, "Clock rate out of range: %ld\n",
781 /* Support legacy board-file configuration */
782 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
783 priv->rmii_ref_clk_sel = true;
784 priv->rmii_ref_clk_sel_val = true;
790 static struct phy_driver ksphy_driver[] = {
792 .phy_id = PHY_ID_KS8737,
793 .phy_id_mask = MICREL_PHY_ID_MASK,
794 .name = "Micrel KS8737",
795 .features = PHY_BASIC_FEATURES,
796 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
797 .driver_data = &ks8737_type,
798 .config_init = kszphy_config_init,
799 .config_aneg = genphy_config_aneg,
800 .read_status = genphy_read_status,
801 .ack_interrupt = kszphy_ack_interrupt,
802 .config_intr = kszphy_config_intr,
803 .suspend = genphy_suspend,
804 .resume = genphy_resume,
806 .phy_id = PHY_ID_KSZ8021,
807 .phy_id_mask = 0x00ffffff,
808 .name = "Micrel KSZ8021 or KSZ8031",
809 .features = PHY_BASIC_FEATURES,
810 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
811 .driver_data = &ksz8021_type,
812 .probe = kszphy_probe,
813 .config_init = kszphy_config_init,
814 .config_aneg = genphy_config_aneg,
815 .read_status = genphy_read_status,
816 .ack_interrupt = kszphy_ack_interrupt,
817 .config_intr = kszphy_config_intr,
818 .get_sset_count = kszphy_get_sset_count,
819 .get_strings = kszphy_get_strings,
820 .get_stats = kszphy_get_stats,
821 .suspend = genphy_suspend,
822 .resume = genphy_resume,
824 .phy_id = PHY_ID_KSZ8031,
825 .phy_id_mask = 0x00ffffff,
826 .name = "Micrel KSZ8031",
827 .features = PHY_BASIC_FEATURES,
828 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
829 .driver_data = &ksz8021_type,
830 .probe = kszphy_probe,
831 .config_init = kszphy_config_init,
832 .config_aneg = genphy_config_aneg,
833 .read_status = genphy_read_status,
834 .ack_interrupt = kszphy_ack_interrupt,
835 .config_intr = kszphy_config_intr,
836 .get_sset_count = kszphy_get_sset_count,
837 .get_strings = kszphy_get_strings,
838 .get_stats = kszphy_get_stats,
839 .suspend = genphy_suspend,
840 .resume = genphy_resume,
842 .phy_id = PHY_ID_KSZ8041,
843 .phy_id_mask = MICREL_PHY_ID_MASK,
844 .name = "Micrel KSZ8041",
845 .features = PHY_BASIC_FEATURES,
846 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
847 .driver_data = &ksz8041_type,
848 .probe = kszphy_probe,
849 .config_init = ksz8041_config_init,
850 .config_aneg = ksz8041_config_aneg,
851 .read_status = genphy_read_status,
852 .ack_interrupt = kszphy_ack_interrupt,
853 .config_intr = kszphy_config_intr,
854 .get_sset_count = kszphy_get_sset_count,
855 .get_strings = kszphy_get_strings,
856 .get_stats = kszphy_get_stats,
857 .suspend = genphy_suspend,
858 .resume = genphy_resume,
860 .phy_id = PHY_ID_KSZ8041RNLI,
861 .phy_id_mask = MICREL_PHY_ID_MASK,
862 .name = "Micrel KSZ8041RNLI",
863 .features = PHY_BASIC_FEATURES,
864 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
865 .driver_data = &ksz8041_type,
866 .probe = kszphy_probe,
867 .config_init = kszphy_config_init,
868 .config_aneg = genphy_config_aneg,
869 .read_status = genphy_read_status,
870 .ack_interrupt = kszphy_ack_interrupt,
871 .config_intr = kszphy_config_intr,
872 .get_sset_count = kszphy_get_sset_count,
873 .get_strings = kszphy_get_strings,
874 .get_stats = kszphy_get_stats,
875 .suspend = genphy_suspend,
876 .resume = genphy_resume,
878 .phy_id = PHY_ID_KSZ8051,
879 .phy_id_mask = MICREL_PHY_ID_MASK,
880 .name = "Micrel KSZ8051",
881 .features = PHY_BASIC_FEATURES,
882 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
883 .driver_data = &ksz8051_type,
884 .probe = kszphy_probe,
885 .config_init = kszphy_config_init,
886 .config_aneg = genphy_config_aneg,
887 .read_status = genphy_read_status,
888 .ack_interrupt = kszphy_ack_interrupt,
889 .config_intr = kszphy_config_intr,
890 .get_sset_count = kszphy_get_sset_count,
891 .get_strings = kszphy_get_strings,
892 .get_stats = kszphy_get_stats,
893 .suspend = genphy_suspend,
894 .resume = genphy_resume,
896 .phy_id = PHY_ID_KSZ8001,
897 .name = "Micrel KSZ8001 or KS8721",
898 .phy_id_mask = 0x00fffffc,
899 .features = PHY_BASIC_FEATURES,
900 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
901 .driver_data = &ksz8041_type,
902 .probe = kszphy_probe,
903 .config_init = kszphy_config_init,
904 .config_aneg = genphy_config_aneg,
905 .read_status = genphy_read_status,
906 .ack_interrupt = kszphy_ack_interrupt,
907 .config_intr = kszphy_config_intr,
908 .get_sset_count = kszphy_get_sset_count,
909 .get_strings = kszphy_get_strings,
910 .get_stats = kszphy_get_stats,
911 .suspend = genphy_suspend,
912 .resume = genphy_resume,
914 .phy_id = PHY_ID_KSZ8081,
915 .name = "Micrel KSZ8081 or KSZ8091",
916 .phy_id_mask = MICREL_PHY_ID_MASK,
917 .features = PHY_BASIC_FEATURES,
918 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
919 .driver_data = &ksz8081_type,
920 .probe = kszphy_probe,
921 .config_init = kszphy_config_init,
922 .config_aneg = genphy_config_aneg,
923 .read_status = genphy_read_status,
924 .ack_interrupt = kszphy_ack_interrupt,
925 .config_intr = kszphy_config_intr,
926 .get_sset_count = kszphy_get_sset_count,
927 .get_strings = kszphy_get_strings,
928 .get_stats = kszphy_get_stats,
929 .suspend = kszphy_suspend,
930 .resume = kszphy_resume,
932 .phy_id = PHY_ID_KSZ8061,
933 .name = "Micrel KSZ8061",
934 .phy_id_mask = MICREL_PHY_ID_MASK,
935 .features = PHY_BASIC_FEATURES,
936 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
937 .config_init = kszphy_config_init,
938 .config_aneg = genphy_config_aneg,
939 .read_status = genphy_read_status,
940 .ack_interrupt = kszphy_ack_interrupt,
941 .config_intr = kszphy_config_intr,
942 .suspend = genphy_suspend,
943 .resume = genphy_resume,
945 .phy_id = PHY_ID_KSZ9021,
946 .phy_id_mask = 0x000ffffe,
947 .name = "Micrel KSZ9021 Gigabit PHY",
948 .features = PHY_GBIT_FEATURES,
949 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
950 .driver_data = &ksz9021_type,
951 .probe = kszphy_probe,
952 .config_init = ksz9021_config_init,
953 .config_aneg = genphy_config_aneg,
954 .read_status = genphy_read_status,
955 .ack_interrupt = kszphy_ack_interrupt,
956 .config_intr = kszphy_config_intr,
957 .get_sset_count = kszphy_get_sset_count,
958 .get_strings = kszphy_get_strings,
959 .get_stats = kszphy_get_stats,
960 .suspend = genphy_suspend,
961 .resume = genphy_resume,
962 .read_mmd = ksz9021_rd_mmd_phyreg,
963 .write_mmd = ksz9021_wr_mmd_phyreg,
965 .phy_id = PHY_ID_KSZ9031,
966 .phy_id_mask = MICREL_PHY_ID_MASK,
967 .name = "Micrel KSZ9031 Gigabit PHY",
968 .features = PHY_GBIT_FEATURES,
969 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
970 .driver_data = &ksz9021_type,
971 .probe = kszphy_probe,
972 .config_init = ksz9031_config_init,
973 .config_aneg = genphy_config_aneg,
974 .read_status = ksz9031_read_status,
975 .ack_interrupt = kszphy_ack_interrupt,
976 .config_intr = kszphy_config_intr,
977 .get_sset_count = kszphy_get_sset_count,
978 .get_strings = kszphy_get_strings,
979 .get_stats = kszphy_get_stats,
980 .suspend = genphy_suspend,
981 .resume = kszphy_resume,
983 .phy_id = PHY_ID_KSZ8873MLL,
984 .phy_id_mask = MICREL_PHY_ID_MASK,
985 .name = "Micrel KSZ8873MLL Switch",
986 .flags = PHY_HAS_MAGICANEG,
987 .config_init = kszphy_config_init,
988 .config_aneg = ksz8873mll_config_aneg,
989 .read_status = ksz8873mll_read_status,
990 .suspend = genphy_suspend,
991 .resume = genphy_resume,
993 .phy_id = PHY_ID_KSZ886X,
994 .phy_id_mask = MICREL_PHY_ID_MASK,
995 .name = "Micrel KSZ886X Switch",
996 .features = PHY_BASIC_FEATURES,
997 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
998 .config_init = kszphy_config_init,
999 .config_aneg = genphy_config_aneg,
1000 .read_status = genphy_read_status,
1001 .suspend = genphy_suspend,
1002 .resume = genphy_resume,
1004 .phy_id = PHY_ID_KSZ8795,
1005 .phy_id_mask = MICREL_PHY_ID_MASK,
1006 .name = "Micrel KSZ8795",
1007 .features = PHY_BASIC_FEATURES,
1008 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1009 .config_init = kszphy_config_init,
1010 .config_aneg = ksz8873mll_config_aneg,
1011 .read_status = ksz8873mll_read_status,
1012 .suspend = genphy_suspend,
1013 .resume = genphy_resume,
1016 module_phy_driver(ksphy_driver);
1018 MODULE_DESCRIPTION("Micrel PHY driver");
1019 MODULE_AUTHOR("David J. Choi");
1020 MODULE_LICENSE("GPL");
1022 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1023 { PHY_ID_KSZ9021, 0x000ffffe },
1024 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1025 { PHY_ID_KSZ8001, 0x00fffffc },
1026 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1027 { PHY_ID_KSZ8021, 0x00ffffff },
1028 { PHY_ID_KSZ8031, 0x00ffffff },
1029 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1030 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1031 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1032 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1033 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1034 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1038 MODULE_DEVICE_TABLE(mdio, micrel_tbl);