3 * Elecsys Corporation <www.elecsyscorp.com>
4 * Kevin Smith <kevin.smith@elecsyscorp.com>
8 * Marvell Semiconductor <www.marvell.com>
9 * Prafulla Wadaskar <prafulla@marvell.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 * PHY driver for mv88e61xx ethernet switches.
17 * This driver configures the mv88e61xx for basic use as a PHY. The switch
18 * supports a VLAN configuration that determines how traffic will be routed
19 * between the ports. This driver uses a simple configuration that routes
20 * traffic from each PHY port only to the CPU port, and from the CPU port to
23 * The configuration determines which PHY ports to activate using the
24 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
25 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
26 * connected to unless it is connected over a PHY interface (not MII).
28 * This driver was written for and tested on the mv88e6176 with an SGMII
29 * connection. Other configurations should be supported, but some additions or
30 * changes may be required.
41 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
44 #define PORT_MASK ((1 << PORT_COUNT) - 1)
46 /* Device addresses */
47 #define DEVADDR_PHY(p) (p)
48 #define DEVADDR_PORT(p) (0x10 + (p))
49 #define DEVADDR_SERDES 0x0F
50 #define DEVADDR_GLOBAL_1 0x1B
51 #define DEVADDR_GLOBAL_2 0x1C
53 /* SMI indirection registers for multichip addressing mode */
54 #define SMI_CMD_REG 0x00
55 #define SMI_DATA_REG 0x01
57 /* Global registers */
58 #define GLOBAL1_STATUS 0x00
59 #define GLOBAL1_CTRL 0x04
60 #define GLOBAL1_MON_CTRL 0x1A
62 /* Global 2 registers */
63 #define GLOBAL2_REG_PHY_CMD 0x18
64 #define GLOBAL2_REG_PHY_DATA 0x19
67 #define PORT_REG_STATUS 0x00
68 #define PORT_REG_PHYS_CTRL 0x01
69 #define PORT_REG_SWITCH_ID 0x03
70 #define PORT_REG_CTRL 0x04
71 #define PORT_REG_VLAN_MAP 0x06
72 #define PORT_REG_VLAN_ID 0x07
75 #define PHY_REG_CTRL1 0x10
76 #define PHY_REG_STATUS1 0x11
77 #define PHY_REG_PAGE 0x16
79 /* Serdes registers */
80 #define SERDES_REG_CTRL_1 0x10
82 /* Phy page numbers */
83 #define PHY_PAGE_COPPER 0
84 #define PHY_PAGE_SERDES 1
87 #define GLOBAL1_CTRL_SWRESET BIT(15)
89 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
90 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
92 #define PORT_REG_STATUS_LINK BIT(11)
93 #define PORT_REG_STATUS_DUPLEX BIT(10)
95 #define PORT_REG_STATUS_SPEED_SHIFT 8
96 #define PORT_REG_STATUS_SPEED_WIDTH 2
97 #define PORT_REG_STATUS_SPEED_10 0
98 #define PORT_REG_STATUS_SPEED_100 1
99 #define PORT_REG_STATUS_SPEED_1000 2
101 #define PORT_REG_STATUS_CMODE_MASK 0xF
102 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
103 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
104 #define PORT_REG_STATUS_CMODE_SGMII 0xa
106 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
107 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
109 #define PORT_REG_CTRL_PSTATE_SHIFT 0
110 #define PORT_REG_CTRL_PSTATE_WIDTH 2
112 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
113 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
115 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
116 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
118 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
120 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
121 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
124 #define PORT_REG_CTRL_PSTATE_DISABLED 0
125 #define PORT_REG_CTRL_PSTATE_FORWARD 3
127 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
128 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
129 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131 /* PHY Status Register */
132 #define PHY_REG_STATUS1_SPEED 0xc000
133 #define PHY_REG_STATUS1_GBIT 0x8000
134 #define PHY_REG_STATUS1_100 0x4000
135 #define PHY_REG_STATUS1_DUPLEX 0x2000
136 #define PHY_REG_STATUS1_SPDDONE 0x0800
137 #define PHY_REG_STATUS1_LINK 0x0400
138 #define PHY_REG_STATUS1_ENERGY 0x0010
141 * Macros for building commands for indirect addressing modes. These are valid
142 * for both the indirect multichip addressing mode and the PHY indirection
143 * required for the writes to any PHY register.
145 #define SMI_BUSY BIT(15)
146 #define SMI_CMD_CLAUSE_22 BIT(12)
147 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
148 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
151 SMI_CMD_CLAUSE_22_OP_READ)
152 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
153 SMI_CMD_CLAUSE_22_OP_WRITE)
155 #define SMI_CMD_ADDR_SHIFT 5
156 #define SMI_CMD_ADDR_WIDTH 5
157 #define SMI_CMD_REG_SHIFT 0
158 #define SMI_CMD_REG_WIDTH 5
160 /* Check for required macros */
161 #ifndef CONFIG_MV88E61XX_PHY_PORTS
162 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
165 #ifndef CONFIG_MV88E61XX_CPU_PORT
166 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
169 /* ID register values for different switch models */
170 #define PORT_SWITCH_ID_6172 0x1720
171 #define PORT_SWITCH_ID_6176 0x1760
172 #define PORT_SWITCH_ID_6240 0x2400
173 #define PORT_SWITCH_ID_6352 0x3520
175 struct mv88e61xx_phy_priv {
176 struct mii_dev *mdio_bus;
181 static inline int smi_cmd(int cmd, int addr, int reg)
183 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
185 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
189 static inline int smi_cmd_read(int addr, int reg)
191 return smi_cmd(SMI_CMD_READ, addr, reg);
194 static inline int smi_cmd_write(int addr, int reg)
196 return smi_cmd(SMI_CMD_WRITE, addr, reg);
199 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
204 /* Wait for the current SMI indirect command to complete */
205 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
211 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
212 if (val >= 0 && (val & SMI_BUSY) == 0)
218 puts("SMI busy timeout\n");
223 * The mv88e61xx has three types of addresses: the smi bus address, the device
224 * address, and the register address. The smi bus address distinguishes it on
225 * the smi bus from other PHYs or switches. The device address determines
226 * which on-chip register set you are reading/writing (the various PHYs, their
227 * associated ports, or global configuration registers). The register address
228 * is the offset of the register you are reading/writing.
230 * When the mv88e61xx is hardware configured to have address zero, it behaves in
231 * single-chip addressing mode, where it responds to all SMI addresses, using
232 * the smi address as its device address. This obviously only works when this
233 * is the only chip on the SMI bus. This allows the driver to access device
234 * registers without using indirection. When the chip is configured to a
235 * non-zero address, it only responds to that SMI address and requires indirect
236 * writes to access the different device addresses.
238 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
240 struct mv88e61xx_phy_priv *priv = phydev->priv;
241 struct mii_dev *mdio_bus = priv->mdio_bus;
242 int smi_addr = priv->smi_addr;
245 /* In single-chip mode, the device can be addressed directly */
247 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
249 /* Wait for the bus to become free */
250 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
254 /* Issue the read command */
255 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
256 smi_cmd_read(dev, reg));
260 /* Wait for the read command to complete */
261 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
266 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
270 return bitfield_extract(res, 0, 16);
273 /* See the comment above mv88e61xx_reg_read */
274 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
277 struct mv88e61xx_phy_priv *priv = phydev->priv;
278 struct mii_dev *mdio_bus = priv->mdio_bus;
279 int smi_addr = priv->smi_addr;
282 /* In single-chip mode, the device can be addressed directly */
284 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
288 /* Wait for the bus to become free */
289 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
293 /* Set the data to write */
294 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
299 /* Issue the write command */
300 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
301 smi_cmd_write(dev, reg));
305 /* Wait for the write command to complete */
306 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
313 static int mv88e61xx_phy_wait(struct phy_device *phydev)
319 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
320 GLOBAL2_REG_PHY_CMD);
321 if (val >= 0 && (val & SMI_BUSY) == 0)
330 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
333 struct phy_device *phydev;
336 phydev = (struct phy_device *)smi_wrapper->priv;
338 /* Issue command to read */
339 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
341 smi_cmd_read(dev, reg));
343 /* Wait for data to be read */
344 res = mv88e61xx_phy_wait(phydev);
348 /* Read retrieved data */
349 return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
350 GLOBAL2_REG_PHY_DATA);
353 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
354 int devad, int reg, u16 data)
356 struct phy_device *phydev;
359 phydev = (struct phy_device *)smi_wrapper->priv;
361 /* Set the data to write */
362 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
363 GLOBAL2_REG_PHY_DATA, data);
366 /* Issue the write command */
367 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
369 smi_cmd_write(dev, reg));
373 /* Wait for command to complete */
374 return mv88e61xx_phy_wait(phydev);
377 /* Wrapper function to make calls to phy_read_indirect simpler */
378 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
380 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
381 MDIO_DEVAD_NONE, reg);
384 /* Wrapper function to make calls to phy_read_indirect simpler */
385 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
388 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
389 MDIO_DEVAD_NONE, reg, val);
392 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
394 return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
397 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
400 return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
403 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
405 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
408 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
412 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
418 static bool mv88e61xx_6352_family(struct phy_device *phydev)
420 struct mv88e61xx_phy_priv *priv = phydev->priv;
423 case PORT_SWITCH_ID_6172:
424 case PORT_SWITCH_ID_6176:
425 case PORT_SWITCH_ID_6240:
426 case PORT_SWITCH_ID_6352:
432 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
436 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
439 return res & PORT_REG_STATUS_CMODE_MASK;
442 static int mv88e61xx_parse_status(struct phy_device *phydev)
445 unsigned int mii_reg;
447 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
449 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
450 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
453 puts("Waiting for PHY realtime link");
454 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
455 /* Timeout reached ? */
456 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
457 puts(" TIMEOUT !\n");
462 if ((i++ % 1000) == 0)
465 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
469 udelay(500000); /* another 500 ms (results in faster booting) */
471 if (mii_reg & PHY_REG_STATUS1_LINK)
477 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
478 phydev->duplex = DUPLEX_FULL;
480 phydev->duplex = DUPLEX_HALF;
482 speed = mii_reg & PHY_REG_STATUS1_SPEED;
485 case PHY_REG_STATUS1_GBIT:
486 phydev->speed = SPEED_1000;
488 case PHY_REG_STATUS1_100:
489 phydev->speed = SPEED_100;
492 phydev->speed = SPEED_10;
499 static int mv88e61xx_switch_reset(struct phy_device *phydev)
505 /* Disable all ports */
506 for (port = 0; port < PORT_COUNT; port++) {
507 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
510 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
511 PORT_REG_CTRL_PSTATE_WIDTH,
512 PORT_REG_CTRL_PSTATE_DISABLED);
513 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
518 /* Wait 2 ms for queues to drain */
522 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
525 val |= GLOBAL1_CTRL_SWRESET;
526 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
531 /* Wait up to 1 second for switch reset complete */
532 for (time = 1000; time; time--) {
533 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
535 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
545 static int mv88e61xx_serdes_init(struct phy_device *phydev)
549 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
553 /* Power up serdes module */
554 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
557 val &= ~(BMCR_PDOWN);
558 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
565 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
569 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
572 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
573 PORT_REG_CTRL_PSTATE_WIDTH,
574 PORT_REG_CTRL_PSTATE_FORWARD);
575 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
582 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
587 /* Set VID to port number plus one */
588 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
591 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
592 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
594 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
599 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
602 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
603 PORT_REG_VLAN_MAP_TABLE_WIDTH,
605 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
612 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
618 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
621 if (!(val & PORT_REG_STATUS_LINK)) {
622 /* Temporarily force link to read port configuration */
626 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
629 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
630 PORT_REG_PHYS_CTRL_LINK_VALUE);
631 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
636 /* Wait for status register to reflect forced link */
638 val = mv88e61xx_port_read(phydev, port,
642 if (val & PORT_REG_STATUS_LINK)
652 if (val & PORT_REG_STATUS_DUPLEX)
653 phydev->duplex = DUPLEX_FULL;
655 phydev->duplex = DUPLEX_HALF;
657 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
658 PORT_REG_STATUS_SPEED_WIDTH);
660 case PORT_REG_STATUS_SPEED_1000:
661 phydev->speed = SPEED_1000;
663 case PORT_REG_STATUS_SPEED_100:
664 phydev->speed = SPEED_100;
667 phydev->speed = SPEED_10;
675 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
678 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
679 PORT_REG_PHYS_CTRL_LINK_VALUE);
680 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
689 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
694 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
697 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
698 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
699 CONFIG_MV88E61XX_CPU_PORT);
700 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
701 GLOBAL1_MON_CTRL, val);
705 /* Allow CPU to route to any port */
706 val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
707 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
711 /* Enable CPU port */
712 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
716 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
720 /* If CPU is connected to serdes, initialize serdes */
721 if (mv88e61xx_6352_family(phydev)) {
722 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
725 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
726 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
727 val == PORT_REG_STATUS_CMODE_SGMII) {
728 val = mv88e61xx_serdes_init(phydev);
737 static int mv88e61xx_switch_init(struct phy_device *phydev)
745 res = mv88e61xx_switch_reset(phydev);
749 res = mv88e61xx_set_cpu_port(phydev);
758 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
762 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
765 val &= ~(BMCR_PDOWN);
766 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
773 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
778 * Enable energy-detect sensing on PHY, used to determine when a PHY
779 * port is physically connected
781 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
784 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
785 PHY_REG_CTRL1_ENERGY_DET_WIDTH,
786 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
787 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
794 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
798 val = mv88e61xx_port_enable(phydev, phy);
802 val = mv88e61xx_port_set_vlan(phydev, phy,
803 1 << CONFIG_MV88E61XX_CPU_PORT);
810 static int mv88e61xx_probe(struct phy_device *phydev)
812 struct mii_dev *smi_wrapper;
813 struct mv88e61xx_phy_priv *priv;
816 res = mv88e61xx_hw_reset(phydev);
820 priv = malloc(sizeof(*priv));
824 memset(priv, 0, sizeof(*priv));
827 * This device requires indirect reads/writes to the PHY registers
828 * which the generic PHY code can't handle. Make a wrapper MII device
829 * to handle reads/writes
831 smi_wrapper = mdio_alloc();
838 * Store the mdio bus in the private data, as we are going to replace
839 * the bus with the wrapper bus
841 priv->mdio_bus = phydev->bus;
844 * Store the smi bus address in private data. This lets us use the
845 * phydev addr field for device address instead, as the genphy code
848 priv->smi_addr = phydev->addr;
851 * Store the phy_device in the wrapper mii device. This lets us get it
852 * back when genphy functions call phy_read/phy_write.
854 smi_wrapper->priv = phydev;
855 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
856 smi_wrapper->read = mv88e61xx_phy_read_indirect;
857 smi_wrapper->write = mv88e61xx_phy_write_indirect;
859 /* Replace the bus with the wrapper device */
860 phydev->bus = smi_wrapper;
864 priv->id = mv88e61xx_get_switch_id(phydev);
869 static int mv88e61xx_phy_config(struct phy_device *phydev)
875 res = mv88e61xx_switch_init(phydev);
879 for (i = 0; i < PORT_COUNT; i++) {
880 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
883 res = mv88e61xx_phy_enable(phydev, i);
885 printf("Error enabling PHY %i\n", i);
888 res = mv88e61xx_phy_setup(phydev, i);
890 printf("Error setting up PHY %i\n", i);
893 res = mv88e61xx_phy_config_port(phydev, i);
895 printf("Error configuring PHY %i\n", i);
899 res = genphy_config_aneg(phydev);
901 printf("Error setting PHY %i autoneg\n", i);
904 res = phy_reset(phydev);
906 printf("Error resetting PHY %i\n", i);
910 /* Return success if any PHY succeeds */
918 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
922 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
927 * After reset, the energy detect signal remains high for a few seconds
928 * regardless of whether a cable is connected. This function will
929 * return false positives during this time.
931 return (val & PHY_REG_STATUS1_ENERGY) == 0;
934 static int mv88e61xx_phy_startup(struct phy_device *phydev)
939 int speed = phydev->speed;
940 int duplex = phydev->duplex;
942 for (i = 0; i < PORT_COUNT; i++) {
943 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
945 if (!mv88e61xx_phy_is_connected(phydev))
947 res = genphy_update_link(phydev);
950 res = mv88e61xx_parse_status(phydev);
953 link = (link || phydev->link);
958 /* Restore CPU interface speed and duplex after it was changed for
960 phydev->speed = speed;
961 phydev->duplex = duplex;
966 static struct phy_driver mv88e61xx_driver = {
967 .name = "Marvell MV88E61xx",
970 .features = PHY_GBIT_FEATURES,
971 .probe = mv88e61xx_probe,
972 .config = mv88e61xx_phy_config,
973 .startup = mv88e61xx_phy_startup,
974 .shutdown = &genphy_shutdown,
977 int phy_mv88e61xx_init(void)
979 phy_register(&mv88e61xx_driver);
985 * Overload weak get_phy_id definition since we need non-standard functions
986 * to read PHY registers
988 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
990 struct phy_device temp_phy;
991 struct mv88e61xx_phy_priv temp_priv;
992 struct mii_dev temp_mii;
996 * Buid temporary data structures that the chip reading code needs to
999 temp_priv.mdio_bus = bus;
1000 temp_priv.smi_addr = smi_addr;
1001 temp_phy.priv = &temp_priv;
1002 temp_mii.priv = &temp_phy;
1004 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1008 *phy_id = val << 16;
1010 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1014 *phy_id |= (val & 0xffff);