2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
28 #include <linux/vmalloc.h>
31 #include <asm/byteorder.h>
33 #include "qlcnic_hdr.h"
35 #define _QLCNIC_LINUX_MAJOR 5
36 #define _QLCNIC_LINUX_MINOR 0
37 #define _QLCNIC_LINUX_SUBVERSION 15
38 #define QLCNIC_LINUX_VERSIONID "5.0.15"
39 #define QLCNIC_DRV_IDC_VER 0x01
40 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
41 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
43 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
44 #define _major(v) (((v) >> 24) & 0xff)
45 #define _minor(v) (((v) >> 16) & 0xff)
46 #define _build(v) ((v) & 0xffff)
48 /* version in image has weird encoding:
51 * 31:16 - build (little endian)
53 #define QLCNIC_DECODE_VERSION(v) \
54 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
56 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
57 #define QLCNIC_NUM_FLASH_SECTORS (64)
58 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
59 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
60 * QLCNIC_FLASH_SECTOR_SIZE)
62 #define RCV_DESC_RINGSIZE(rds_ring) \
63 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
64 #define RCV_BUFF_RINGSIZE(rds_ring) \
65 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
66 #define STATUS_DESC_RINGSIZE(sds_ring) \
67 (sizeof(struct status_desc) * (sds_ring)->num_desc)
68 #define TX_BUFF_RINGSIZE(tx_ring) \
69 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
70 #define TX_DESC_RINGSIZE(tx_ring) \
71 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
73 #define QLCNIC_P3P_A0 0x50
75 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
77 #define FIRST_PAGE_GROUP_START 0
78 #define FIRST_PAGE_GROUP_END 0x100000
80 #define P3P_MAX_MTU (9600)
81 #define P3P_MIN_MTU (68)
82 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
84 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
85 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
86 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
87 #define QLCNIC_LRO_BUFFER_EXTRA 2048
89 /* Opcodes to be used with the commands */
90 #define TX_ETHER_PKT 0x01
91 #define TX_TCP_PKT 0x02
92 #define TX_UDP_PKT 0x03
93 #define TX_IP_PKT 0x04
94 #define TX_TCP_LSO 0x05
95 #define TX_TCP_LSO6 0x06
96 #define TX_TCPV6_PKT 0x0b
97 #define TX_UDPV6_PKT 0x0c
100 #define MAX_TSO_HEADER_DESC 2
101 #define MGMT_CMD_DESC_RESV 4
102 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
103 + MGMT_CMD_DESC_RESV)
104 #define QLCNIC_MAX_TX_TIMEOUTS 2
107 * Following are the states of the Phantom. Phantom will set them and
108 * Host will read to check if the fields are correct.
110 #define PHAN_INITIALIZE_FAILED 0xffff
111 #define PHAN_INITIALIZE_COMPLETE 0xff01
113 /* Host writes the following to notify that it has done the init-handshake */
114 #define PHAN_INITIALIZE_ACK 0xf00f
115 #define PHAN_PEG_RCV_INITIALIZED 0xff01
117 #define NUM_RCV_DESC_RINGS 3
118 #define NUM_STS_DESC_RINGS 4
120 #define RCV_RING_NORMAL 0
121 #define RCV_RING_JUMBO 1
123 #define MIN_CMD_DESCRIPTORS 64
124 #define MIN_RCV_DESCRIPTORS 64
125 #define MIN_JUMBO_DESCRIPTORS 32
127 #define MAX_CMD_DESCRIPTORS 1024
128 #define MAX_RCV_DESCRIPTORS_1G 4096
129 #define MAX_RCV_DESCRIPTORS_10G 8192
130 #define MAX_RCV_DESCRIPTORS_VF 2048
131 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
132 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
134 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
135 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
136 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
137 #define MAX_RDS_RINGS 2
139 #define get_next_index(index, length) \
140 (((index) + 1) & ((length) - 1))
143 * Following data structures describe the descriptors that will be used.
144 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
145 * we are doing LSO (above the 1500 size packet) only.
148 #define FLAGS_VLAN_TAGGED 0x10
149 #define FLAGS_VLAN_OOB 0x40
151 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
152 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
153 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
154 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
155 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
158 #define qlcnic_set_tx_port(_desc, _port) \
159 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
161 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
162 ((_desc)->flags_opcode |= \
163 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
165 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
166 ((_desc)->nfrags__length = \
167 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
169 struct cmd_desc_type0 {
170 u8 tcp_hdr_offset; /* For LSO only */
171 u8 ip_hdr_offset; /* For LSO only */
172 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
173 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
177 __le16 reference_handle;
179 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
180 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
181 __le16 conn_id; /* IPSec offoad only */
186 __le16 buffer_length[4];
190 u8 eth_addr[ETH_ALEN];
193 } __attribute__ ((aligned(64)));
195 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
197 __le16 reference_handle;
199 __le32 buffer_length; /* allocated buffer length (usually 2K) */
203 /* opcode field in status_desc */
204 #define QLCNIC_SYN_OFFLOAD 0x03
205 #define QLCNIC_RXPKT_DESC 0x04
206 #define QLCNIC_OLD_RXPKT_DESC 0x3f
207 #define QLCNIC_RESPONSE_DESC 0x05
208 #define QLCNIC_LRO_DESC 0x12
210 /* for status field in status_desc */
211 #define STATUS_CKSUM_LOOP 0
212 #define STATUS_CKSUM_OK 2
214 /* owner bits of status_desc */
215 #define STATUS_OWNER_HOST (0x1ULL << 56)
216 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
218 /* Status descriptor:
219 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
220 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
221 53-55 desc_cnt, 56-57 owner, 58-63 opcode
223 #define qlcnic_get_sts_port(sts_data) \
225 #define qlcnic_get_sts_status(sts_data) \
226 (((sts_data) >> 4) & 0x0F)
227 #define qlcnic_get_sts_type(sts_data) \
228 (((sts_data) >> 8) & 0x0F)
229 #define qlcnic_get_sts_totallength(sts_data) \
230 (((sts_data) >> 12) & 0xFFFF)
231 #define qlcnic_get_sts_refhandle(sts_data) \
232 (((sts_data) >> 28) & 0xFFFF)
233 #define qlcnic_get_sts_prot(sts_data) \
234 (((sts_data) >> 44) & 0x0F)
235 #define qlcnic_get_sts_pkt_offset(sts_data) \
236 (((sts_data) >> 48) & 0x1F)
237 #define qlcnic_get_sts_desc_cnt(sts_data) \
238 (((sts_data) >> 53) & 0x7)
239 #define qlcnic_get_sts_opcode(sts_data) \
240 (((sts_data) >> 58) & 0x03F)
242 #define qlcnic_get_lro_sts_refhandle(sts_data) \
243 ((sts_data) & 0x0FFFF)
244 #define qlcnic_get_lro_sts_length(sts_data) \
245 (((sts_data) >> 16) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
247 (((sts_data) >> 32) & 0x0FF)
248 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
249 (((sts_data) >> 40) & 0x0FF)
250 #define qlcnic_get_lro_sts_timestamp(sts_data) \
251 (((sts_data) >> 48) & 0x1)
252 #define qlcnic_get_lro_sts_type(sts_data) \
253 (((sts_data) >> 49) & 0x7)
254 #define qlcnic_get_lro_sts_push_flag(sts_data) \
255 (((sts_data) >> 52) & 0x1)
256 #define qlcnic_get_lro_sts_seq_number(sts_data) \
257 ((sts_data) & 0x0FFFFFFFF)
261 __le64 status_desc_data[2];
262 } __attribute__ ((aligned(16)));
264 /* UNIFIED ROMIMAGE */
265 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
266 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
267 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
268 #define QLCNIC_UNI_DIR_SECT_FW 0x7
271 #define QLCNIC_UNI_CHIP_REV_OFF 10
272 #define QLCNIC_UNI_FLAGS_OFF 11
273 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
274 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
275 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
277 struct uni_table_desc{
284 struct uni_data_desc{
290 /* Flash Defines and Structures */
291 #define QLCNIC_FLT_LOCATION 0x3F1000
292 #define QLCNIC_FW_IMAGE_REGION 0x74
293 struct qlcnic_flt_header {
300 struct qlcnic_flt_entry {
310 /* Magic number to let user know flash is programmed */
311 #define QLCNIC_BDINFO_MAGIC 0x12345678
313 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
314 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
315 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
316 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
317 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
318 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
319 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
320 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
321 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
322 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
323 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
324 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
325 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
326 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
328 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
330 /* Flash memory map */
331 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
332 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
333 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
334 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
336 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
337 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
338 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
339 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
341 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
342 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
344 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
345 #define QLCNIC_UNIFIED_ROMIMAGE 0
346 #define QLCNIC_FLASH_ROMIMAGE 1
347 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
349 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
350 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
352 extern char qlcnic_driver_name[];
354 /* Number of status descriptors to handle per interrupt */
355 #define MAX_STATUS_HANDLE (64)
358 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
359 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
361 struct qlcnic_skb_frag {
366 /* Following defines are for the state of the buffers */
367 #define QLCNIC_BUFFER_FREE 0
368 #define QLCNIC_BUFFER_BUSY 1
371 * There will be one qlcnic_buffer per skb packet. These will be
372 * used to save the dma info for pci_unmap_page()
374 struct qlcnic_cmd_buffer {
376 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
380 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
381 struct qlcnic_rx_buffer {
384 struct list_head list;
389 #define QLCNIC_GBE 0x01
390 #define QLCNIC_XGBE 0x02
393 * One hardware_context{} per adapter
394 * contains interrupt info as well shared hardware info.
396 struct qlcnic_hardware_context {
397 void __iomem *pci_base0;
398 void __iomem *ocm_win_crb;
400 unsigned long pci_len0;
403 struct mutex mem_lock;
412 struct qlcnic_adapter_stats {
426 u64 skb_alloc_failure;
428 u64 rx_dma_map_error;
429 u64 tx_dma_map_error;
433 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
434 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
436 struct qlcnic_host_rds_ring {
442 void __iomem *crb_rcv_producer;
443 struct rcv_desc *desc_head;
444 struct qlcnic_rx_buffer *rx_buf_arr;
445 struct list_head free_list;
447 dma_addr_t phys_addr;
450 struct qlcnic_host_sds_ring {
453 void __iomem *crb_sts_consumer;
454 void __iomem *crb_intr_mask;
456 struct status_desc *desc_head;
457 struct qlcnic_adapter *adapter;
458 struct napi_struct napi;
459 struct list_head free_list[NUM_RCV_DESC_RINGS];
463 dma_addr_t phys_addr;
464 char name[IFNAMSIZ+4];
467 struct qlcnic_host_tx_ring {
471 void __iomem *crb_cmd_producer;
474 struct netdev_queue *txq;
476 struct qlcnic_cmd_buffer *cmd_buf_arr;
477 struct cmd_desc_type0 *desc_head;
478 dma_addr_t phys_addr;
479 dma_addr_t hw_cons_phys_addr;
483 * Receive context. There is one such structure per instance of the
484 * receive processing. Any state information that is relevant to
485 * the receive, and is must be in this structure. The global data may be
488 struct qlcnic_recv_context {
489 struct qlcnic_host_rds_ring *rds_rings;
490 struct qlcnic_host_sds_ring *sds_rings;
497 /* HW context creation */
499 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
500 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
501 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
503 #define QLCNIC_CDRP_CMD_BIT 0x80000000
506 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
507 * in the crb QLCNIC_CDRP_CRB_OFFSET.
509 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
510 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
512 #define QLCNIC_CDRP_RSP_OK 0x00000001
513 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
514 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
517 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
518 * the crb QLCNIC_CDRP_CRB_OFFSET.
520 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
521 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
523 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
524 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
525 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
526 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
527 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
528 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
529 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
530 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
531 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
532 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
533 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
534 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
535 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
536 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
537 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
538 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
539 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
540 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
541 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
543 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
544 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
545 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
546 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
547 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
548 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
549 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
550 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
551 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
552 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
554 #define QLCNIC_RCODE_SUCCESS 0
555 #define QLCNIC_RCODE_TIMEOUT 17
556 #define QLCNIC_DESTROY_CTX_RESET 0
559 * Capabilities Announced
561 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
562 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
563 #define QLCNIC_CAP0_LSO (1 << 6)
564 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
565 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
566 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
571 #define QLCNIC_HOST_CTX_STATE_FREED 0
572 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
578 struct qlcnic_hostrq_sds_ring {
579 __le64 host_phys_addr; /* Ring base addr */
580 __le32 ring_size; /* Ring entries */
582 __le16 rsvd; /* Padding */
585 struct qlcnic_hostrq_rds_ring {
586 __le64 host_phys_addr; /* Ring base addr */
587 __le64 buff_size; /* Packet buffer size */
588 __le32 ring_size; /* Ring entries */
589 __le32 ring_kind; /* Class of ring */
592 struct qlcnic_hostrq_rx_ctx {
593 __le64 host_rsp_dma_addr; /* Response dma'd here */
594 __le32 capabilities[4]; /* Flag bit vector */
595 __le32 host_int_crb_mode; /* Interrupt crb usage */
596 __le32 host_rds_crb_mode; /* RDS crb usage */
597 /* These ring offsets are relative to data[0] below */
598 __le32 rds_ring_offset; /* Offset to RDS config */
599 __le32 sds_ring_offset; /* Offset to SDS config */
600 __le16 num_rds_rings; /* Count of RDS rings */
601 __le16 num_sds_rings; /* Count of SDS rings */
602 __le16 valid_field_offset;
605 u8 reserved[128]; /* reserve space for future expansion*/
606 /* MUST BE 64-bit aligned.
607 The following is packed:
609 - N hostrq_sds_rings */
613 struct qlcnic_cardrsp_rds_ring{
614 __le32 host_producer_crb; /* Crb to use */
615 __le32 rsvd1; /* Padding */
618 struct qlcnic_cardrsp_sds_ring {
619 __le32 host_consumer_crb; /* Crb to use */
620 __le32 interrupt_crb; /* Crb to use */
623 struct qlcnic_cardrsp_rx_ctx {
624 /* These ring offsets are relative to data[0] below */
625 __le32 rds_ring_offset; /* Offset to RDS config */
626 __le32 sds_ring_offset; /* Offset to SDS config */
627 __le32 host_ctx_state; /* Starting State */
628 __le32 num_fn_per_port; /* How many PCI fn share the port */
629 __le16 num_rds_rings; /* Count of RDS rings */
630 __le16 num_sds_rings; /* Count of SDS rings */
631 __le16 context_id; /* Handle for context */
632 u8 phys_port; /* Physical id of port */
633 u8 virt_port; /* Virtual/Logical id of port */
634 u8 reserved[128]; /* save space for future expansion */
635 /* MUST BE 64-bit aligned.
636 The following is packed:
637 - N cardrsp_rds_rings
638 - N cardrs_sds_rings */
642 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
643 (sizeof(HOSTRQ_RX) + \
644 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
645 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
647 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
648 (sizeof(CARDRSP_RX) + \
649 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
650 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
656 struct qlcnic_hostrq_cds_ring {
657 __le64 host_phys_addr; /* Ring base addr */
658 __le32 ring_size; /* Ring entries */
659 __le32 rsvd; /* Padding */
662 struct qlcnic_hostrq_tx_ctx {
663 __le64 host_rsp_dma_addr; /* Response dma'd here */
664 __le64 cmd_cons_dma_addr; /* */
665 __le64 dummy_dma_addr; /* */
666 __le32 capabilities[4]; /* Flag bit vector */
667 __le32 host_int_crb_mode; /* Interrupt crb usage */
668 __le32 rsvd1; /* Padding */
669 __le16 rsvd2; /* Padding */
670 __le16 interrupt_ctl;
672 __le16 rsvd3; /* Padding */
673 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
674 u8 reserved[128]; /* future expansion */
677 struct qlcnic_cardrsp_cds_ring {
678 __le32 host_producer_crb; /* Crb to use */
679 __le32 interrupt_crb; /* Crb to use */
682 struct qlcnic_cardrsp_tx_ctx {
683 __le32 host_ctx_state; /* Starting state */
684 __le16 context_id; /* Handle for context */
685 u8 phys_port; /* Physical id of port */
686 u8 virt_port; /* Virtual/Logical id of port */
687 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
688 u8 reserved[128]; /* future expansion */
691 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
692 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
696 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
697 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
698 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
699 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
701 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
702 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
703 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
704 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
705 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
710 #define MC_COUNT_P3P 38
712 #define QLCNIC_MAC_NOOP 0
713 #define QLCNIC_MAC_ADD 1
714 #define QLCNIC_MAC_DEL 2
715 #define QLCNIC_MAC_VLAN_ADD 3
716 #define QLCNIC_MAC_VLAN_DEL 4
718 struct qlcnic_mac_list_s {
719 struct list_head list;
720 uint8_t mac_addr[ETH_ALEN+2];
724 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
725 * adjusted based on configured MTU.
727 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
728 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
729 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
730 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
732 #define QLCNIC_INTR_DEFAULT 0x04
734 union qlcnic_nic_intr_coalesce_data {
744 struct qlcnic_nic_intr_coalesce {
746 u16 rate_sample_time;
751 union qlcnic_nic_intr_coalesce_data normal;
752 union qlcnic_nic_intr_coalesce_data low;
753 union qlcnic_nic_intr_coalesce_data high;
754 union qlcnic_nic_intr_coalesce_data irq;
757 #define QLCNIC_HOST_REQUEST 0x13
758 #define QLCNIC_REQUEST 0x14
760 #define QLCNIC_MAC_EVENT 0x1
762 #define QLCNIC_IP_UP 2
763 #define QLCNIC_IP_DOWN 3
766 * Driver --> Firmware
768 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
769 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
770 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
771 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
772 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
773 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
774 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
775 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
776 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
778 * Firmware --> Driver
781 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
783 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
784 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
785 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
787 #define QLCNIC_LRO_REQUEST_CLEANUP 4
789 /* Capabilites received */
790 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
791 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
792 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
793 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
796 #define LINKEVENT_MODULE_NOT_PRESENT 1
797 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
798 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
799 #define LINKEVENT_MODULE_OPTICAL_LRM 4
800 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
801 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
802 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
803 #define LINKEVENT_MODULE_TWINAX 8
805 #define LINKSPEED_10GBPS 10000
806 #define LINKSPEED_1GBPS 1000
807 #define LINKSPEED_100MBPS 100
808 #define LINKSPEED_10MBPS 10
810 #define LINKSPEED_ENCODED_10MBPS 0
811 #define LINKSPEED_ENCODED_100MBPS 1
812 #define LINKSPEED_ENCODED_1GBPS 2
814 #define LINKEVENT_AUTONEG_DISABLED 0
815 #define LINKEVENT_AUTONEG_ENABLED 1
817 #define LINKEVENT_HALF_DUPLEX 0
818 #define LINKEVENT_FULL_DUPLEX 1
820 #define LINKEVENT_LINKSPEED_MBPS 0
821 #define LINKEVENT_LINKSPEED_ENCODED 1
823 /* firmware response header:
824 * 63:58 - message type
828 * 47:40 - completion id
833 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
834 ((msg_hdr >> 32) & 0xFF)
836 struct qlcnic_fw_msg {
846 struct qlcnic_nic_req {
852 struct qlcnic_mac_req {
858 struct qlcnic_vlan_req {
863 struct qlcnic_ipaddr {
868 #define QLCNIC_MSI_ENABLED 0x02
869 #define QLCNIC_MSIX_ENABLED 0x04
870 #define QLCNIC_LRO_ENABLED 0x08
871 #define QLCNIC_LRO_DISABLED 0x00
872 #define QLCNIC_BRIDGE_ENABLED 0X10
873 #define QLCNIC_DIAG_ENABLED 0x20
874 #define QLCNIC_ESWITCH_ENABLED 0x40
875 #define QLCNIC_ADAPTER_INITIALIZED 0x80
876 #define QLCNIC_TAGGING_ENABLED 0x100
877 #define QLCNIC_MACSPOOF 0x200
878 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
879 #define QLCNIC_PROMISC_DISABLED 0x800
880 #define QLCNIC_NEED_FLR 0x1000
881 #define QLCNIC_IS_MSI_FAMILY(adapter) \
882 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
884 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
885 #define QLCNIC_MSIX_TBL_SPACE 8192
886 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
887 #define QLCNIC_MSIX_TBL_PGSIZE 4096
889 #define QLCNIC_NETDEV_WEIGHT 128
890 #define QLCNIC_ADAPTER_UP_MAGIC 777
892 #define __QLCNIC_FW_ATTACHED 0
893 #define __QLCNIC_DEV_UP 1
894 #define __QLCNIC_RESETTING 2
895 #define __QLCNIC_START_FW 4
896 #define __QLCNIC_AER 5
898 #define QLCNIC_INTERRUPT_TEST 1
899 #define QLCNIC_LOOPBACK_TEST 2
900 #define QLCNIC_LED_TEST 3
902 #define QLCNIC_FILTER_AGE 80
903 #define QLCNIC_READD_AGE 20
904 #define QLCNIC_LB_MAX_FILTERS 64
906 struct qlcnic_filter {
907 struct hlist_node fnode;
913 struct qlcnic_filter_hash {
914 struct hlist_head *fhead;
919 struct qlcnic_adapter {
920 struct qlcnic_hardware_context *ahw;
921 struct qlcnic_recv_context *recv_ctx;
922 struct qlcnic_host_tx_ring *tx_ring;
923 struct net_device *netdev;
924 struct pci_dev *pdev;
983 u8 mac_addr[ETH_ALEN];
987 struct vlan_group *vlgrp;
988 struct qlcnic_npar_info *npars;
989 struct qlcnic_eswitch *eswitch;
990 struct qlcnic_nic_template *nic_ops;
992 struct qlcnic_adapter_stats stats;
993 struct list_head mac_list;
995 void __iomem *tgt_mask_reg;
996 void __iomem *tgt_status_reg;
997 void __iomem *crb_int_state_reg;
998 void __iomem *isr_int_vec;
1000 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1002 struct delayed_work fw_work;
1004 struct qlcnic_nic_intr_coalesce coal;
1006 struct qlcnic_filter_hash fhash;
1008 spinlock_t tx_clean_lock;
1009 spinlock_t mac_learn_lock;
1010 __le32 file_prd_off; /*File fw product offset*/
1012 const struct firmware *fw;
1015 struct qlcnic_info {
1017 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1019 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1021 __le32 capabilities;
1033 struct qlcnic_pci_info {
1034 __le16 id; /* pci function id */
1035 __le16 active; /* 1 = Enabled */
1036 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1037 __le16 default_port; /* default port number */
1039 __le16 tx_min_bw; /* Multiple of 100mbpc */
1041 __le16 reserved1[2];
1047 struct qlcnic_npar_info {
1063 struct qlcnic_eswitch {
1067 u8 active_ucast_filters;
1068 u8 max_ucast_filters;
1069 u8 max_active_vlans;
1072 #define QLCNIC_SWITCH_ENABLE BIT_1
1073 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1074 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1075 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1079 /* Return codes for Error handling */
1080 #define QL_STATUS_INVALID_PARAM -1
1082 #define MAX_BW 100 /* % of link speed */
1083 #define MAX_VLAN_ID 4095
1084 #define MIN_VLAN_ID 2
1085 #define DEFAULT_MAC_LEARN 1
1087 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1088 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1090 struct qlcnic_pci_func_cfg {
1100 struct qlcnic_npar_func_cfg {
1111 struct qlcnic_pm_func_cfg {
1118 struct qlcnic_esw_func_cfg {
1132 #define QLCNIC_STATS_VERSION 1
1133 #define QLCNIC_STATS_PORT 1
1134 #define QLCNIC_STATS_ESWITCH 2
1135 #define QLCNIC_QUERY_RX_COUNTER 0
1136 #define QLCNIC_QUERY_TX_COUNTER 1
1137 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1139 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1141 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1142 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1144 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1145 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1149 struct __qlcnic_esw_statistics {
1154 __le64 unicast_frames;
1155 __le64 multicast_frames;
1156 __le64 broadcast_frames;
1157 __le64 dropped_frames;
1159 __le64 local_frames;
1164 struct qlcnic_esw_statistics {
1165 struct __qlcnic_esw_statistics rx;
1166 struct __qlcnic_esw_statistics tx;
1169 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1170 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1172 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1173 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1174 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1175 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1176 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1177 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1179 #define ADDR_IN_RANGE(addr, low, high) \
1180 (((addr) < (high)) && ((addr) >= (low)))
1182 #define QLCRD32(adapter, off) \
1183 (qlcnic_hw_read_wx_2M(adapter, off))
1184 #define QLCWR32(adapter, off, val) \
1185 (qlcnic_hw_write_wx_2M(adapter, off, val))
1187 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1188 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1190 #define qlcnic_rom_lock(a) \
1191 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1192 #define qlcnic_rom_unlock(a) \
1193 qlcnic_pcie_sem_unlock((a), 2)
1194 #define qlcnic_phy_lock(a) \
1195 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1196 #define qlcnic_phy_unlock(a) \
1197 qlcnic_pcie_sem_unlock((a), 3)
1198 #define qlcnic_api_lock(a) \
1199 qlcnic_pcie_sem_lock((a), 5, 0)
1200 #define qlcnic_api_unlock(a) \
1201 qlcnic_pcie_sem_unlock((a), 5)
1202 #define qlcnic_sw_lock(a) \
1203 qlcnic_pcie_sem_lock((a), 6, 0)
1204 #define qlcnic_sw_unlock(a) \
1205 qlcnic_pcie_sem_unlock((a), 6)
1206 #define crb_win_lock(a) \
1207 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1208 #define crb_win_unlock(a) \
1209 qlcnic_pcie_sem_unlock((a), 7)
1211 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1212 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1213 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1214 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1215 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1217 /* Functions from qlcnic_init.c */
1218 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1219 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1220 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1221 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1222 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1223 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1224 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1226 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1227 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1228 u8 *bytes, size_t size);
1229 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1230 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1232 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1234 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1235 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1237 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1238 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1240 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1241 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1242 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1244 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1245 void qlcnic_watchdog_task(struct work_struct *work);
1246 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1247 struct qlcnic_host_rds_ring *rds_ring);
1248 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1249 void qlcnic_set_multi(struct net_device *netdev);
1250 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1251 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1252 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1253 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1254 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1255 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1256 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1258 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1259 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1260 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1261 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1262 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1263 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1264 struct qlcnic_host_tx_ring *tx_ring);
1265 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1267 /* Functions from qlcnic_main.c */
1268 int qlcnic_reset_context(struct qlcnic_adapter *);
1269 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1270 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1271 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1272 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1273 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1275 /* Management functions */
1276 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1277 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1278 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1279 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1281 /* eSwitch management functions */
1282 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1283 struct qlcnic_esw_func_cfg *);
1284 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1285 struct qlcnic_esw_func_cfg *);
1286 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1287 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1288 struct __qlcnic_esw_statistics *);
1289 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1290 struct __qlcnic_esw_statistics *);
1291 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1292 extern int qlcnic_config_tso;
1295 * QLOGIC Board information
1298 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1299 struct qlcnic_brdinfo {
1300 unsigned short vendor;
1301 unsigned short device;
1302 unsigned short sub_vendor;
1303 unsigned short sub_device;
1304 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1307 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1308 {0x1077, 0x8020, 0x1077, 0x203,
1309 "8200 Series Single Port 10GbE Converged Network Adapter "
1310 "(TCP/IP Networking)"},
1311 {0x1077, 0x8020, 0x1077, 0x207,
1312 "8200 Series Dual Port 10GbE Converged Network Adapter "
1313 "(TCP/IP Networking)"},
1314 {0x1077, 0x8020, 0x1077, 0x20b,
1315 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1316 {0x1077, 0x8020, 0x1077, 0x20c,
1317 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1318 {0x1077, 0x8020, 0x1077, 0x20f,
1319 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1320 {0x1077, 0x8020, 0x103c, 0x3733,
1321 "NC523SFP 10Gb 2-port Server Adapter"},
1322 {0x1077, 0x8020, 0x103c, 0x3346,
1323 "CN1000Q Dual Port Converged Network Adapter"},
1324 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1327 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1329 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1332 if (tx_ring->producer < tx_ring->sw_consumer)
1333 return tx_ring->sw_consumer - tx_ring->producer;
1335 return tx_ring->sw_consumer + tx_ring->num_desc -
1339 extern const struct ethtool_ops qlcnic_ethtool_ops;
1341 struct qlcnic_nic_template {
1342 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1343 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1344 int (*start_firmware) (struct qlcnic_adapter *);
1347 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1348 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1349 printk(KERN_INFO "%s: %s: " _fmt, \
1350 dev_name(&adapter->pdev->dev), \
1351 __func__, ##_args); \
1354 #endif /* __QLCNIC_H_ */