2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
45 #include <linux/vmalloc.h>
48 #include <asm/byteorder.h>
50 #include "qlcnic_hdr.h"
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 12
55 #define QLCNIC_LINUX_VERSIONID "5.0.12"
56 #define QLCNIC_DRV_IDC_VER 0x01
57 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
58 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
60 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
61 #define _major(v) (((v) >> 24) & 0xff)
62 #define _minor(v) (((v) >> 16) & 0xff)
63 #define _build(v) ((v) & 0xffff)
65 /* version in image has weird encoding:
68 * 31:16 - build (little endian)
70 #define QLCNIC_DECODE_VERSION(v) \
71 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
73 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
74 #define QLCNIC_NUM_FLASH_SECTORS (64)
75 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
76 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
77 * QLCNIC_FLASH_SECTOR_SIZE)
79 #define RCV_DESC_RINGSIZE(rds_ring) \
80 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
81 #define RCV_BUFF_RINGSIZE(rds_ring) \
82 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
83 #define STATUS_DESC_RINGSIZE(sds_ring) \
84 (sizeof(struct status_desc) * (sds_ring)->num_desc)
85 #define TX_BUFF_RINGSIZE(tx_ring) \
86 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
87 #define TX_DESC_RINGSIZE(tx_ring) \
88 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
90 #define QLCNIC_P3P_A0 0x50
92 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
94 #define FIRST_PAGE_GROUP_START 0
95 #define FIRST_PAGE_GROUP_END 0x100000
97 #define P3P_MAX_MTU (9600)
98 #define P3P_MIN_MTU (68)
99 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
101 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
102 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
103 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
104 #define QLCNIC_LRO_BUFFER_EXTRA 2048
106 /* Opcodes to be used with the commands */
107 #define TX_ETHER_PKT 0x01
108 #define TX_TCP_PKT 0x02
109 #define TX_UDP_PKT 0x03
110 #define TX_IP_PKT 0x04
111 #define TX_TCP_LSO 0x05
112 #define TX_TCP_LSO6 0x06
113 #define TX_IPSEC 0x07
114 #define TX_IPSEC_CMD 0x0a
115 #define TX_TCPV6_PKT 0x0b
116 #define TX_UDPV6_PKT 0x0c
119 #define MAX_TSO_HEADER_DESC 2
120 #define MGMT_CMD_DESC_RESV 4
121 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
122 + MGMT_CMD_DESC_RESV)
123 #define QLCNIC_MAX_TX_TIMEOUTS 2
126 * Following are the states of the Phantom. Phantom will set them and
127 * Host will read to check if the fields are correct.
129 #define PHAN_INITIALIZE_FAILED 0xffff
130 #define PHAN_INITIALIZE_COMPLETE 0xff01
132 /* Host writes the following to notify that it has done the init-handshake */
133 #define PHAN_INITIALIZE_ACK 0xf00f
134 #define PHAN_PEG_RCV_INITIALIZED 0xff01
136 #define NUM_RCV_DESC_RINGS 3
137 #define NUM_STS_DESC_RINGS 4
139 #define RCV_RING_NORMAL 0
140 #define RCV_RING_JUMBO 1
142 #define MIN_CMD_DESCRIPTORS 64
143 #define MIN_RCV_DESCRIPTORS 64
144 #define MIN_JUMBO_DESCRIPTORS 32
146 #define MAX_CMD_DESCRIPTORS 1024
147 #define MAX_RCV_DESCRIPTORS_1G 4096
148 #define MAX_RCV_DESCRIPTORS_10G 8192
149 #define MAX_RCV_DESCRIPTORS_VF 2048
150 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
151 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
153 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
154 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
155 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
156 #define MAX_RDS_RINGS 2
158 #define get_next_index(index, length) \
159 (((index) + 1) & ((length) - 1))
162 * Following data structures describe the descriptors that will be used.
163 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
164 * we are doing LSO (above the 1500 size packet) only.
167 #define FLAGS_VLAN_TAGGED 0x10
168 #define FLAGS_VLAN_OOB 0x40
170 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
171 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
172 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
173 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
174 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
175 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
177 #define qlcnic_set_tx_port(_desc, _port) \
178 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
180 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
181 ((_desc)->flags_opcode |= \
182 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
184 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
185 ((_desc)->nfrags__length = \
186 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
188 struct cmd_desc_type0 {
189 u8 tcp_hdr_offset; /* For LSO only */
190 u8 ip_hdr_offset; /* For LSO only */
191 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
192 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
196 __le16 reference_handle;
198 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
199 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
200 __le16 conn_id; /* IPSec offoad only */
205 __le16 buffer_length[4];
209 u8 eth_addr[ETH_ALEN];
212 } __attribute__ ((aligned(64)));
214 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
216 __le16 reference_handle;
218 __le32 buffer_length; /* allocated buffer length (usually 2K) */
222 /* opcode field in status_desc */
223 #define QLCNIC_SYN_OFFLOAD 0x03
224 #define QLCNIC_RXPKT_DESC 0x04
225 #define QLCNIC_OLD_RXPKT_DESC 0x3f
226 #define QLCNIC_RESPONSE_DESC 0x05
227 #define QLCNIC_LRO_DESC 0x12
229 /* for status field in status_desc */
230 #define STATUS_CKSUM_LOOP 0
231 #define STATUS_CKSUM_OK 2
233 /* owner bits of status_desc */
234 #define STATUS_OWNER_HOST (0x1ULL << 56)
235 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
237 /* Status descriptor:
238 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
239 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
240 53-55 desc_cnt, 56-57 owner, 58-63 opcode
242 #define qlcnic_get_sts_port(sts_data) \
244 #define qlcnic_get_sts_status(sts_data) \
245 (((sts_data) >> 4) & 0x0F)
246 #define qlcnic_get_sts_type(sts_data) \
247 (((sts_data) >> 8) & 0x0F)
248 #define qlcnic_get_sts_totallength(sts_data) \
249 (((sts_data) >> 12) & 0xFFFF)
250 #define qlcnic_get_sts_refhandle(sts_data) \
251 (((sts_data) >> 28) & 0xFFFF)
252 #define qlcnic_get_sts_prot(sts_data) \
253 (((sts_data) >> 44) & 0x0F)
254 #define qlcnic_get_sts_pkt_offset(sts_data) \
255 (((sts_data) >> 48) & 0x1F)
256 #define qlcnic_get_sts_desc_cnt(sts_data) \
257 (((sts_data) >> 53) & 0x7)
258 #define qlcnic_get_sts_opcode(sts_data) \
259 (((sts_data) >> 58) & 0x03F)
261 #define qlcnic_get_lro_sts_refhandle(sts_data) \
262 ((sts_data) & 0x0FFFF)
263 #define qlcnic_get_lro_sts_length(sts_data) \
264 (((sts_data) >> 16) & 0x0FFFF)
265 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
266 (((sts_data) >> 32) & 0x0FF)
267 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
268 (((sts_data) >> 40) & 0x0FF)
269 #define qlcnic_get_lro_sts_timestamp(sts_data) \
270 (((sts_data) >> 48) & 0x1)
271 #define qlcnic_get_lro_sts_type(sts_data) \
272 (((sts_data) >> 49) & 0x7)
273 #define qlcnic_get_lro_sts_push_flag(sts_data) \
274 (((sts_data) >> 52) & 0x1)
275 #define qlcnic_get_lro_sts_seq_number(sts_data) \
276 ((sts_data) & 0x0FFFFFFFF)
280 __le64 status_desc_data[2];
281 } __attribute__ ((aligned(16)));
283 /* UNIFIED ROMIMAGE */
284 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
285 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
286 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
287 #define QLCNIC_UNI_DIR_SECT_FW 0x7
290 #define QLCNIC_UNI_CHIP_REV_OFF 10
291 #define QLCNIC_UNI_FLAGS_OFF 11
292 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
293 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
294 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
296 struct uni_table_desc{
303 struct uni_data_desc{
309 /* Magic number to let user know flash is programmed */
310 #define QLCNIC_BDINFO_MAGIC 0x12345678
312 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
313 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
314 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
315 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
316 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
317 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
318 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
319 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
320 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
321 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
322 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
323 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
324 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
325 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
327 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
329 /* Flash memory map */
330 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
331 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
332 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
333 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
335 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
336 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
337 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
338 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
340 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
341 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
343 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
344 #define QLCNIC_UNIFIED_ROMIMAGE 0
345 #define QLCNIC_FLASH_ROMIMAGE 1
346 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
348 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
349 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
351 extern char qlcnic_driver_name[];
353 /* Number of status descriptors to handle per interrupt */
354 #define MAX_STATUS_HANDLE (64)
357 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
358 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
360 struct qlcnic_skb_frag {
365 struct qlcnic_recv_crb {
366 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
367 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
368 u32 sw_int_mask[NUM_STS_DESC_RINGS];
371 /* Following defines are for the state of the buffers */
372 #define QLCNIC_BUFFER_FREE 0
373 #define QLCNIC_BUFFER_BUSY 1
376 * There will be one qlcnic_buffer per skb packet. These will be
377 * used to save the dma info for pci_unmap_page()
379 struct qlcnic_cmd_buffer {
381 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
385 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
386 struct qlcnic_rx_buffer {
387 struct list_head list;
394 #define QLCNIC_GBE 0x01
395 #define QLCNIC_XGBE 0x02
398 * One hardware_context{} per adapter
399 * contains interrupt info as well shared hardware info.
401 struct qlcnic_hardware_context {
402 void __iomem *pci_base0;
403 void __iomem *ocm_win_crb;
405 unsigned long pci_len0;
408 struct mutex mem_lock;
417 struct qlcnic_adapter_stats {
431 u64 skb_alloc_failure;
433 u64 rx_dma_map_error;
434 u64 tx_dma_map_error;
438 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
439 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
441 struct qlcnic_host_rds_ring {
447 void __iomem *crb_rcv_producer;
448 struct rcv_desc *desc_head;
449 struct qlcnic_rx_buffer *rx_buf_arr;
450 struct list_head free_list;
452 dma_addr_t phys_addr;
455 struct qlcnic_host_sds_ring {
458 void __iomem *crb_sts_consumer;
459 void __iomem *crb_intr_mask;
461 struct status_desc *desc_head;
462 struct qlcnic_adapter *adapter;
463 struct napi_struct napi;
464 struct list_head free_list[NUM_RCV_DESC_RINGS];
468 dma_addr_t phys_addr;
469 char name[IFNAMSIZ+4];
472 struct qlcnic_host_tx_ring {
476 void __iomem *crb_cmd_producer;
479 struct netdev_queue *txq;
481 struct qlcnic_cmd_buffer *cmd_buf_arr;
482 struct cmd_desc_type0 *desc_head;
483 dma_addr_t phys_addr;
484 dma_addr_t hw_cons_phys_addr;
488 * Receive context. There is one such structure per instance of the
489 * receive processing. Any state information that is relevant to
490 * the receive, and is must be in this structure. The global data may be
493 struct qlcnic_recv_context {
498 struct qlcnic_host_rds_ring *rds_rings;
499 struct qlcnic_host_sds_ring *sds_rings;
502 /* HW context creation */
504 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
505 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
506 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
508 #define QLCNIC_CDRP_CMD_BIT 0x80000000
511 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
512 * in the crb QLCNIC_CDRP_CRB_OFFSET.
514 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
515 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
517 #define QLCNIC_CDRP_RSP_OK 0x00000001
518 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
519 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
522 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
523 * the crb QLCNIC_CDRP_CRB_OFFSET.
525 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
526 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
528 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
529 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
530 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
531 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
532 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
533 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
534 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
535 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
536 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
537 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
538 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
539 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
540 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
541 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
542 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
543 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
544 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
545 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
546 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
547 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
548 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
549 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
550 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
551 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
552 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
553 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
554 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
556 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
557 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
558 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
559 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
560 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
561 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
562 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
563 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
564 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
565 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
566 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
568 #define QLCNIC_RCODE_SUCCESS 0
569 #define QLCNIC_RCODE_TIMEOUT 17
570 #define QLCNIC_DESTROY_CTX_RESET 0
573 * Capabilities Announced
575 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
576 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
577 #define QLCNIC_CAP0_LSO (1 << 6)
578 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
579 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
580 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
585 #define QLCNIC_HOST_CTX_STATE_FREED 0
586 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
592 struct qlcnic_hostrq_sds_ring {
593 __le64 host_phys_addr; /* Ring base addr */
594 __le32 ring_size; /* Ring entries */
596 __le16 rsvd; /* Padding */
599 struct qlcnic_hostrq_rds_ring {
600 __le64 host_phys_addr; /* Ring base addr */
601 __le64 buff_size; /* Packet buffer size */
602 __le32 ring_size; /* Ring entries */
603 __le32 ring_kind; /* Class of ring */
606 struct qlcnic_hostrq_rx_ctx {
607 __le64 host_rsp_dma_addr; /* Response dma'd here */
608 __le32 capabilities[4]; /* Flag bit vector */
609 __le32 host_int_crb_mode; /* Interrupt crb usage */
610 __le32 host_rds_crb_mode; /* RDS crb usage */
611 /* These ring offsets are relative to data[0] below */
612 __le32 rds_ring_offset; /* Offset to RDS config */
613 __le32 sds_ring_offset; /* Offset to SDS config */
614 __le16 num_rds_rings; /* Count of RDS rings */
615 __le16 num_sds_rings; /* Count of SDS rings */
616 __le16 valid_field_offset;
619 u8 reserved[128]; /* reserve space for future expansion*/
620 /* MUST BE 64-bit aligned.
621 The following is packed:
623 - N hostrq_sds_rings */
627 struct qlcnic_cardrsp_rds_ring{
628 __le32 host_producer_crb; /* Crb to use */
629 __le32 rsvd1; /* Padding */
632 struct qlcnic_cardrsp_sds_ring {
633 __le32 host_consumer_crb; /* Crb to use */
634 __le32 interrupt_crb; /* Crb to use */
637 struct qlcnic_cardrsp_rx_ctx {
638 /* These ring offsets are relative to data[0] below */
639 __le32 rds_ring_offset; /* Offset to RDS config */
640 __le32 sds_ring_offset; /* Offset to SDS config */
641 __le32 host_ctx_state; /* Starting State */
642 __le32 num_fn_per_port; /* How many PCI fn share the port */
643 __le16 num_rds_rings; /* Count of RDS rings */
644 __le16 num_sds_rings; /* Count of SDS rings */
645 __le16 context_id; /* Handle for context */
646 u8 phys_port; /* Physical id of port */
647 u8 virt_port; /* Virtual/Logical id of port */
648 u8 reserved[128]; /* save space for future expansion */
649 /* MUST BE 64-bit aligned.
650 The following is packed:
651 - N cardrsp_rds_rings
652 - N cardrs_sds_rings */
656 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
657 (sizeof(HOSTRQ_RX) + \
658 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
659 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
661 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
662 (sizeof(CARDRSP_RX) + \
663 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
664 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
670 struct qlcnic_hostrq_cds_ring {
671 __le64 host_phys_addr; /* Ring base addr */
672 __le32 ring_size; /* Ring entries */
673 __le32 rsvd; /* Padding */
676 struct qlcnic_hostrq_tx_ctx {
677 __le64 host_rsp_dma_addr; /* Response dma'd here */
678 __le64 cmd_cons_dma_addr; /* */
679 __le64 dummy_dma_addr; /* */
680 __le32 capabilities[4]; /* Flag bit vector */
681 __le32 host_int_crb_mode; /* Interrupt crb usage */
682 __le32 rsvd1; /* Padding */
683 __le16 rsvd2; /* Padding */
684 __le16 interrupt_ctl;
686 __le16 rsvd3; /* Padding */
687 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
688 u8 reserved[128]; /* future expansion */
691 struct qlcnic_cardrsp_cds_ring {
692 __le32 host_producer_crb; /* Crb to use */
693 __le32 interrupt_crb; /* Crb to use */
696 struct qlcnic_cardrsp_tx_ctx {
697 __le32 host_ctx_state; /* Starting state */
698 __le16 context_id; /* Handle for context */
699 u8 phys_port; /* Physical id of port */
700 u8 virt_port; /* Virtual/Logical id of port */
701 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
702 u8 reserved[128]; /* future expansion */
705 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
706 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
710 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
711 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
712 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
713 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
715 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
716 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
717 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
718 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
719 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
724 #define MC_COUNT_P3P 38
726 #define QLCNIC_MAC_NOOP 0
727 #define QLCNIC_MAC_ADD 1
728 #define QLCNIC_MAC_DEL 2
729 #define QLCNIC_MAC_VLAN_ADD 3
730 #define QLCNIC_MAC_VLAN_DEL 4
732 struct qlcnic_mac_list_s {
733 struct list_head list;
734 uint8_t mac_addr[ETH_ALEN+2];
738 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
739 * adjusted based on configured MTU.
741 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
742 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
743 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
744 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
746 #define QLCNIC_INTR_DEFAULT 0x04
748 union qlcnic_nic_intr_coalesce_data {
758 struct qlcnic_nic_intr_coalesce {
760 u16 rate_sample_time;
765 union qlcnic_nic_intr_coalesce_data normal;
766 union qlcnic_nic_intr_coalesce_data low;
767 union qlcnic_nic_intr_coalesce_data high;
768 union qlcnic_nic_intr_coalesce_data irq;
771 #define QLCNIC_HOST_REQUEST 0x13
772 #define QLCNIC_REQUEST 0x14
774 #define QLCNIC_MAC_EVENT 0x1
776 #define QLCNIC_IP_UP 2
777 #define QLCNIC_IP_DOWN 3
780 * Driver --> Firmware
782 #define QLCNIC_H2C_OPCODE_START 0
783 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
784 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
785 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
786 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
787 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
788 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
789 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
790 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
791 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
792 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
793 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
794 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
795 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
796 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
797 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
798 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
799 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
800 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
801 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
802 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
803 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
804 #define QLCNIC_C2C_OPCODE 22
805 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
806 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
807 #define QLCNIC_H2C_OPCODE_LAST 25
809 * Firmware --> Driver
812 #define QLCNIC_C2H_OPCODE_START 128
813 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
814 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
815 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
816 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
817 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
818 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
819 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
820 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
821 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
822 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
823 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
824 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
825 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
826 #define QLCNIC_C2H_OPCODE_LAST 142
828 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
829 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
830 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
832 #define QLCNIC_LRO_REQUEST_CLEANUP 4
834 /* Capabilites received */
835 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
836 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
837 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
838 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
841 #define LINKEVENT_MODULE_NOT_PRESENT 1
842 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
843 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
844 #define LINKEVENT_MODULE_OPTICAL_LRM 4
845 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
846 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
847 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
848 #define LINKEVENT_MODULE_TWINAX 8
850 #define LINKSPEED_10GBPS 10000
851 #define LINKSPEED_1GBPS 1000
852 #define LINKSPEED_100MBPS 100
853 #define LINKSPEED_10MBPS 10
855 #define LINKSPEED_ENCODED_10MBPS 0
856 #define LINKSPEED_ENCODED_100MBPS 1
857 #define LINKSPEED_ENCODED_1GBPS 2
859 #define LINKEVENT_AUTONEG_DISABLED 0
860 #define LINKEVENT_AUTONEG_ENABLED 1
862 #define LINKEVENT_HALF_DUPLEX 0
863 #define LINKEVENT_FULL_DUPLEX 1
865 #define LINKEVENT_LINKSPEED_MBPS 0
866 #define LINKEVENT_LINKSPEED_ENCODED 1
868 #define AUTO_FW_RESET_ENABLED 0x01
869 /* firmware response header:
870 * 63:58 - message type
874 * 47:40 - completion id
879 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
880 ((msg_hdr >> 32) & 0xFF)
882 struct qlcnic_fw_msg {
892 struct qlcnic_nic_req {
898 struct qlcnic_mac_req {
904 struct qlcnic_vlan_req {
909 struct qlcnic_ipaddr {
914 #define QLCNIC_MSI_ENABLED 0x02
915 #define QLCNIC_MSIX_ENABLED 0x04
916 #define QLCNIC_LRO_ENABLED 0x08
917 #define QLCNIC_LRO_DISABLED 0x00
918 #define QLCNIC_BRIDGE_ENABLED 0X10
919 #define QLCNIC_DIAG_ENABLED 0x20
920 #define QLCNIC_ESWITCH_ENABLED 0x40
921 #define QLCNIC_ADAPTER_INITIALIZED 0x80
922 #define QLCNIC_TAGGING_ENABLED 0x100
923 #define QLCNIC_MACSPOOF 0x200
924 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
925 #define QLCNIC_PROMISC_DISABLED 0x800
926 #define QLCNIC_IS_MSI_FAMILY(adapter) \
927 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
929 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
930 #define QLCNIC_MSIX_TBL_SPACE 8192
931 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
932 #define QLCNIC_MSIX_TBL_PGSIZE 4096
934 #define QLCNIC_NETDEV_WEIGHT 128
935 #define QLCNIC_ADAPTER_UP_MAGIC 777
937 #define __QLCNIC_FW_ATTACHED 0
938 #define __QLCNIC_DEV_UP 1
939 #define __QLCNIC_RESETTING 2
940 #define __QLCNIC_START_FW 4
941 #define __QLCNIC_AER 5
943 #define QLCNIC_INTERRUPT_TEST 1
944 #define QLCNIC_LOOPBACK_TEST 2
946 #define QLCNIC_FILTER_AGE 80
947 #define QLCNIC_READD_AGE 20
948 #define QLCNIC_LB_MAX_FILTERS 64
950 struct qlcnic_filter {
951 struct hlist_node fnode;
957 struct qlcnic_filter_hash {
958 struct hlist_head *fhead;
963 struct qlcnic_adapter {
964 struct qlcnic_hardware_context ahw;
966 struct net_device *netdev;
967 struct pci_dev *pdev;
968 struct list_head mac_list;
970 spinlock_t tx_clean_lock;
971 spinlock_t mac_learn_lock;
1029 u8 mac_addr[ETH_ALEN];
1033 struct vlan_group *vlgrp;
1034 struct qlcnic_npar_info *npars;
1035 struct qlcnic_eswitch *eswitch;
1036 struct qlcnic_nic_template *nic_ops;
1038 struct qlcnic_adapter_stats stats;
1040 struct qlcnic_recv_context recv_ctx;
1041 struct qlcnic_host_tx_ring *tx_ring;
1043 void __iomem *tgt_mask_reg;
1044 void __iomem *tgt_status_reg;
1045 void __iomem *crb_int_state_reg;
1046 void __iomem *isr_int_vec;
1048 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1050 struct delayed_work fw_work;
1052 struct qlcnic_nic_intr_coalesce coal;
1054 struct qlcnic_filter_hash fhash;
1056 unsigned long state;
1057 __le32 file_prd_off; /*File fw product offset*/
1059 const struct firmware *fw;
1062 struct qlcnic_info {
1064 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1066 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1068 __le32 capabilities;
1080 struct qlcnic_pci_info {
1081 __le16 id; /* pci function id */
1082 __le16 active; /* 1 = Enabled */
1083 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1084 __le16 default_port; /* default port number */
1086 __le16 tx_min_bw; /* Multiple of 100mbpc */
1088 __le16 reserved1[2];
1094 struct qlcnic_npar_info {
1110 struct qlcnic_eswitch {
1114 u8 active_ucast_filters;
1115 u8 max_ucast_filters;
1116 u8 max_active_vlans;
1119 #define QLCNIC_SWITCH_ENABLE BIT_1
1120 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1121 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1122 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1126 /* Return codes for Error handling */
1127 #define QL_STATUS_INVALID_PARAM -1
1129 #define MAX_BW 100 /* % of link speed */
1130 #define MAX_VLAN_ID 4095
1131 #define MIN_VLAN_ID 2
1132 #define MAX_TX_QUEUES 1
1133 #define MAX_RX_QUEUES 4
1134 #define DEFAULT_MAC_LEARN 1
1136 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1137 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1138 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1139 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1141 struct qlcnic_pci_func_cfg {
1151 struct qlcnic_npar_func_cfg {
1162 struct qlcnic_pm_func_cfg {
1169 struct qlcnic_esw_func_cfg {
1183 #define QLCNIC_STATS_VERSION 1
1184 #define QLCNIC_STATS_PORT 1
1185 #define QLCNIC_STATS_ESWITCH 2
1186 #define QLCNIC_QUERY_RX_COUNTER 0
1187 #define QLCNIC_QUERY_TX_COUNTER 1
1188 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1190 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1192 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1193 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1195 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1196 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1200 struct __qlcnic_esw_statistics {
1205 __le64 unicast_frames;
1206 __le64 multicast_frames;
1207 __le64 broadcast_frames;
1208 __le64 dropped_frames;
1210 __le64 local_frames;
1215 struct qlcnic_esw_statistics {
1216 struct __qlcnic_esw_statistics rx;
1217 struct __qlcnic_esw_statistics tx;
1220 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1221 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1223 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1224 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1225 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1226 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1227 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1228 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1230 #define ADDR_IN_RANGE(addr, low, high) \
1231 (((addr) < (high)) && ((addr) >= (low)))
1233 #define QLCRD32(adapter, off) \
1234 (qlcnic_hw_read_wx_2M(adapter, off))
1235 #define QLCWR32(adapter, off, val) \
1236 (qlcnic_hw_write_wx_2M(adapter, off, val))
1238 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1239 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1241 #define qlcnic_rom_lock(a) \
1242 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1243 #define qlcnic_rom_unlock(a) \
1244 qlcnic_pcie_sem_unlock((a), 2)
1245 #define qlcnic_phy_lock(a) \
1246 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1247 #define qlcnic_phy_unlock(a) \
1248 qlcnic_pcie_sem_unlock((a), 3)
1249 #define qlcnic_api_lock(a) \
1250 qlcnic_pcie_sem_lock((a), 5, 0)
1251 #define qlcnic_api_unlock(a) \
1252 qlcnic_pcie_sem_unlock((a), 5)
1253 #define qlcnic_sw_lock(a) \
1254 qlcnic_pcie_sem_lock((a), 6, 0)
1255 #define qlcnic_sw_unlock(a) \
1256 qlcnic_pcie_sem_unlock((a), 6)
1257 #define crb_win_lock(a) \
1258 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1259 #define crb_win_unlock(a) \
1260 qlcnic_pcie_sem_unlock((a), 7)
1262 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1263 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1264 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1265 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1266 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1268 /* Functions from qlcnic_init.c */
1269 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1270 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1271 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1272 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1273 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1274 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1275 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1277 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1278 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1279 u8 *bytes, size_t size);
1280 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1281 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1283 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1285 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1286 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1288 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1289 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1291 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1292 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1293 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1295 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1296 void qlcnic_watchdog_task(struct work_struct *work);
1297 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1298 struct qlcnic_host_rds_ring *rds_ring);
1299 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1300 void qlcnic_set_multi(struct net_device *netdev);
1301 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1302 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1303 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1304 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1305 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1306 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1307 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1309 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1310 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1311 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1312 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1313 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1314 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1315 struct qlcnic_host_tx_ring *tx_ring);
1316 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1317 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1318 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1320 /* Functions from qlcnic_main.c */
1321 int qlcnic_request_quiscent_mode(struct qlcnic_adapter *adapter);
1322 void qlcnic_clear_quiscent_mode(struct qlcnic_adapter *adapter);
1323 int qlcnic_reset_context(struct qlcnic_adapter *);
1324 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1325 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1326 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1327 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1328 int qlcnic_check_loopback_buff(unsigned char *data);
1329 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1330 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1332 /* Management functions */
1333 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1334 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1335 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1336 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1338 /* eSwitch management functions */
1339 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1340 struct qlcnic_esw_func_cfg *);
1341 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1342 struct qlcnic_esw_func_cfg *);
1343 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1344 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1345 struct __qlcnic_esw_statistics *);
1346 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1347 struct __qlcnic_esw_statistics *);
1348 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1349 extern int qlcnic_config_tso;
1352 * QLOGIC Board information
1355 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1356 struct qlcnic_brdinfo {
1357 unsigned short vendor;
1358 unsigned short device;
1359 unsigned short sub_vendor;
1360 unsigned short sub_device;
1361 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1364 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1365 {0x1077, 0x8020, 0x1077, 0x203,
1366 "8200 Series Single Port 10GbE Converged Network Adapter "
1367 "(TCP/IP Networking)"},
1368 {0x1077, 0x8020, 0x1077, 0x207,
1369 "8200 Series Dual Port 10GbE Converged Network Adapter "
1370 "(TCP/IP Networking)"},
1371 {0x1077, 0x8020, 0x1077, 0x20b,
1372 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1373 {0x1077, 0x8020, 0x1077, 0x20c,
1374 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1375 {0x1077, 0x8020, 0x1077, 0x20f,
1376 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1377 {0x1077, 0x8020, 0x103c, 0x3733,
1378 "NC523SFP 10Gb 2-port Server Adapter"},
1379 {0x1077, 0x8020, 0x103c, 0x3346,
1380 "CN1000Q Dual Port Converged Network Adapter"},
1381 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1384 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1386 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1389 if (tx_ring->producer < tx_ring->sw_consumer)
1390 return tx_ring->sw_consumer - tx_ring->producer;
1392 return tx_ring->sw_consumer + tx_ring->num_desc -
1396 extern const struct ethtool_ops qlcnic_ethtool_ops;
1398 struct qlcnic_nic_template {
1399 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1400 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1401 int (*start_firmware) (struct qlcnic_adapter *);
1404 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1405 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1406 printk(KERN_INFO "%s: %s: " _fmt, \
1407 dev_name(&adapter->pdev->dev), \
1408 __func__, ##_args); \
1411 #endif /* __QLCNIC_H_ */