2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
45 #include <linux/vmalloc.h>
48 #include <asm/byteorder.h>
50 #include "qlcnic_hdr.h"
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 2
55 #define QLCNIC_LINUX_VERSIONID "5.0.2"
56 #define QLCNIC_DRV_IDC_VER 0x01
58 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
59 #define _major(v) (((v) >> 24) & 0xff)
60 #define _minor(v) (((v) >> 16) & 0xff)
61 #define _build(v) ((v) & 0xffff)
63 /* version in image has weird encoding:
66 * 31:16 - build (little endian)
68 #define QLCNIC_DECODE_VERSION(v) \
69 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71 #define QLCNIC_NUM_FLASH_SECTORS (64)
72 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
73 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
74 * QLCNIC_FLASH_SECTOR_SIZE)
76 #define RCV_DESC_RINGSIZE(rds_ring) \
77 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
78 #define RCV_BUFF_RINGSIZE(rds_ring) \
79 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
80 #define STATUS_DESC_RINGSIZE(sds_ring) \
81 (sizeof(struct status_desc) * (sds_ring)->num_desc)
82 #define TX_BUFF_RINGSIZE(tx_ring) \
83 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
84 #define TX_DESC_RINGSIZE(tx_ring) \
85 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87 #define QLCNIC_P3P_A0 0x50
89 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
91 #define FIRST_PAGE_GROUP_START 0
92 #define FIRST_PAGE_GROUP_END 0x100000
94 #define P3_MAX_MTU (9600)
95 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
97 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
98 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
99 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
100 #define QLCNIC_LRO_BUFFER_EXTRA 2048
102 /* Opcodes to be used with the commands */
103 #define TX_ETHER_PKT 0x01
104 #define TX_TCP_PKT 0x02
105 #define TX_UDP_PKT 0x03
106 #define TX_IP_PKT 0x04
107 #define TX_TCP_LSO 0x05
108 #define TX_TCP_LSO6 0x06
109 #define TX_IPSEC 0x07
110 #define TX_IPSEC_CMD 0x0a
111 #define TX_TCPV6_PKT 0x0b
112 #define TX_UDPV6_PKT 0x0c
115 #define MAX_BUFFERS_PER_CMD 32
116 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
117 #define QLCNIC_MAX_TX_TIMEOUTS 2
120 * Following are the states of the Phantom. Phantom will set them and
121 * Host will read to check if the fields are correct.
123 #define PHAN_INITIALIZE_FAILED 0xffff
124 #define PHAN_INITIALIZE_COMPLETE 0xff01
126 /* Host writes the following to notify that it has done the init-handshake */
127 #define PHAN_INITIALIZE_ACK 0xf00f
128 #define PHAN_PEG_RCV_INITIALIZED 0xff01
130 #define NUM_RCV_DESC_RINGS 3
131 #define NUM_STS_DESC_RINGS 4
133 #define RCV_RING_NORMAL 0
134 #define RCV_RING_JUMBO 1
136 #define MIN_CMD_DESCRIPTORS 64
137 #define MIN_RCV_DESCRIPTORS 64
138 #define MIN_JUMBO_DESCRIPTORS 32
140 #define MAX_CMD_DESCRIPTORS 1024
141 #define MAX_RCV_DESCRIPTORS_1G 4096
142 #define MAX_RCV_DESCRIPTORS_10G 8192
143 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
144 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
146 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
147 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
149 #define get_next_index(index, length) \
150 (((index) + 1) & ((length) - 1))
152 #define MPORT_MULTI_FUNCTION_MODE 0x2222
155 * Following data structures describe the descriptors that will be used.
156 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
157 * we are doing LSO (above the 1500 size packet) only.
160 #define FLAGS_VLAN_TAGGED 0x10
161 #define FLAGS_VLAN_OOB 0x40
163 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
164 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
165 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
166 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
167 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
168 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
170 #define qlcnic_set_tx_port(_desc, _port) \
171 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
173 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
174 ((_desc)->flags_opcode = \
175 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
177 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
178 ((_desc)->nfrags__length = \
179 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
181 struct cmd_desc_type0 {
182 u8 tcp_hdr_offset; /* For LSO only */
183 u8 ip_hdr_offset; /* For LSO only */
184 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
185 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
189 __le16 reference_handle;
191 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
192 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
193 __le16 conn_id; /* IPSec offoad only */
198 __le16 buffer_length[4];
206 } __attribute__ ((aligned(64)));
208 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
210 __le16 reference_handle;
212 __le32 buffer_length; /* allocated buffer length (usually 2K) */
216 /* opcode field in status_desc */
217 #define QLCNIC_SYN_OFFLOAD 0x03
218 #define QLCNIC_RXPKT_DESC 0x04
219 #define QLCNIC_OLD_RXPKT_DESC 0x3f
220 #define QLCNIC_RESPONSE_DESC 0x05
221 #define QLCNIC_LRO_DESC 0x12
223 /* for status field in status_desc */
224 #define STATUS_CKSUM_OK (2)
226 /* owner bits of status_desc */
227 #define STATUS_OWNER_HOST (0x1ULL << 56)
228 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
230 /* Status descriptor:
231 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
232 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
233 53-55 desc_cnt, 56-57 owner, 58-63 opcode
235 #define qlcnic_get_sts_port(sts_data) \
237 #define qlcnic_get_sts_status(sts_data) \
238 (((sts_data) >> 4) & 0x0F)
239 #define qlcnic_get_sts_type(sts_data) \
240 (((sts_data) >> 8) & 0x0F)
241 #define qlcnic_get_sts_totallength(sts_data) \
242 (((sts_data) >> 12) & 0xFFFF)
243 #define qlcnic_get_sts_refhandle(sts_data) \
244 (((sts_data) >> 28) & 0xFFFF)
245 #define qlcnic_get_sts_prot(sts_data) \
246 (((sts_data) >> 44) & 0x0F)
247 #define qlcnic_get_sts_pkt_offset(sts_data) \
248 (((sts_data) >> 48) & 0x1F)
249 #define qlcnic_get_sts_desc_cnt(sts_data) \
250 (((sts_data) >> 53) & 0x7)
251 #define qlcnic_get_sts_opcode(sts_data) \
252 (((sts_data) >> 58) & 0x03F)
254 #define qlcnic_get_lro_sts_refhandle(sts_data) \
255 ((sts_data) & 0x0FFFF)
256 #define qlcnic_get_lro_sts_length(sts_data) \
257 (((sts_data) >> 16) & 0x0FFFF)
258 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
259 (((sts_data) >> 32) & 0x0FF)
260 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
261 (((sts_data) >> 40) & 0x0FF)
262 #define qlcnic_get_lro_sts_timestamp(sts_data) \
263 (((sts_data) >> 48) & 0x1)
264 #define qlcnic_get_lro_sts_type(sts_data) \
265 (((sts_data) >> 49) & 0x7)
266 #define qlcnic_get_lro_sts_push_flag(sts_data) \
267 (((sts_data) >> 52) & 0x1)
268 #define qlcnic_get_lro_sts_seq_number(sts_data) \
269 ((sts_data) & 0x0FFFFFFFF)
273 __le64 status_desc_data[2];
274 } __attribute__ ((aligned(16)));
276 /* UNIFIED ROMIMAGE */
277 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
278 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
279 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
280 #define QLCNIC_UNI_DIR_SECT_FW 0x7
283 #define QLCNIC_UNI_CHIP_REV_OFF 10
284 #define QLCNIC_UNI_FLAGS_OFF 11
285 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
286 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
287 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
289 struct uni_table_desc{
296 struct uni_data_desc{
302 /* Magic number to let user know flash is programmed */
303 #define QLCNIC_BDINFO_MAGIC 0x12345678
305 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
306 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
307 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
308 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
309 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
310 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
311 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
312 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
313 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
314 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
315 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
316 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
317 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
318 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
320 /* Flash memory map */
321 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
322 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
323 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
324 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
326 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
327 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
328 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
329 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
331 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
332 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
334 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
335 #define QLCNIC_UNIFIED_ROMIMAGE 0
336 #define QLCNIC_FLASH_ROMIMAGE 1
337 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
339 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
340 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
342 extern char qlcnic_driver_name[];
344 /* Number of status descriptors to handle per interrupt */
345 #define MAX_STATUS_HANDLE (64)
348 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
349 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
351 struct qlcnic_skb_frag {
356 struct qlcnic_recv_crb {
357 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
358 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
359 u32 sw_int_mask[NUM_STS_DESC_RINGS];
362 /* Following defines are for the state of the buffers */
363 #define QLCNIC_BUFFER_FREE 0
364 #define QLCNIC_BUFFER_BUSY 1
367 * There will be one qlcnic_buffer per skb packet. These will be
368 * used to save the dma info for pci_unmap_page()
370 struct qlcnic_cmd_buffer {
372 struct qlcnic_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
376 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
377 struct qlcnic_rx_buffer {
378 struct list_head list;
386 #define QLCNIC_GBE 0x01
387 #define QLCNIC_XGBE 0x02
390 * One hardware_context{} per adapter
391 * contains interrupt info as well shared hardware info.
393 struct qlcnic_hardware_context {
394 void __iomem *pci_base0;
395 void __iomem *ocm_win_crb;
397 unsigned long pci_len0;
400 struct mutex mem_lock;
409 struct qlcnic_adapter_stats {
423 u64 skb_alloc_failure;
426 u64 rx_dma_map_error;
427 u64 tx_dma_map_error;
431 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
432 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
434 struct qlcnic_host_rds_ring {
440 void __iomem *crb_rcv_producer;
441 struct rcv_desc *desc_head;
442 struct qlcnic_rx_buffer *rx_buf_arr;
443 struct list_head free_list;
445 dma_addr_t phys_addr;
448 struct qlcnic_host_sds_ring {
451 void __iomem *crb_sts_consumer;
452 void __iomem *crb_intr_mask;
454 struct status_desc *desc_head;
455 struct qlcnic_adapter *adapter;
456 struct napi_struct napi;
457 struct list_head free_list[NUM_RCV_DESC_RINGS];
461 dma_addr_t phys_addr;
462 char name[IFNAMSIZ+4];
465 struct qlcnic_host_tx_ring {
469 void __iomem *crb_cmd_producer;
472 struct netdev_queue *txq;
474 struct qlcnic_cmd_buffer *cmd_buf_arr;
475 struct cmd_desc_type0 *desc_head;
476 dma_addr_t phys_addr;
477 dma_addr_t hw_cons_phys_addr;
481 * Receive context. There is one such structure per instance of the
482 * receive processing. Any state information that is relevant to
483 * the receive, and is must be in this structure. The global data may be
486 struct qlcnic_recv_context {
491 struct qlcnic_host_rds_ring *rds_rings;
492 struct qlcnic_host_sds_ring *sds_rings;
495 /* HW context creation */
497 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
498 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
499 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
501 #define QLCNIC_CDRP_CMD_BIT 0x80000000
504 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
505 * in the crb QLCNIC_CDRP_CRB_OFFSET.
507 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
508 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
510 #define QLCNIC_CDRP_RSP_OK 0x00000001
511 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
512 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
515 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
516 * the crb QLCNIC_CDRP_CRB_OFFSET.
518 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
519 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
521 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
522 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
523 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
524 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
525 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
526 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
527 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
528 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
529 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
530 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
531 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
532 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
533 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
534 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
535 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
536 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
537 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
538 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
539 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
540 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
541 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
542 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
543 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
544 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
545 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
546 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
547 #define QLCNIC_CDRP_CMD_MAX 0x0000001f
549 #define QLCNIC_RCODE_SUCCESS 0
550 #define QLCNIC_RCODE_TIMEOUT 17
551 #define QLCNIC_DESTROY_CTX_RESET 0
554 * Capabilities Announced
556 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
557 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
558 #define QLCNIC_CAP0_LSO (1 << 6)
559 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
560 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
565 #define QLCHAL_VERSION 1
567 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
573 struct qlcnic_hostrq_sds_ring {
574 __le64 host_phys_addr; /* Ring base addr */
575 __le32 ring_size; /* Ring entries */
577 __le16 rsvd; /* Padding */
580 struct qlcnic_hostrq_rds_ring {
581 __le64 host_phys_addr; /* Ring base addr */
582 __le64 buff_size; /* Packet buffer size */
583 __le32 ring_size; /* Ring entries */
584 __le32 ring_kind; /* Class of ring */
587 struct qlcnic_hostrq_rx_ctx {
588 __le64 host_rsp_dma_addr; /* Response dma'd here */
589 __le32 capabilities[4]; /* Flag bit vector */
590 __le32 host_int_crb_mode; /* Interrupt crb usage */
591 __le32 host_rds_crb_mode; /* RDS crb usage */
592 /* These ring offsets are relative to data[0] below */
593 __le32 rds_ring_offset; /* Offset to RDS config */
594 __le32 sds_ring_offset; /* Offset to SDS config */
595 __le16 num_rds_rings; /* Count of RDS rings */
596 __le16 num_sds_rings; /* Count of SDS rings */
597 __le16 rsvd1; /* Padding */
598 __le16 rsvd2; /* Padding */
599 u8 reserved[128]; /* reserve space for future expansion*/
600 /* MUST BE 64-bit aligned.
601 The following is packed:
603 - N hostrq_sds_rings */
607 struct qlcnic_cardrsp_rds_ring{
608 __le32 host_producer_crb; /* Crb to use */
609 __le32 rsvd1; /* Padding */
612 struct qlcnic_cardrsp_sds_ring {
613 __le32 host_consumer_crb; /* Crb to use */
614 __le32 interrupt_crb; /* Crb to use */
617 struct qlcnic_cardrsp_rx_ctx {
618 /* These ring offsets are relative to data[0] below */
619 __le32 rds_ring_offset; /* Offset to RDS config */
620 __le32 sds_ring_offset; /* Offset to SDS config */
621 __le32 host_ctx_state; /* Starting State */
622 __le32 num_fn_per_port; /* How many PCI fn share the port */
623 __le16 num_rds_rings; /* Count of RDS rings */
624 __le16 num_sds_rings; /* Count of SDS rings */
625 __le16 context_id; /* Handle for context */
626 u8 phys_port; /* Physical id of port */
627 u8 virt_port; /* Virtual/Logical id of port */
628 u8 reserved[128]; /* save space for future expansion */
629 /* MUST BE 64-bit aligned.
630 The following is packed:
631 - N cardrsp_rds_rings
632 - N cardrs_sds_rings */
636 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
637 (sizeof(HOSTRQ_RX) + \
638 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
639 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
641 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
642 (sizeof(CARDRSP_RX) + \
643 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
644 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
650 struct qlcnic_hostrq_cds_ring {
651 __le64 host_phys_addr; /* Ring base addr */
652 __le32 ring_size; /* Ring entries */
653 __le32 rsvd; /* Padding */
656 struct qlcnic_hostrq_tx_ctx {
657 __le64 host_rsp_dma_addr; /* Response dma'd here */
658 __le64 cmd_cons_dma_addr; /* */
659 __le64 dummy_dma_addr; /* */
660 __le32 capabilities[4]; /* Flag bit vector */
661 __le32 host_int_crb_mode; /* Interrupt crb usage */
662 __le32 rsvd1; /* Padding */
663 __le16 rsvd2; /* Padding */
664 __le16 interrupt_ctl;
666 __le16 rsvd3; /* Padding */
667 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
668 u8 reserved[128]; /* future expansion */
671 struct qlcnic_cardrsp_cds_ring {
672 __le32 host_producer_crb; /* Crb to use */
673 __le32 interrupt_crb; /* Crb to use */
676 struct qlcnic_cardrsp_tx_ctx {
677 __le32 host_ctx_state; /* Starting state */
678 __le16 context_id; /* Handle for context */
679 u8 phys_port; /* Physical id of port */
680 u8 virt_port; /* Virtual/Logical id of port */
681 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
682 u8 reserved[128]; /* future expansion */
685 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
686 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
690 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
691 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
692 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
693 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
695 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
696 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
697 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
698 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
699 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
704 #define MC_COUNT_P3 38
706 #define QLCNIC_MAC_NOOP 0
707 #define QLCNIC_MAC_ADD 1
708 #define QLCNIC_MAC_DEL 2
710 struct qlcnic_mac_list_s {
711 struct list_head list;
712 uint8_t mac_addr[ETH_ALEN+2];
716 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
717 * adjusted based on configured MTU.
719 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
720 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
721 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
722 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
724 #define QLCNIC_INTR_DEFAULT 0x04
726 union qlcnic_nic_intr_coalesce_data {
736 struct qlcnic_nic_intr_coalesce {
738 u16 rate_sample_time;
743 union qlcnic_nic_intr_coalesce_data normal;
744 union qlcnic_nic_intr_coalesce_data low;
745 union qlcnic_nic_intr_coalesce_data high;
746 union qlcnic_nic_intr_coalesce_data irq;
749 #define QLCNIC_HOST_REQUEST 0x13
750 #define QLCNIC_REQUEST 0x14
752 #define QLCNIC_MAC_EVENT 0x1
754 #define QLCNIC_IP_UP 2
755 #define QLCNIC_IP_DOWN 3
758 * Driver --> Firmware
760 #define QLCNIC_H2C_OPCODE_START 0
761 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
762 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
763 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
764 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
765 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
766 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
767 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
768 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
769 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
770 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
771 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
772 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
773 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
774 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
775 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
776 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
777 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
778 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
779 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
780 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
781 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
782 #define QLCNIC_C2C_OPCODE 22
783 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
784 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
785 #define QLCNIC_H2C_OPCODE_LAST 25
787 * Firmware --> Driver
790 #define QLCNIC_C2H_OPCODE_START 128
791 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
792 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
793 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
794 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
795 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
796 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
797 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
798 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
799 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
800 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
801 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
802 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
803 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
804 #define QLCNIC_C2H_OPCODE_LAST 142
806 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
807 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
808 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
810 #define QLCNIC_LRO_REQUEST_CLEANUP 4
812 /* Capabilites received */
813 #define QLCNIC_FW_CAPABILITY_BDG (1 << 8)
814 #define QLCNIC_FW_CAPABILITY_FVLANTX (1 << 9)
815 #define QLCNIC_FW_CAPABILITY_HW_LRO (1 << 10)
818 #define LINKEVENT_MODULE_NOT_PRESENT 1
819 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
820 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
821 #define LINKEVENT_MODULE_OPTICAL_LRM 4
822 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
823 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
824 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
825 #define LINKEVENT_MODULE_TWINAX 8
827 #define LINKSPEED_10GBPS 10000
828 #define LINKSPEED_1GBPS 1000
829 #define LINKSPEED_100MBPS 100
830 #define LINKSPEED_10MBPS 10
832 #define LINKSPEED_ENCODED_10MBPS 0
833 #define LINKSPEED_ENCODED_100MBPS 1
834 #define LINKSPEED_ENCODED_1GBPS 2
836 #define LINKEVENT_AUTONEG_DISABLED 0
837 #define LINKEVENT_AUTONEG_ENABLED 1
839 #define LINKEVENT_HALF_DUPLEX 0
840 #define LINKEVENT_FULL_DUPLEX 1
842 #define LINKEVENT_LINKSPEED_MBPS 0
843 #define LINKEVENT_LINKSPEED_ENCODED 1
845 #define AUTO_FW_RESET_ENABLED 0x01
846 /* firmware response header:
847 * 63:58 - message type
851 * 47:40 - completion id
856 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
857 ((msg_hdr >> 32) & 0xFF)
859 struct qlcnic_fw_msg {
869 struct qlcnic_nic_req {
875 struct qlcnic_mac_req {
881 #define QLCNIC_MSI_ENABLED 0x02
882 #define QLCNIC_MSIX_ENABLED 0x04
883 #define QLCNIC_LRO_ENABLED 0x08
884 #define QLCNIC_BRIDGE_ENABLED 0X10
885 #define QLCNIC_DIAG_ENABLED 0x20
886 #define QLCNIC_IS_MSI_FAMILY(adapter) \
887 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
889 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
890 #define QLCNIC_MSIX_TBL_SPACE 8192
891 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
893 #define QLCNIC_NETDEV_WEIGHT 128
894 #define QLCNIC_ADAPTER_UP_MAGIC 777
896 #define __QLCNIC_FW_ATTACHED 0
897 #define __QLCNIC_DEV_UP 1
898 #define __QLCNIC_RESETTING 2
899 #define __QLCNIC_START_FW 4
901 #define QLCNIC_INTERRUPT_TEST 1
902 #define QLCNIC_LOOPBACK_TEST 2
904 struct qlcnic_adapter {
905 struct qlcnic_hardware_context ahw;
907 struct net_device *netdev;
908 struct pci_dev *pdev;
909 struct list_head mac_list;
911 spinlock_t tx_clean_lock;
961 u8 mac_addr[ETH_ALEN];
965 struct qlcnic_adapter_stats stats;
967 struct qlcnic_recv_context recv_ctx;
968 struct qlcnic_host_tx_ring *tx_ring;
970 void __iomem *tgt_mask_reg;
971 void __iomem *tgt_status_reg;
972 void __iomem *crb_int_state_reg;
973 void __iomem *isr_int_vec;
975 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
977 struct delayed_work fw_work;
979 struct work_struct tx_timeout_task;
981 struct qlcnic_nic_intr_coalesce coal;
984 __le32 file_prd_off; /*File fw product offset*/
986 const struct firmware *fw;
989 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
990 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
992 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
993 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
994 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
995 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
996 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
997 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
999 #define ADDR_IN_RANGE(addr, low, high) \
1000 (((addr) < (high)) && ((addr) >= (low)))
1002 #define QLCRD32(adapter, off) \
1003 (qlcnic_hw_read_wx_2M(adapter, off))
1004 #define QLCWR32(adapter, off, val) \
1005 (qlcnic_hw_write_wx_2M(adapter, off, val))
1007 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1008 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1010 #define qlcnic_rom_lock(a) \
1011 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1012 #define qlcnic_rom_unlock(a) \
1013 qlcnic_pcie_sem_unlock((a), 2)
1014 #define qlcnic_phy_lock(a) \
1015 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1016 #define qlcnic_phy_unlock(a) \
1017 qlcnic_pcie_sem_unlock((a), 3)
1018 #define qlcnic_api_lock(a) \
1019 qlcnic_pcie_sem_lock((a), 5, 0)
1020 #define qlcnic_api_unlock(a) \
1021 qlcnic_pcie_sem_unlock((a), 5)
1022 #define qlcnic_sw_lock(a) \
1023 qlcnic_pcie_sem_lock((a), 6, 0)
1024 #define qlcnic_sw_unlock(a) \
1025 qlcnic_pcie_sem_unlock((a), 6)
1026 #define crb_win_lock(a) \
1027 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1028 #define crb_win_unlock(a) \
1029 qlcnic_pcie_sem_unlock((a), 7)
1031 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1032 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1033 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1035 /* Functions from qlcnic_init.c */
1036 int qlcnic_phantom_init(struct qlcnic_adapter *adapter);
1037 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1038 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1039 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1040 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1041 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1042 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1044 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1045 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1046 u8 *bytes, size_t size);
1047 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1048 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1050 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1052 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1053 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1055 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1056 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1058 int qlcnic_init_firmware(struct qlcnic_adapter *adapter);
1059 void qlcnic_watchdog_task(struct work_struct *work);
1060 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1061 struct qlcnic_host_rds_ring *rds_ring);
1062 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1063 void qlcnic_set_multi(struct net_device *netdev);
1064 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1065 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1066 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1067 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1068 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1069 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1070 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1072 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1073 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1074 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1075 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable);
1076 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1077 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1078 struct qlcnic_host_tx_ring *tx_ring);
1079 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac);
1080 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1081 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1083 /* Functions from qlcnic_main.c */
1084 int qlcnic_reset_context(struct qlcnic_adapter *);
1085 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1086 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1087 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1088 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1089 int qlcnic_check_loopback_buff(unsigned char *data);
1090 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1091 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1094 * QLOGIC Board information
1097 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1098 struct qlcnic_brdinfo {
1099 unsigned short vendor;
1100 unsigned short device;
1101 unsigned short sub_vendor;
1102 unsigned short sub_device;
1103 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1106 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1107 {0x1077, 0x8020, 0x1077, 0x203,
1108 "8200 Series Single Port 10GbE Converged Network Adapter "
1109 "(TCP/IP Networking)"},
1110 {0x1077, 0x8020, 0x1077, 0x207,
1111 "8200 Series Dual Port 10GbE Converged Network Adapter "
1112 "(TCP/IP Networking)"},
1113 {0x1077, 0x8020, 0x1077, 0x20b,
1114 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1115 {0x1077, 0x8020, 0x1077, 0x20c,
1116 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1117 {0x1077, 0x8020, 0x1077, 0x20f,
1118 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1119 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1122 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1124 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1127 if (tx_ring->producer < tx_ring->sw_consumer)
1128 return tx_ring->sw_consumer - tx_ring->producer;
1130 return tx_ring->sw_consumer + tx_ring->num_desc -
1134 extern const struct ethtool_ops qlcnic_ethtool_ops;
1136 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1137 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1138 printk(KERN_INFO "%s: %s: " _fmt, \
1139 dev_name(&adapter->pdev->dev), \
1140 __func__, ##_args); \
1143 #endif /* __QLCNIC_H_ */