2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
28 #include <linux/vmalloc.h>
31 #include <asm/byteorder.h>
33 #include "qlcnic_hdr.h"
35 #define _QLCNIC_LINUX_MAJOR 5
36 #define _QLCNIC_LINUX_MINOR 0
37 #define _QLCNIC_LINUX_SUBVERSION 13
38 #define QLCNIC_LINUX_VERSIONID "5.0.13"
39 #define QLCNIC_DRV_IDC_VER 0x01
40 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
41 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
43 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
44 #define _major(v) (((v) >> 24) & 0xff)
45 #define _minor(v) (((v) >> 16) & 0xff)
46 #define _build(v) ((v) & 0xffff)
48 /* version in image has weird encoding:
51 * 31:16 - build (little endian)
53 #define QLCNIC_DECODE_VERSION(v) \
54 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
56 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
57 #define QLCNIC_NUM_FLASH_SECTORS (64)
58 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
59 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
60 * QLCNIC_FLASH_SECTOR_SIZE)
62 #define RCV_DESC_RINGSIZE(rds_ring) \
63 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
64 #define RCV_BUFF_RINGSIZE(rds_ring) \
65 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
66 #define STATUS_DESC_RINGSIZE(sds_ring) \
67 (sizeof(struct status_desc) * (sds_ring)->num_desc)
68 #define TX_BUFF_RINGSIZE(tx_ring) \
69 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
70 #define TX_DESC_RINGSIZE(tx_ring) \
71 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
73 #define QLCNIC_P3P_A0 0x50
75 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
77 #define FIRST_PAGE_GROUP_START 0
78 #define FIRST_PAGE_GROUP_END 0x100000
80 #define P3P_MAX_MTU (9600)
81 #define P3P_MIN_MTU (68)
82 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
84 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
85 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
86 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
87 #define QLCNIC_LRO_BUFFER_EXTRA 2048
89 /* Opcodes to be used with the commands */
90 #define TX_ETHER_PKT 0x01
91 #define TX_TCP_PKT 0x02
92 #define TX_UDP_PKT 0x03
93 #define TX_IP_PKT 0x04
94 #define TX_TCP_LSO 0x05
95 #define TX_TCP_LSO6 0x06
97 #define TX_IPSEC_CMD 0x0a
98 #define TX_TCPV6_PKT 0x0b
99 #define TX_UDPV6_PKT 0x0c
102 #define MAX_TSO_HEADER_DESC 2
103 #define MGMT_CMD_DESC_RESV 4
104 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
105 + MGMT_CMD_DESC_RESV)
106 #define QLCNIC_MAX_TX_TIMEOUTS 2
109 * Following are the states of the Phantom. Phantom will set them and
110 * Host will read to check if the fields are correct.
112 #define PHAN_INITIALIZE_FAILED 0xffff
113 #define PHAN_INITIALIZE_COMPLETE 0xff01
115 /* Host writes the following to notify that it has done the init-handshake */
116 #define PHAN_INITIALIZE_ACK 0xf00f
117 #define PHAN_PEG_RCV_INITIALIZED 0xff01
119 #define NUM_RCV_DESC_RINGS 3
120 #define NUM_STS_DESC_RINGS 4
122 #define RCV_RING_NORMAL 0
123 #define RCV_RING_JUMBO 1
125 #define MIN_CMD_DESCRIPTORS 64
126 #define MIN_RCV_DESCRIPTORS 64
127 #define MIN_JUMBO_DESCRIPTORS 32
129 #define MAX_CMD_DESCRIPTORS 1024
130 #define MAX_RCV_DESCRIPTORS_1G 4096
131 #define MAX_RCV_DESCRIPTORS_10G 8192
132 #define MAX_RCV_DESCRIPTORS_VF 2048
133 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
134 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
136 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
137 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
138 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
139 #define MAX_RDS_RINGS 2
141 #define get_next_index(index, length) \
142 (((index) + 1) & ((length) - 1))
145 * Following data structures describe the descriptors that will be used.
146 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
147 * we are doing LSO (above the 1500 size packet) only.
150 #define FLAGS_VLAN_TAGGED 0x10
151 #define FLAGS_VLAN_OOB 0x40
153 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
154 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
155 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
157 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
158 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160 #define qlcnic_set_tx_port(_desc, _port) \
161 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
164 ((_desc)->flags_opcode |= \
165 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
168 ((_desc)->nfrags__length = \
169 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171 struct cmd_desc_type0 {
172 u8 tcp_hdr_offset; /* For LSO only */
173 u8 ip_hdr_offset; /* For LSO only */
174 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
175 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
179 __le16 reference_handle;
181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
182 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
183 __le16 conn_id; /* IPSec offoad only */
188 __le16 buffer_length[4];
192 u8 eth_addr[ETH_ALEN];
195 } __attribute__ ((aligned(64)));
197 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
199 __le16 reference_handle;
201 __le32 buffer_length; /* allocated buffer length (usually 2K) */
205 /* opcode field in status_desc */
206 #define QLCNIC_SYN_OFFLOAD 0x03
207 #define QLCNIC_RXPKT_DESC 0x04
208 #define QLCNIC_OLD_RXPKT_DESC 0x3f
209 #define QLCNIC_RESPONSE_DESC 0x05
210 #define QLCNIC_LRO_DESC 0x12
212 /* for status field in status_desc */
213 #define STATUS_CKSUM_LOOP 0
214 #define STATUS_CKSUM_OK 2
216 /* owner bits of status_desc */
217 #define STATUS_OWNER_HOST (0x1ULL << 56)
218 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220 /* Status descriptor:
221 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
222 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
223 53-55 desc_cnt, 56-57 owner, 58-63 opcode
225 #define qlcnic_get_sts_port(sts_data) \
227 #define qlcnic_get_sts_status(sts_data) \
228 (((sts_data) >> 4) & 0x0F)
229 #define qlcnic_get_sts_type(sts_data) \
230 (((sts_data) >> 8) & 0x0F)
231 #define qlcnic_get_sts_totallength(sts_data) \
232 (((sts_data) >> 12) & 0xFFFF)
233 #define qlcnic_get_sts_refhandle(sts_data) \
234 (((sts_data) >> 28) & 0xFFFF)
235 #define qlcnic_get_sts_prot(sts_data) \
236 (((sts_data) >> 44) & 0x0F)
237 #define qlcnic_get_sts_pkt_offset(sts_data) \
238 (((sts_data) >> 48) & 0x1F)
239 #define qlcnic_get_sts_desc_cnt(sts_data) \
240 (((sts_data) >> 53) & 0x7)
241 #define qlcnic_get_sts_opcode(sts_data) \
242 (((sts_data) >> 58) & 0x03F)
244 #define qlcnic_get_lro_sts_refhandle(sts_data) \
245 ((sts_data) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_length(sts_data) \
247 (((sts_data) >> 16) & 0x0FFFF)
248 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
249 (((sts_data) >> 32) & 0x0FF)
250 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
251 (((sts_data) >> 40) & 0x0FF)
252 #define qlcnic_get_lro_sts_timestamp(sts_data) \
253 (((sts_data) >> 48) & 0x1)
254 #define qlcnic_get_lro_sts_type(sts_data) \
255 (((sts_data) >> 49) & 0x7)
256 #define qlcnic_get_lro_sts_push_flag(sts_data) \
257 (((sts_data) >> 52) & 0x1)
258 #define qlcnic_get_lro_sts_seq_number(sts_data) \
259 ((sts_data) & 0x0FFFFFFFF)
263 __le64 status_desc_data[2];
264 } __attribute__ ((aligned(16)));
266 /* UNIFIED ROMIMAGE */
267 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
268 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
269 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
270 #define QLCNIC_UNI_DIR_SECT_FW 0x7
273 #define QLCNIC_UNI_CHIP_REV_OFF 10
274 #define QLCNIC_UNI_FLAGS_OFF 11
275 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
276 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
277 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
279 struct uni_table_desc{
286 struct uni_data_desc{
292 /* Magic number to let user know flash is programmed */
293 #define QLCNIC_BDINFO_MAGIC 0x12345678
295 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
296 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
297 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
298 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
299 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
300 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
301 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
302 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
303 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
304 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
305 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
306 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
307 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
308 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
310 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
312 /* Flash memory map */
313 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
314 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
315 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
316 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
318 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
319 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
320 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
321 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
323 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
324 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
326 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
327 #define QLCNIC_UNIFIED_ROMIMAGE 0
328 #define QLCNIC_FLASH_ROMIMAGE 1
329 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
331 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
332 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
334 extern char qlcnic_driver_name[];
336 /* Number of status descriptors to handle per interrupt */
337 #define MAX_STATUS_HANDLE (64)
340 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
341 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
343 struct qlcnic_skb_frag {
348 struct qlcnic_recv_crb {
349 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
350 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
351 u32 sw_int_mask[NUM_STS_DESC_RINGS];
354 /* Following defines are for the state of the buffers */
355 #define QLCNIC_BUFFER_FREE 0
356 #define QLCNIC_BUFFER_BUSY 1
359 * There will be one qlcnic_buffer per skb packet. These will be
360 * used to save the dma info for pci_unmap_page()
362 struct qlcnic_cmd_buffer {
364 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
368 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
369 struct qlcnic_rx_buffer {
370 struct list_head list;
377 #define QLCNIC_GBE 0x01
378 #define QLCNIC_XGBE 0x02
381 * One hardware_context{} per adapter
382 * contains interrupt info as well shared hardware info.
384 struct qlcnic_hardware_context {
385 void __iomem *pci_base0;
386 void __iomem *ocm_win_crb;
388 unsigned long pci_len0;
391 struct mutex mem_lock;
400 struct qlcnic_adapter_stats {
414 u64 skb_alloc_failure;
416 u64 rx_dma_map_error;
417 u64 tx_dma_map_error;
421 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
422 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
424 struct qlcnic_host_rds_ring {
430 void __iomem *crb_rcv_producer;
431 struct rcv_desc *desc_head;
432 struct qlcnic_rx_buffer *rx_buf_arr;
433 struct list_head free_list;
435 dma_addr_t phys_addr;
438 struct qlcnic_host_sds_ring {
441 void __iomem *crb_sts_consumer;
442 void __iomem *crb_intr_mask;
444 struct status_desc *desc_head;
445 struct qlcnic_adapter *adapter;
446 struct napi_struct napi;
447 struct list_head free_list[NUM_RCV_DESC_RINGS];
451 dma_addr_t phys_addr;
452 char name[IFNAMSIZ+4];
455 struct qlcnic_host_tx_ring {
459 void __iomem *crb_cmd_producer;
462 struct netdev_queue *txq;
464 struct qlcnic_cmd_buffer *cmd_buf_arr;
465 struct cmd_desc_type0 *desc_head;
466 dma_addr_t phys_addr;
467 dma_addr_t hw_cons_phys_addr;
471 * Receive context. There is one such structure per instance of the
472 * receive processing. Any state information that is relevant to
473 * the receive, and is must be in this structure. The global data may be
476 struct qlcnic_recv_context {
481 struct qlcnic_host_rds_ring *rds_rings;
482 struct qlcnic_host_sds_ring *sds_rings;
485 /* HW context creation */
487 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
488 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
489 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
491 #define QLCNIC_CDRP_CMD_BIT 0x80000000
494 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
495 * in the crb QLCNIC_CDRP_CRB_OFFSET.
497 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
498 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
500 #define QLCNIC_CDRP_RSP_OK 0x00000001
501 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
502 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
505 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
506 * the crb QLCNIC_CDRP_CRB_OFFSET.
508 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
509 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
511 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
512 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
513 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
514 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
515 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
516 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
517 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
518 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
519 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
520 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
521 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
522 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
523 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
524 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
525 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
526 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
527 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
528 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
529 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
530 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
531 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
532 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
533 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
534 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
535 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
536 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
537 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
539 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
540 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
541 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
542 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
543 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
544 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
545 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
546 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
547 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
548 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
549 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
551 #define QLCNIC_RCODE_SUCCESS 0
552 #define QLCNIC_RCODE_TIMEOUT 17
553 #define QLCNIC_DESTROY_CTX_RESET 0
556 * Capabilities Announced
558 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
559 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
560 #define QLCNIC_CAP0_LSO (1 << 6)
561 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
562 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
563 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
568 #define QLCNIC_HOST_CTX_STATE_FREED 0
569 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
575 struct qlcnic_hostrq_sds_ring {
576 __le64 host_phys_addr; /* Ring base addr */
577 __le32 ring_size; /* Ring entries */
579 __le16 rsvd; /* Padding */
582 struct qlcnic_hostrq_rds_ring {
583 __le64 host_phys_addr; /* Ring base addr */
584 __le64 buff_size; /* Packet buffer size */
585 __le32 ring_size; /* Ring entries */
586 __le32 ring_kind; /* Class of ring */
589 struct qlcnic_hostrq_rx_ctx {
590 __le64 host_rsp_dma_addr; /* Response dma'd here */
591 __le32 capabilities[4]; /* Flag bit vector */
592 __le32 host_int_crb_mode; /* Interrupt crb usage */
593 __le32 host_rds_crb_mode; /* RDS crb usage */
594 /* These ring offsets are relative to data[0] below */
595 __le32 rds_ring_offset; /* Offset to RDS config */
596 __le32 sds_ring_offset; /* Offset to SDS config */
597 __le16 num_rds_rings; /* Count of RDS rings */
598 __le16 num_sds_rings; /* Count of SDS rings */
599 __le16 valid_field_offset;
602 u8 reserved[128]; /* reserve space for future expansion*/
603 /* MUST BE 64-bit aligned.
604 The following is packed:
606 - N hostrq_sds_rings */
610 struct qlcnic_cardrsp_rds_ring{
611 __le32 host_producer_crb; /* Crb to use */
612 __le32 rsvd1; /* Padding */
615 struct qlcnic_cardrsp_sds_ring {
616 __le32 host_consumer_crb; /* Crb to use */
617 __le32 interrupt_crb; /* Crb to use */
620 struct qlcnic_cardrsp_rx_ctx {
621 /* These ring offsets are relative to data[0] below */
622 __le32 rds_ring_offset; /* Offset to RDS config */
623 __le32 sds_ring_offset; /* Offset to SDS config */
624 __le32 host_ctx_state; /* Starting State */
625 __le32 num_fn_per_port; /* How many PCI fn share the port */
626 __le16 num_rds_rings; /* Count of RDS rings */
627 __le16 num_sds_rings; /* Count of SDS rings */
628 __le16 context_id; /* Handle for context */
629 u8 phys_port; /* Physical id of port */
630 u8 virt_port; /* Virtual/Logical id of port */
631 u8 reserved[128]; /* save space for future expansion */
632 /* MUST BE 64-bit aligned.
633 The following is packed:
634 - N cardrsp_rds_rings
635 - N cardrs_sds_rings */
639 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
640 (sizeof(HOSTRQ_RX) + \
641 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
642 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
644 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
645 (sizeof(CARDRSP_RX) + \
646 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
647 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
653 struct qlcnic_hostrq_cds_ring {
654 __le64 host_phys_addr; /* Ring base addr */
655 __le32 ring_size; /* Ring entries */
656 __le32 rsvd; /* Padding */
659 struct qlcnic_hostrq_tx_ctx {
660 __le64 host_rsp_dma_addr; /* Response dma'd here */
661 __le64 cmd_cons_dma_addr; /* */
662 __le64 dummy_dma_addr; /* */
663 __le32 capabilities[4]; /* Flag bit vector */
664 __le32 host_int_crb_mode; /* Interrupt crb usage */
665 __le32 rsvd1; /* Padding */
666 __le16 rsvd2; /* Padding */
667 __le16 interrupt_ctl;
669 __le16 rsvd3; /* Padding */
670 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
671 u8 reserved[128]; /* future expansion */
674 struct qlcnic_cardrsp_cds_ring {
675 __le32 host_producer_crb; /* Crb to use */
676 __le32 interrupt_crb; /* Crb to use */
679 struct qlcnic_cardrsp_tx_ctx {
680 __le32 host_ctx_state; /* Starting state */
681 __le16 context_id; /* Handle for context */
682 u8 phys_port; /* Physical id of port */
683 u8 virt_port; /* Virtual/Logical id of port */
684 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
685 u8 reserved[128]; /* future expansion */
688 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
689 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
693 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
694 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
695 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
696 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
698 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
699 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
700 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
701 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
702 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
707 #define MC_COUNT_P3P 38
709 #define QLCNIC_MAC_NOOP 0
710 #define QLCNIC_MAC_ADD 1
711 #define QLCNIC_MAC_DEL 2
712 #define QLCNIC_MAC_VLAN_ADD 3
713 #define QLCNIC_MAC_VLAN_DEL 4
715 struct qlcnic_mac_list_s {
716 struct list_head list;
717 uint8_t mac_addr[ETH_ALEN+2];
721 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
722 * adjusted based on configured MTU.
724 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
725 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
726 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
727 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
729 #define QLCNIC_INTR_DEFAULT 0x04
731 union qlcnic_nic_intr_coalesce_data {
741 struct qlcnic_nic_intr_coalesce {
743 u16 rate_sample_time;
748 union qlcnic_nic_intr_coalesce_data normal;
749 union qlcnic_nic_intr_coalesce_data low;
750 union qlcnic_nic_intr_coalesce_data high;
751 union qlcnic_nic_intr_coalesce_data irq;
754 #define QLCNIC_HOST_REQUEST 0x13
755 #define QLCNIC_REQUEST 0x14
757 #define QLCNIC_MAC_EVENT 0x1
759 #define QLCNIC_IP_UP 2
760 #define QLCNIC_IP_DOWN 3
763 * Driver --> Firmware
765 #define QLCNIC_H2C_OPCODE_START 0
766 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
767 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
768 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
769 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
770 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
771 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
772 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
773 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
774 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
775 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
776 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
777 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
778 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
779 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
780 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
781 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
782 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
783 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
784 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
785 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
786 #define QLCNIC_C2C_OPCODE 22
787 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
788 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
789 #define QLCNIC_H2C_OPCODE_LAST 25
791 * Firmware --> Driver
794 #define QLCNIC_C2H_OPCODE_START 128
795 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
796 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
797 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
798 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
799 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
800 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
801 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
802 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
803 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
804 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
805 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
806 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
807 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
808 #define QLCNIC_C2H_OPCODE_LAST 142
810 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
811 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
812 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
814 #define QLCNIC_LRO_REQUEST_CLEANUP 4
816 /* Capabilites received */
817 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
818 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
819 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
820 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
823 #define LINKEVENT_MODULE_NOT_PRESENT 1
824 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
825 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
826 #define LINKEVENT_MODULE_OPTICAL_LRM 4
827 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
828 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
829 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
830 #define LINKEVENT_MODULE_TWINAX 8
832 #define LINKSPEED_10GBPS 10000
833 #define LINKSPEED_1GBPS 1000
834 #define LINKSPEED_100MBPS 100
835 #define LINKSPEED_10MBPS 10
837 #define LINKSPEED_ENCODED_10MBPS 0
838 #define LINKSPEED_ENCODED_100MBPS 1
839 #define LINKSPEED_ENCODED_1GBPS 2
841 #define LINKEVENT_AUTONEG_DISABLED 0
842 #define LINKEVENT_AUTONEG_ENABLED 1
844 #define LINKEVENT_HALF_DUPLEX 0
845 #define LINKEVENT_FULL_DUPLEX 1
847 #define LINKEVENT_LINKSPEED_MBPS 0
848 #define LINKEVENT_LINKSPEED_ENCODED 1
850 #define AUTO_FW_RESET_ENABLED 0x01
851 /* firmware response header:
852 * 63:58 - message type
856 * 47:40 - completion id
861 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
862 ((msg_hdr >> 32) & 0xFF)
864 struct qlcnic_fw_msg {
874 struct qlcnic_nic_req {
880 struct qlcnic_mac_req {
886 struct qlcnic_vlan_req {
891 struct qlcnic_ipaddr {
896 #define QLCNIC_MSI_ENABLED 0x02
897 #define QLCNIC_MSIX_ENABLED 0x04
898 #define QLCNIC_LRO_ENABLED 0x08
899 #define QLCNIC_LRO_DISABLED 0x00
900 #define QLCNIC_BRIDGE_ENABLED 0X10
901 #define QLCNIC_DIAG_ENABLED 0x20
902 #define QLCNIC_ESWITCH_ENABLED 0x40
903 #define QLCNIC_ADAPTER_INITIALIZED 0x80
904 #define QLCNIC_TAGGING_ENABLED 0x100
905 #define QLCNIC_MACSPOOF 0x200
906 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
907 #define QLCNIC_PROMISC_DISABLED 0x800
908 #define QLCNIC_NEED_FLR 0x1000
909 #define QLCNIC_IS_MSI_FAMILY(adapter) \
910 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
912 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
913 #define QLCNIC_MSIX_TBL_SPACE 8192
914 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
915 #define QLCNIC_MSIX_TBL_PGSIZE 4096
917 #define QLCNIC_NETDEV_WEIGHT 128
918 #define QLCNIC_ADAPTER_UP_MAGIC 777
920 #define __QLCNIC_FW_ATTACHED 0
921 #define __QLCNIC_DEV_UP 1
922 #define __QLCNIC_RESETTING 2
923 #define __QLCNIC_START_FW 4
924 #define __QLCNIC_AER 5
926 #define QLCNIC_INTERRUPT_TEST 1
927 #define QLCNIC_LOOPBACK_TEST 2
929 #define QLCNIC_FILTER_AGE 80
930 #define QLCNIC_READD_AGE 20
931 #define QLCNIC_LB_MAX_FILTERS 64
933 struct qlcnic_filter {
934 struct hlist_node fnode;
940 struct qlcnic_filter_hash {
941 struct hlist_head *fhead;
946 struct qlcnic_adapter {
947 struct qlcnic_hardware_context ahw;
949 struct net_device *netdev;
950 struct pci_dev *pdev;
951 struct list_head mac_list;
953 spinlock_t tx_clean_lock;
954 spinlock_t mac_learn_lock;
1012 u8 mac_addr[ETH_ALEN];
1016 struct vlan_group *vlgrp;
1017 struct qlcnic_npar_info *npars;
1018 struct qlcnic_eswitch *eswitch;
1019 struct qlcnic_nic_template *nic_ops;
1021 struct qlcnic_adapter_stats stats;
1023 struct qlcnic_recv_context recv_ctx;
1024 struct qlcnic_host_tx_ring *tx_ring;
1026 void __iomem *tgt_mask_reg;
1027 void __iomem *tgt_status_reg;
1028 void __iomem *crb_int_state_reg;
1029 void __iomem *isr_int_vec;
1031 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1033 struct delayed_work fw_work;
1035 struct qlcnic_nic_intr_coalesce coal;
1037 struct qlcnic_filter_hash fhash;
1039 unsigned long state;
1040 __le32 file_prd_off; /*File fw product offset*/
1042 const struct firmware *fw;
1045 struct qlcnic_info {
1047 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1049 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1051 __le32 capabilities;
1063 struct qlcnic_pci_info {
1064 __le16 id; /* pci function id */
1065 __le16 active; /* 1 = Enabled */
1066 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1067 __le16 default_port; /* default port number */
1069 __le16 tx_min_bw; /* Multiple of 100mbpc */
1071 __le16 reserved1[2];
1077 struct qlcnic_npar_info {
1093 struct qlcnic_eswitch {
1097 u8 active_ucast_filters;
1098 u8 max_ucast_filters;
1099 u8 max_active_vlans;
1102 #define QLCNIC_SWITCH_ENABLE BIT_1
1103 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1104 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1105 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1109 /* Return codes for Error handling */
1110 #define QL_STATUS_INVALID_PARAM -1
1112 #define MAX_BW 100 /* % of link speed */
1113 #define MAX_VLAN_ID 4095
1114 #define MIN_VLAN_ID 2
1115 #define MAX_TX_QUEUES 1
1116 #define MAX_RX_QUEUES 4
1117 #define DEFAULT_MAC_LEARN 1
1119 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1120 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1121 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1122 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1124 struct qlcnic_pci_func_cfg {
1134 struct qlcnic_npar_func_cfg {
1145 struct qlcnic_pm_func_cfg {
1152 struct qlcnic_esw_func_cfg {
1166 #define QLCNIC_STATS_VERSION 1
1167 #define QLCNIC_STATS_PORT 1
1168 #define QLCNIC_STATS_ESWITCH 2
1169 #define QLCNIC_QUERY_RX_COUNTER 0
1170 #define QLCNIC_QUERY_TX_COUNTER 1
1171 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1173 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1175 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1176 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1178 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1179 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1183 struct __qlcnic_esw_statistics {
1188 __le64 unicast_frames;
1189 __le64 multicast_frames;
1190 __le64 broadcast_frames;
1191 __le64 dropped_frames;
1193 __le64 local_frames;
1198 struct qlcnic_esw_statistics {
1199 struct __qlcnic_esw_statistics rx;
1200 struct __qlcnic_esw_statistics tx;
1203 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1204 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1206 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1207 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1208 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1209 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1210 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1211 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1213 #define ADDR_IN_RANGE(addr, low, high) \
1214 (((addr) < (high)) && ((addr) >= (low)))
1216 #define QLCRD32(adapter, off) \
1217 (qlcnic_hw_read_wx_2M(adapter, off))
1218 #define QLCWR32(adapter, off, val) \
1219 (qlcnic_hw_write_wx_2M(adapter, off, val))
1221 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1222 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1224 #define qlcnic_rom_lock(a) \
1225 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1226 #define qlcnic_rom_unlock(a) \
1227 qlcnic_pcie_sem_unlock((a), 2)
1228 #define qlcnic_phy_lock(a) \
1229 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1230 #define qlcnic_phy_unlock(a) \
1231 qlcnic_pcie_sem_unlock((a), 3)
1232 #define qlcnic_api_lock(a) \
1233 qlcnic_pcie_sem_lock((a), 5, 0)
1234 #define qlcnic_api_unlock(a) \
1235 qlcnic_pcie_sem_unlock((a), 5)
1236 #define qlcnic_sw_lock(a) \
1237 qlcnic_pcie_sem_lock((a), 6, 0)
1238 #define qlcnic_sw_unlock(a) \
1239 qlcnic_pcie_sem_unlock((a), 6)
1240 #define crb_win_lock(a) \
1241 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1242 #define crb_win_unlock(a) \
1243 qlcnic_pcie_sem_unlock((a), 7)
1245 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1246 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1247 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1248 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1249 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1251 /* Functions from qlcnic_init.c */
1252 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1253 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1254 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1255 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1256 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1257 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1258 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1260 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1261 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1262 u8 *bytes, size_t size);
1263 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1264 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1266 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1268 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1269 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1271 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1272 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1274 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1275 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1276 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1278 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1279 void qlcnic_watchdog_task(struct work_struct *work);
1280 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1281 struct qlcnic_host_rds_ring *rds_ring);
1282 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1283 void qlcnic_set_multi(struct net_device *netdev);
1284 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1285 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1286 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1287 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1288 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1289 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1290 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1292 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1293 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1294 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1295 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1296 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1297 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1298 struct qlcnic_host_tx_ring *tx_ring);
1299 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1301 /* Functions from qlcnic_main.c */
1302 int qlcnic_reset_context(struct qlcnic_adapter *);
1303 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1304 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1305 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1306 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1307 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1309 /* Management functions */
1310 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1311 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1312 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1313 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1315 /* eSwitch management functions */
1316 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1317 struct qlcnic_esw_func_cfg *);
1318 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1319 struct qlcnic_esw_func_cfg *);
1320 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1321 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1322 struct __qlcnic_esw_statistics *);
1323 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1324 struct __qlcnic_esw_statistics *);
1325 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1326 extern int qlcnic_config_tso;
1329 * QLOGIC Board information
1332 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1333 struct qlcnic_brdinfo {
1334 unsigned short vendor;
1335 unsigned short device;
1336 unsigned short sub_vendor;
1337 unsigned short sub_device;
1338 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1341 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1342 {0x1077, 0x8020, 0x1077, 0x203,
1343 "8200 Series Single Port 10GbE Converged Network Adapter "
1344 "(TCP/IP Networking)"},
1345 {0x1077, 0x8020, 0x1077, 0x207,
1346 "8200 Series Dual Port 10GbE Converged Network Adapter "
1347 "(TCP/IP Networking)"},
1348 {0x1077, 0x8020, 0x1077, 0x20b,
1349 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1350 {0x1077, 0x8020, 0x1077, 0x20c,
1351 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1352 {0x1077, 0x8020, 0x1077, 0x20f,
1353 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1354 {0x1077, 0x8020, 0x103c, 0x3733,
1355 "NC523SFP 10Gb 2-port Server Adapter"},
1356 {0x1077, 0x8020, 0x103c, 0x3346,
1357 "CN1000Q Dual Port Converged Network Adapter"},
1358 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1361 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1363 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1366 if (tx_ring->producer < tx_ring->sw_consumer)
1367 return tx_ring->sw_consumer - tx_ring->producer;
1369 return tx_ring->sw_consumer + tx_ring->num_desc -
1373 extern const struct ethtool_ops qlcnic_ethtool_ops;
1375 struct qlcnic_nic_template {
1376 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1377 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1378 int (*start_firmware) (struct qlcnic_adapter *);
1381 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1382 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1383 printk(KERN_INFO "%s: %s: " _fmt, \
1384 dev_name(&adapter->pdev->dev), \
1385 __func__, ##_args); \
1388 #endif /* __QLCNIC_H_ */