2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
45 #include <linux/vmalloc.h>
48 #include <asm/byteorder.h>
50 #include "qlcnic_hdr.h"
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 10
55 #define QLCNIC_LINUX_VERSIONID "5.0.10"
56 #define QLCNIC_DRV_IDC_VER 0x01
57 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
58 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
60 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
61 #define _major(v) (((v) >> 24) & 0xff)
62 #define _minor(v) (((v) >> 16) & 0xff)
63 #define _build(v) ((v) & 0xffff)
65 /* version in image has weird encoding:
68 * 31:16 - build (little endian)
70 #define QLCNIC_DECODE_VERSION(v) \
71 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
73 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
74 #define QLCNIC_NUM_FLASH_SECTORS (64)
75 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
76 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
77 * QLCNIC_FLASH_SECTOR_SIZE)
79 #define RCV_DESC_RINGSIZE(rds_ring) \
80 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
81 #define RCV_BUFF_RINGSIZE(rds_ring) \
82 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
83 #define STATUS_DESC_RINGSIZE(sds_ring) \
84 (sizeof(struct status_desc) * (sds_ring)->num_desc)
85 #define TX_BUFF_RINGSIZE(tx_ring) \
86 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
87 #define TX_DESC_RINGSIZE(tx_ring) \
88 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
90 #define QLCNIC_P3P_A0 0x50
92 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
94 #define FIRST_PAGE_GROUP_START 0
95 #define FIRST_PAGE_GROUP_END 0x100000
97 #define P3_MAX_MTU (9600)
98 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
100 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
101 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
102 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
103 #define QLCNIC_LRO_BUFFER_EXTRA 2048
105 /* Opcodes to be used with the commands */
106 #define TX_ETHER_PKT 0x01
107 #define TX_TCP_PKT 0x02
108 #define TX_UDP_PKT 0x03
109 #define TX_IP_PKT 0x04
110 #define TX_TCP_LSO 0x05
111 #define TX_TCP_LSO6 0x06
112 #define TX_IPSEC 0x07
113 #define TX_IPSEC_CMD 0x0a
114 #define TX_TCPV6_PKT 0x0b
115 #define TX_UDPV6_PKT 0x0c
118 #define MAX_TSO_HEADER_DESC 2
119 #define MGMT_CMD_DESC_RESV 4
120 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
121 + MGMT_CMD_DESC_RESV)
122 #define QLCNIC_MAX_TX_TIMEOUTS 2
125 * Following are the states of the Phantom. Phantom will set them and
126 * Host will read to check if the fields are correct.
128 #define PHAN_INITIALIZE_FAILED 0xffff
129 #define PHAN_INITIALIZE_COMPLETE 0xff01
131 /* Host writes the following to notify that it has done the init-handshake */
132 #define PHAN_INITIALIZE_ACK 0xf00f
133 #define PHAN_PEG_RCV_INITIALIZED 0xff01
135 #define NUM_RCV_DESC_RINGS 3
136 #define NUM_STS_DESC_RINGS 4
138 #define RCV_RING_NORMAL 0
139 #define RCV_RING_JUMBO 1
141 #define MIN_CMD_DESCRIPTORS 64
142 #define MIN_RCV_DESCRIPTORS 64
143 #define MIN_JUMBO_DESCRIPTORS 32
145 #define MAX_CMD_DESCRIPTORS 1024
146 #define MAX_RCV_DESCRIPTORS_1G 4096
147 #define MAX_RCV_DESCRIPTORS_10G 8192
148 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
149 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
151 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
152 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
153 #define MAX_RDS_RINGS 2
155 #define get_next_index(index, length) \
156 (((index) + 1) & ((length) - 1))
159 * Following data structures describe the descriptors that will be used.
160 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
161 * we are doing LSO (above the 1500 size packet) only.
164 #define FLAGS_VLAN_TAGGED 0x10
165 #define FLAGS_VLAN_OOB 0x40
167 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
168 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
169 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
170 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
171 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
172 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
174 #define qlcnic_set_tx_port(_desc, _port) \
175 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
177 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
178 ((_desc)->flags_opcode |= \
179 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
181 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
182 ((_desc)->nfrags__length = \
183 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
185 struct cmd_desc_type0 {
186 u8 tcp_hdr_offset; /* For LSO only */
187 u8 ip_hdr_offset; /* For LSO only */
188 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
189 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
193 __le16 reference_handle;
195 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
196 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
197 __le16 conn_id; /* IPSec offoad only */
202 __le16 buffer_length[4];
206 u8 eth_addr[ETH_ALEN];
209 } __attribute__ ((aligned(64)));
211 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
213 __le16 reference_handle;
215 __le32 buffer_length; /* allocated buffer length (usually 2K) */
219 /* opcode field in status_desc */
220 #define QLCNIC_SYN_OFFLOAD 0x03
221 #define QLCNIC_RXPKT_DESC 0x04
222 #define QLCNIC_OLD_RXPKT_DESC 0x3f
223 #define QLCNIC_RESPONSE_DESC 0x05
224 #define QLCNIC_LRO_DESC 0x12
226 /* for status field in status_desc */
227 #define STATUS_CKSUM_LOOP 0
228 #define STATUS_CKSUM_OK 2
230 /* owner bits of status_desc */
231 #define STATUS_OWNER_HOST (0x1ULL << 56)
232 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
234 /* Status descriptor:
235 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
236 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
237 53-55 desc_cnt, 56-57 owner, 58-63 opcode
239 #define qlcnic_get_sts_port(sts_data) \
241 #define qlcnic_get_sts_status(sts_data) \
242 (((sts_data) >> 4) & 0x0F)
243 #define qlcnic_get_sts_type(sts_data) \
244 (((sts_data) >> 8) & 0x0F)
245 #define qlcnic_get_sts_totallength(sts_data) \
246 (((sts_data) >> 12) & 0xFFFF)
247 #define qlcnic_get_sts_refhandle(sts_data) \
248 (((sts_data) >> 28) & 0xFFFF)
249 #define qlcnic_get_sts_prot(sts_data) \
250 (((sts_data) >> 44) & 0x0F)
251 #define qlcnic_get_sts_pkt_offset(sts_data) \
252 (((sts_data) >> 48) & 0x1F)
253 #define qlcnic_get_sts_desc_cnt(sts_data) \
254 (((sts_data) >> 53) & 0x7)
255 #define qlcnic_get_sts_opcode(sts_data) \
256 (((sts_data) >> 58) & 0x03F)
258 #define qlcnic_get_lro_sts_refhandle(sts_data) \
259 ((sts_data) & 0x0FFFF)
260 #define qlcnic_get_lro_sts_length(sts_data) \
261 (((sts_data) >> 16) & 0x0FFFF)
262 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
263 (((sts_data) >> 32) & 0x0FF)
264 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
265 (((sts_data) >> 40) & 0x0FF)
266 #define qlcnic_get_lro_sts_timestamp(sts_data) \
267 (((sts_data) >> 48) & 0x1)
268 #define qlcnic_get_lro_sts_type(sts_data) \
269 (((sts_data) >> 49) & 0x7)
270 #define qlcnic_get_lro_sts_push_flag(sts_data) \
271 (((sts_data) >> 52) & 0x1)
272 #define qlcnic_get_lro_sts_seq_number(sts_data) \
273 ((sts_data) & 0x0FFFFFFFF)
277 __le64 status_desc_data[2];
278 } __attribute__ ((aligned(16)));
280 /* UNIFIED ROMIMAGE */
281 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
282 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
283 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
284 #define QLCNIC_UNI_DIR_SECT_FW 0x7
287 #define QLCNIC_UNI_CHIP_REV_OFF 10
288 #define QLCNIC_UNI_FLAGS_OFF 11
289 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
290 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
291 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
293 struct uni_table_desc{
300 struct uni_data_desc{
306 /* Magic number to let user know flash is programmed */
307 #define QLCNIC_BDINFO_MAGIC 0x12345678
309 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
310 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
311 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
312 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
313 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
314 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
315 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
316 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
317 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
318 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
319 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
320 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
321 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
322 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
324 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
326 /* Flash memory map */
327 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
328 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
329 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
330 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
332 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
333 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
334 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
335 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
337 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
338 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
340 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
341 #define QLCNIC_UNIFIED_ROMIMAGE 0
342 #define QLCNIC_FLASH_ROMIMAGE 1
343 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
345 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
346 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
348 extern char qlcnic_driver_name[];
350 /* Number of status descriptors to handle per interrupt */
351 #define MAX_STATUS_HANDLE (64)
354 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
355 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
357 struct qlcnic_skb_frag {
362 struct qlcnic_recv_crb {
363 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
364 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
365 u32 sw_int_mask[NUM_STS_DESC_RINGS];
368 /* Following defines are for the state of the buffers */
369 #define QLCNIC_BUFFER_FREE 0
370 #define QLCNIC_BUFFER_BUSY 1
373 * There will be one qlcnic_buffer per skb packet. These will be
374 * used to save the dma info for pci_unmap_page()
376 struct qlcnic_cmd_buffer {
378 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
382 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
383 struct qlcnic_rx_buffer {
384 struct list_head list;
391 #define QLCNIC_GBE 0x01
392 #define QLCNIC_XGBE 0x02
395 * One hardware_context{} per adapter
396 * contains interrupt info as well shared hardware info.
398 struct qlcnic_hardware_context {
399 void __iomem *pci_base0;
400 void __iomem *ocm_win_crb;
402 unsigned long pci_len0;
405 struct mutex mem_lock;
414 struct qlcnic_adapter_stats {
428 u64 skb_alloc_failure;
430 u64 rx_dma_map_error;
431 u64 tx_dma_map_error;
435 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
436 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
438 struct qlcnic_host_rds_ring {
444 void __iomem *crb_rcv_producer;
445 struct rcv_desc *desc_head;
446 struct qlcnic_rx_buffer *rx_buf_arr;
447 struct list_head free_list;
449 dma_addr_t phys_addr;
452 struct qlcnic_host_sds_ring {
455 void __iomem *crb_sts_consumer;
456 void __iomem *crb_intr_mask;
458 struct status_desc *desc_head;
459 struct qlcnic_adapter *adapter;
460 struct napi_struct napi;
461 struct list_head free_list[NUM_RCV_DESC_RINGS];
465 dma_addr_t phys_addr;
466 char name[IFNAMSIZ+4];
469 struct qlcnic_host_tx_ring {
473 void __iomem *crb_cmd_producer;
476 struct netdev_queue *txq;
478 struct qlcnic_cmd_buffer *cmd_buf_arr;
479 struct cmd_desc_type0 *desc_head;
480 dma_addr_t phys_addr;
481 dma_addr_t hw_cons_phys_addr;
485 * Receive context. There is one such structure per instance of the
486 * receive processing. Any state information that is relevant to
487 * the receive, and is must be in this structure. The global data may be
490 struct qlcnic_recv_context {
495 struct qlcnic_host_rds_ring *rds_rings;
496 struct qlcnic_host_sds_ring *sds_rings;
499 /* HW context creation */
501 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
502 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
503 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
505 #define QLCNIC_CDRP_CMD_BIT 0x80000000
508 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
509 * in the crb QLCNIC_CDRP_CRB_OFFSET.
511 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
512 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
514 #define QLCNIC_CDRP_RSP_OK 0x00000001
515 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
516 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
519 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
520 * the crb QLCNIC_CDRP_CRB_OFFSET.
522 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
523 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
525 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
526 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
527 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
528 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
529 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
530 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
531 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
532 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
533 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
534 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
535 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
536 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
537 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
538 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
539 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
540 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
541 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
542 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
543 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
544 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
545 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
546 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
547 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
548 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
549 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
550 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
551 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
553 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
554 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
555 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
556 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
557 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
558 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
559 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
560 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
561 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
562 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
563 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
565 #define QLCNIC_RCODE_SUCCESS 0
566 #define QLCNIC_RCODE_TIMEOUT 17
567 #define QLCNIC_DESTROY_CTX_RESET 0
570 * Capabilities Announced
572 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
573 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
574 #define QLCNIC_CAP0_LSO (1 << 6)
575 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
576 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
577 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
582 #define QLCNIC_HOST_CTX_STATE_FREED 0
583 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
589 struct qlcnic_hostrq_sds_ring {
590 __le64 host_phys_addr; /* Ring base addr */
591 __le32 ring_size; /* Ring entries */
593 __le16 rsvd; /* Padding */
596 struct qlcnic_hostrq_rds_ring {
597 __le64 host_phys_addr; /* Ring base addr */
598 __le64 buff_size; /* Packet buffer size */
599 __le32 ring_size; /* Ring entries */
600 __le32 ring_kind; /* Class of ring */
603 struct qlcnic_hostrq_rx_ctx {
604 __le64 host_rsp_dma_addr; /* Response dma'd here */
605 __le32 capabilities[4]; /* Flag bit vector */
606 __le32 host_int_crb_mode; /* Interrupt crb usage */
607 __le32 host_rds_crb_mode; /* RDS crb usage */
608 /* These ring offsets are relative to data[0] below */
609 __le32 rds_ring_offset; /* Offset to RDS config */
610 __le32 sds_ring_offset; /* Offset to SDS config */
611 __le16 num_rds_rings; /* Count of RDS rings */
612 __le16 num_sds_rings; /* Count of SDS rings */
613 __le16 valid_field_offset;
616 u8 reserved[128]; /* reserve space for future expansion*/
617 /* MUST BE 64-bit aligned.
618 The following is packed:
620 - N hostrq_sds_rings */
624 struct qlcnic_cardrsp_rds_ring{
625 __le32 host_producer_crb; /* Crb to use */
626 __le32 rsvd1; /* Padding */
629 struct qlcnic_cardrsp_sds_ring {
630 __le32 host_consumer_crb; /* Crb to use */
631 __le32 interrupt_crb; /* Crb to use */
634 struct qlcnic_cardrsp_rx_ctx {
635 /* These ring offsets are relative to data[0] below */
636 __le32 rds_ring_offset; /* Offset to RDS config */
637 __le32 sds_ring_offset; /* Offset to SDS config */
638 __le32 host_ctx_state; /* Starting State */
639 __le32 num_fn_per_port; /* How many PCI fn share the port */
640 __le16 num_rds_rings; /* Count of RDS rings */
641 __le16 num_sds_rings; /* Count of SDS rings */
642 __le16 context_id; /* Handle for context */
643 u8 phys_port; /* Physical id of port */
644 u8 virt_port; /* Virtual/Logical id of port */
645 u8 reserved[128]; /* save space for future expansion */
646 /* MUST BE 64-bit aligned.
647 The following is packed:
648 - N cardrsp_rds_rings
649 - N cardrs_sds_rings */
653 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
654 (sizeof(HOSTRQ_RX) + \
655 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
656 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
658 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
659 (sizeof(CARDRSP_RX) + \
660 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
661 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
667 struct qlcnic_hostrq_cds_ring {
668 __le64 host_phys_addr; /* Ring base addr */
669 __le32 ring_size; /* Ring entries */
670 __le32 rsvd; /* Padding */
673 struct qlcnic_hostrq_tx_ctx {
674 __le64 host_rsp_dma_addr; /* Response dma'd here */
675 __le64 cmd_cons_dma_addr; /* */
676 __le64 dummy_dma_addr; /* */
677 __le32 capabilities[4]; /* Flag bit vector */
678 __le32 host_int_crb_mode; /* Interrupt crb usage */
679 __le32 rsvd1; /* Padding */
680 __le16 rsvd2; /* Padding */
681 __le16 interrupt_ctl;
683 __le16 rsvd3; /* Padding */
684 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
685 u8 reserved[128]; /* future expansion */
688 struct qlcnic_cardrsp_cds_ring {
689 __le32 host_producer_crb; /* Crb to use */
690 __le32 interrupt_crb; /* Crb to use */
693 struct qlcnic_cardrsp_tx_ctx {
694 __le32 host_ctx_state; /* Starting state */
695 __le16 context_id; /* Handle for context */
696 u8 phys_port; /* Physical id of port */
697 u8 virt_port; /* Virtual/Logical id of port */
698 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
699 u8 reserved[128]; /* future expansion */
702 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
703 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
707 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
708 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
709 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
710 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
712 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
713 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
714 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
715 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
716 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
721 #define MC_COUNT_P3 38
723 #define QLCNIC_MAC_NOOP 0
724 #define QLCNIC_MAC_ADD 1
725 #define QLCNIC_MAC_DEL 2
726 #define QLCNIC_MAC_VLAN_ADD 3
727 #define QLCNIC_MAC_VLAN_DEL 4
729 struct qlcnic_mac_list_s {
730 struct list_head list;
731 uint8_t mac_addr[ETH_ALEN+2];
735 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
736 * adjusted based on configured MTU.
738 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
739 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
740 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
741 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
743 #define QLCNIC_INTR_DEFAULT 0x04
745 union qlcnic_nic_intr_coalesce_data {
755 struct qlcnic_nic_intr_coalesce {
757 u16 rate_sample_time;
762 union qlcnic_nic_intr_coalesce_data normal;
763 union qlcnic_nic_intr_coalesce_data low;
764 union qlcnic_nic_intr_coalesce_data high;
765 union qlcnic_nic_intr_coalesce_data irq;
768 #define QLCNIC_HOST_REQUEST 0x13
769 #define QLCNIC_REQUEST 0x14
771 #define QLCNIC_MAC_EVENT 0x1
773 #define QLCNIC_IP_UP 2
774 #define QLCNIC_IP_DOWN 3
777 * Driver --> Firmware
779 #define QLCNIC_H2C_OPCODE_START 0
780 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
781 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
782 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
783 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
784 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
785 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
786 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
787 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
788 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
789 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
790 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
791 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
792 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
793 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
794 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
795 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
796 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
797 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
798 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
799 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
800 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
801 #define QLCNIC_C2C_OPCODE 22
802 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
803 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
804 #define QLCNIC_H2C_OPCODE_LAST 25
806 * Firmware --> Driver
809 #define QLCNIC_C2H_OPCODE_START 128
810 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
811 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
812 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
813 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
814 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
815 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
816 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
817 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
818 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
819 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
820 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
821 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
822 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
823 #define QLCNIC_C2H_OPCODE_LAST 142
825 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
826 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
827 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
829 #define QLCNIC_LRO_REQUEST_CLEANUP 4
831 /* Capabilites received */
832 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
833 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
834 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
835 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
838 #define LINKEVENT_MODULE_NOT_PRESENT 1
839 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
840 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
841 #define LINKEVENT_MODULE_OPTICAL_LRM 4
842 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
843 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
844 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
845 #define LINKEVENT_MODULE_TWINAX 8
847 #define LINKSPEED_10GBPS 10000
848 #define LINKSPEED_1GBPS 1000
849 #define LINKSPEED_100MBPS 100
850 #define LINKSPEED_10MBPS 10
852 #define LINKSPEED_ENCODED_10MBPS 0
853 #define LINKSPEED_ENCODED_100MBPS 1
854 #define LINKSPEED_ENCODED_1GBPS 2
856 #define LINKEVENT_AUTONEG_DISABLED 0
857 #define LINKEVENT_AUTONEG_ENABLED 1
859 #define LINKEVENT_HALF_DUPLEX 0
860 #define LINKEVENT_FULL_DUPLEX 1
862 #define LINKEVENT_LINKSPEED_MBPS 0
863 #define LINKEVENT_LINKSPEED_ENCODED 1
865 #define AUTO_FW_RESET_ENABLED 0x01
866 /* firmware response header:
867 * 63:58 - message type
871 * 47:40 - completion id
876 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
877 ((msg_hdr >> 32) & 0xFF)
879 struct qlcnic_fw_msg {
889 struct qlcnic_nic_req {
895 struct qlcnic_mac_req {
901 #define QLCNIC_MSI_ENABLED 0x02
902 #define QLCNIC_MSIX_ENABLED 0x04
903 #define QLCNIC_LRO_ENABLED 0x08
904 #define QLCNIC_LRO_DISABLED 0x00
905 #define QLCNIC_BRIDGE_ENABLED 0X10
906 #define QLCNIC_DIAG_ENABLED 0x20
907 #define QLCNIC_ESWITCH_ENABLED 0x40
908 #define QLCNIC_ADAPTER_INITIALIZED 0x80
909 #define QLCNIC_TAGGING_ENABLED 0x100
910 #define QLCNIC_MACSPOOF 0x200
911 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
912 #define QLCNIC_IS_MSI_FAMILY(adapter) \
913 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
915 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
916 #define QLCNIC_MSIX_TBL_SPACE 8192
917 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
918 #define QLCNIC_MSIX_TBL_PGSIZE 4096
920 #define QLCNIC_NETDEV_WEIGHT 128
921 #define QLCNIC_ADAPTER_UP_MAGIC 777
923 #define __QLCNIC_FW_ATTACHED 0
924 #define __QLCNIC_DEV_UP 1
925 #define __QLCNIC_RESETTING 2
926 #define __QLCNIC_START_FW 4
927 #define __QLCNIC_AER 5
929 #define QLCNIC_INTERRUPT_TEST 1
930 #define QLCNIC_LOOPBACK_TEST 2
932 #define QLCNIC_FILTER_AGE 80
933 #define QLCNIC_LB_MAX_FILTERS 64
935 struct qlcnic_filter {
936 struct hlist_node fnode;
942 struct qlcnic_filter_hash {
943 struct hlist_head *fhead;
948 struct qlcnic_adapter {
949 struct qlcnic_hardware_context ahw;
951 struct net_device *netdev;
952 struct pci_dev *pdev;
953 struct list_head mac_list;
955 spinlock_t tx_clean_lock;
956 spinlock_t mac_learn_lock;
1012 u8 mac_addr[ETH_ALEN];
1016 struct vlan_group *vlgrp;
1017 struct qlcnic_npar_info *npars;
1018 struct qlcnic_eswitch *eswitch;
1019 struct qlcnic_nic_template *nic_ops;
1021 struct qlcnic_adapter_stats stats;
1023 struct qlcnic_recv_context recv_ctx;
1024 struct qlcnic_host_tx_ring *tx_ring;
1026 void __iomem *tgt_mask_reg;
1027 void __iomem *tgt_status_reg;
1028 void __iomem *crb_int_state_reg;
1029 void __iomem *isr_int_vec;
1031 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1033 struct delayed_work fw_work;
1035 struct qlcnic_nic_intr_coalesce coal;
1037 struct qlcnic_filter_hash fhash;
1039 unsigned long state;
1040 __le32 file_prd_off; /*File fw product offset*/
1042 const struct firmware *fw;
1045 struct qlcnic_info {
1047 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1049 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1051 __le32 capabilities;
1063 struct qlcnic_pci_info {
1064 __le16 id; /* pci function id */
1065 __le16 active; /* 1 = Enabled */
1066 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1067 __le16 default_port; /* default port number */
1069 __le16 tx_min_bw; /* Multiple of 100mbpc */
1071 __le16 reserved1[2];
1077 struct qlcnic_npar_info {
1093 struct qlcnic_eswitch {
1097 u8 active_ucast_filters;
1098 u8 max_ucast_filters;
1099 u8 max_active_vlans;
1102 #define QLCNIC_SWITCH_ENABLE BIT_1
1103 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1104 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1105 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1109 /* Return codes for Error handling */
1110 #define QL_STATUS_INVALID_PARAM -1
1114 #define MAX_VLAN_ID 4095
1115 #define MIN_VLAN_ID 2
1116 #define MAX_TX_QUEUES 1
1117 #define MAX_RX_QUEUES 4
1118 #define DEFAULT_MAC_LEARN 1
1120 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID)
1121 #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW)
1122 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1123 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1125 struct qlcnic_pci_func_cfg {
1135 struct qlcnic_npar_func_cfg {
1146 struct qlcnic_pm_func_cfg {
1153 struct qlcnic_esw_func_cfg {
1167 #define QLCNIC_STATS_VERSION 1
1168 #define QLCNIC_STATS_PORT 1
1169 #define QLCNIC_STATS_ESWITCH 2
1170 #define QLCNIC_QUERY_RX_COUNTER 0
1171 #define QLCNIC_QUERY_TX_COUNTER 1
1172 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1174 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1176 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1177 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1179 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1180 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1184 struct __qlcnic_esw_statistics {
1189 __le64 unicast_frames;
1190 __le64 multicast_frames;
1191 __le64 broadcast_frames;
1192 __le64 dropped_frames;
1194 __le64 local_frames;
1199 struct qlcnic_esw_statistics {
1200 struct __qlcnic_esw_statistics rx;
1201 struct __qlcnic_esw_statistics tx;
1204 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1205 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1207 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1208 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1209 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1210 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1211 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1212 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1214 #define ADDR_IN_RANGE(addr, low, high) \
1215 (((addr) < (high)) && ((addr) >= (low)))
1217 #define QLCRD32(adapter, off) \
1218 (qlcnic_hw_read_wx_2M(adapter, off))
1219 #define QLCWR32(adapter, off, val) \
1220 (qlcnic_hw_write_wx_2M(adapter, off, val))
1222 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1223 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1225 #define qlcnic_rom_lock(a) \
1226 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1227 #define qlcnic_rom_unlock(a) \
1228 qlcnic_pcie_sem_unlock((a), 2)
1229 #define qlcnic_phy_lock(a) \
1230 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1231 #define qlcnic_phy_unlock(a) \
1232 qlcnic_pcie_sem_unlock((a), 3)
1233 #define qlcnic_api_lock(a) \
1234 qlcnic_pcie_sem_lock((a), 5, 0)
1235 #define qlcnic_api_unlock(a) \
1236 qlcnic_pcie_sem_unlock((a), 5)
1237 #define qlcnic_sw_lock(a) \
1238 qlcnic_pcie_sem_lock((a), 6, 0)
1239 #define qlcnic_sw_unlock(a) \
1240 qlcnic_pcie_sem_unlock((a), 6)
1241 #define crb_win_lock(a) \
1242 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1243 #define crb_win_unlock(a) \
1244 qlcnic_pcie_sem_unlock((a), 7)
1246 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1247 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1248 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1249 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1250 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1252 /* Functions from qlcnic_init.c */
1253 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1254 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1255 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1256 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1257 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1258 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1259 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1261 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1262 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1263 u8 *bytes, size_t size);
1264 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1265 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1267 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1269 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1270 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1272 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1273 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1275 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1276 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1277 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1279 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1280 void qlcnic_watchdog_task(struct work_struct *work);
1281 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1282 struct qlcnic_host_rds_ring *rds_ring);
1283 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1284 void qlcnic_set_multi(struct net_device *netdev);
1285 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1286 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1287 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1288 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1289 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1290 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1291 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1293 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1294 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1295 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1296 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1297 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1298 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1299 struct qlcnic_host_tx_ring *tx_ring);
1300 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1301 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1302 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1304 /* Functions from qlcnic_main.c */
1305 int qlcnic_reset_context(struct qlcnic_adapter *);
1306 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1307 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1308 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1309 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1310 int qlcnic_check_loopback_buff(unsigned char *data);
1311 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1312 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1314 /* Management functions */
1315 int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*);
1316 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1317 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1318 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1319 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1320 int qlcnic_reset_partition(struct qlcnic_adapter *, u8);
1322 /* eSwitch management functions */
1323 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8,
1324 struct qlcnic_eswitch *);
1325 int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8,
1326 struct qlcnic_eswitch *);
1327 int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8);
1328 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1329 struct qlcnic_esw_func_cfg *);
1330 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1331 struct qlcnic_esw_func_cfg *);
1332 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1333 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1334 struct __qlcnic_esw_statistics *);
1335 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1336 struct __qlcnic_esw_statistics *);
1337 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1338 extern int qlcnic_config_tso;
1341 * QLOGIC Board information
1344 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1345 struct qlcnic_brdinfo {
1346 unsigned short vendor;
1347 unsigned short device;
1348 unsigned short sub_vendor;
1349 unsigned short sub_device;
1350 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1353 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1354 {0x1077, 0x8020, 0x1077, 0x203,
1355 "8200 Series Single Port 10GbE Converged Network Adapter "
1356 "(TCP/IP Networking)"},
1357 {0x1077, 0x8020, 0x1077, 0x207,
1358 "8200 Series Dual Port 10GbE Converged Network Adapter "
1359 "(TCP/IP Networking)"},
1360 {0x1077, 0x8020, 0x1077, 0x20b,
1361 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1362 {0x1077, 0x8020, 0x1077, 0x20c,
1363 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1364 {0x1077, 0x8020, 0x1077, 0x20f,
1365 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1366 {0x1077, 0x8020, 0x103c, 0x3733,
1367 "NC523SFP 10Gb 2-port Flex-10 Server Adapter"},
1368 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1371 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1373 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1376 if (tx_ring->producer < tx_ring->sw_consumer)
1377 return tx_ring->sw_consumer - tx_ring->producer;
1379 return tx_ring->sw_consumer + tx_ring->num_desc -
1383 extern const struct ethtool_ops qlcnic_ethtool_ops;
1385 struct qlcnic_nic_template {
1386 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1387 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1388 int (*start_firmware) (struct qlcnic_adapter *);
1391 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1392 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1393 printk(KERN_INFO "%s: %s: " _fmt, \
1394 dev_name(&adapter->pdev->dev), \
1395 __func__, ##_args); \
1398 #endif /* __QLCNIC_H_ */