drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <linux/slab.h>
  28 #include <net/ip.h>
  29
  30 #define MASK(n) ((1ULL<<(n))-1)
  31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  32
  33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  34
  35 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  37 #define CRB_WINDOW_2M   (0x130060)
  38 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  39 #define CRB_INDIRECT_2M (0x1e0000UL)
  40
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem *addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem *addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static const struct crb_128M_2M_block_map
  58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  59     {{{0, 0,         0,         0} } },         /* 0: PCI */
  60     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  61           {1, 0x0110000, 0x0120000, 0x130000},
  62           {1, 0x0120000, 0x0122000, 0x124000},
  63           {1, 0x0130000, 0x0132000, 0x126000},
  64           {1, 0x0140000, 0x0142000, 0x128000},
  65           {1, 0x0150000, 0x0152000, 0x12a000},
  66           {1, 0x0160000, 0x0170000, 0x110000},
  67           {1, 0x0170000, 0x0172000, 0x12e000},
  68           {0, 0x0000000, 0x0000000, 0x000000},
  69           {0, 0x0000000, 0x0000000, 0x000000},
  70           {0, 0x0000000, 0x0000000, 0x000000},
  71           {0, 0x0000000, 0x0000000, 0x000000},
  72           {0, 0x0000000, 0x0000000, 0x000000},
  73           {0, 0x0000000, 0x0000000, 0x000000},
  74           {1, 0x01e0000, 0x01e0800, 0x122000},
  75           {0, 0x0000000, 0x0000000, 0x000000} } },
  76         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  77     {{{0, 0,         0,         0} } },     /* 3: */
  78     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  79     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  80     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  81     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  82     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {0, 0x0000000, 0x0000000, 0x000000},
  92       {0, 0x0000000, 0x0000000, 0x000000},
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  98     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 114     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 130     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {0, 0x0000000, 0x0000000, 0x000000},
 144       {0, 0x0000000, 0x0000000, 0x000000},
 145       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 146         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 147         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 148         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 149         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 150         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 151         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 152         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 153         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 154         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 155         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 156         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 157         {{{0, 0,         0,         0} } },     /* 23: */
 158         {{{0, 0,         0,         0} } },     /* 24: */
 159         {{{0, 0,         0,         0} } },     /* 25: */
 160         {{{0, 0,         0,         0} } },     /* 26: */
 161         {{{0, 0,         0,         0} } },     /* 27: */
 162         {{{0, 0,         0,         0} } },     /* 28: */
 163         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 164     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 165     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 166         {{{0} } },                              /* 32: PCI */
 167         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 168           {1, 0x2110000, 0x2120000, 0x130000},
 169           {1, 0x2120000, 0x2122000, 0x124000},
 170           {1, 0x2130000, 0x2132000, 0x126000},
 171           {1, 0x2140000, 0x2142000, 0x128000},
 172           {1, 0x2150000, 0x2152000, 0x12a000},
 173           {1, 0x2160000, 0x2170000, 0x110000},
 174           {1, 0x2170000, 0x2172000, 0x12e000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000},
 177           {0, 0x0000000, 0x0000000, 0x000000},
 178           {0, 0x0000000, 0x0000000, 0x000000},
 179           {0, 0x0000000, 0x0000000, 0x000000},
 180           {0, 0x0000000, 0x0000000, 0x000000},
 181           {0, 0x0000000, 0x0000000, 0x000000},
 182           {0, 0x0000000, 0x0000000, 0x000000} } },
 183         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 184         {{{0} } },                              /* 35: */
 185         {{{0} } },                              /* 36: */
 186         {{{0} } },                              /* 37: */
 187         {{{0} } },                              /* 38: */
 188         {{{0} } },                              /* 39: */
 189         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 190         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 191         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 192         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 193         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 194         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 195         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 196         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 197         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 198         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 199         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 200         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 201         {{{0} } },                              /* 52: */
 202         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 203         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 204         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 205         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 206         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 207         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 208         {{{0} } },                              /* 59: I2C0 */
 209         {{{0} } },                              /* 60: I2C1 */
 210         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 211         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 212         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 213 };
 214
 215 /*
 216  * top 12 bits of crb internal address (hub, agent)
 217  */
 218 static const unsigned crb_hub_agt[64] = {
 219         0,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 223         0,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 246         0,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 249         0,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 251         0,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 254         0,
 255         0,
 256         0,
 257         0,
 258         0,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 265         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 270         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 271         0,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 274         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 276         0,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 280         0,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 282         0,
 283 };
 284
 285 /*  PCI Windowing for DDR regions.  */
 286
 287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 288
 289 int
 290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 291 {
 292         int done = 0, timeout = 0;
 293
 294         while (!done) {
 295                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 296                 if (done == 1)
 297                         break;
 298                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 299                         dev_err(&adapter->pdev->dev,
 300                                 "Failed to acquire sem=%d lock;reg_id=%d\n",
 301                                 sem, id_reg);
 302                         return -EIO;
 303                 }
 304                 msleep(1);
 305         }
 306
 307         if (id_reg)
 308                 QLCWR32(adapter, id_reg, adapter->portnum);
 309
 310         return 0;
 311 }
 312
 313 void
 314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 315 {
 316         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 317 }
 318
 319 static int
 320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 321                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 322 {
 323         u32 i, producer, consumer;
 324         struct qlcnic_cmd_buffer *pbuf;
 325         struct cmd_desc_type0 *cmd_desc;
 326         struct qlcnic_host_tx_ring *tx_ring;
 327
 328         i = 0;
 329
 330         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 331                 return -EIO;
 332
 333         tx_ring = adapter->tx_ring;
 334         __netif_tx_lock_bh(tx_ring->txq);
 335
 336         producer = tx_ring->producer;
 337         consumer = tx_ring->sw_consumer;
 338
 339         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 340                 netif_tx_stop_queue(tx_ring->txq);
 341                 __netif_tx_unlock_bh(tx_ring->txq);
 342                 adapter->stats.xmit_off++;
 343                 return -EBUSY;
 344         }
 345
 346         do {
 347                 cmd_desc = &cmd_desc_arr[i];
 348
 349                 pbuf = &tx_ring->cmd_buf_arr[producer];
 350                 pbuf->skb = NULL;
 351                 pbuf->frag_count = 0;
 352
 353                 memcpy(&tx_ring->desc_head[producer],
 354                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 355
 356                 producer = get_next_index(producer, tx_ring->num_desc);
 357                 i++;
 358
 359         } while (i != nr_desc);
 360
 361         tx_ring->producer = producer;
 362
 363         qlcnic_update_cmd_producer(adapter, tx_ring);
 364
 365         __netif_tx_unlock_bh(tx_ring->txq);
 366
 367         return 0;
 368 }
 369
 370 static int
 371 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 372                                 unsigned op)
 373 {
 374         struct qlcnic_nic_req req;
 375         struct qlcnic_mac_req *mac_req;
 376         u64 word;
 377
 378         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 379         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 380
 381         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 382         req.req_hdr = cpu_to_le64(word);
 383
 384         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 385         mac_req->op = op;
 386         memcpy(mac_req->mac_addr, addr, 6);
 387
 388         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 389 }
 390
 391 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 392 {
 393         struct list_head *head;
 394         struct qlcnic_mac_list_s *cur;
 395
 396         /* look up if already exists */
 397         list_for_each(head, &adapter->mac_list) {
 398                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 399                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 400                         return 0;
 401         }
 402
 403         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 404         if (cur == NULL) {
 405                 dev_err(&adapter->netdev->dev,
 406                         "failed to add mac address filter\n");
 407                 return -ENOMEM;
 408         }
 409         memcpy(cur->mac_addr, addr, ETH_ALEN);
 410         list_add_tail(&cur->list, &adapter->mac_list);
 411
 412         return qlcnic_sre_macaddr_change(adapter,
 413                                 cur->mac_addr, QLCNIC_MAC_ADD);
 414 }
 415
 416 void qlcnic_set_multi(struct net_device *netdev)
 417 {
 418         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 419         struct netdev_hw_addr *ha;
 420         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 421         u32 mode = VPORT_MISS_MODE_DROP;
 422
 423         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 424                 return;
 425
 426         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 427         qlcnic_nic_add_mac(adapter, bcast_addr);
 428
 429         if (netdev->flags & IFF_PROMISC) {
 430                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 431                 goto send_fw_cmd;
 432         }
 433
 434         if ((netdev->flags & IFF_ALLMULTI) ||
 435             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 436                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 437                 goto send_fw_cmd;
 438         }
 439
 440         if (!netdev_mc_empty(netdev)) {
 441                 netdev_for_each_mc_addr(ha, netdev) {
 442                         qlcnic_nic_add_mac(adapter, ha->addr);
 443                 }
 444         }
 445
 446 send_fw_cmd:
 447         qlcnic_nic_set_promisc(adapter, mode);
 448 }
 449
 450 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 451 {
 452         struct qlcnic_nic_req req;
 453         u64 word;
 454
 455         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 456
 457         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 458
 459         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 460                         ((u64)adapter->portnum << 16);
 461         req.req_hdr = cpu_to_le64(word);
 462
 463         req.words[0] = cpu_to_le64(mode);
 464
 465         return qlcnic_send_cmd_descs(adapter,
 466                                 (struct cmd_desc_type0 *)&req, 1);
 467 }
 468
 469 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 470 {
 471         struct qlcnic_mac_list_s *cur;
 472         struct list_head *head = &adapter->mac_list;
 473
 474         while (!list_empty(head)) {
 475                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 476                 qlcnic_sre_macaddr_change(adapter,
 477                                 cur->mac_addr, QLCNIC_MAC_DEL);
 478                 list_del(&cur->list);
 479                 kfree(cur);
 480         }
 481 }
 482
 483 #define QLCNIC_CONFIG_INTR_COALESCE     3
 484
 485 /*
 486  * Send the interrupt coalescing parameter set by ethtool to the card.
 487  */
 488 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 489 {
 490         struct qlcnic_nic_req req;
 491         u64 word[6];
 492         int rv, i;
 493
 494         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 495
 496         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 497
 498         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 499         req.req_hdr = cpu_to_le64(word[0]);
 500
 501         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 502         for (i = 0; i < 6; i++)
 503                 req.words[i] = cpu_to_le64(word[i]);
 504
 505         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 506         if (rv != 0)
 507                 dev_err(&adapter->netdev->dev,
 508                         "Could not send interrupt coalescing parameters\n");
 509
 510         return rv;
 511 }
 512
 513 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 514 {
 515         struct qlcnic_nic_req req;
 516         u64 word;
 517         int rv;
 518
 519         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 520                 return 0;
 521
 522         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 523
 524         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 525
 526         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 527         req.req_hdr = cpu_to_le64(word);
 528
 529         req.words[0] = cpu_to_le64(enable);
 530
 531         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 532         if (rv != 0)
 533                 dev_err(&adapter->netdev->dev,
 534                         "Could not send configure hw lro request\n");
 535
 536         adapter->flags ^= QLCNIC_LRO_ENABLED;
 537
 538         return rv;
 539 }
 540
 541 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 542 {
 543         struct qlcnic_nic_req req;
 544         u64 word;
 545         int rv;
 546
 547         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 548                 return 0;
 549
 550         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 551
 552         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 553
 554         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 555                 ((u64)adapter->portnum << 16);
 556         req.req_hdr = cpu_to_le64(word);
 557
 558         req.words[0] = cpu_to_le64(enable);
 559
 560         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 561         if (rv != 0)
 562                 dev_err(&adapter->netdev->dev,
 563                         "Could not send configure bridge mode request\n");
 564
 565         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 566
 567         return rv;
 568 }
 569
 570
 571 #define RSS_HASHTYPE_IP_TCP     0x3
 572
 573 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 574 {
 575         struct qlcnic_nic_req req;
 576         u64 word;
 577         int i, rv;
 578
 579         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 580                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 581                         0x255b0ec26d5a56daULL };
 582
 583
 584         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 585         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 586
 587         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 588         req.req_hdr = cpu_to_le64(word);
 589
 590         /*
 591          * RSS request:
 592          * bits 3-0: hash_method
 593          *      5-4: hash_type_ipv4
 594          *      7-6: hash_type_ipv6
 595          *        8: enable
 596          *        9: use indirection table
 597          *    47-10: reserved
 598          *    63-48: indirection table mask
 599          */
 600         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 601                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 602                 ((u64)(enable & 0x1) << 8) |
 603                 ((0x7ULL) << 48);
 604         req.words[0] = cpu_to_le64(word);
 605         for (i = 0; i < 5; i++)
 606                 req.words[i+1] = cpu_to_le64(key[i]);
 607
 608         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 609         if (rv != 0)
 610                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 611
 612         return rv;
 613 }
 614
 615 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
 616 {
 617         struct qlcnic_nic_req req;
 618         u64 word;
 619         int rv;
 620
 621         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 622         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 623
 624         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 625         req.req_hdr = cpu_to_le64(word);
 626
 627         req.words[0] = cpu_to_le64(cmd);
 628         req.words[1] = cpu_to_le64(ip);
 629
 630         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 631         if (rv != 0)
 632                 dev_err(&adapter->netdev->dev,
 633                                 "could not notify %s IP 0x%x reuqest\n",
 634                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 635
 636         return rv;
 637 }
 638
 639 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 640 {
 641         struct qlcnic_nic_req req;
 642         u64 word;
 643         int rv;
 644
 645         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 646         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 647
 648         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 649         req.req_hdr = cpu_to_le64(word);
 650         req.words[0] = cpu_to_le64(enable | (enable << 8));
 651
 652         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 653         if (rv != 0)
 654                 dev_err(&adapter->netdev->dev,
 655                                 "could not configure link notification\n");
 656
 657         return rv;
 658 }
 659
 660 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 661 {
 662         struct qlcnic_nic_req req;
 663         u64 word;
 664         int rv;
 665
 666         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 667         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 668
 669         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 670                 ((u64)adapter->portnum << 16) |
 671                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 672
 673         req.req_hdr = cpu_to_le64(word);
 674
 675         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 676         if (rv != 0)
 677                 dev_err(&adapter->netdev->dev,
 678                                  "could not cleanup lro flows\n");
 679
 680         return rv;
 681 }
 682
 683 /*
 684  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 685  * @returns 0 on success, negative on failure
 686  */
 687
 688 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 689 {
 690         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 691         int rc = 0;
 692
 693         if (mtu > P3_MAX_MTU) {
 694                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 695                                                 P3_MAX_MTU);
 696                 return -EINVAL;
 697         }
 698
 699         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 700
 701         if (!rc)
 702                 netdev->mtu = mtu;
 703
 704         return rc;
 705 }
 706
 707 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac)
 708 {
 709         u32 crbaddr;
 710         int pci_func = adapter->ahw.pci_func;
 711
 712         crbaddr = CRB_MAC_BLOCK_START +
 713                 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
 714
 715         qlcnic_fetch_mac(adapter, crbaddr, crbaddr+4, pci_func & 1, mac);
 716
 717         return 0;
 718 }
 719
 720 /*
 721  * Changes the CRB window to the specified window.
 722  */
 723  /* Returns < 0 if off is not valid,
 724  *       1 if window access is needed. 'off' is set to offset from
 725  *         CRB space in 128M pci map
 726  *       0 if no window access is needed. 'off' is set to 2M addr
 727  * In: 'off' is offset from base in 128M pci map
 728  */
 729 static int
 730 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 731                 ulong off, void __iomem **addr)
 732 {
 733         const struct crb_128M_2M_sub_block_map *m;
 734
 735         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 736                 return -EINVAL;
 737
 738         off -= QLCNIC_PCI_CRBSPACE;
 739
 740         /*
 741          * Try direct map
 742          */
 743         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 744
 745         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 746                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 747                         (off - m->start_128M);
 748                 return 0;
 749         }
 750
 751         /*
 752          * Not in direct map, use crb window
 753          */
 754         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 755         return 1;
 756 }
 757
 758 /*
 759  * In: 'off' is offset from CRB space in 128M pci map
 760  * Out: 'off' is 2M pci map addr
 761  * side effect: lock crb window
 762  */
 763 static void
 764 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 765 {
 766         u32 window;
 767         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 768
 769         off -= QLCNIC_PCI_CRBSPACE;
 770
 771         window = CRB_HI(off);
 772
 773         writel(window, addr);
 774         if (readl(addr) != window) {
 775                 if (printk_ratelimit())
 776                         dev_warn(&adapter->pdev->dev,
 777                                 "failed to set CRB window to %d off 0x%lx\n",
 778                                 window, off);
 779         }
 780 }
 781
 782 int
 783 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 784 {
 785         unsigned long flags;
 786         int rv;
 787         void __iomem *addr = NULL;
 788
 789         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 790
 791         if (rv == 0) {
 792                 writel(data, addr);
 793                 return 0;
 794         }
 795
 796         if (rv > 0) {
 797                 /* indirect access */
 798                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 799                 crb_win_lock(adapter);
 800                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 801                 writel(data, addr);
 802                 crb_win_unlock(adapter);
 803                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 804                 return 0;
 805         }
 806
 807         dev_err(&adapter->pdev->dev,
 808                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 809         dump_stack();
 810         return -EIO;
 811 }
 812
 813 u32
 814 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 815 {
 816         unsigned long flags;
 817         int rv;
 818         u32 data;
 819         void __iomem *addr = NULL;
 820
 821         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 822
 823         if (rv == 0)
 824                 return readl(addr);
 825
 826         if (rv > 0) {
 827                 /* indirect access */
 828                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 829                 crb_win_lock(adapter);
 830                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 831                 data = readl(addr);
 832                 crb_win_unlock(adapter);
 833                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 834                 return data;
 835         }
 836
 837         dev_err(&adapter->pdev->dev,
 838                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 839         dump_stack();
 840         return -1;
 841 }
 842
 843
 844 void __iomem *
 845 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 846 {
 847         void __iomem *addr = NULL;
 848
 849         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 850
 851         return addr;
 852 }
 853
 854
 855 static int
 856 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 857                 u64 addr, u32 *start)
 858 {
 859         u32 window;
 860
 861         window = OCM_WIN_P3P(addr);
 862
 863         writel(window, adapter->ahw.ocm_win_crb);
 864         /* read back to flush */
 865         readl(adapter->ahw.ocm_win_crb);
 866
 867         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 868         return 0;
 869 }
 870
 871 static int
 872 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 873                 u64 *data, int op)
 874 {
 875         void __iomem *addr;
 876         int ret;
 877         u32 start;
 878
 879         mutex_lock(&adapter->ahw.mem_lock);
 880
 881         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 882         if (ret != 0)
 883                 goto unlock;
 884
 885         addr = adapter->ahw.pci_base0 + start;
 886
 887         if (op == 0)    /* read */
 888                 *data = readq(addr);
 889         else            /* write */
 890                 writeq(*data, addr);
 891
 892 unlock:
 893         mutex_unlock(&adapter->ahw.mem_lock);
 894
 895         return ret;
 896 }
 897
 898 void
 899 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
 900 {
 901         void __iomem *addr = adapter->ahw.pci_base0 +
 902                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 903
 904         mutex_lock(&adapter->ahw.mem_lock);
 905         *data = readq(addr);
 906         mutex_unlock(&adapter->ahw.mem_lock);
 907 }
 908
 909 void
 910 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
 911 {
 912         void __iomem *addr = adapter->ahw.pci_base0 +
 913                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 914
 915         mutex_lock(&adapter->ahw.mem_lock);
 916         writeq(data, addr);
 917         mutex_unlock(&adapter->ahw.mem_lock);
 918 }
 919
 920 #define MAX_CTL_CHECK   1000
 921
 922 int
 923 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 924                 u64 off, u64 data)
 925 {
 926         int i, j, ret;
 927         u32 temp, off8;
 928         void __iomem *mem_crb;
 929
 930         /* Only 64-bit aligned access */
 931         if (off & 7)
 932                 return -EIO;
 933
 934         /* P3 onward, test agent base for MIU and SIU is same */
 935         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 936                                 QLCNIC_ADDR_QDR_NET_MAX)) {
 937                 mem_crb = qlcnic_get_ioaddr(adapter,
 938                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 939                 goto correct;
 940         }
 941
 942         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 943                 mem_crb = qlcnic_get_ioaddr(adapter,
 944                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 945                 goto correct;
 946         }
 947
 948         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
 949                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
 950
 951         return -EIO;
 952
 953 correct:
 954         off8 = off & ~0xf;
 955
 956         mutex_lock(&adapter->ahw.mem_lock);
 957
 958         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
 959         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
 960
 961         i = 0;
 962         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
 963         writel((TA_CTL_START | TA_CTL_ENABLE),
 964                         (mem_crb + TEST_AGT_CTRL));
 965
 966         for (j = 0; j < MAX_CTL_CHECK; j++) {
 967                 temp = readl(mem_crb + TEST_AGT_CTRL);
 968                 if ((temp & TA_CTL_BUSY) == 0)
 969                         break;
 970         }
 971
 972         if (j >= MAX_CTL_CHECK) {
 973                 ret = -EIO;
 974                 goto done;
 975         }
 976
 977         i = (off & 0xf) ? 0 : 2;
 978         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
 979                         mem_crb + MIU_TEST_AGT_WRDATA(i));
 980         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
 981                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
 982         i = (off & 0xf) ? 2 : 0;
 983
 984         writel(data & 0xffffffff,
 985                         mem_crb + MIU_TEST_AGT_WRDATA(i));
 986         writel((data >> 32) & 0xffffffff,
 987                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
 988
 989         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
 990         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
 991                         (mem_crb + TEST_AGT_CTRL));
 992
 993         for (j = 0; j < MAX_CTL_CHECK; j++) {
 994                 temp = readl(mem_crb + TEST_AGT_CTRL);
 995                 if ((temp & TA_CTL_BUSY) == 0)
 996                         break;
 997         }
 998
 999         if (j >= MAX_CTL_CHECK) {
1000                 if (printk_ratelimit())
1001                         dev_err(&adapter->pdev->dev,
1002                                         "failed to write through agent\n");
1003                 ret = -EIO;
1004         } else
1005                 ret = 0;
1006
1007 done:
1008         mutex_unlock(&adapter->ahw.mem_lock);
1009
1010         return ret;
1011 }
1012
1013 int
1014 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1015                 u64 off, u64 *data)
1016 {
1017         int j, ret;
1018         u32 temp, off8;
1019         u64 val;
1020         void __iomem *mem_crb;
1021
1022         /* Only 64-bit aligned access */
1023         if (off & 7)
1024                 return -EIO;
1025
1026         /* P3 onward, test agent base for MIU and SIU is same */
1027         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1028                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1029                 mem_crb = qlcnic_get_ioaddr(adapter,
1030                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1031                 goto correct;
1032         }
1033
1034         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1035                 mem_crb = qlcnic_get_ioaddr(adapter,
1036                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1037                 goto correct;
1038         }
1039
1040         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1041                 return qlcnic_pci_mem_access_direct(adapter,
1042                                 off, data, 0);
1043         }
1044
1045         return -EIO;
1046
1047 correct:
1048         off8 = off & ~0xf;
1049
1050         mutex_lock(&adapter->ahw.mem_lock);
1051
1052         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1053         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1054         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1055         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1056
1057         for (j = 0; j < MAX_CTL_CHECK; j++) {
1058                 temp = readl(mem_crb + TEST_AGT_CTRL);
1059                 if ((temp & TA_CTL_BUSY) == 0)
1060                         break;
1061         }
1062
1063         if (j >= MAX_CTL_CHECK) {
1064                 if (printk_ratelimit())
1065                         dev_err(&adapter->pdev->dev,
1066                                         "failed to read through agent\n");
1067                 ret = -EIO;
1068         } else {
1069                 off8 = MIU_TEST_AGT_RDDATA_LO;
1070                 if (off & 0xf)
1071                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1072
1073                 temp = readl(mem_crb + off8 + 4);
1074                 val = (u64)temp << 32;
1075                 val |= readl(mem_crb + off8);
1076                 *data = val;
1077                 ret = 0;
1078         }
1079
1080         mutex_unlock(&adapter->ahw.mem_lock);
1081
1082         return ret;
1083 }
1084
1085 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1086 {
1087         int offset, board_type, magic;
1088         struct pci_dev *pdev = adapter->pdev;
1089
1090         offset = QLCNIC_FW_MAGIC_OFFSET;
1091         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1092                 return -EIO;
1093
1094         if (magic != QLCNIC_BDINFO_MAGIC) {
1095                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1096                         magic);
1097                 return -EIO;
1098         }
1099
1100         offset = QLCNIC_BRDTYPE_OFFSET;
1101         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1102                 return -EIO;
1103
1104         adapter->ahw.board_type = board_type;
1105
1106         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1107                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1108                 if ((gpio & 0x8000) == 0)
1109                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1110         }
1111
1112         switch (board_type) {
1113         case QLCNIC_BRDTYPE_P3_HMEZ:
1114         case QLCNIC_BRDTYPE_P3_XG_LOM:
1115         case QLCNIC_BRDTYPE_P3_10G_CX4:
1116         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1117         case QLCNIC_BRDTYPE_P3_IMEZ:
1118         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1119         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1120         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1121         case QLCNIC_BRDTYPE_P3_10G_XFP:
1122         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1123                 adapter->ahw.port_type = QLCNIC_XGBE;
1124                 break;
1125         case QLCNIC_BRDTYPE_P3_REF_QG:
1126         case QLCNIC_BRDTYPE_P3_4_GB:
1127         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1128                 adapter->ahw.port_type = QLCNIC_GBE;
1129                 break;
1130         case QLCNIC_BRDTYPE_P3_10G_TP:
1131                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1132                         QLCNIC_XGBE : QLCNIC_GBE;
1133                 break;
1134         default:
1135                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1136                 adapter->ahw.port_type = QLCNIC_XGBE;
1137                 break;
1138         }
1139
1140         return 0;
1141 }
1142
1143 int
1144 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1145 {
1146         u32 wol_cfg;
1147
1148         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1149         if (wol_cfg & (1UL << adapter->portnum)) {
1150                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1151                 if (wol_cfg & (1 << adapter->portnum))
1152                         return 1;
1153         }
1154
1155         return 0;
1156 }
1157
1158 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1159 {
1160         struct qlcnic_nic_req   req;
1161         int rv;
1162         u64 word;
1163
1164         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1165         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1166
1167         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1168         req.req_hdr = cpu_to_le64(word);
1169
1170         req.words[0] = cpu_to_le64((u64)rate << 32);
1171         req.words[1] = cpu_to_le64(state);
1172
1173         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1174         if (rv)
1175                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1176
1177         return rv;
1178 }
1179
1180 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1181 {
1182         struct qlcnic_nic_req   req;
1183         int                     rv;
1184         u64                     word;
1185
1186         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1187         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1188
1189         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1190                         ((u64)adapter->portnum << 16);
1191         req.req_hdr = cpu_to_le64(word);
1192         req.words[0] = cpu_to_le64(flag);
1193
1194         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1195         if (rv)
1196                 dev_err(&adapter->pdev->dev,
1197                         "%sting loopback mode failed.\n",
1198                                         flag ? "Set" : "Reset");
1199         return rv;
1200 }
1201
1202 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1203 {
1204         if (qlcnic_set_fw_loopback(adapter, 1))
1205                 return -EIO;
1206
1207         if (qlcnic_nic_set_promisc(adapter,
1208                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1209                 qlcnic_set_fw_loopback(adapter, 0);
1210                 return -EIO;
1211         }
1212
1213         msleep(1000);
1214         return 0;
1215 }
1216
1217 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1218 {
1219         int mode = VPORT_MISS_MODE_DROP;
1220         struct net_device *netdev = adapter->netdev;
1221
1222         qlcnic_set_fw_loopback(adapter, 0);
1223
1224         if (netdev->flags & IFF_PROMISC)
1225                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1226         else if (netdev->flags & IFF_ALLMULTI)
1227                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1228
1229         qlcnic_nic_set_promisc(adapter, mode);
1230 }