drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42
  43 #include "qlge.h"
  44
  45 char qlge_driver_name[] = DRV_NAME;
  46 const char qlge_driver_version[] = DRV_VERSION;
  47
  48 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  49 MODULE_DESCRIPTION(DRV_STRING " ");
  50 MODULE_LICENSE("GPL");
  51 MODULE_VERSION(DRV_VERSION);
  52
  53 static const u32 default_msg =
  54     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  55 /* NETIF_MSG_TIMER |    */
  56     NETIF_MSG_IFDOWN |
  57     NETIF_MSG_IFUP |
  58     NETIF_MSG_RX_ERR |
  59     NETIF_MSG_TX_ERR |
  60     NETIF_MSG_TX_QUEUED |
  61     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  62 /* NETIF_MSG_PKTDATA | */
  63     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  64
  65 static int debug = 0x00007fff;  /* defaults above */
  66 module_param(debug, int, 0);
  67 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  68
  69 #define MSIX_IRQ 0
  70 #define MSI_IRQ 1
  71 #define LEG_IRQ 2
  72 static int irq_type = MSIX_IRQ;
  73 module_param(irq_type, int, MSIX_IRQ);
  74 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  75
  76 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  77         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int seconds = 3;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 ssleep(1);
 134         } while (--seconds);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 251         if (status)
 252                 return status;
 253         switch (type) {
 254         case MAC_ADDR_TYPE_MULTI_MAC:
 255         case MAC_ADDR_TYPE_CAM_MAC:
 256                 {
 257                         status =
 258                             ql_wait_reg_rdy(qdev,
 259                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 260                         if (status)
 261                                 goto exit;
 262                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 263                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 264                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 265                         status =
 266                             ql_wait_reg_rdy(qdev,
 267                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 268                         if (status)
 269                                 goto exit;
 270                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 271                         status =
 272                             ql_wait_reg_rdy(qdev,
 273                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 274                         if (status)
 275                                 goto exit;
 276                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 277                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 278                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 279                         status =
 280                             ql_wait_reg_rdy(qdev,
 281                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 282                         if (status)
 283                                 goto exit;
 284                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 285                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 286                                 status =
 287                                     ql_wait_reg_rdy(qdev,
 288                                         MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 289                                 if (status)
 290                                         goto exit;
 291                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 292                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 293                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 294                                 status =
 295                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 296                                                     MAC_ADDR_MR, MAC_ADDR_E);
 297                                 if (status)
 298                                         goto exit;
 299                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 300                         }
 301                         break;
 302                 }
 303         case MAC_ADDR_TYPE_VLAN:
 304         case MAC_ADDR_TYPE_MULTI_FLTR:
 305         default:
 306                 QPRINTK(qdev, IFUP, CRIT,
 307                         "Address type %d not yet supported.\n", type);
 308                 status = -EPERM;
 309         }
 310 exit:
 311         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 312         return status;
 313 }
 314
 315 /* Set up a MAC, multicast or VLAN address for the
 316  * inbound frame matching.
 317  */
 318 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 319                                u16 index)
 320 {
 321         u32 offset = 0;
 322         int status = 0;
 323
 324         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 325         if (status)
 326                 return status;
 327         switch (type) {
 328         case MAC_ADDR_TYPE_MULTI_MAC:
 329         case MAC_ADDR_TYPE_CAM_MAC:
 330                 {
 331                         u32 cam_output;
 332                         u32 upper = (addr[0] << 8) | addr[1];
 333                         u32 lower =
 334                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 335                             (addr[5]);
 336
 337                         QPRINTK(qdev, IFUP, INFO,
 338                                 "Adding %s address %02x:%02x:%02x:%02x:%02x:%02x"
 339                                 " at index %d in the CAM.\n",
 340                                 ((type ==
 341                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 342                                  "UNICAST"), addr[0], addr[1], addr[2], addr[3],
 343                                 addr[4], addr[5], index);
 344
 345                         status =
 346                             ql_wait_reg_rdy(qdev,
 347                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 348                         if (status)
 349                                 goto exit;
 350                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 351                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 352                                    type);       /* type */
 353                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 354                         status =
 355                             ql_wait_reg_rdy(qdev,
 356                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 357                         if (status)
 358                                 goto exit;
 359                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 360                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 361                                    type);       /* type */
 362                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 363                         status =
 364                             ql_wait_reg_rdy(qdev,
 365                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 366                         if (status)
 367                                 goto exit;
 368                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 369                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 370                                    type);       /* type */
 371                         /* This field should also include the queue id
 372                            and possibly the function id.  Right now we hardcode
 373                            the route field to NIC core.
 374                          */
 375                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 376                                 cam_output = (CAM_OUT_ROUTE_NIC |
 377                                               (qdev->
 378                                                func << CAM_OUT_FUNC_SHIFT) |
 379                                               (qdev->
 380                                                rss_ring_first_cq_id <<
 381                                                CAM_OUT_CQ_ID_SHIFT));
 382                                 if (qdev->vlgrp)
 383                                         cam_output |= CAM_OUT_RV;
 384                                 /* route to NIC core */
 385                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 386                         }
 387                         break;
 388                 }
 389         case MAC_ADDR_TYPE_VLAN:
 390                 {
 391                         u32 enable_bit = *((u32 *) &addr[0]);
 392                         /* For VLAN, the addr actually holds a bit that
 393                          * either enables or disables the vlan id we are
 394                          * addressing. It's either MAC_ADDR_E on or off.
 395                          * That's bit-27 we're talking about.
 396                          */
 397                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 398                                 (enable_bit ? "Adding" : "Removing"),
 399                                 index, (enable_bit ? "to" : "from"));
 400
 401                         status =
 402                             ql_wait_reg_rdy(qdev,
 403                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 404                         if (status)
 405                                 goto exit;
 406                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 407                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 408                                    type |       /* type */
 409                                    enable_bit); /* enable/disable */
 410                         break;
 411                 }
 412         case MAC_ADDR_TYPE_MULTI_FLTR:
 413         default:
 414                 QPRINTK(qdev, IFUP, CRIT,
 415                         "Address type %d not yet supported.\n", type);
 416                 status = -EPERM;
 417         }
 418 exit:
 419         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 420         return status;
 421 }
 422
 423 /* Get a specific frame routing value from the CAM.
 424  * Used for debug and reg dump.
 425  */
 426 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 427 {
 428         int status = 0;
 429
 430         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 431         if (status)
 432                 goto exit;
 433
 434         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
 435         if (status)
 436                 goto exit;
 437
 438         ql_write32(qdev, RT_IDX,
 439                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 440         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
 441         if (status)
 442                 goto exit;
 443         *value = ql_read32(qdev, RT_DATA);
 444 exit:
 445         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 446         return status;
 447 }
 448
 449 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 450  * to route different frame types to various inbound queues.  We send broadcast/
 451  * multicast/error frames to the default queue for slow handling,
 452  * and CAM hit/RSS frames to the fast handling queues.
 453  */
 454 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 455                               int enable)
 456 {
 457         int status;
 458         u32 value = 0;
 459
 460         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 461         if (status)
 462                 return status;
 463
 464         QPRINTK(qdev, IFUP, DEBUG,
 465                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 466                 (enable ? "Adding" : "Removing"),
 467                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 468                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 469                 ((index ==
 470                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 471                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 472                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 474                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 475                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 476                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 477                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 478                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 479                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 480                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 481                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 482                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 483                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 484                 (enable ? "to" : "from"));
 485
 486         switch (mask) {
 487         case RT_IDX_CAM_HIT:
 488                 {
 489                         value = RT_IDX_DST_CAM_Q |      /* dest */
 490                             RT_IDX_TYPE_NICQ |  /* type */
 491                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 492                         break;
 493                 }
 494         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 495                 {
 496                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 497                             RT_IDX_TYPE_NICQ |  /* type */
 498                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 499                         break;
 500                 }
 501         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 502                 {
 503                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 504                             RT_IDX_TYPE_NICQ |  /* type */
 505                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 506                         break;
 507                 }
 508         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 509                 {
 510                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 511                             RT_IDX_TYPE_NICQ |  /* type */
 512                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 513                         break;
 514                 }
 515         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 516                 {
 517                         value = RT_IDX_DST_CAM_Q |      /* dest */
 518                             RT_IDX_TYPE_NICQ |  /* type */
 519                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 520                         break;
 521                 }
 522         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 523                 {
 524                         value = RT_IDX_DST_CAM_Q |      /* dest */
 525                             RT_IDX_TYPE_NICQ |  /* type */
 526                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 527                         break;
 528                 }
 529         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 530                 {
 531                         value = RT_IDX_DST_RSS |        /* dest */
 532                             RT_IDX_TYPE_NICQ |  /* type */
 533                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 534                         break;
 535                 }
 536         case 0:         /* Clear the E-bit on an entry. */
 537                 {
 538                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 539                             RT_IDX_TYPE_NICQ |  /* type */
 540                             (index << RT_IDX_IDX_SHIFT);/* index */
 541                         break;
 542                 }
 543         default:
 544                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 545                         mask);
 546                 status = -EPERM;
 547                 goto exit;
 548         }
 549
 550         if (value) {
 551                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 552                 if (status)
 553                         goto exit;
 554                 value |= (enable ? RT_IDX_E : 0);
 555                 ql_write32(qdev, RT_IDX, value);
 556                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 557         }
 558 exit:
 559         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 560         return status;
 561 }
 562
 563 static void ql_enable_interrupts(struct ql_adapter *qdev)
 564 {
 565         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 566 }
 567
 568 static void ql_disable_interrupts(struct ql_adapter *qdev)
 569 {
 570         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 571 }
 572
 573 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 574  * Otherwise, we may have multiple outstanding workers and don't want to
 575  * enable until the last one finishes. In this case, the irq_cnt gets
 576  * incremented everytime we queue a worker and decremented everytime
 577  * a worker finishes.  Once it hits zero we enable the interrupt.
 578  */
 579 void ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 580 {
 581         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags)))
 582                 ql_write32(qdev, INTR_EN,
 583                            qdev->intr_context[intr].intr_en_mask);
 584         else {
 585                 if (qdev->legacy_check)
 586                         spin_lock(&qdev->legacy_lock);
 587                 if (atomic_dec_and_test(&qdev->intr_context[intr].irq_cnt)) {
 588                         QPRINTK(qdev, INTR, ERR, "Enabling interrupt %d.\n",
 589                                 intr);
 590                         ql_write32(qdev, INTR_EN,
 591                                    qdev->intr_context[intr].intr_en_mask);
 592                 } else {
 593                         QPRINTK(qdev, INTR, ERR,
 594                                 "Skip enable, other queue(s) are active.\n");
 595                 }
 596                 if (qdev->legacy_check)
 597                         spin_unlock(&qdev->legacy_lock);
 598         }
 599 }
 600
 601 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 602 {
 603         u32 var = 0;
 604
 605         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags)))
 606                 goto exit;
 607         else if (!atomic_read(&qdev->intr_context[intr].irq_cnt)) {
 608                 ql_write32(qdev, INTR_EN,
 609                            qdev->intr_context[intr].intr_dis_mask);
 610                 var = ql_read32(qdev, STS);
 611         }
 612         atomic_inc(&qdev->intr_context[intr].irq_cnt);
 613 exit:
 614         return var;
 615 }
 616
 617 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 618 {
 619         int i;
 620         for (i = 0; i < qdev->intr_count; i++) {
 621                 /* The enable call does a atomic_dec_and_test
 622                  * and enables only if the result is zero.
 623                  * So we precharge it here.
 624                  */
 625                 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 626                 ql_enable_completion_interrupt(qdev, i);
 627         }
 628
 629 }
 630
 631 int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
 632 {
 633         int status = 0;
 634         /* wait for reg to come ready */
 635         status = ql_wait_reg_rdy(qdev,
 636                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 637         if (status)
 638                 goto exit;
 639         /* set up for reg read */
 640         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 641         /* wait for reg to come ready */
 642         status = ql_wait_reg_rdy(qdev,
 643                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 644         if (status)
 645                 goto exit;
 646         /* get the data */
 647         *data = ql_read32(qdev, FLASH_DATA);
 648 exit:
 649         return status;
 650 }
 651
 652 static int ql_get_flash_params(struct ql_adapter *qdev)
 653 {
 654         int i;
 655         int status;
 656         u32 *p = (u32 *)&qdev->flash;
 657
 658         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 659                 return -ETIMEDOUT;
 660
 661         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 662                 status = ql_read_flash_word(qdev, i, p);
 663                 if (status) {
 664                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 665                         goto exit;
 666                 }
 667
 668         }
 669 exit:
 670         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 671         return status;
 672 }
 673
 674 /* xgmac register are located behind the xgmac_addr and xgmac_data
 675  * register pair.  Each read/write requires us to wait for the ready
 676  * bit before reading/writing the data.
 677  */
 678 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 679 {
 680         int status;
 681         /* wait for reg to come ready */
 682         status = ql_wait_reg_rdy(qdev,
 683                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 684         if (status)
 685                 return status;
 686         /* write the data to the data reg */
 687         ql_write32(qdev, XGMAC_DATA, data);
 688         /* trigger the write */
 689         ql_write32(qdev, XGMAC_ADDR, reg);
 690         return status;
 691 }
 692
 693 /* xgmac register are located behind the xgmac_addr and xgmac_data
 694  * register pair.  Each read/write requires us to wait for the ready
 695  * bit before reading/writing the data.
 696  */
 697 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 698 {
 699         int status = 0;
 700         /* wait for reg to come ready */
 701         status = ql_wait_reg_rdy(qdev,
 702                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 703         if (status)
 704                 goto exit;
 705         /* set up for reg read */
 706         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 707         /* wait for reg to come ready */
 708         status = ql_wait_reg_rdy(qdev,
 709                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 710         if (status)
 711                 goto exit;
 712         /* get the data */
 713         *data = ql_read32(qdev, XGMAC_DATA);
 714 exit:
 715         return status;
 716 }
 717
 718 /* This is used for reading the 64-bit statistics regs. */
 719 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 720 {
 721         int status = 0;
 722         u32 hi = 0;
 723         u32 lo = 0;
 724
 725         status = ql_read_xgmac_reg(qdev, reg, &lo);
 726         if (status)
 727                 goto exit;
 728
 729         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 730         if (status)
 731                 goto exit;
 732
 733         *data = (u64) lo | ((u64) hi << 32);
 734
 735 exit:
 736         return status;
 737 }
 738
 739 /* Take the MAC Core out of reset.
 740  * Enable statistics counting.
 741  * Take the transmitter/receiver out of reset.
 742  * This functionality may be done in the MPI firmware at a
 743  * later date.
 744  */
 745 static int ql_port_initialize(struct ql_adapter *qdev)
 746 {
 747         int status = 0;
 748         u32 data;
 749
 750         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 751                 /* Another function has the semaphore, so
 752                  * wait for the port init bit to come ready.
 753                  */
 754                 QPRINTK(qdev, LINK, INFO,
 755                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 756                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 757                 if (status) {
 758                         QPRINTK(qdev, LINK, CRIT,
 759                                 "Port initialize timed out.\n");
 760                 }
 761                 return status;
 762         }
 763
 764         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 765         /* Set the core reset. */
 766         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 767         if (status)
 768                 goto end;
 769         data |= GLOBAL_CFG_RESET;
 770         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 771         if (status)
 772                 goto end;
 773
 774         /* Clear the core reset and turn on jumbo for receiver. */
 775         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 776         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 777         data |= GLOBAL_CFG_TX_STAT_EN;
 778         data |= GLOBAL_CFG_RX_STAT_EN;
 779         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 780         if (status)
 781                 goto end;
 782
 783         /* Enable transmitter, and clear it's reset. */
 784         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 785         if (status)
 786                 goto end;
 787         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 788         data |= TX_CFG_EN;      /* Enable the transmitter. */
 789         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 790         if (status)
 791                 goto end;
 792
 793         /* Enable receiver and clear it's reset. */
 794         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 795         if (status)
 796                 goto end;
 797         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 798         data |= RX_CFG_EN;      /* Enable the receiver. */
 799         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 800         if (status)
 801                 goto end;
 802
 803         /* Turn on jumbo. */
 804         status =
 805             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 806         if (status)
 807                 goto end;
 808         status =
 809             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 810         if (status)
 811                 goto end;
 812
 813         /* Signal to the world that the port is enabled.        */
 814         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 815 end:
 816         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 817         return status;
 818 }
 819
 820 /* Get the next large buffer. */
 821 struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 822 {
 823         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 824         rx_ring->lbq_curr_idx++;
 825         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 826                 rx_ring->lbq_curr_idx = 0;
 827         rx_ring->lbq_free_cnt++;
 828         return lbq_desc;
 829 }
 830
 831 /* Get the next small buffer. */
 832 struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 833 {
 834         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 835         rx_ring->sbq_curr_idx++;
 836         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 837                 rx_ring->sbq_curr_idx = 0;
 838         rx_ring->sbq_free_cnt++;
 839         return sbq_desc;
 840 }
 841
 842 /* Update an rx ring index. */
 843 static void ql_update_cq(struct rx_ring *rx_ring)
 844 {
 845         rx_ring->cnsmr_idx++;
 846         rx_ring->curr_entry++;
 847         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 848                 rx_ring->cnsmr_idx = 0;
 849                 rx_ring->curr_entry = rx_ring->cq_base;
 850         }
 851 }
 852
 853 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 854 {
 855         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 856 }
 857
 858 /* Process (refill) a large buffer queue. */
 859 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 860 {
 861         int clean_idx = rx_ring->lbq_clean_idx;
 862         struct bq_desc *lbq_desc;
 863         struct bq_element *bq;
 864         u64 map;
 865         int i;
 866
 867         while (rx_ring->lbq_free_cnt > 16) {
 868                 for (i = 0; i < 16; i++) {
 869                         QPRINTK(qdev, RX_STATUS, DEBUG,
 870                                 "lbq: try cleaning clean_idx = %d.\n",
 871                                 clean_idx);
 872                         lbq_desc = &rx_ring->lbq[clean_idx];
 873                         bq = lbq_desc->bq;
 874                         if (lbq_desc->p.lbq_page == NULL) {
 875                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 876                                         "lbq: getting new page for index %d.\n",
 877                                         lbq_desc->index);
 878                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 879                                 if (lbq_desc->p.lbq_page == NULL) {
 880                                         QPRINTK(qdev, RX_STATUS, ERR,
 881                                                 "Couldn't get a page.\n");
 882                                         return;
 883                                 }
 884                                 map = pci_map_page(qdev->pdev,
 885                                                    lbq_desc->p.lbq_page,
 886                                                    0, PAGE_SIZE,
 887                                                    PCI_DMA_FROMDEVICE);
 888                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 889                                         QPRINTK(qdev, RX_STATUS, ERR,
 890                                                 "PCI mapping failed.\n");
 891                                         return;
 892                                 }
 893                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 894                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 895                                 bq->addr_lo =   /*lbq_desc->addr_lo = */
 896                                     cpu_to_le32(map);
 897                                 bq->addr_hi =   /*lbq_desc->addr_hi = */
 898                                     cpu_to_le32(map >> 32);
 899                         }
 900                         clean_idx++;
 901                         if (clean_idx == rx_ring->lbq_len)
 902                                 clean_idx = 0;
 903                 }
 904
 905                 rx_ring->lbq_clean_idx = clean_idx;
 906                 rx_ring->lbq_prod_idx += 16;
 907                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 908                         rx_ring->lbq_prod_idx = 0;
 909                 QPRINTK(qdev, RX_STATUS, DEBUG,
 910                         "lbq: updating prod idx = %d.\n",
 911                         rx_ring->lbq_prod_idx);
 912                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 913                                 rx_ring->lbq_prod_idx_db_reg);
 914                 rx_ring->lbq_free_cnt -= 16;
 915         }
 916 }
 917
 918 /* Process (refill) a small buffer queue. */
 919 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 920 {
 921         int clean_idx = rx_ring->sbq_clean_idx;
 922         struct bq_desc *sbq_desc;
 923         struct bq_element *bq;
 924         u64 map;
 925         int i;
 926
 927         while (rx_ring->sbq_free_cnt > 16) {
 928                 for (i = 0; i < 16; i++) {
 929                         sbq_desc = &rx_ring->sbq[clean_idx];
 930                         QPRINTK(qdev, RX_STATUS, DEBUG,
 931                                 "sbq: try cleaning clean_idx = %d.\n",
 932                                 clean_idx);
 933                         bq = sbq_desc->bq;
 934                         if (sbq_desc->p.skb == NULL) {
 935                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 936                                         "sbq: getting new skb for index %d.\n",
 937                                         sbq_desc->index);
 938                                 sbq_desc->p.skb =
 939                                     netdev_alloc_skb(qdev->ndev,
 940                                                      rx_ring->sbq_buf_size);
 941                                 if (sbq_desc->p.skb == NULL) {
 942                                         QPRINTK(qdev, PROBE, ERR,
 943                                                 "Couldn't get an skb.\n");
 944                                         rx_ring->sbq_clean_idx = clean_idx;
 945                                         return;
 946                                 }
 947                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 948                                 map = pci_map_single(qdev->pdev,
 949                                                      sbq_desc->p.skb->data,
 950                                                      rx_ring->sbq_buf_size /
 951                                                      2, PCI_DMA_FROMDEVICE);
 952                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 953                                 pci_unmap_len_set(sbq_desc, maplen,
 954                                                   rx_ring->sbq_buf_size / 2);
 955                                 bq->addr_lo = cpu_to_le32(map);
 956                                 bq->addr_hi = cpu_to_le32(map >> 32);
 957                         }
 958
 959                         clean_idx++;
 960                         if (clean_idx == rx_ring->sbq_len)
 961                                 clean_idx = 0;
 962                 }
 963                 rx_ring->sbq_clean_idx = clean_idx;
 964                 rx_ring->sbq_prod_idx += 16;
 965                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 966                         rx_ring->sbq_prod_idx = 0;
 967                 QPRINTK(qdev, RX_STATUS, DEBUG,
 968                         "sbq: updating prod idx = %d.\n",
 969                         rx_ring->sbq_prod_idx);
 970                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 971                                 rx_ring->sbq_prod_idx_db_reg);
 972
 973                 rx_ring->sbq_free_cnt -= 16;
 974         }
 975 }
 976
 977 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 978                                     struct rx_ring *rx_ring)
 979 {
 980         ql_update_sbq(qdev, rx_ring);
 981         ql_update_lbq(qdev, rx_ring);
 982 }
 983
 984 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
 985  * fails at some stage, or from the interrupt when a tx completes.
 986  */
 987 static void ql_unmap_send(struct ql_adapter *qdev,
 988                           struct tx_ring_desc *tx_ring_desc, int mapped)
 989 {
 990         int i;
 991         for (i = 0; i < mapped; i++) {
 992                 if (i == 0 || (i == 7 && mapped > 7)) {
 993                         /*
 994                          * Unmap the skb->data area, or the
 995                          * external sglist (AKA the Outbound
 996                          * Address List (OAL)).
 997                          * If its the zeroeth element, then it's
 998                          * the skb->data area.  If it's the 7th
 999                          * element and there is more than 6 frags,
1000                          * then its an OAL.
1001                          */
1002                         if (i == 7) {
1003                                 QPRINTK(qdev, TX_DONE, DEBUG,
1004                                         "unmapping OAL area.\n");
1005                         }
1006                         pci_unmap_single(qdev->pdev,
1007                                          pci_unmap_addr(&tx_ring_desc->map[i],
1008                                                         mapaddr),
1009                                          pci_unmap_len(&tx_ring_desc->map[i],
1010                                                        maplen),
1011                                          PCI_DMA_TODEVICE);
1012                 } else {
1013                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1014                                 i);
1015                         pci_unmap_page(qdev->pdev,
1016                                        pci_unmap_addr(&tx_ring_desc->map[i],
1017                                                       mapaddr),
1018                                        pci_unmap_len(&tx_ring_desc->map[i],
1019                                                      maplen), PCI_DMA_TODEVICE);
1020                 }
1021         }
1022
1023 }
1024
1025 /* Map the buffers for this transmit.  This will return
1026  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1027  */
1028 static int ql_map_send(struct ql_adapter *qdev,
1029                        struct ob_mac_iocb_req *mac_iocb_ptr,
1030                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1031 {
1032         int len = skb_headlen(skb);
1033         dma_addr_t map;
1034         int frag_idx, err, map_idx = 0;
1035         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1036         int frag_cnt = skb_shinfo(skb)->nr_frags;
1037
1038         if (frag_cnt) {
1039                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1040         }
1041         /*
1042          * Map the skb buffer first.
1043          */
1044         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1045
1046         err = pci_dma_mapping_error(qdev->pdev, map);
1047         if (err) {
1048                 QPRINTK(qdev, TX_QUEUED, ERR,
1049                         "PCI mapping failed with error: %d\n", err);
1050
1051                 return NETDEV_TX_BUSY;
1052         }
1053
1054         tbd->len = cpu_to_le32(len);
1055         tbd->addr = cpu_to_le64(map);
1056         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1057         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1058         map_idx++;
1059
1060         /*
1061          * This loop fills the remainder of the 8 address descriptors
1062          * in the IOCB.  If there are more than 7 fragments, then the
1063          * eighth address desc will point to an external list (OAL).
1064          * When this happens, the remainder of the frags will be stored
1065          * in this list.
1066          */
1067         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1068                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1069                 tbd++;
1070                 if (frag_idx == 6 && frag_cnt > 7) {
1071                         /* Let's tack on an sglist.
1072                          * Our control block will now
1073                          * look like this:
1074                          * iocb->seg[0] = skb->data
1075                          * iocb->seg[1] = frag[0]
1076                          * iocb->seg[2] = frag[1]
1077                          * iocb->seg[3] = frag[2]
1078                          * iocb->seg[4] = frag[3]
1079                          * iocb->seg[5] = frag[4]
1080                          * iocb->seg[6] = frag[5]
1081                          * iocb->seg[7] = ptr to OAL (external sglist)
1082                          * oal->seg[0] = frag[6]
1083                          * oal->seg[1] = frag[7]
1084                          * oal->seg[2] = frag[8]
1085                          * oal->seg[3] = frag[9]
1086                          * oal->seg[4] = frag[10]
1087                          *      etc...
1088                          */
1089                         /* Tack on the OAL in the eighth segment of IOCB. */
1090                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1091                                              sizeof(struct oal),
1092                                              PCI_DMA_TODEVICE);
1093                         err = pci_dma_mapping_error(qdev->pdev, map);
1094                         if (err) {
1095                                 QPRINTK(qdev, TX_QUEUED, ERR,
1096                                         "PCI mapping outbound address list with error: %d\n",
1097                                         err);
1098                                 goto map_error;
1099                         }
1100
1101                         tbd->addr = cpu_to_le64(map);
1102                         /*
1103                          * The length is the number of fragments
1104                          * that remain to be mapped times the length
1105                          * of our sglist (OAL).
1106                          */
1107                         tbd->len =
1108                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1109                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1110                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1111                                            map);
1112                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1113                                           sizeof(struct oal));
1114                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1115                         map_idx++;
1116                 }
1117
1118                 map =
1119                     pci_map_page(qdev->pdev, frag->page,
1120                                  frag->page_offset, frag->size,
1121                                  PCI_DMA_TODEVICE);
1122
1123                 err = pci_dma_mapping_error(qdev->pdev, map);
1124                 if (err) {
1125                         QPRINTK(qdev, TX_QUEUED, ERR,
1126                                 "PCI mapping frags failed with error: %d.\n",
1127                                 err);
1128                         goto map_error;
1129                 }
1130
1131                 tbd->addr = cpu_to_le64(map);
1132                 tbd->len = cpu_to_le32(frag->size);
1133                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1134                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1135                                   frag->size);
1136
1137         }
1138         /* Save the number of segments we've mapped. */
1139         tx_ring_desc->map_cnt = map_idx;
1140         /* Terminate the last segment. */
1141         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1142         return NETDEV_TX_OK;
1143
1144 map_error:
1145         /*
1146          * If the first frag mapping failed, then i will be zero.
1147          * This causes the unmap of the skb->data area.  Otherwise
1148          * we pass in the number of frags that mapped successfully
1149          * so they can be umapped.
1150          */
1151         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1152         return NETDEV_TX_BUSY;
1153 }
1154
1155 void ql_realign_skb(struct sk_buff *skb, int len)
1156 {
1157         void *temp_addr = skb->data;
1158
1159         /* Undo the skb_reserve(skb,32) we did before
1160          * giving to hardware, and realign data on
1161          * a 2-byte boundary.
1162          */
1163         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1164         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1165         skb_copy_to_linear_data(skb, temp_addr,
1166                 (unsigned int)len);
1167 }
1168
1169 /*
1170  * This function builds an skb for the given inbound
1171  * completion.  It will be rewritten for readability in the near
1172  * future, but for not it works well.
1173  */
1174 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1175                                        struct rx_ring *rx_ring,
1176                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1177 {
1178         struct bq_desc *lbq_desc;
1179         struct bq_desc *sbq_desc;
1180         struct sk_buff *skb = NULL;
1181         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1182        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1183
1184         /*
1185          * Handle the header buffer if present.
1186          */
1187         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1188             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1189                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1190                 /*
1191                  * Headers fit nicely into a small buffer.
1192                  */
1193                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1194                 pci_unmap_single(qdev->pdev,
1195                                 pci_unmap_addr(sbq_desc, mapaddr),
1196                                 pci_unmap_len(sbq_desc, maplen),
1197                                 PCI_DMA_FROMDEVICE);
1198                 skb = sbq_desc->p.skb;
1199                 ql_realign_skb(skb, hdr_len);
1200                 skb_put(skb, hdr_len);
1201                 sbq_desc->p.skb = NULL;
1202         }
1203
1204         /*
1205          * Handle the data buffer(s).
1206          */
1207         if (unlikely(!length)) {        /* Is there data too? */
1208                 QPRINTK(qdev, RX_STATUS, DEBUG,
1209                         "No Data buffer in this packet.\n");
1210                 return skb;
1211         }
1212
1213         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1214                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1215                         QPRINTK(qdev, RX_STATUS, DEBUG,
1216                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1217                         /*
1218                          * Data is less than small buffer size so it's
1219                          * stuffed in a small buffer.
1220                          * For this case we append the data
1221                          * from the "data" small buffer to the "header" small
1222                          * buffer.
1223                          */
1224                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1225                         pci_dma_sync_single_for_cpu(qdev->pdev,
1226                                                     pci_unmap_addr
1227                                                     (sbq_desc, mapaddr),
1228                                                     pci_unmap_len
1229                                                     (sbq_desc, maplen),
1230                                                     PCI_DMA_FROMDEVICE);
1231                         memcpy(skb_put(skb, length),
1232                                sbq_desc->p.skb->data, length);
1233                         pci_dma_sync_single_for_device(qdev->pdev,
1234                                                        pci_unmap_addr
1235                                                        (sbq_desc,
1236                                                         mapaddr),
1237                                                        pci_unmap_len
1238                                                        (sbq_desc,
1239                                                         maplen),
1240                                                        PCI_DMA_FROMDEVICE);
1241                 } else {
1242                         QPRINTK(qdev, RX_STATUS, DEBUG,
1243                                 "%d bytes in a single small buffer.\n", length);
1244                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1245                         skb = sbq_desc->p.skb;
1246                         ql_realign_skb(skb, length);
1247                         skb_put(skb, length);
1248                         pci_unmap_single(qdev->pdev,
1249                                          pci_unmap_addr(sbq_desc,
1250                                                         mapaddr),
1251                                          pci_unmap_len(sbq_desc,
1252                                                        maplen),
1253                                          PCI_DMA_FROMDEVICE);
1254                         sbq_desc->p.skb = NULL;
1255                 }
1256         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1257                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1258                         QPRINTK(qdev, RX_STATUS, DEBUG,
1259                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1260                         /*
1261                          * The data is in a single large buffer.  We
1262                          * chain it to the header buffer's skb and let
1263                          * it rip.
1264                          */
1265                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1266                         pci_unmap_page(qdev->pdev,
1267                                        pci_unmap_addr(lbq_desc,
1268                                                       mapaddr),
1269                                        pci_unmap_len(lbq_desc, maplen),
1270                                        PCI_DMA_FROMDEVICE);
1271                         QPRINTK(qdev, RX_STATUS, DEBUG,
1272                                 "Chaining page to skb.\n");
1273                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1274                                            0, length);
1275                         skb->len += length;
1276                         skb->data_len += length;
1277                         skb->truesize += length;
1278                         lbq_desc->p.lbq_page = NULL;
1279                 } else {
1280                         /*
1281                          * The headers and data are in a single large buffer. We
1282                          * copy it to a new skb and let it go. This can happen with
1283                          * jumbo mtu on a non-TCP/UDP frame.
1284                          */
1285                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1286                         skb = netdev_alloc_skb(qdev->ndev, length);
1287                         if (skb == NULL) {
1288                                 QPRINTK(qdev, PROBE, DEBUG,
1289                                         "No skb available, drop the packet.\n");
1290                                 return NULL;
1291                         }
1292                         skb_reserve(skb, NET_IP_ALIGN);
1293                         QPRINTK(qdev, RX_STATUS, DEBUG,
1294                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1295                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1296                                            0, length);
1297                         skb->len += length;
1298                         skb->data_len += length;
1299                         skb->truesize += length;
1300                         length -= length;
1301                         lbq_desc->p.lbq_page = NULL;
1302                         __pskb_pull_tail(skb,
1303                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1304                                 VLAN_ETH_HLEN : ETH_HLEN);
1305                 }
1306         } else {
1307                 /*
1308                  * The data is in a chain of large buffers
1309                  * pointed to by a small buffer.  We loop
1310                  * thru and chain them to the our small header
1311                  * buffer's skb.
1312                  * frags:  There are 18 max frags and our small
1313                  *         buffer will hold 32 of them. The thing is,
1314                  *         we'll use 3 max for our 9000 byte jumbo
1315                  *         frames.  If the MTU goes up we could
1316                  *          eventually be in trouble.
1317                  */
1318                 int size, offset, i = 0;
1319                 struct bq_element *bq, bq_array[8];
1320                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1321                 pci_unmap_single(qdev->pdev,
1322                                  pci_unmap_addr(sbq_desc, mapaddr),
1323                                  pci_unmap_len(sbq_desc, maplen),
1324                                  PCI_DMA_FROMDEVICE);
1325                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1326                         /*
1327                          * This is an non TCP/UDP IP frame, so
1328                          * the headers aren't split into a small
1329                          * buffer.  We have to use the small buffer
1330                          * that contains our sg list as our skb to
1331                          * send upstairs. Copy the sg list here to
1332                          * a local buffer and use it to find the
1333                          * pages to chain.
1334                          */
1335                         QPRINTK(qdev, RX_STATUS, DEBUG,
1336                                 "%d bytes of headers & data in chain of large.\n", length);
1337                         skb = sbq_desc->p.skb;
1338                         bq = &bq_array[0];
1339                         memcpy(bq, skb->data, sizeof(bq_array));
1340                         sbq_desc->p.skb = NULL;
1341                         skb_reserve(skb, NET_IP_ALIGN);
1342                 } else {
1343                         QPRINTK(qdev, RX_STATUS, DEBUG,
1344                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1345                         bq = (struct bq_element *)sbq_desc->p.skb->data;
1346                 }
1347                 while (length > 0) {
1348                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1349                         if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1350                                 QPRINTK(qdev, RX_STATUS, ERR,
1351                                         "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1352                                         lbq_desc->bq->addr_lo, bq->addr_lo);
1353                                 return NULL;
1354                         }
1355                         pci_unmap_page(qdev->pdev,
1356                                        pci_unmap_addr(lbq_desc,
1357                                                       mapaddr),
1358                                        pci_unmap_len(lbq_desc,
1359                                                      maplen),
1360                                        PCI_DMA_FROMDEVICE);
1361                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1362                         offset = 0;
1363
1364                         QPRINTK(qdev, RX_STATUS, DEBUG,
1365                                 "Adding page %d to skb for %d bytes.\n",
1366                                 i, size);
1367                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1368                                            offset, size);
1369                         skb->len += size;
1370                         skb->data_len += size;
1371                         skb->truesize += size;
1372                         length -= size;
1373                         lbq_desc->p.lbq_page = NULL;
1374                         bq++;
1375                         i++;
1376                 }
1377                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1378                                 VLAN_ETH_HLEN : ETH_HLEN);
1379         }
1380         return skb;
1381 }
1382
1383 /* Process an inbound completion from an rx ring. */
1384 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1385                                    struct rx_ring *rx_ring,
1386                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1387 {
1388         struct net_device *ndev = qdev->ndev;
1389         struct sk_buff *skb = NULL;
1390
1391         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1392
1393         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1394         if (unlikely(!skb)) {
1395                 QPRINTK(qdev, RX_STATUS, DEBUG,
1396                         "No skb available, drop packet.\n");
1397                 return;
1398         }
1399
1400         prefetch(skb->data);
1401         skb->dev = ndev;
1402         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1403                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1404                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1405                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1406                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1407                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1408                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1409                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1410         }
1411         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1412                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1413         }
1414         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1415                 QPRINTK(qdev, RX_STATUS, ERR,
1416                         "Bad checksum for this %s packet.\n",
1417                         ((ib_mac_rsp->
1418                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1419                 skb->ip_summed = CHECKSUM_NONE;
1420         } else if (qdev->rx_csum &&
1421                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1422                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1423                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1424                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1425                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1426         }
1427         qdev->stats.rx_packets++;
1428         qdev->stats.rx_bytes += skb->len;
1429         skb->protocol = eth_type_trans(skb, ndev);
1430         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1431                 QPRINTK(qdev, RX_STATUS, DEBUG,
1432                         "Passing a VLAN packet upstream.\n");
1433                 vlan_hwaccel_rx(skb, qdev->vlgrp,
1434                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1435         } else {
1436                 QPRINTK(qdev, RX_STATUS, DEBUG,
1437                         "Passing a normal packet upstream.\n");
1438                 netif_rx(skb);
1439         }
1440         ndev->last_rx = jiffies;
1441 }
1442
1443 /* Process an outbound completion from an rx ring. */
1444 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1445                                    struct ob_mac_iocb_rsp *mac_rsp)
1446 {
1447         struct tx_ring *tx_ring;
1448         struct tx_ring_desc *tx_ring_desc;
1449
1450         QL_DUMP_OB_MAC_RSP(mac_rsp);
1451         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1452         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1453         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1454         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1455         qdev->stats.tx_packets++;
1456         dev_kfree_skb(tx_ring_desc->skb);
1457         tx_ring_desc->skb = NULL;
1458
1459         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1460                                         OB_MAC_IOCB_RSP_S |
1461                                         OB_MAC_IOCB_RSP_L |
1462                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1463                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1464                         QPRINTK(qdev, TX_DONE, WARNING,
1465                                 "Total descriptor length did not match transfer length.\n");
1466                 }
1467                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1468                         QPRINTK(qdev, TX_DONE, WARNING,
1469                                 "Frame too short to be legal, not sent.\n");
1470                 }
1471                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1472                         QPRINTK(qdev, TX_DONE, WARNING,
1473                                 "Frame too long, but sent anyway.\n");
1474                 }
1475                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1476                         QPRINTK(qdev, TX_DONE, WARNING,
1477                                 "PCI backplane error. Frame not sent.\n");
1478                 }
1479         }
1480         atomic_inc(&tx_ring->tx_count);
1481 }
1482
1483 /* Fire up a handler to reset the MPI processor. */
1484 void ql_queue_fw_error(struct ql_adapter *qdev)
1485 {
1486         netif_stop_queue(qdev->ndev);
1487         netif_carrier_off(qdev->ndev);
1488         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1489 }
1490
1491 void ql_queue_asic_error(struct ql_adapter *qdev)
1492 {
1493         netif_stop_queue(qdev->ndev);
1494         netif_carrier_off(qdev->ndev);
1495         ql_disable_interrupts(qdev);
1496         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1497 }
1498
1499 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1500                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1501 {
1502         switch (ib_ae_rsp->event) {
1503         case MGMT_ERR_EVENT:
1504                 QPRINTK(qdev, RX_ERR, ERR,
1505                         "Management Processor Fatal Error.\n");
1506                 ql_queue_fw_error(qdev);
1507                 return;
1508
1509         case CAM_LOOKUP_ERR_EVENT:
1510                 QPRINTK(qdev, LINK, ERR,
1511                         "Multiple CAM hits lookup occurred.\n");
1512                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1513                 ql_queue_asic_error(qdev);
1514                 return;
1515
1516         case SOFT_ECC_ERROR_EVENT:
1517                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1518                 ql_queue_asic_error(qdev);
1519                 break;
1520
1521         case PCI_ERR_ANON_BUF_RD:
1522                 QPRINTK(qdev, RX_ERR, ERR,
1523                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1524                         ib_ae_rsp->q_id);
1525                 ql_queue_asic_error(qdev);
1526                 break;
1527
1528         default:
1529                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1530                         ib_ae_rsp->event);
1531                 ql_queue_asic_error(qdev);
1532                 break;
1533         }
1534 }
1535
1536 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1537 {
1538         struct ql_adapter *qdev = rx_ring->qdev;
1539         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1540         struct ob_mac_iocb_rsp *net_rsp = NULL;
1541         int count = 0;
1542
1543         /* While there are entries in the completion queue. */
1544         while (prod != rx_ring->cnsmr_idx) {
1545
1546                 QPRINTK(qdev, RX_STATUS, DEBUG,
1547                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1548                         prod, rx_ring->cnsmr_idx);
1549
1550                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1551                 rmb();
1552                 switch (net_rsp->opcode) {
1553
1554                 case OPCODE_OB_MAC_TSO_IOCB:
1555                 case OPCODE_OB_MAC_IOCB:
1556                         ql_process_mac_tx_intr(qdev, net_rsp);
1557                         break;
1558                 default:
1559                         QPRINTK(qdev, RX_STATUS, DEBUG,
1560                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1561                                 net_rsp->opcode);
1562                 }
1563                 count++;
1564                 ql_update_cq(rx_ring);
1565                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1566         }
1567         ql_write_cq_idx(rx_ring);
1568         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1569                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1570                 if (atomic_read(&tx_ring->queue_stopped) &&
1571                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1572                         /*
1573                          * The queue got stopped because the tx_ring was full.
1574                          * Wake it up, because it's now at least 25% empty.
1575                          */
1576                         netif_wake_queue(qdev->ndev);
1577         }
1578
1579         return count;
1580 }
1581
1582 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1583 {
1584         struct ql_adapter *qdev = rx_ring->qdev;
1585         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1586         struct ql_net_rsp_iocb *net_rsp;
1587         int count = 0;
1588
1589         /* While there are entries in the completion queue. */
1590         while (prod != rx_ring->cnsmr_idx) {
1591
1592                 QPRINTK(qdev, RX_STATUS, DEBUG,
1593                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1594                         prod, rx_ring->cnsmr_idx);
1595
1596                 net_rsp = rx_ring->curr_entry;
1597                 rmb();
1598                 switch (net_rsp->opcode) {
1599                 case OPCODE_IB_MAC_IOCB:
1600                         ql_process_mac_rx_intr(qdev, rx_ring,
1601                                                (struct ib_mac_iocb_rsp *)
1602                                                net_rsp);
1603                         break;
1604
1605                 case OPCODE_IB_AE_IOCB:
1606                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1607                                                 net_rsp);
1608                         break;
1609                 default:
1610                         {
1611                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1612                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1613                                         net_rsp->opcode);
1614                         }
1615                 }
1616                 count++;
1617                 ql_update_cq(rx_ring);
1618                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1619                 if (count == budget)
1620                         break;
1621         }
1622         ql_update_buffer_queues(qdev, rx_ring);
1623         ql_write_cq_idx(rx_ring);
1624         return count;
1625 }
1626
1627 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1628 {
1629         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1630         struct ql_adapter *qdev = rx_ring->qdev;
1631         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1632
1633         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1634                 rx_ring->cq_id);
1635
1636         if (work_done < budget) {
1637                 __netif_rx_complete(qdev->ndev, napi);
1638                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1639         }
1640         return work_done;
1641 }
1642
1643 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1644 {
1645         struct ql_adapter *qdev = netdev_priv(ndev);
1646
1647         qdev->vlgrp = grp;
1648         if (grp) {
1649                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1650                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1651                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1652         } else {
1653                 QPRINTK(qdev, IFUP, DEBUG,
1654                         "Turning off VLAN in NIC_RCV_CFG.\n");
1655                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1656         }
1657 }
1658
1659 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1660 {
1661         struct ql_adapter *qdev = netdev_priv(ndev);
1662         u32 enable_bit = MAC_ADDR_E;
1663
1664         spin_lock(&qdev->hw_lock);
1665         if (ql_set_mac_addr_reg
1666             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1667                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1668         }
1669         spin_unlock(&qdev->hw_lock);
1670 }
1671
1672 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1673 {
1674         struct ql_adapter *qdev = netdev_priv(ndev);
1675         u32 enable_bit = 0;
1676
1677         spin_lock(&qdev->hw_lock);
1678         if (ql_set_mac_addr_reg
1679             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1680                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1681         }
1682         spin_unlock(&qdev->hw_lock);
1683
1684 }
1685
1686 /* Worker thread to process a given rx_ring that is dedicated
1687  * to outbound completions.
1688  */
1689 static void ql_tx_clean(struct work_struct *work)
1690 {
1691         struct rx_ring *rx_ring =
1692             container_of(work, struct rx_ring, rx_work.work);
1693         ql_clean_outbound_rx_ring(rx_ring);
1694         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1695
1696 }
1697
1698 /* Worker thread to process a given rx_ring that is dedicated
1699  * to inbound completions.
1700  */
1701 static void ql_rx_clean(struct work_struct *work)
1702 {
1703         struct rx_ring *rx_ring =
1704             container_of(work, struct rx_ring, rx_work.work);
1705         ql_clean_inbound_rx_ring(rx_ring, 64);
1706         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1707 }
1708
1709 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1710 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1711 {
1712         struct rx_ring *rx_ring = dev_id;
1713         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1714                               &rx_ring->rx_work, 0);
1715         return IRQ_HANDLED;
1716 }
1717
1718 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1719 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1720 {
1721         struct rx_ring *rx_ring = dev_id;
1722         struct ql_adapter *qdev = rx_ring->qdev;
1723         netif_rx_schedule(qdev->ndev, &rx_ring->napi);
1724         return IRQ_HANDLED;
1725 }
1726
1727 /* We check here to see if we're already handling a legacy
1728  * interrupt.  If we are, then it must belong to another
1729  * chip with which we're sharing the interrupt line.
1730  */
1731 int ql_legacy_check(struct ql_adapter *qdev)
1732 {
1733         int err;
1734         spin_lock(&qdev->legacy_lock);
1735         err = atomic_read(&qdev->intr_context[0].irq_cnt);
1736         spin_unlock(&qdev->legacy_lock);
1737         return err;
1738 }
1739
1740 /* This handles a fatal error, MPI activity, and the default
1741  * rx_ring in an MSI-X multiple vector environment.
1742  * In MSI/Legacy environment it also process the rest of
1743  * the rx_rings.
1744  */
1745 static irqreturn_t qlge_isr(int irq, void *dev_id)
1746 {
1747         struct rx_ring *rx_ring = dev_id;
1748         struct ql_adapter *qdev = rx_ring->qdev;
1749         struct intr_context *intr_context = &qdev->intr_context[0];
1750         u32 var;
1751         int i;
1752         int work_done = 0;
1753
1754         if (qdev->legacy_check && qdev->legacy_check(qdev)) {
1755                 QPRINTK(qdev, INTR, INFO, "Already busy, not our interrupt.\n");
1756                 return IRQ_NONE;        /* Not our interrupt */
1757         }
1758
1759         var = ql_read32(qdev, STS);
1760
1761         /*
1762          * Check for fatal error.
1763          */
1764         if (var & STS_FE) {
1765                 ql_queue_asic_error(qdev);
1766                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1767                 var = ql_read32(qdev, ERR_STS);
1768                 QPRINTK(qdev, INTR, ERR,
1769                         "Resetting chip. Error Status Register = 0x%x\n", var);
1770                 return IRQ_HANDLED;
1771         }
1772
1773         /*
1774          * Check MPI processor activity.
1775          */
1776         if (var & STS_PI) {
1777                 /*
1778                  * We've got an async event or mailbox completion.
1779                  * Handle it and clear the source of the interrupt.
1780                  */
1781                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1782                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1783                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1784                                       &qdev->mpi_work, 0);
1785                 work_done++;
1786         }
1787
1788         /*
1789          * Check the default queue and wake handler if active.
1790          */
1791         rx_ring = &qdev->rx_ring[0];
1792         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1793                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1794                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1795                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1796                                       &rx_ring->rx_work, 0);
1797                 work_done++;
1798         }
1799
1800         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1801                 /*
1802                  * Start the DPC for each active queue.
1803                  */
1804                 for (i = 1; i < qdev->rx_ring_count; i++) {
1805                         rx_ring = &qdev->rx_ring[i];
1806                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1807                             rx_ring->cnsmr_idx) {
1808                                 QPRINTK(qdev, INTR, INFO,
1809                                         "Waking handler for rx_ring[%d].\n", i);
1810                                 ql_disable_completion_interrupt(qdev,
1811                                                                 intr_context->
1812                                                                 intr);
1813                                 if (i < qdev->rss_ring_first_cq_id)
1814                                         queue_delayed_work_on(rx_ring->cpu,
1815                                                               qdev->q_workqueue,
1816                                                               &rx_ring->rx_work,
1817                                                               0);
1818                                 else
1819                                         netif_rx_schedule(qdev->ndev,
1820                                                           &rx_ring->napi);
1821                                 work_done++;
1822                         }
1823                 }
1824         }
1825         return work_done ? IRQ_HANDLED : IRQ_NONE;
1826 }
1827
1828 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1829 {
1830
1831         if (skb_is_gso(skb)) {
1832                 int err;
1833                 if (skb_header_cloned(skb)) {
1834                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1835                         if (err)
1836                                 return err;
1837                 }
1838
1839                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1840                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1841                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1842                 mac_iocb_ptr->total_hdrs_len =
1843                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1844                 mac_iocb_ptr->net_trans_offset =
1845                     cpu_to_le16(skb_network_offset(skb) |
1846                                 skb_transport_offset(skb)
1847                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1848                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1849                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1850                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1851                         struct iphdr *iph = ip_hdr(skb);
1852                         iph->check = 0;
1853                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1854                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1855                                                                  iph->daddr, 0,
1856                                                                  IPPROTO_TCP,
1857                                                                  0);
1858                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1859                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1860                         tcp_hdr(skb)->check =
1861                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1862                                              &ipv6_hdr(skb)->daddr,
1863                                              0, IPPROTO_TCP, 0);
1864                 }
1865                 return 1;
1866         }
1867         return 0;
1868 }
1869
1870 static void ql_hw_csum_setup(struct sk_buff *skb,
1871                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1872 {
1873         int len;
1874         struct iphdr *iph = ip_hdr(skb);
1875         u16 *check;
1876         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1877         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1878         mac_iocb_ptr->net_trans_offset =
1879                 cpu_to_le16(skb_network_offset(skb) |
1880                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1881
1882         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1883         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1884         if (likely(iph->protocol == IPPROTO_TCP)) {
1885                 check = &(tcp_hdr(skb)->check);
1886                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1887                 mac_iocb_ptr->total_hdrs_len =
1888                     cpu_to_le16(skb_transport_offset(skb) +
1889                                 (tcp_hdr(skb)->doff << 2));
1890         } else {
1891                 check = &(udp_hdr(skb)->check);
1892                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1893                 mac_iocb_ptr->total_hdrs_len =
1894                     cpu_to_le16(skb_transport_offset(skb) +
1895                                 sizeof(struct udphdr));
1896         }
1897         *check = ~csum_tcpudp_magic(iph->saddr,
1898                                     iph->daddr, len, iph->protocol, 0);
1899 }
1900
1901 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1902 {
1903         struct tx_ring_desc *tx_ring_desc;
1904         struct ob_mac_iocb_req *mac_iocb_ptr;
1905         struct ql_adapter *qdev = netdev_priv(ndev);
1906         int tso;
1907         struct tx_ring *tx_ring;
1908         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1909
1910         tx_ring = &qdev->tx_ring[tx_ring_idx];
1911
1912         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1913                 QPRINTK(qdev, TX_QUEUED, INFO,
1914                         "%s: shutting down tx queue %d du to lack of resources.\n",
1915                         __func__, tx_ring_idx);
1916                 netif_stop_queue(ndev);
1917                 atomic_inc(&tx_ring->queue_stopped);
1918                 return NETDEV_TX_BUSY;
1919         }
1920         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1921         mac_iocb_ptr = tx_ring_desc->queue_entry;
1922         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1923         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1924                 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1925                 return NETDEV_TX_BUSY;
1926         }
1927
1928         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1929         mac_iocb_ptr->tid = tx_ring_desc->index;
1930         /* We use the upper 32-bits to store the tx queue for this IO.
1931          * When we get the completion we can use it to establish the context.
1932          */
1933         mac_iocb_ptr->txq_idx = tx_ring_idx;
1934         tx_ring_desc->skb = skb;
1935
1936         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1937
1938         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1939                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1940                         vlan_tx_tag_get(skb));
1941                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1942                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1943         }
1944         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1945         if (tso < 0) {
1946                 dev_kfree_skb_any(skb);
1947                 return NETDEV_TX_OK;
1948         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1949                 ql_hw_csum_setup(skb,
1950                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1951         }
1952         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1953         tx_ring->prod_idx++;
1954         if (tx_ring->prod_idx == tx_ring->wq_len)
1955                 tx_ring->prod_idx = 0;
1956         wmb();
1957
1958         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1959         ndev->trans_start = jiffies;
1960         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1961                 tx_ring->prod_idx, skb->len);
1962
1963         atomic_dec(&tx_ring->tx_count);
1964         return NETDEV_TX_OK;
1965 }
1966
1967 static void ql_free_shadow_space(struct ql_adapter *qdev)
1968 {
1969         if (qdev->rx_ring_shadow_reg_area) {
1970                 pci_free_consistent(qdev->pdev,
1971                                     PAGE_SIZE,
1972                                     qdev->rx_ring_shadow_reg_area,
1973                                     qdev->rx_ring_shadow_reg_dma);
1974                 qdev->rx_ring_shadow_reg_area = NULL;
1975         }
1976         if (qdev->tx_ring_shadow_reg_area) {
1977                 pci_free_consistent(qdev->pdev,
1978                                     PAGE_SIZE,
1979                                     qdev->tx_ring_shadow_reg_area,
1980                                     qdev->tx_ring_shadow_reg_dma);
1981                 qdev->tx_ring_shadow_reg_area = NULL;
1982         }
1983 }
1984
1985 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1986 {
1987         qdev->rx_ring_shadow_reg_area =
1988             pci_alloc_consistent(qdev->pdev,
1989                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1990         if (qdev->rx_ring_shadow_reg_area == NULL) {
1991                 QPRINTK(qdev, IFUP, ERR,
1992                         "Allocation of RX shadow space failed.\n");
1993                 return -ENOMEM;
1994         }
1995         qdev->tx_ring_shadow_reg_area =
1996             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
1997                                  &qdev->tx_ring_shadow_reg_dma);
1998         if (qdev->tx_ring_shadow_reg_area == NULL) {
1999                 QPRINTK(qdev, IFUP, ERR,
2000                         "Allocation of TX shadow space failed.\n");
2001                 goto err_wqp_sh_area;
2002         }
2003         return 0;
2004
2005 err_wqp_sh_area:
2006         pci_free_consistent(qdev->pdev,
2007                             PAGE_SIZE,
2008                             qdev->rx_ring_shadow_reg_area,
2009                             qdev->rx_ring_shadow_reg_dma);
2010         return -ENOMEM;
2011 }
2012
2013 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2014 {
2015         struct tx_ring_desc *tx_ring_desc;
2016         int i;
2017         struct ob_mac_iocb_req *mac_iocb_ptr;
2018
2019         mac_iocb_ptr = tx_ring->wq_base;
2020         tx_ring_desc = tx_ring->q;
2021         for (i = 0; i < tx_ring->wq_len; i++) {
2022                 tx_ring_desc->index = i;
2023                 tx_ring_desc->skb = NULL;
2024                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2025                 mac_iocb_ptr++;
2026                 tx_ring_desc++;
2027         }
2028         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2029         atomic_set(&tx_ring->queue_stopped, 0);
2030 }
2031
2032 static void ql_free_tx_resources(struct ql_adapter *qdev,
2033                                  struct tx_ring *tx_ring)
2034 {
2035         if (tx_ring->wq_base) {
2036                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2037                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2038                 tx_ring->wq_base = NULL;
2039         }
2040         kfree(tx_ring->q);
2041         tx_ring->q = NULL;
2042 }
2043
2044 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2045                                  struct tx_ring *tx_ring)
2046 {
2047         tx_ring->wq_base =
2048             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2049                                  &tx_ring->wq_base_dma);
2050
2051         if ((tx_ring->wq_base == NULL)
2052             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2053                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2054                 return -ENOMEM;
2055         }
2056         tx_ring->q =
2057             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2058         if (tx_ring->q == NULL)
2059                 goto err;
2060
2061         return 0;
2062 err:
2063         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2064                             tx_ring->wq_base, tx_ring->wq_base_dma);
2065         return -ENOMEM;
2066 }
2067
2068 void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2069 {
2070         int i;
2071         struct bq_desc *lbq_desc;
2072
2073         for (i = 0; i < rx_ring->lbq_len; i++) {
2074                 lbq_desc = &rx_ring->lbq[i];
2075                 if (lbq_desc->p.lbq_page) {
2076                         pci_unmap_page(qdev->pdev,
2077                                        pci_unmap_addr(lbq_desc, mapaddr),
2078                                        pci_unmap_len(lbq_desc, maplen),
2079                                        PCI_DMA_FROMDEVICE);
2080
2081                         put_page(lbq_desc->p.lbq_page);
2082                         lbq_desc->p.lbq_page = NULL;
2083                 }
2084                 lbq_desc->bq->addr_lo = 0;
2085                 lbq_desc->bq->addr_hi = 0;
2086         }
2087 }
2088
2089 /*
2090  * Allocate and map a page for each element of the lbq.
2091  */
2092 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2093                                 struct rx_ring *rx_ring)
2094 {
2095         int i;
2096         struct bq_desc *lbq_desc;
2097         u64 map;
2098         struct bq_element *bq = rx_ring->lbq_base;
2099
2100         for (i = 0; i < rx_ring->lbq_len; i++) {
2101                 lbq_desc = &rx_ring->lbq[i];
2102                 memset(lbq_desc, 0, sizeof(lbq_desc));
2103                 lbq_desc->bq = bq;
2104                 lbq_desc->index = i;
2105                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2106                 if (unlikely(!lbq_desc->p.lbq_page)) {
2107                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2108                         goto mem_error;
2109                 } else {
2110                         map = pci_map_page(qdev->pdev,
2111                                            lbq_desc->p.lbq_page,
2112                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2113                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2114                                 QPRINTK(qdev, IFUP, ERR,
2115                                         "PCI mapping failed.\n");
2116                                 goto mem_error;
2117                         }
2118                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2119                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2120                         bq->addr_lo = cpu_to_le32(map);
2121                         bq->addr_hi = cpu_to_le32(map >> 32);
2122                 }
2123                 bq++;
2124         }
2125         return 0;
2126 mem_error:
2127         ql_free_lbq_buffers(qdev, rx_ring);
2128         return -ENOMEM;
2129 }
2130
2131 void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2132 {
2133         int i;
2134         struct bq_desc *sbq_desc;
2135
2136         for (i = 0; i < rx_ring->sbq_len; i++) {
2137                 sbq_desc = &rx_ring->sbq[i];
2138                 if (sbq_desc == NULL) {
2139                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2140                         return;
2141                 }
2142                 if (sbq_desc->p.skb) {
2143                         pci_unmap_single(qdev->pdev,
2144                                          pci_unmap_addr(sbq_desc, mapaddr),
2145                                          pci_unmap_len(sbq_desc, maplen),
2146                                          PCI_DMA_FROMDEVICE);
2147                         dev_kfree_skb(sbq_desc->p.skb);
2148                         sbq_desc->p.skb = NULL;
2149                 }
2150                 if (sbq_desc->bq == NULL) {
2151                         QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2152                                 i);
2153                         return;
2154                 }
2155                 sbq_desc->bq->addr_lo = 0;
2156                 sbq_desc->bq->addr_hi = 0;
2157         }
2158 }
2159
2160 /* Allocate and map an skb for each element of the sbq. */
2161 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2162                                 struct rx_ring *rx_ring)
2163 {
2164         int i;
2165         struct bq_desc *sbq_desc;
2166         struct sk_buff *skb;
2167         u64 map;
2168         struct bq_element *bq = rx_ring->sbq_base;
2169
2170         for (i = 0; i < rx_ring->sbq_len; i++) {
2171                 sbq_desc = &rx_ring->sbq[i];
2172                 memset(sbq_desc, 0, sizeof(sbq_desc));
2173                 sbq_desc->index = i;
2174                 sbq_desc->bq = bq;
2175                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2176                 if (unlikely(!skb)) {
2177                         /* Better luck next round */
2178                         QPRINTK(qdev, IFUP, ERR,
2179                                 "small buff alloc failed for %d bytes at index %d.\n",
2180                                 rx_ring->sbq_buf_size, i);
2181                         goto mem_err;
2182                 }
2183                 skb_reserve(skb, QLGE_SB_PAD);
2184                 sbq_desc->p.skb = skb;
2185                 /*
2186                  * Map only half the buffer. Because the
2187                  * other half may get some data copied to it
2188                  * when the completion arrives.
2189                  */
2190                 map = pci_map_single(qdev->pdev,
2191                                      skb->data,
2192                                      rx_ring->sbq_buf_size / 2,
2193                                      PCI_DMA_FROMDEVICE);
2194                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2195                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2196                         goto mem_err;
2197                 }
2198                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2199                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2200                 bq->addr_lo =   /*sbq_desc->addr_lo = */
2201                     cpu_to_le32(map);
2202                 bq->addr_hi =   /*sbq_desc->addr_hi = */
2203                     cpu_to_le32(map >> 32);
2204                 bq++;
2205         }
2206         return 0;
2207 mem_err:
2208         ql_free_sbq_buffers(qdev, rx_ring);
2209         return -ENOMEM;
2210 }
2211
2212 static void ql_free_rx_resources(struct ql_adapter *qdev,
2213                                  struct rx_ring *rx_ring)
2214 {
2215         if (rx_ring->sbq_len)
2216                 ql_free_sbq_buffers(qdev, rx_ring);
2217         if (rx_ring->lbq_len)
2218                 ql_free_lbq_buffers(qdev, rx_ring);
2219
2220         /* Free the small buffer queue. */
2221         if (rx_ring->sbq_base) {
2222                 pci_free_consistent(qdev->pdev,
2223                                     rx_ring->sbq_size,
2224                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2225                 rx_ring->sbq_base = NULL;
2226         }
2227
2228         /* Free the small buffer queue control blocks. */
2229         kfree(rx_ring->sbq);
2230         rx_ring->sbq = NULL;
2231
2232         /* Free the large buffer queue. */
2233         if (rx_ring->lbq_base) {
2234                 pci_free_consistent(qdev->pdev,
2235                                     rx_ring->lbq_size,
2236                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2237                 rx_ring->lbq_base = NULL;
2238         }
2239
2240         /* Free the large buffer queue control blocks. */
2241         kfree(rx_ring->lbq);
2242         rx_ring->lbq = NULL;
2243
2244         /* Free the rx queue. */
2245         if (rx_ring->cq_base) {
2246                 pci_free_consistent(qdev->pdev,
2247                                     rx_ring->cq_size,
2248                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2249                 rx_ring->cq_base = NULL;
2250         }
2251 }
2252
2253 /* Allocate queues and buffers for this completions queue based
2254  * on the values in the parameter structure. */
2255 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2256                                  struct rx_ring *rx_ring)
2257 {
2258
2259         /*
2260          * Allocate the completion queue for this rx_ring.
2261          */
2262         rx_ring->cq_base =
2263             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2264                                  &rx_ring->cq_base_dma);
2265
2266         if (rx_ring->cq_base == NULL) {
2267                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2268                 return -ENOMEM;
2269         }
2270
2271         if (rx_ring->sbq_len) {
2272                 /*
2273                  * Allocate small buffer queue.
2274                  */
2275                 rx_ring->sbq_base =
2276                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2277                                          &rx_ring->sbq_base_dma);
2278
2279                 if (rx_ring->sbq_base == NULL) {
2280                         QPRINTK(qdev, IFUP, ERR,
2281                                 "Small buffer queue allocation failed.\n");
2282                         goto err_mem;
2283                 }
2284
2285                 /*
2286                  * Allocate small buffer queue control blocks.
2287                  */
2288                 rx_ring->sbq =
2289                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2290                             GFP_KERNEL);
2291                 if (rx_ring->sbq == NULL) {
2292                         QPRINTK(qdev, IFUP, ERR,
2293                                 "Small buffer queue control block allocation failed.\n");
2294                         goto err_mem;
2295                 }
2296
2297                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2298                         QPRINTK(qdev, IFUP, ERR,
2299                                 "Small buffer allocation failed.\n");
2300                         goto err_mem;
2301                 }
2302         }
2303
2304         if (rx_ring->lbq_len) {
2305                 /*
2306                  * Allocate large buffer queue.
2307                  */
2308                 rx_ring->lbq_base =
2309                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2310                                          &rx_ring->lbq_base_dma);
2311
2312                 if (rx_ring->lbq_base == NULL) {
2313                         QPRINTK(qdev, IFUP, ERR,
2314                                 "Large buffer queue allocation failed.\n");
2315                         goto err_mem;
2316                 }
2317                 /*
2318                  * Allocate large buffer queue control blocks.
2319                  */
2320                 rx_ring->lbq =
2321                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2322                             GFP_KERNEL);
2323                 if (rx_ring->lbq == NULL) {
2324                         QPRINTK(qdev, IFUP, ERR,
2325                                 "Large buffer queue control block allocation failed.\n");
2326                         goto err_mem;
2327                 }
2328
2329                 /*
2330                  * Allocate the buffers.
2331                  */
2332                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2333                         QPRINTK(qdev, IFUP, ERR,
2334                                 "Large buffer allocation failed.\n");
2335                         goto err_mem;
2336                 }
2337         }
2338
2339         return 0;
2340
2341 err_mem:
2342         ql_free_rx_resources(qdev, rx_ring);
2343         return -ENOMEM;
2344 }
2345
2346 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2347 {
2348         struct tx_ring *tx_ring;
2349         struct tx_ring_desc *tx_ring_desc;
2350         int i, j;
2351
2352         /*
2353          * Loop through all queues and free
2354          * any resources.
2355          */
2356         for (j = 0; j < qdev->tx_ring_count; j++) {
2357                 tx_ring = &qdev->tx_ring[j];
2358                 for (i = 0; i < tx_ring->wq_len; i++) {
2359                         tx_ring_desc = &tx_ring->q[i];
2360                         if (tx_ring_desc && tx_ring_desc->skb) {
2361                                 QPRINTK(qdev, IFDOWN, ERR,
2362                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2363                                         tx_ring_desc->skb, j,
2364                                         tx_ring_desc->index);
2365                                 ql_unmap_send(qdev, tx_ring_desc,
2366                                               tx_ring_desc->map_cnt);
2367                                 dev_kfree_skb(tx_ring_desc->skb);
2368                                 tx_ring_desc->skb = NULL;
2369                         }
2370                 }
2371         }
2372 }
2373
2374 static void ql_free_ring_cb(struct ql_adapter *qdev)
2375 {
2376         kfree(qdev->ring_mem);
2377 }
2378
2379 static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2380 {
2381         /* Allocate space for tx/rx ring control blocks. */
2382         qdev->ring_mem_size =
2383             (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2384             (qdev->rx_ring_count * sizeof(struct rx_ring));
2385         qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2386         if (qdev->ring_mem == NULL) {
2387                 return -ENOMEM;
2388         } else {
2389                 qdev->rx_ring = qdev->ring_mem;
2390                 qdev->tx_ring = qdev->ring_mem +
2391                     (qdev->rx_ring_count * sizeof(struct rx_ring));
2392         }
2393         return 0;
2394 }
2395
2396 static void ql_free_mem_resources(struct ql_adapter *qdev)
2397 {
2398         int i;
2399
2400         for (i = 0; i < qdev->tx_ring_count; i++)
2401                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2402         for (i = 0; i < qdev->rx_ring_count; i++)
2403                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2404         ql_free_shadow_space(qdev);
2405 }
2406
2407 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2408 {
2409         int i;
2410
2411         /* Allocate space for our shadow registers and such. */
2412         if (ql_alloc_shadow_space(qdev))
2413                 return -ENOMEM;
2414
2415         for (i = 0; i < qdev->rx_ring_count; i++) {
2416                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2417                         QPRINTK(qdev, IFUP, ERR,
2418                                 "RX resource allocation failed.\n");
2419                         goto err_mem;
2420                 }
2421         }
2422         /* Allocate tx queue resources */
2423         for (i = 0; i < qdev->tx_ring_count; i++) {
2424                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2425                         QPRINTK(qdev, IFUP, ERR,
2426                                 "TX resource allocation failed.\n");
2427                         goto err_mem;
2428                 }
2429         }
2430         return 0;
2431
2432 err_mem:
2433         ql_free_mem_resources(qdev);
2434         return -ENOMEM;
2435 }
2436
2437 /* Set up the rx ring control block and pass it to the chip.
2438  * The control block is defined as
2439  * "Completion Queue Initialization Control Block", or cqicb.
2440  */
2441 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2442 {
2443         struct cqicb *cqicb = &rx_ring->cqicb;
2444         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2445             (rx_ring->cq_id * sizeof(u64) * 4);
2446         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2447             (rx_ring->cq_id * sizeof(u64) * 4);
2448         void __iomem *doorbell_area =
2449             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2450         int err = 0;
2451         u16 bq_len;
2452
2453         /* Set up the shadow registers for this ring. */
2454         rx_ring->prod_idx_sh_reg = shadow_reg;
2455         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2456         shadow_reg += sizeof(u64);
2457         shadow_reg_dma += sizeof(u64);
2458         rx_ring->lbq_base_indirect = shadow_reg;
2459         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2460         shadow_reg += sizeof(u64);
2461         shadow_reg_dma += sizeof(u64);
2462         rx_ring->sbq_base_indirect = shadow_reg;
2463         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2464
2465         /* PCI doorbell mem area + 0x00 for consumer index register */
2466         rx_ring->cnsmr_idx_db_reg = (u32 *) doorbell_area;
2467         rx_ring->cnsmr_idx = 0;
2468         rx_ring->curr_entry = rx_ring->cq_base;
2469
2470         /* PCI doorbell mem area + 0x04 for valid register */
2471         rx_ring->valid_db_reg = doorbell_area + 0x04;
2472
2473         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2474         rx_ring->lbq_prod_idx_db_reg = (u32 *) (doorbell_area + 0x18);
2475
2476         /* PCI doorbell mem area + 0x1c */
2477         rx_ring->sbq_prod_idx_db_reg = (u32 *) (doorbell_area + 0x1c);
2478
2479         memset((void *)cqicb, 0, sizeof(struct cqicb));
2480         cqicb->msix_vect = rx_ring->irq;
2481
2482         cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
2483
2484         cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2485         cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2486
2487         cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2488         cqicb->prod_idx_addr_hi =
2489             cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2490
2491         /*
2492          * Set up the control block load flags.
2493          */
2494         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2495             FLAGS_LV |          /* Load MSI-X vector */
2496             FLAGS_LI;           /* Load irq delay values */
2497         if (rx_ring->lbq_len) {
2498                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2499                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2500                 cqicb->lbq_addr_lo =
2501                     cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2502                 cqicb->lbq_addr_hi =
2503                     cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
2504                 cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
2505                 bq_len = (u16) rx_ring->lbq_len;
2506                 cqicb->lbq_len = cpu_to_le16(bq_len);
2507                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2508                 rx_ring->lbq_curr_idx = 0;
2509                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2510                 rx_ring->lbq_free_cnt = 16;
2511         }
2512         if (rx_ring->sbq_len) {
2513                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2514                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2515                 cqicb->sbq_addr_lo =
2516                     cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2517                 cqicb->sbq_addr_hi =
2518                     cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2519                 cqicb->sbq_buf_size =
2520                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2521                 bq_len = (u16) rx_ring->sbq_len;
2522                 cqicb->sbq_len = cpu_to_le16(bq_len);
2523                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2524                 rx_ring->sbq_curr_idx = 0;
2525                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2526                 rx_ring->sbq_free_cnt = 16;
2527         }
2528         switch (rx_ring->type) {
2529         case TX_Q:
2530                 /* If there's only one interrupt, then we use
2531                  * worker threads to process the outbound
2532                  * completion handling rx_rings. We do this so
2533                  * they can be run on multiple CPUs. There is
2534                  * room to play with this more where we would only
2535                  * run in a worker if there are more than x number
2536                  * of outbound completions on the queue and more
2537                  * than one queue active.  Some threshold that
2538                  * would indicate a benefit in spite of the cost
2539                  * of a context switch.
2540                  * If there's more than one interrupt, then the
2541                  * outbound completions are processed in the ISR.
2542                  */
2543                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2544                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2545                 else {
2546                         /* With all debug warnings on we see a WARN_ON message
2547                          * when we free the skb in the interrupt context.
2548                          */
2549                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2550                 }
2551                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2552                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2553                 break;
2554         case DEFAULT_Q:
2555                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2556                 cqicb->irq_delay = 0;
2557                 cqicb->pkt_delay = 0;
2558                 break;
2559         case RX_Q:
2560                 /* Inbound completion handling rx_rings run in
2561                  * separate NAPI contexts.
2562                  */
2563                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2564                                64);
2565                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2566                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2567                 break;
2568         default:
2569                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2570                         rx_ring->type);
2571         }
2572         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2573         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2574                            CFG_LCQ, rx_ring->cq_id);
2575         if (err) {
2576                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2577                 return err;
2578         }
2579         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2580         /*
2581          * Advance the producer index for the buffer queues.
2582          */
2583         wmb();
2584         if (rx_ring->lbq_len)
2585                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2586                                 rx_ring->lbq_prod_idx_db_reg);
2587         if (rx_ring->sbq_len)
2588                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2589                                 rx_ring->sbq_prod_idx_db_reg);
2590         return err;
2591 }
2592
2593 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2594 {
2595         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2596         void __iomem *doorbell_area =
2597             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2598         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2599             (tx_ring->wq_id * sizeof(u64));
2600         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2601             (tx_ring->wq_id * sizeof(u64));
2602         int err = 0;
2603
2604         /*
2605          * Assign doorbell registers for this tx_ring.
2606          */
2607         /* TX PCI doorbell mem area for tx producer index */
2608         tx_ring->prod_idx_db_reg = (u32 *) doorbell_area;
2609         tx_ring->prod_idx = 0;
2610         /* TX PCI doorbell mem area + 0x04 */
2611         tx_ring->valid_db_reg = doorbell_area + 0x04;
2612
2613         /*
2614          * Assign shadow registers for this tx_ring.
2615          */
2616         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2617         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2618
2619         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2620         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2621                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2622         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2623         wqicb->rid = 0;
2624         wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2625         wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2626
2627         wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2628         wqicb->cnsmr_idx_addr_hi =
2629             cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2630
2631         ql_init_tx_ring(qdev, tx_ring);
2632
2633         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2634                            (u16) tx_ring->wq_id);
2635         if (err) {
2636                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2637                 return err;
2638         }
2639         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2640         return err;
2641 }
2642
2643 static void ql_disable_msix(struct ql_adapter *qdev)
2644 {
2645         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2646                 pci_disable_msix(qdev->pdev);
2647                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2648                 kfree(qdev->msi_x_entry);
2649                 qdev->msi_x_entry = NULL;
2650         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2651                 pci_disable_msi(qdev->pdev);
2652                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2653         }
2654 }
2655
2656 static void ql_enable_msix(struct ql_adapter *qdev)
2657 {
2658         int i;
2659
2660         qdev->intr_count = 1;
2661         /* Get the MSIX vectors. */
2662         if (irq_type == MSIX_IRQ) {
2663                 /* Try to alloc space for the msix struct,
2664                  * if it fails then go to MSI/legacy.
2665                  */
2666                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2667                                             sizeof(struct msix_entry),
2668                                             GFP_KERNEL);
2669                 if (!qdev->msi_x_entry) {
2670                         irq_type = MSI_IRQ;
2671                         goto msi;
2672                 }
2673
2674                 for (i = 0; i < qdev->rx_ring_count; i++)
2675                         qdev->msi_x_entry[i].entry = i;
2676
2677                 if (!pci_enable_msix
2678                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2679                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2680                         qdev->intr_count = qdev->rx_ring_count;
2681                         QPRINTK(qdev, IFUP, INFO,
2682                                 "MSI-X Enabled, got %d vectors.\n",
2683                                 qdev->intr_count);
2684                         return;
2685                 } else {
2686                         kfree(qdev->msi_x_entry);
2687                         qdev->msi_x_entry = NULL;
2688                         QPRINTK(qdev, IFUP, WARNING,
2689                                 "MSI-X Enable failed, trying MSI.\n");
2690                         irq_type = MSI_IRQ;
2691                 }
2692         }
2693 msi:
2694         if (irq_type == MSI_IRQ) {
2695                 if (!pci_enable_msi(qdev->pdev)) {
2696                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2697                         QPRINTK(qdev, IFUP, INFO,
2698                                 "Running with MSI interrupts.\n");
2699                         return;
2700                 }
2701         }
2702         irq_type = LEG_IRQ;
2703         spin_lock_init(&qdev->legacy_lock);
2704         qdev->legacy_check = ql_legacy_check;
2705         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2706 }
2707
2708 /*
2709  * Here we build the intr_context structures based on
2710  * our rx_ring count and intr vector count.
2711  * The intr_context structure is used to hook each vector
2712  * to possibly different handlers.
2713  */
2714 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2715 {
2716         int i = 0;
2717         struct intr_context *intr_context = &qdev->intr_context[0];
2718
2719         ql_enable_msix(qdev);
2720
2721         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2722                 /* Each rx_ring has it's
2723                  * own intr_context since we have separate
2724                  * vectors for each queue.
2725                  * This only true when MSI-X is enabled.
2726                  */
2727                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2728                         qdev->rx_ring[i].irq = i;
2729                         intr_context->intr = i;
2730                         intr_context->qdev = qdev;
2731                         /*
2732                          * We set up each vectors enable/disable/read bits so
2733                          * there's no bit/mask calculations in the critical path.
2734                          */
2735                         intr_context->intr_en_mask =
2736                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2737                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2738                             | i;
2739                         intr_context->intr_dis_mask =
2740                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2741                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2742                             INTR_EN_IHD | i;
2743                         intr_context->intr_read_mask =
2744                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2745                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2746                             i;
2747
2748                         if (i == 0) {
2749                                 /*
2750                                  * Default queue handles bcast/mcast plus
2751                                  * async events.  Needs buffers.
2752                                  */
2753                                 intr_context->handler = qlge_isr;
2754                                 sprintf(intr_context->name, "%s-default-queue",
2755                                         qdev->ndev->name);
2756                         } else if (i < qdev->rss_ring_first_cq_id) {
2757                                 /*
2758                                  * Outbound queue is for outbound completions only.
2759                                  */
2760                                 intr_context->handler = qlge_msix_tx_isr;
2761                                 sprintf(intr_context->name, "%s-txq-%d",
2762                                         qdev->ndev->name, i);
2763                         } else {
2764                                 /*
2765                                  * Inbound queues handle unicast frames only.
2766                                  */
2767                                 intr_context->handler = qlge_msix_rx_isr;
2768                                 sprintf(intr_context->name, "%s-rxq-%d",
2769                                         qdev->ndev->name, i);
2770                         }
2771                 }
2772         } else {
2773                 /*
2774                  * All rx_rings use the same intr_context since
2775                  * there is only one vector.
2776                  */
2777                 intr_context->intr = 0;
2778                 intr_context->qdev = qdev;
2779                 /*
2780                  * We set up each vectors enable/disable/read bits so
2781                  * there's no bit/mask calculations in the critical path.
2782                  */
2783                 intr_context->intr_en_mask =
2784                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2785                 intr_context->intr_dis_mask =
2786                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2787                     INTR_EN_TYPE_DISABLE;
2788                 intr_context->intr_read_mask =
2789                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2790                 /*
2791                  * Single interrupt means one handler for all rings.
2792                  */
2793                 intr_context->handler = qlge_isr;
2794                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2795                 for (i = 0; i < qdev->rx_ring_count; i++)
2796                         qdev->rx_ring[i].irq = 0;
2797         }
2798 }
2799
2800 static void ql_free_irq(struct ql_adapter *qdev)
2801 {
2802         int i;
2803         struct intr_context *intr_context = &qdev->intr_context[0];
2804
2805         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2806                 if (intr_context->hooked) {
2807                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2808                                 free_irq(qdev->msi_x_entry[i].vector,
2809                                          &qdev->rx_ring[i]);
2810                                 QPRINTK(qdev, IFDOWN, ERR,
2811                                         "freeing msix interrupt %d.\n", i);
2812                         } else {
2813                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2814                                 QPRINTK(qdev, IFDOWN, ERR,
2815                                         "freeing msi interrupt %d.\n", i);
2816                         }
2817                 }
2818         }
2819         ql_disable_msix(qdev);
2820 }
2821
2822 static int ql_request_irq(struct ql_adapter *qdev)
2823 {
2824         int i;
2825         int status = 0;
2826         struct pci_dev *pdev = qdev->pdev;
2827         struct intr_context *intr_context = &qdev->intr_context[0];
2828
2829         ql_resolve_queues_to_irqs(qdev);
2830
2831         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2832                 atomic_set(&intr_context->irq_cnt, 0);
2833                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2834                         status = request_irq(qdev->msi_x_entry[i].vector,
2835                                              intr_context->handler,
2836                                              0,
2837                                              intr_context->name,
2838                                              &qdev->rx_ring[i]);
2839                         if (status) {
2840                                 QPRINTK(qdev, IFUP, ERR,
2841                                         "Failed request for MSIX interrupt %d.\n",
2842                                         i);
2843                                 goto err_irq;
2844                         } else {
2845                                 QPRINTK(qdev, IFUP, INFO,
2846                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2847                                         i,
2848                                         qdev->rx_ring[i].type ==
2849                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2850                                         qdev->rx_ring[i].type ==
2851                                         TX_Q ? "TX_Q" : "",
2852                                         qdev->rx_ring[i].type ==
2853                                         RX_Q ? "RX_Q" : "", intr_context->name);
2854                         }
2855                 } else {
2856                         QPRINTK(qdev, IFUP, DEBUG,
2857                                 "trying msi or legacy interrupts.\n");
2858                         QPRINTK(qdev, IFUP, DEBUG,
2859                                 "%s: irq = %d.\n", __func__, pdev->irq);
2860                         QPRINTK(qdev, IFUP, DEBUG,
2861                                 "%s: context->name = %s.\n", __func__,
2862                                intr_context->name);
2863                         QPRINTK(qdev, IFUP, DEBUG,
2864                                 "%s: dev_id = 0x%p.\n", __func__,
2865                                &qdev->rx_ring[0]);
2866                         status =
2867                             request_irq(pdev->irq, qlge_isr,
2868                                         test_bit(QL_MSI_ENABLED,
2869                                                  &qdev->
2870                                                  flags) ? 0 : IRQF_SHARED,
2871                                         intr_context->name, &qdev->rx_ring[0]);
2872                         if (status)
2873                                 goto err_irq;
2874
2875                         QPRINTK(qdev, IFUP, ERR,
2876                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2877                                 i,
2878                                 qdev->rx_ring[0].type ==
2879                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2880                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2881                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2882                                 intr_context->name);
2883                 }
2884                 intr_context->hooked = 1;
2885         }
2886         return status;
2887 err_irq:
2888         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2889         ql_free_irq(qdev);
2890         return status;
2891 }
2892
2893 static int ql_start_rss(struct ql_adapter *qdev)
2894 {
2895         struct ricb *ricb = &qdev->ricb;
2896         int status = 0;
2897         int i;
2898         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2899
2900         memset((void *)ricb, 0, sizeof(ricb));
2901
2902         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2903         ricb->flags =
2904             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2905              RSS_RT6);
2906         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2907
2908         /*
2909          * Fill out the Indirection Table.
2910          */
2911         for (i = 0; i < 32; i++)
2912                 hash_id[i] = i & 1;
2913
2914         /*
2915          * Random values for the IPv6 and IPv4 Hash Keys.
2916          */
2917         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2918         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2919
2920         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2921
2922         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2923         if (status) {
2924                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2925                 return status;
2926         }
2927         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2928         return status;
2929 }
2930
2931 /* Initialize the frame-to-queue routing. */
2932 static int ql_route_initialize(struct ql_adapter *qdev)
2933 {
2934         int status = 0;
2935         int i;
2936
2937         /* Clear all the entries in the routing table. */
2938         for (i = 0; i < 16; i++) {
2939                 status = ql_set_routing_reg(qdev, i, 0, 0);
2940                 if (status) {
2941                         QPRINTK(qdev, IFUP, ERR,
2942                                 "Failed to init routing register for CAM packets.\n");
2943                         return status;
2944                 }
2945         }
2946
2947         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2948         if (status) {
2949                 QPRINTK(qdev, IFUP, ERR,
2950                         "Failed to init routing register for error packets.\n");
2951                 return status;
2952         }
2953         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2954         if (status) {
2955                 QPRINTK(qdev, IFUP, ERR,
2956                         "Failed to init routing register for broadcast packets.\n");
2957                 return status;
2958         }
2959         /* If we have more than one inbound queue, then turn on RSS in the
2960          * routing block.
2961          */
2962         if (qdev->rss_ring_count > 1) {
2963                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2964                                         RT_IDX_RSS_MATCH, 1);
2965                 if (status) {
2966                         QPRINTK(qdev, IFUP, ERR,
2967                                 "Failed to init routing register for MATCH RSS packets.\n");
2968                         return status;
2969                 }
2970         }
2971
2972         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2973                                     RT_IDX_CAM_HIT, 1);
2974         if (status) {
2975                 QPRINTK(qdev, IFUP, ERR,
2976                         "Failed to init routing register for CAM packets.\n");
2977                 return status;
2978         }
2979         return status;
2980 }
2981
2982 static int ql_adapter_initialize(struct ql_adapter *qdev)
2983 {
2984         u32 value, mask;
2985         int i;
2986         int status = 0;
2987
2988         /*
2989          * Set up the System register to halt on errors.
2990          */
2991         value = SYS_EFE | SYS_FAE;
2992         mask = value << 16;
2993         ql_write32(qdev, SYS, mask | value);
2994
2995         /* Set the default queue. */
2996         value = NIC_RCV_CFG_DFQ;
2997         mask = NIC_RCV_CFG_DFQ_MASK;
2998         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2999
3000         /* Set the MPI interrupt to enabled. */
3001         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3002
3003         /* Enable the function, set pagesize, enable error checking. */
3004         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3005             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3006
3007         /* Set/clear header splitting. */
3008         mask = FSC_VM_PAGESIZE_MASK |
3009             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3010         ql_write32(qdev, FSC, mask | value);
3011
3012         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3013                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3014
3015         /* Start up the rx queues. */
3016         for (i = 0; i < qdev->rx_ring_count; i++) {
3017                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3018                 if (status) {
3019                         QPRINTK(qdev, IFUP, ERR,
3020                                 "Failed to start rx ring[%d].\n", i);
3021                         return status;
3022                 }
3023         }
3024
3025         /* If there is more than one inbound completion queue
3026          * then download a RICB to configure RSS.
3027          */
3028         if (qdev->rss_ring_count > 1) {
3029                 status = ql_start_rss(qdev);
3030                 if (status) {
3031                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3032                         return status;
3033                 }
3034         }
3035
3036         /* Start up the tx queues. */
3037         for (i = 0; i < qdev->tx_ring_count; i++) {
3038                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3039                 if (status) {
3040                         QPRINTK(qdev, IFUP, ERR,
3041                                 "Failed to start tx ring[%d].\n", i);
3042                         return status;
3043                 }
3044         }
3045
3046         status = ql_port_initialize(qdev);
3047         if (status) {
3048                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3049                 return status;
3050         }
3051
3052         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3053                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3054         if (status) {
3055                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3056                 return status;
3057         }
3058
3059         status = ql_route_initialize(qdev);
3060         if (status) {
3061                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3062                 return status;
3063         }
3064
3065         /* Start NAPI for the RSS queues. */
3066         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3067                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3068                         i);
3069                 napi_enable(&qdev->rx_ring[i].napi);
3070         }
3071
3072         return status;
3073 }
3074
3075 /* Issue soft reset to chip. */
3076 static int ql_adapter_reset(struct ql_adapter *qdev)
3077 {
3078         u32 value;
3079         int max_wait_time;
3080         int status = 0;
3081         int resetCnt = 0;
3082
3083 #define MAX_RESET_CNT   1
3084 issueReset:
3085         resetCnt++;
3086         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3087         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3088         /* Wait for reset to complete. */
3089         max_wait_time = 3;
3090         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3091                 max_wait_time);
3092         do {
3093                 value = ql_read32(qdev, RST_FO);
3094                 if ((value & RST_FO_FR) == 0)
3095                         break;
3096
3097                 ssleep(1);
3098         } while ((--max_wait_time));
3099         if (value & RST_FO_FR) {
3100                 QPRINTK(qdev, IFDOWN, ERR,
3101                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3102                 if (resetCnt < MAX_RESET_CNT)
3103                         goto issueReset;
3104         }
3105         if (max_wait_time == 0) {
3106                 status = -ETIMEDOUT;
3107                 QPRINTK(qdev, IFDOWN, ERR,
3108                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3109         }
3110
3111         return status;
3112 }
3113
3114 static void ql_display_dev_info(struct net_device *ndev)
3115 {
3116         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3117
3118         QPRINTK(qdev, PROBE, INFO,
3119                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3120                 "XG Roll = %d, XG Rev = %d.\n",
3121                 qdev->func,
3122                 qdev->chip_rev_id & 0x0000000f,
3123                 qdev->chip_rev_id >> 4 & 0x0000000f,
3124                 qdev->chip_rev_id >> 8 & 0x0000000f,
3125                 qdev->chip_rev_id >> 12 & 0x0000000f);
3126         QPRINTK(qdev, PROBE, INFO,
3127                 "MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3128                 ndev->dev_addr[0], ndev->dev_addr[1],
3129                 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3130                 ndev->dev_addr[5]);
3131 }
3132
3133 static int ql_adapter_down(struct ql_adapter *qdev)
3134 {
3135         struct net_device *ndev = qdev->ndev;
3136         int i, status = 0;
3137         struct rx_ring *rx_ring;
3138
3139         netif_stop_queue(ndev);
3140         netif_carrier_off(ndev);
3141
3142         cancel_delayed_work_sync(&qdev->asic_reset_work);
3143         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3144         cancel_delayed_work_sync(&qdev->mpi_work);
3145
3146         /* The default queue at index 0 is always processed in
3147          * a workqueue.
3148          */
3149         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3150
3151         /* The rest of the rx_rings are processed in
3152          * a workqueue only if it's a single interrupt
3153          * environment (MSI/Legacy).
3154          */
3155         for (i = 1; i > qdev->rx_ring_count; i++) {
3156                 rx_ring = &qdev->rx_ring[i];
3157                 /* Only the RSS rings use NAPI on multi irq
3158                  * environment.  Outbound completion processing
3159                  * is done in interrupt context.
3160                  */
3161                 if (i >= qdev->rss_ring_first_cq_id) {
3162                         napi_disable(&rx_ring->napi);
3163                 } else {
3164                         cancel_delayed_work_sync(&rx_ring->rx_work);
3165                 }
3166         }
3167
3168         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3169
3170         ql_disable_interrupts(qdev);
3171
3172         ql_tx_ring_clean(qdev);
3173
3174         spin_lock(&qdev->hw_lock);
3175         status = ql_adapter_reset(qdev);
3176         if (status)
3177                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3178                         qdev->func);
3179         spin_unlock(&qdev->hw_lock);
3180         return status;
3181 }
3182
3183 static int ql_adapter_up(struct ql_adapter *qdev)
3184 {
3185         int err = 0;
3186
3187         spin_lock(&qdev->hw_lock);
3188         err = ql_adapter_initialize(qdev);
3189         if (err) {
3190                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3191                 spin_unlock(&qdev->hw_lock);
3192                 goto err_init;
3193         }
3194         spin_unlock(&qdev->hw_lock);
3195         set_bit(QL_ADAPTER_UP, &qdev->flags);
3196         ql_enable_interrupts(qdev);
3197         ql_enable_all_completion_interrupts(qdev);
3198         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3199                 netif_carrier_on(qdev->ndev);
3200                 netif_start_queue(qdev->ndev);
3201         }
3202
3203         return 0;
3204 err_init:
3205         ql_adapter_reset(qdev);
3206         return err;
3207 }
3208
3209 static int ql_cycle_adapter(struct ql_adapter *qdev)
3210 {
3211         int status;
3212
3213         status = ql_adapter_down(qdev);
3214         if (status)
3215                 goto error;
3216
3217         status = ql_adapter_up(qdev);
3218         if (status)
3219                 goto error;
3220
3221         return status;
3222 error:
3223         QPRINTK(qdev, IFUP, ALERT,
3224                 "Driver up/down cycle failed, closing device\n");
3225         rtnl_lock();
3226         dev_close(qdev->ndev);
3227         rtnl_unlock();
3228         return status;
3229 }
3230
3231 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3232 {
3233         ql_free_mem_resources(qdev);
3234         ql_free_irq(qdev);
3235 }
3236
3237 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3238 {
3239         int status = 0;
3240
3241         if (ql_alloc_mem_resources(qdev)) {
3242                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3243                 return -ENOMEM;
3244         }
3245         status = ql_request_irq(qdev);
3246         if (status)
3247                 goto err_irq;
3248         return status;
3249 err_irq:
3250         ql_free_mem_resources(qdev);
3251         return status;
3252 }
3253
3254 static int qlge_close(struct net_device *ndev)
3255 {
3256         struct ql_adapter *qdev = netdev_priv(ndev);
3257
3258         /*
3259          * Wait for device to recover from a reset.
3260          * (Rarely happens, but possible.)
3261          */
3262         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3263                 msleep(1);
3264         ql_adapter_down(qdev);
3265         ql_release_adapter_resources(qdev);
3266         ql_free_ring_cb(qdev);
3267         return 0;
3268 }
3269
3270 static int ql_configure_rings(struct ql_adapter *qdev)
3271 {
3272         int i;
3273         struct rx_ring *rx_ring;
3274         struct tx_ring *tx_ring;
3275         int cpu_cnt = num_online_cpus();
3276
3277         /*
3278          * For each processor present we allocate one
3279          * rx_ring for outbound completions, and one
3280          * rx_ring for inbound completions.  Plus there is
3281          * always the one default queue.  For the CPU
3282          * counts we end up with the following rx_rings:
3283          * rx_ring count =
3284          *  one default queue +
3285          *  (CPU count * outbound completion rx_ring) +
3286          *  (CPU count * inbound (RSS) completion rx_ring)
3287          * To keep it simple we limit the total number of
3288          * queues to < 32, so we truncate CPU to 8.
3289          * This limitation can be removed when requested.
3290          */
3291
3292         if (cpu_cnt > 8)
3293                 cpu_cnt = 8;
3294
3295         /*
3296          * rx_ring[0] is always the default queue.
3297          */
3298         /* Allocate outbound completion ring for each CPU. */
3299         qdev->tx_ring_count = cpu_cnt;
3300         /* Allocate inbound completion (RSS) ring for each CPU. */
3301         qdev->rss_ring_count = cpu_cnt;
3302         /* cq_id for the first inbound ring handler. */
3303         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3304         /*
3305          * qdev->rx_ring_count:
3306          * Total number of rx_rings.  This includes the one
3307          * default queue, a number of outbound completion
3308          * handler rx_rings, and the number of inbound
3309          * completion handler rx_rings.
3310          */
3311         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3312
3313         if (ql_alloc_ring_cb(qdev))
3314                 return -ENOMEM;
3315
3316         for (i = 0; i < qdev->tx_ring_count; i++) {
3317                 tx_ring = &qdev->tx_ring[i];
3318                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3319                 tx_ring->qdev = qdev;
3320                 tx_ring->wq_id = i;
3321                 tx_ring->wq_len = qdev->tx_ring_size;
3322                 tx_ring->wq_size =
3323                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3324
3325                 /*
3326                  * The completion queue ID for the tx rings start
3327                  * immediately after the default Q ID, which is zero.
3328                  */
3329                 tx_ring->cq_id = i + 1;
3330         }
3331
3332         for (i = 0; i < qdev->rx_ring_count; i++) {
3333                 rx_ring = &qdev->rx_ring[i];
3334                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3335                 rx_ring->qdev = qdev;
3336                 rx_ring->cq_id = i;
3337                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3338                 if (i == 0) {   /* Default queue at index 0. */
3339                         /*
3340                          * Default queue handles bcast/mcast plus
3341                          * async events.  Needs buffers.
3342                          */
3343                         rx_ring->cq_len = qdev->rx_ring_size;
3344                         rx_ring->cq_size =
3345                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3346                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3347                         rx_ring->lbq_size =
3348                             rx_ring->lbq_len * sizeof(struct bq_element);
3349                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3350                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3351                         rx_ring->sbq_size =
3352                             rx_ring->sbq_len * sizeof(struct bq_element);
3353                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3354                         rx_ring->type = DEFAULT_Q;
3355                 } else if (i < qdev->rss_ring_first_cq_id) {
3356                         /*
3357                          * Outbound queue handles outbound completions only.
3358                          */
3359                         /* outbound cq is same size as tx_ring it services. */
3360                         rx_ring->cq_len = qdev->tx_ring_size;
3361                         rx_ring->cq_size =
3362                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3363                         rx_ring->lbq_len = 0;
3364                         rx_ring->lbq_size = 0;
3365                         rx_ring->lbq_buf_size = 0;
3366                         rx_ring->sbq_len = 0;
3367                         rx_ring->sbq_size = 0;
3368                         rx_ring->sbq_buf_size = 0;
3369                         rx_ring->type = TX_Q;
3370                 } else {        /* Inbound completions (RSS) queues */
3371                         /*
3372                          * Inbound queues handle unicast frames only.
3373                          */
3374                         rx_ring->cq_len = qdev->rx_ring_size;
3375                         rx_ring->cq_size =
3376                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3377                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3378                         rx_ring->lbq_size =
3379                             rx_ring->lbq_len * sizeof(struct bq_element);
3380                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3381                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3382                         rx_ring->sbq_size =
3383                             rx_ring->sbq_len * sizeof(struct bq_element);
3384                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3385                         rx_ring->type = RX_Q;
3386                 }
3387         }
3388         return 0;
3389 }
3390
3391 static int qlge_open(struct net_device *ndev)
3392 {
3393         int err = 0;
3394         struct ql_adapter *qdev = netdev_priv(ndev);
3395
3396         err = ql_configure_rings(qdev);
3397         if (err)
3398                 return err;
3399
3400         err = ql_get_adapter_resources(qdev);
3401         if (err)
3402                 goto error_up;
3403
3404         err = ql_adapter_up(qdev);
3405         if (err)
3406                 goto error_up;
3407
3408         return err;
3409
3410 error_up:
3411         ql_release_adapter_resources(qdev);
3412         ql_free_ring_cb(qdev);
3413         return err;
3414 }
3415
3416 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3417 {
3418         struct ql_adapter *qdev = netdev_priv(ndev);
3419
3420         if (ndev->mtu == 1500 && new_mtu == 9000) {
3421                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3422         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3423                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3424         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3425                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3426                 return 0;
3427         } else
3428                 return -EINVAL;
3429         ndev->mtu = new_mtu;
3430         return 0;
3431 }
3432
3433 static struct net_device_stats *qlge_get_stats(struct net_device
3434                                                *ndev)
3435 {
3436         struct ql_adapter *qdev = netdev_priv(ndev);
3437         return &qdev->stats;
3438 }
3439
3440 static void qlge_set_multicast_list(struct net_device *ndev)
3441 {
3442         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3443         struct dev_mc_list *mc_ptr;
3444         int i;
3445
3446         spin_lock(&qdev->hw_lock);
3447         /*
3448          * Set or clear promiscuous mode if a
3449          * transition is taking place.
3450          */
3451         if (ndev->flags & IFF_PROMISC) {
3452                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3453                         if (ql_set_routing_reg
3454                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3455                                 QPRINTK(qdev, HW, ERR,
3456                                         "Failed to set promiscous mode.\n");
3457                         } else {
3458                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3459                         }
3460                 }
3461         } else {
3462                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3463                         if (ql_set_routing_reg
3464                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3465                                 QPRINTK(qdev, HW, ERR,
3466                                         "Failed to clear promiscous mode.\n");
3467                         } else {
3468                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3469                         }
3470                 }
3471         }
3472
3473         /*
3474          * Set or clear all multicast mode if a
3475          * transition is taking place.
3476          */
3477         if ((ndev->flags & IFF_ALLMULTI) ||
3478             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3479                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3480                         if (ql_set_routing_reg
3481                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3482                                 QPRINTK(qdev, HW, ERR,
3483                                         "Failed to set all-multi mode.\n");
3484                         } else {
3485                                 set_bit(QL_ALLMULTI, &qdev->flags);
3486                         }
3487                 }
3488         } else {
3489                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3490                         if (ql_set_routing_reg
3491                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3492                                 QPRINTK(qdev, HW, ERR,
3493                                         "Failed to clear all-multi mode.\n");
3494                         } else {
3495                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3496                         }
3497                 }
3498         }
3499
3500         if (ndev->mc_count) {
3501                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3502                      i++, mc_ptr = mc_ptr->next)
3503                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3504                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3505                                 QPRINTK(qdev, HW, ERR,
3506                                         "Failed to loadmulticast address.\n");
3507                                 goto exit;
3508                         }
3509                 if (ql_set_routing_reg
3510                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3511                         QPRINTK(qdev, HW, ERR,
3512                                 "Failed to set multicast match mode.\n");
3513                 } else {
3514                         set_bit(QL_ALLMULTI, &qdev->flags);
3515                 }
3516         }
3517 exit:
3518         spin_unlock(&qdev->hw_lock);
3519 }
3520
3521 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3522 {
3523         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3524         struct sockaddr *addr = p;
3525
3526         if (netif_running(ndev))
3527                 return -EBUSY;
3528
3529         if (!is_valid_ether_addr(addr->sa_data))
3530                 return -EADDRNOTAVAIL;
3531         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3532
3533         spin_lock(&qdev->hw_lock);
3534         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3535                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3536                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3537                 return -1;
3538         }
3539         spin_unlock(&qdev->hw_lock);
3540
3541         return 0;
3542 }
3543
3544 static void qlge_tx_timeout(struct net_device *ndev)
3545 {
3546         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3547         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3548 }
3549
3550 static void ql_asic_reset_work(struct work_struct *work)
3551 {
3552         struct ql_adapter *qdev =
3553             container_of(work, struct ql_adapter, asic_reset_work.work);
3554         ql_cycle_adapter(qdev);
3555 }
3556
3557 static void ql_get_board_info(struct ql_adapter *qdev)
3558 {
3559         qdev->func =
3560             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3561         if (qdev->func) {
3562                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3563                 qdev->port_link_up = STS_PL1;
3564                 qdev->port_init = STS_PI1;
3565                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3566                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3567         } else {
3568                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3569                 qdev->port_link_up = STS_PL0;
3570                 qdev->port_init = STS_PI0;
3571                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3572                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3573         }
3574         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3575 }
3576
3577 static void ql_release_all(struct pci_dev *pdev)
3578 {
3579         struct net_device *ndev = pci_get_drvdata(pdev);
3580         struct ql_adapter *qdev = netdev_priv(ndev);
3581
3582         if (qdev->workqueue) {
3583                 destroy_workqueue(qdev->workqueue);
3584                 qdev->workqueue = NULL;
3585         }
3586         if (qdev->q_workqueue) {
3587                 destroy_workqueue(qdev->q_workqueue);
3588                 qdev->q_workqueue = NULL;
3589         }
3590         if (qdev->reg_base)
3591                 iounmap((void *)qdev->reg_base);
3592         if (qdev->doorbell_area)
3593                 iounmap(qdev->doorbell_area);
3594         pci_release_regions(pdev);
3595         pci_set_drvdata(pdev, NULL);
3596 }
3597
3598 static int __devinit ql_init_device(struct pci_dev *pdev,
3599                                     struct net_device *ndev, int cards_found)
3600 {
3601         struct ql_adapter *qdev = netdev_priv(ndev);
3602         int pos, err = 0;
3603         u16 val16;
3604
3605         memset((void *)qdev, 0, sizeof(qdev));
3606         err = pci_enable_device(pdev);
3607         if (err) {
3608                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3609                 return err;
3610         }
3611
3612         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3613         if (pos <= 0) {
3614                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3615                         "aborting.\n");
3616                 goto err_out;
3617         } else {
3618                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3619                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3620                 val16 |= (PCI_EXP_DEVCTL_CERE |
3621                           PCI_EXP_DEVCTL_NFERE |
3622                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3623                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3624         }
3625
3626         err = pci_request_regions(pdev, DRV_NAME);
3627         if (err) {
3628                 dev_err(&pdev->dev, "PCI region request failed.\n");
3629                 goto err_out;
3630         }
3631
3632         pci_set_master(pdev);
3633         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3634                 set_bit(QL_DMA64, &qdev->flags);
3635                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3636         } else {
3637                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3638                 if (!err)
3639                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3640         }
3641
3642         if (err) {
3643                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3644                 goto err_out;
3645         }
3646
3647         pci_set_drvdata(pdev, ndev);
3648         qdev->reg_base =
3649             ioremap_nocache(pci_resource_start(pdev, 1),
3650                             pci_resource_len(pdev, 1));
3651         if (!qdev->reg_base) {
3652                 dev_err(&pdev->dev, "Register mapping failed.\n");
3653                 err = -ENOMEM;
3654                 goto err_out;
3655         }
3656
3657         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3658         qdev->doorbell_area =
3659             ioremap_nocache(pci_resource_start(pdev, 3),
3660                             pci_resource_len(pdev, 3));
3661         if (!qdev->doorbell_area) {
3662                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3663                 err = -ENOMEM;
3664                 goto err_out;
3665         }
3666
3667         ql_get_board_info(qdev);
3668         qdev->ndev = ndev;
3669         qdev->pdev = pdev;
3670         qdev->msg_enable = netif_msg_init(debug, default_msg);
3671         spin_lock_init(&qdev->hw_lock);
3672         spin_lock_init(&qdev->stats_lock);
3673
3674         /* make sure the EEPROM is good */
3675         err = ql_get_flash_params(qdev);
3676         if (err) {
3677                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3678                 goto err_out;
3679         }
3680
3681         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3682                 goto err_out;
3683
3684         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3685         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3686
3687         /* Set up the default ring sizes. */
3688         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3689         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3690
3691         /* Set up the coalescing parameters. */
3692         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3693         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3694         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3695         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3696
3697         /*
3698          * Set up the operating parameters.
3699          */
3700         qdev->rx_csum = 1;
3701
3702         qdev->q_workqueue = create_workqueue(ndev->name);
3703         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3704         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3705         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3706         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3707
3708         if (!cards_found) {
3709                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3710                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3711                          DRV_NAME, DRV_VERSION);
3712         }
3713         return 0;
3714 err_out:
3715         ql_release_all(pdev);
3716         pci_disable_device(pdev);
3717         return err;
3718 }
3719
3720 static int __devinit qlge_probe(struct pci_dev *pdev,
3721                                 const struct pci_device_id *pci_entry)
3722 {
3723         struct net_device *ndev = NULL;
3724         struct ql_adapter *qdev = NULL;
3725         static int cards_found = 0;
3726         int err = 0;
3727
3728         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3729         if (!ndev)
3730                 return -ENOMEM;
3731
3732         err = ql_init_device(pdev, ndev, cards_found);
3733         if (err < 0) {
3734                 free_netdev(ndev);
3735                 return err;
3736         }
3737
3738         qdev = netdev_priv(ndev);
3739         SET_NETDEV_DEV(ndev, &pdev->dev);
3740         ndev->features = (0
3741                           | NETIF_F_IP_CSUM
3742                           | NETIF_F_SG
3743                           | NETIF_F_TSO
3744                           | NETIF_F_TSO6
3745                           | NETIF_F_TSO_ECN
3746                           | NETIF_F_HW_VLAN_TX
3747                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3748
3749         if (test_bit(QL_DMA64, &qdev->flags))
3750                 ndev->features |= NETIF_F_HIGHDMA;
3751
3752         /*
3753          * Set up net_device structure.
3754          */
3755         ndev->tx_queue_len = qdev->tx_ring_size;
3756         ndev->irq = pdev->irq;
3757         ndev->open = qlge_open;
3758         ndev->stop = qlge_close;
3759         ndev->hard_start_xmit = qlge_send;
3760         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3761         ndev->change_mtu = qlge_change_mtu;
3762         ndev->get_stats = qlge_get_stats;
3763         ndev->set_multicast_list = qlge_set_multicast_list;
3764         ndev->set_mac_address = qlge_set_mac_address;
3765         ndev->tx_timeout = qlge_tx_timeout;
3766         ndev->watchdog_timeo = 10 * HZ;
3767         ndev->vlan_rx_register = ql_vlan_rx_register;
3768         ndev->vlan_rx_add_vid = ql_vlan_rx_add_vid;
3769         ndev->vlan_rx_kill_vid = ql_vlan_rx_kill_vid;
3770         err = register_netdev(ndev);
3771         if (err) {
3772                 dev_err(&pdev->dev, "net device registration failed.\n");
3773                 ql_release_all(pdev);
3774                 pci_disable_device(pdev);
3775                 return err;
3776         }
3777         netif_carrier_off(ndev);
3778         netif_stop_queue(ndev);
3779         ql_display_dev_info(ndev);
3780         cards_found++;
3781         return 0;
3782 }
3783
3784 static void __devexit qlge_remove(struct pci_dev *pdev)
3785 {
3786         struct net_device *ndev = pci_get_drvdata(pdev);
3787         unregister_netdev(ndev);
3788         ql_release_all(pdev);
3789         pci_disable_device(pdev);
3790         free_netdev(ndev);
3791 }
3792
3793 /*
3794  * This callback is called by the PCI subsystem whenever
3795  * a PCI bus error is detected.
3796  */
3797 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3798                                                enum pci_channel_state state)
3799 {
3800         struct net_device *ndev = pci_get_drvdata(pdev);
3801         struct ql_adapter *qdev = netdev_priv(ndev);
3802
3803         if (netif_running(ndev))
3804                 ql_adapter_down(qdev);
3805
3806         pci_disable_device(pdev);
3807
3808         /* Request a slot reset. */
3809         return PCI_ERS_RESULT_NEED_RESET;
3810 }
3811
3812 /*
3813  * This callback is called after the PCI buss has been reset.
3814  * Basically, this tries to restart the card from scratch.
3815  * This is a shortened version of the device probe/discovery code,
3816  * it resembles the first-half of the () routine.
3817  */
3818 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3819 {
3820         struct net_device *ndev = pci_get_drvdata(pdev);
3821         struct ql_adapter *qdev = netdev_priv(ndev);
3822
3823         if (pci_enable_device(pdev)) {
3824                 QPRINTK(qdev, IFUP, ERR,
3825                         "Cannot re-enable PCI device after reset.\n");
3826                 return PCI_ERS_RESULT_DISCONNECT;
3827         }
3828
3829         pci_set_master(pdev);
3830
3831         netif_carrier_off(ndev);
3832         netif_stop_queue(ndev);
3833         ql_adapter_reset(qdev);
3834
3835         /* Make sure the EEPROM is good */
3836         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3837
3838         if (!is_valid_ether_addr(ndev->perm_addr)) {
3839                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3840                 return PCI_ERS_RESULT_DISCONNECT;
3841         }
3842
3843         return PCI_ERS_RESULT_RECOVERED;
3844 }
3845
3846 static void qlge_io_resume(struct pci_dev *pdev)
3847 {
3848         struct net_device *ndev = pci_get_drvdata(pdev);
3849         struct ql_adapter *qdev = netdev_priv(ndev);
3850
3851         pci_set_master(pdev);
3852
3853         if (netif_running(ndev)) {
3854                 if (ql_adapter_up(qdev)) {
3855                         QPRINTK(qdev, IFUP, ERR,
3856                                 "Device initialization failed after reset.\n");
3857                         return;
3858                 }
3859         }
3860
3861         netif_device_attach(ndev);
3862 }
3863
3864 static struct pci_error_handlers qlge_err_handler = {
3865         .error_detected = qlge_io_error_detected,
3866         .slot_reset = qlge_io_slot_reset,
3867         .resume = qlge_io_resume,
3868 };
3869
3870 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3871 {
3872         struct net_device *ndev = pci_get_drvdata(pdev);
3873         struct ql_adapter *qdev = netdev_priv(ndev);
3874         int err;
3875
3876         netif_device_detach(ndev);
3877
3878         if (netif_running(ndev)) {
3879                 err = ql_adapter_down(qdev);
3880                 if (!err)
3881                         return err;
3882         }
3883
3884         err = pci_save_state(pdev);
3885         if (err)
3886                 return err;
3887
3888         pci_disable_device(pdev);
3889
3890         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3891
3892         return 0;
3893 }
3894
3895 #ifdef CONFIG_PM
3896 static int qlge_resume(struct pci_dev *pdev)
3897 {
3898         struct net_device *ndev = pci_get_drvdata(pdev);
3899         struct ql_adapter *qdev = netdev_priv(ndev);
3900         int err;
3901
3902         pci_set_power_state(pdev, PCI_D0);
3903         pci_restore_state(pdev);
3904         err = pci_enable_device(pdev);
3905         if (err) {
3906                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3907                 return err;
3908         }
3909         pci_set_master(pdev);
3910
3911         pci_enable_wake(pdev, PCI_D3hot, 0);
3912         pci_enable_wake(pdev, PCI_D3cold, 0);
3913
3914         if (netif_running(ndev)) {
3915                 err = ql_adapter_up(qdev);
3916                 if (err)
3917                         return err;
3918         }
3919
3920         netif_device_attach(ndev);
3921
3922         return 0;
3923 }
3924 #endif /* CONFIG_PM */
3925
3926 static void qlge_shutdown(struct pci_dev *pdev)
3927 {
3928         qlge_suspend(pdev, PMSG_SUSPEND);
3929 }
3930
3931 static struct pci_driver qlge_driver = {
3932         .name = DRV_NAME,
3933         .id_table = qlge_pci_tbl,
3934         .probe = qlge_probe,
3935         .remove = __devexit_p(qlge_remove),
3936 #ifdef CONFIG_PM
3937         .suspend = qlge_suspend,
3938         .resume = qlge_resume,
3939 #endif
3940         .shutdown = qlge_shutdown,
3941         .err_handler = &qlge_err_handler
3942 };
3943
3944 static int __init qlge_init_module(void)
3945 {
3946         return pci_register_driver(&qlge_driver);
3947 }
3948
3949 static void __exit qlge_exit(void)
3950 {
3951         pci_unregister_driver(&qlge_driver);
3952 }
3953
3954 module_init(qlge_init_module);
3955 module_exit(qlge_exit);