2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit = 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
94 RTL_GIGA_MAC_NONE = 0x00,
95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device *);
169 static void rtl_hw_start_8168(struct net_device *);
170 static void rtl_hw_start_8101(struct net_device *);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
188 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
195 static int rx_copybreak = 16383;
202 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
237 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8,
239 FuncForceEvent = 0xfc,
242 enum rtl8110_registers {
248 enum rtl8168_8101_registers {
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0f
254 #define CSIAR_BYTE_ENABLE_SHIFT 12
255 #define CSIAR_ADDR_MASK 0x0fff
258 #define EPHYAR_FLAG 0x80000000
259 #define EPHYAR_WRITE_CMD 0x80000000
260 #define EPHYAR_REG_MASK 0x1f
261 #define EPHYAR_REG_SHIFT 16
262 #define EPHYAR_DATA_MASK 0xffff
264 #define FIX_NAK_1 (1 << 4)
265 #define FIX_NAK_2 (1 << 3)
267 #define EFUSEAR_FLAG 0x80000000
268 #define EFUSEAR_WRITE_CMD 0x80000000
269 #define EFUSEAR_READ_CMD 0x00000000
270 #define EFUSEAR_REG_MASK 0x03ff
271 #define EFUSEAR_REG_SHIFT 8
272 #define EFUSEAR_DATA_MASK 0xff
275 enum rtl_register_content {
276 /* InterruptStatusBits */
280 TxDescUnavail = 0x0080,
302 /* TXPoll register p.5 */
303 HPQ = 0x80, /* Poll cmd on the high prio queue */
304 NPQ = 0x40, /* Poll cmd on the low prio queue */
305 FSWInt = 0x01, /* Forced software interrupt */
309 Cfg9346_Unlock = 0xc0,
314 AcceptBroadcast = 0x08,
315 AcceptMulticast = 0x04,
317 AcceptAllPhys = 0x01,
324 TxInterFrameGapShift = 24,
325 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
327 /* Config1 register p.24 */
330 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
331 Speed_down = (1 << 4),
335 PMEnable = (1 << 0), /* Power Management Enable */
337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz = 0x01,
339 PCI_Clock_33MHz = 0x00,
341 /* Config3 register p.25 */
342 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
344 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
346 /* Config5 register p.27 */
347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake = (1 << 1), /* LanWake enable/disable */
351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
354 TBIReset = 0x80000000,
355 TBILoopback = 0x40000000,
356 TBINwEnable = 0x20000000,
357 TBINwRestart = 0x10000000,
358 TBILinkOk = 0x02000000,
359 TBINwComplete = 0x01000000,
362 EnableBist = (1 << 15), // 8168 8101
363 Mac_dbgo_oe = (1 << 14), // 8168 8101
364 Normal_mode = (1 << 13), // unused
365 Force_half_dup = (1 << 12), // 8168 8101
366 Force_rxflow_en = (1 << 11), // 8168 8101
367 Force_txflow_en = (1 << 10), // 8168 8101
368 Cxpl_dbg_sel = (1 << 9), // 8168 8101
369 ASF = (1 << 8), // 8168 8101
370 PktCntrDisable = (1 << 7), // 8168 8101
371 Mac_dbgo_sel = 0x001c, // 8168
376 INTT_0 = 0x0000, // 8168
377 INTT_1 = 0x0001, // 8168
378 INTT_2 = 0x0002, // 8168
379 INTT_3 = 0x0003, // 8168
381 /* rtl8169_PHYstatus */
392 TBILinkOK = 0x02000000,
394 /* DumpCounterCommand */
398 enum desc_status_bit {
399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
417 #define RxProtoUDP (PID1)
418 #define RxProtoTCP (PID0)
419 #define RxProtoIP (PID1 | PID0)
420 #define RxProtoMask RxProtoIP
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
428 #define RsvdMask 0x3fffc000
445 u8 __pad[sizeof(void *) - sizeof(u32)];
449 RTL_FEATURE_WOL = (1 << 0),
450 RTL_FEATURE_MSI = (1 << 1),
451 RTL_FEATURE_GMII = (1 << 2),
454 struct rtl8169_counters {
461 __le32 tx_one_collision;
462 __le32 tx_multi_collision;
470 struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */
473 struct net_device *dev;
474 struct napi_struct napi;
475 spinlock_t lock; /* spin lock flag */
479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
483 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
491 struct timer_list timer;
496 int phy_1000_ctrl_reg;
497 #ifdef CONFIG_R8169_VLAN
498 struct vlan_group *vlgrp;
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
501 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
502 void (*phy_reset_enable)(void __iomem *);
503 void (*hw_start)(struct net_device *);
504 unsigned int (*phy_reset_pending)(void __iomem *);
505 unsigned int (*link_ok)(void __iomem *);
506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
508 struct delayed_work task;
511 struct mii_if_info mii;
512 struct rtl8169_counters counters;
516 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
517 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
518 module_param(rx_copybreak, int, 0);
519 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
520 module_param(use_dac, int, 0);
521 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
522 module_param_named(debug, debug.msg_enable, int, 0);
523 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
524 MODULE_LICENSE("GPL");
525 MODULE_VERSION(RTL8169_VERSION);
527 static int rtl8169_open(struct net_device *dev);
528 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
529 struct net_device *dev);
530 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
531 static int rtl8169_init_ring(struct net_device *dev);
532 static void rtl_hw_start(struct net_device *dev);
533 static int rtl8169_close(struct net_device *dev);
534 static void rtl_set_rx_mode(struct net_device *dev);
535 static void rtl8169_tx_timeout(struct net_device *dev);
536 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
537 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
538 void __iomem *, u32 budget);
539 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
540 static void rtl8169_down(struct net_device *dev);
541 static void rtl8169_rx_clear(struct rtl8169_private *tp);
542 static int rtl8169_poll(struct napi_struct *napi, int budget);
544 static const unsigned int rtl8169_rx_config =
545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
547 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
553 for (i = 20; i > 0; i--) {
555 * Check if the RTL8169 has completed writing to the specified
558 if (!(RTL_R32(PHYAR) & 0x80000000))
563 * Some configurations require a small delay even after the write
564 * completed indication or the next write might fail.
569 static int mdio_read(void __iomem *ioaddr, int reg_addr)
573 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
575 for (i = 20; i > 0; i--) {
577 * Check if the RTL8169 has completed retrieving data from
578 * the specified MII register.
580 if (RTL_R32(PHYAR) & 0x80000000) {
581 value = RTL_R32(PHYAR) & 0xffff;
589 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
591 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
594 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
598 val = mdio_read(ioaddr, reg_addr);
599 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
602 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
608 mdio_write(ioaddr, location, val);
611 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
613 struct rtl8169_private *tp = netdev_priv(dev);
614 void __iomem *ioaddr = tp->mmio_addr;
616 return mdio_read(ioaddr, location);
619 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
623 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
624 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
626 for (i = 0; i < 100; i++) {
627 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
633 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
638 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
640 for (i = 0; i < 100; i++) {
641 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
642 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
651 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
655 RTL_W32(CSIDR, value);
656 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
657 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
659 for (i = 0; i < 100; i++) {
660 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
666 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
671 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
672 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
674 for (i = 0; i < 100; i++) {
675 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
676 value = RTL_R32(CSIDR);
685 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
690 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
692 for (i = 0; i < 300; i++) {
693 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
694 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
703 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
705 RTL_W16(IntrMask, 0x0000);
707 RTL_W16(IntrStatus, 0xffff);
710 static void rtl8169_asic_down(void __iomem *ioaddr)
712 RTL_W8(ChipCmd, 0x00);
713 rtl8169_irq_mask_and_ack(ioaddr);
717 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
719 return RTL_R32(TBICSR) & TBIReset;
722 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
724 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
727 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
729 return RTL_R32(TBICSR) & TBILinkOk;
732 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
734 return RTL_R8(PHYstatus) & LinkStatus;
737 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
739 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
742 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
746 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
747 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
750 static void rtl8169_check_link_status(struct net_device *dev,
751 struct rtl8169_private *tp,
752 void __iomem *ioaddr)
756 spin_lock_irqsave(&tp->lock, flags);
757 if (tp->link_ok(ioaddr)) {
758 /* This is to cancel a scheduled suspend if there's one. */
759 pm_request_resume(&tp->pci_dev->dev);
760 netif_carrier_on(dev);
761 netif_info(tp, ifup, dev, "link up\n");
763 netif_carrier_off(dev);
764 netif_info(tp, ifdown, dev, "link down\n");
765 pm_schedule_suspend(&tp->pci_dev->dev, 100);
767 spin_unlock_irqrestore(&tp->lock, flags);
770 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
772 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
774 void __iomem *ioaddr = tp->mmio_addr;
778 options = RTL_R8(Config1);
779 if (!(options & PMEnable))
782 options = RTL_R8(Config3);
783 if (options & LinkUp)
785 if (options & MagicPacket)
786 wolopts |= WAKE_MAGIC;
788 options = RTL_R8(Config5);
790 wolopts |= WAKE_UCAST;
792 wolopts |= WAKE_BCAST;
794 wolopts |= WAKE_MCAST;
799 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
801 struct rtl8169_private *tp = netdev_priv(dev);
803 spin_lock_irq(&tp->lock);
805 wol->supported = WAKE_ANY;
806 wol->wolopts = __rtl8169_get_wol(tp);
808 spin_unlock_irq(&tp->lock);
811 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
813 void __iomem *ioaddr = tp->mmio_addr;
815 static const struct {
820 { WAKE_ANY, Config1, PMEnable },
821 { WAKE_PHY, Config3, LinkUp },
822 { WAKE_MAGIC, Config3, MagicPacket },
823 { WAKE_UCAST, Config5, UWF },
824 { WAKE_BCAST, Config5, BWF },
825 { WAKE_MCAST, Config5, MWF },
826 { WAKE_ANY, Config5, LanWake }
829 RTL_W8(Cfg9346, Cfg9346_Unlock);
831 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
832 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
833 if (wolopts & cfg[i].opt)
834 options |= cfg[i].mask;
835 RTL_W8(cfg[i].reg, options);
838 RTL_W8(Cfg9346, Cfg9346_Lock);
841 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
843 struct rtl8169_private *tp = netdev_priv(dev);
845 spin_lock_irq(&tp->lock);
848 tp->features |= RTL_FEATURE_WOL;
850 tp->features &= ~RTL_FEATURE_WOL;
851 __rtl8169_set_wol(tp, wol->wolopts);
852 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
854 spin_unlock_irq(&tp->lock);
859 static void rtl8169_get_drvinfo(struct net_device *dev,
860 struct ethtool_drvinfo *info)
862 struct rtl8169_private *tp = netdev_priv(dev);
864 strcpy(info->driver, MODULENAME);
865 strcpy(info->version, RTL8169_VERSION);
866 strcpy(info->bus_info, pci_name(tp->pci_dev));
869 static int rtl8169_get_regs_len(struct net_device *dev)
871 return R8169_REGS_SIZE;
874 static int rtl8169_set_speed_tbi(struct net_device *dev,
875 u8 autoneg, u16 speed, u8 duplex)
877 struct rtl8169_private *tp = netdev_priv(dev);
878 void __iomem *ioaddr = tp->mmio_addr;
882 reg = RTL_R32(TBICSR);
883 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
884 (duplex == DUPLEX_FULL)) {
885 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
886 } else if (autoneg == AUTONEG_ENABLE)
887 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
889 netif_warn(tp, link, dev,
890 "incorrect speed setting refused in TBI mode\n");
897 static int rtl8169_set_speed_xmii(struct net_device *dev,
898 u8 autoneg, u16 speed, u8 duplex)
900 struct rtl8169_private *tp = netdev_priv(dev);
901 void __iomem *ioaddr = tp->mmio_addr;
904 if (autoneg == AUTONEG_ENABLE) {
907 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
908 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
909 ADVERTISE_100HALF | ADVERTISE_100FULL);
910 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
912 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
913 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
915 /* The 8100e/8101e/8102e do Fast Ethernet only. */
916 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
917 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
918 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
919 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
920 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
921 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
922 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
923 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
924 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
926 netif_info(tp, link, dev,
927 "PHY does not support 1000Mbps\n");
930 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
932 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
933 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
934 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
937 * Vendor specific (0x1f) and reserved (0x0e) MII
940 mdio_write(ioaddr, 0x1f, 0x0000);
941 mdio_write(ioaddr, 0x0e, 0x0000);
944 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
945 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
949 if (speed == SPEED_10)
951 else if (speed == SPEED_100)
952 bmcr = BMCR_SPEED100;
956 if (duplex == DUPLEX_FULL)
957 bmcr |= BMCR_FULLDPLX;
959 mdio_write(ioaddr, 0x1f, 0x0000);
962 tp->phy_1000_ctrl_reg = giga_ctrl;
964 mdio_write(ioaddr, MII_BMCR, bmcr);
966 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
967 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
968 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
969 mdio_write(ioaddr, 0x17, 0x2138);
970 mdio_write(ioaddr, 0x0e, 0x0260);
972 mdio_write(ioaddr, 0x17, 0x2108);
973 mdio_write(ioaddr, 0x0e, 0x0000);
980 static int rtl8169_set_speed(struct net_device *dev,
981 u8 autoneg, u16 speed, u8 duplex)
983 struct rtl8169_private *tp = netdev_priv(dev);
986 ret = tp->set_speed(dev, autoneg, speed, duplex);
988 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
989 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
994 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
996 struct rtl8169_private *tp = netdev_priv(dev);
1000 spin_lock_irqsave(&tp->lock, flags);
1001 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1002 spin_unlock_irqrestore(&tp->lock, flags);
1007 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1009 struct rtl8169_private *tp = netdev_priv(dev);
1011 return tp->cp_cmd & RxChkSum;
1014 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1016 struct rtl8169_private *tp = netdev_priv(dev);
1017 void __iomem *ioaddr = tp->mmio_addr;
1018 unsigned long flags;
1020 spin_lock_irqsave(&tp->lock, flags);
1023 tp->cp_cmd |= RxChkSum;
1025 tp->cp_cmd &= ~RxChkSum;
1027 RTL_W16(CPlusCmd, tp->cp_cmd);
1030 spin_unlock_irqrestore(&tp->lock, flags);
1035 #ifdef CONFIG_R8169_VLAN
1037 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1038 struct sk_buff *skb)
1040 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1041 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1044 static void rtl8169_vlan_rx_register(struct net_device *dev,
1045 struct vlan_group *grp)
1047 struct rtl8169_private *tp = netdev_priv(dev);
1048 void __iomem *ioaddr = tp->mmio_addr;
1049 unsigned long flags;
1051 spin_lock_irqsave(&tp->lock, flags);
1054 * Do not disable RxVlan on 8110SCd.
1056 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1057 tp->cp_cmd |= RxVlan;
1059 tp->cp_cmd &= ~RxVlan;
1060 RTL_W16(CPlusCmd, tp->cp_cmd);
1062 spin_unlock_irqrestore(&tp->lock, flags);
1065 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1066 struct sk_buff *skb, int polling)
1068 u32 opts2 = le32_to_cpu(desc->opts2);
1069 struct vlan_group *vlgrp = tp->vlgrp;
1072 if (vlgrp && (opts2 & RxVlanTag)) {
1073 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1081 #else /* !CONFIG_R8169_VLAN */
1083 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1084 struct sk_buff *skb)
1089 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1090 struct sk_buff *skb, int polling)
1097 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1099 struct rtl8169_private *tp = netdev_priv(dev);
1100 void __iomem *ioaddr = tp->mmio_addr;
1104 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1105 cmd->port = PORT_FIBRE;
1106 cmd->transceiver = XCVR_INTERNAL;
1108 status = RTL_R32(TBICSR);
1109 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1110 cmd->autoneg = !!(status & TBINwEnable);
1112 cmd->speed = SPEED_1000;
1113 cmd->duplex = DUPLEX_FULL; /* Always set */
1118 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1120 struct rtl8169_private *tp = netdev_priv(dev);
1122 return mii_ethtool_gset(&tp->mii, cmd);
1125 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1127 struct rtl8169_private *tp = netdev_priv(dev);
1128 unsigned long flags;
1131 spin_lock_irqsave(&tp->lock, flags);
1133 rc = tp->get_settings(dev, cmd);
1135 spin_unlock_irqrestore(&tp->lock, flags);
1139 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1142 struct rtl8169_private *tp = netdev_priv(dev);
1143 unsigned long flags;
1145 if (regs->len > R8169_REGS_SIZE)
1146 regs->len = R8169_REGS_SIZE;
1148 spin_lock_irqsave(&tp->lock, flags);
1149 memcpy_fromio(p, tp->mmio_addr, regs->len);
1150 spin_unlock_irqrestore(&tp->lock, flags);
1153 static u32 rtl8169_get_msglevel(struct net_device *dev)
1155 struct rtl8169_private *tp = netdev_priv(dev);
1157 return tp->msg_enable;
1160 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1162 struct rtl8169_private *tp = netdev_priv(dev);
1164 tp->msg_enable = value;
1167 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1174 "tx_single_collisions",
1175 "tx_multi_collisions",
1183 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1187 return ARRAY_SIZE(rtl8169_gstrings);
1193 static void rtl8169_update_counters(struct net_device *dev)
1195 struct rtl8169_private *tp = netdev_priv(dev);
1196 void __iomem *ioaddr = tp->mmio_addr;
1197 struct rtl8169_counters *counters;
1203 * Some chips are unable to dump tally counters when the receiver
1206 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1209 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1213 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1214 cmd = (u64)paddr & DMA_BIT_MASK(32);
1215 RTL_W32(CounterAddrLow, cmd);
1216 RTL_W32(CounterAddrLow, cmd | CounterDump);
1219 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1220 /* copy updated counters */
1221 memcpy(&tp->counters, counters, sizeof(*counters));
1227 RTL_W32(CounterAddrLow, 0);
1228 RTL_W32(CounterAddrHigh, 0);
1230 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1233 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1234 struct ethtool_stats *stats, u64 *data)
1236 struct rtl8169_private *tp = netdev_priv(dev);
1240 rtl8169_update_counters(dev);
1242 data[0] = le64_to_cpu(tp->counters.tx_packets);
1243 data[1] = le64_to_cpu(tp->counters.rx_packets);
1244 data[2] = le64_to_cpu(tp->counters.tx_errors);
1245 data[3] = le32_to_cpu(tp->counters.rx_errors);
1246 data[4] = le16_to_cpu(tp->counters.rx_missed);
1247 data[5] = le16_to_cpu(tp->counters.align_errors);
1248 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1249 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1250 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1251 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1252 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1253 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1254 data[12] = le16_to_cpu(tp->counters.tx_underun);
1257 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1261 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1266 static const struct ethtool_ops rtl8169_ethtool_ops = {
1267 .get_drvinfo = rtl8169_get_drvinfo,
1268 .get_regs_len = rtl8169_get_regs_len,
1269 .get_link = ethtool_op_get_link,
1270 .get_settings = rtl8169_get_settings,
1271 .set_settings = rtl8169_set_settings,
1272 .get_msglevel = rtl8169_get_msglevel,
1273 .set_msglevel = rtl8169_set_msglevel,
1274 .get_rx_csum = rtl8169_get_rx_csum,
1275 .set_rx_csum = rtl8169_set_rx_csum,
1276 .set_tx_csum = ethtool_op_set_tx_csum,
1277 .set_sg = ethtool_op_set_sg,
1278 .set_tso = ethtool_op_set_tso,
1279 .get_regs = rtl8169_get_regs,
1280 .get_wol = rtl8169_get_wol,
1281 .set_wol = rtl8169_set_wol,
1282 .get_strings = rtl8169_get_strings,
1283 .get_sset_count = rtl8169_get_sset_count,
1284 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1287 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1288 void __iomem *ioaddr)
1291 * The driver currently handles the 8168Bf and the 8168Be identically
1292 * but they can be identified more specifically through the test below
1295 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1297 * Same thing for the 8101Eb and the 8101Ec:
1299 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1301 static const struct {
1307 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1308 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1309 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1310 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1313 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1314 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1315 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1316 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1317 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1318 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1319 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1320 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1321 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1324 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1325 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1326 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1327 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1330 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1331 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1332 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1333 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1334 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1335 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1336 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1337 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1338 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1339 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1340 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1341 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1342 /* FIXME: where did these entries come from ? -- FR */
1343 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1344 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1347 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1348 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1349 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1350 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1351 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1352 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1355 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1359 reg = RTL_R32(TxConfig);
1360 while ((reg & p->mask) != p->val)
1362 tp->mac_version = p->mac_version;
1365 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1367 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1375 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1378 mdio_write(ioaddr, regs->reg, regs->val);
1383 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1385 static const struct phy_reg phy_reg_init[] = {
1447 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1450 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1452 static const struct phy_reg phy_reg_init[] = {
1458 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1461 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1462 void __iomem *ioaddr)
1464 struct pci_dev *pdev = tp->pci_dev;
1465 u16 vendor_id, device_id;
1467 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1468 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1470 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1473 mdio_write(ioaddr, 0x1f, 0x0001);
1474 mdio_write(ioaddr, 0x10, 0xf01b);
1475 mdio_write(ioaddr, 0x1f, 0x0000);
1478 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1479 void __iomem *ioaddr)
1481 static const struct phy_reg phy_reg_init[] = {
1521 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1523 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1526 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1528 static const struct phy_reg phy_reg_init[] = {
1576 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1579 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1581 static const struct phy_reg phy_reg_init[] = {
1586 mdio_write(ioaddr, 0x1f, 0x0001);
1587 mdio_patch(ioaddr, 0x16, 1 << 0);
1589 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1592 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1594 static const struct phy_reg phy_reg_init[] = {
1600 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1603 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1605 static const struct phy_reg phy_reg_init[] = {
1613 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1616 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1618 static const struct phy_reg phy_reg_init[] = {
1624 mdio_write(ioaddr, 0x1f, 0x0000);
1625 mdio_patch(ioaddr, 0x14, 1 << 5);
1626 mdio_patch(ioaddr, 0x0d, 1 << 5);
1628 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1631 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1633 static const struct phy_reg phy_reg_init[] = {
1653 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1655 mdio_patch(ioaddr, 0x14, 1 << 5);
1656 mdio_patch(ioaddr, 0x0d, 1 << 5);
1657 mdio_write(ioaddr, 0x1f, 0x0000);
1660 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1662 static const struct phy_reg phy_reg_init[] = {
1680 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1682 mdio_patch(ioaddr, 0x16, 1 << 0);
1683 mdio_patch(ioaddr, 0x14, 1 << 5);
1684 mdio_patch(ioaddr, 0x0d, 1 << 5);
1685 mdio_write(ioaddr, 0x1f, 0x0000);
1688 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1690 static const struct phy_reg phy_reg_init[] = {
1702 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1704 mdio_patch(ioaddr, 0x16, 1 << 0);
1705 mdio_patch(ioaddr, 0x14, 1 << 5);
1706 mdio_patch(ioaddr, 0x0d, 1 << 5);
1707 mdio_write(ioaddr, 0x1f, 0x0000);
1710 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1712 rtl8168c_3_hw_phy_config(ioaddr);
1715 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1717 static const struct phy_reg phy_reg_init_0[] = {
1736 static const struct phy_reg phy_reg_init_1[] = {
1743 static const struct phy_reg phy_reg_init_2[] = {
2099 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2101 mdio_write(ioaddr, 0x1f, 0x0002);
2102 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2103 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2105 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2107 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2108 static const struct phy_reg phy_reg_init[] = {
2118 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2120 val = mdio_read(ioaddr, 0x0d);
2122 if ((val & 0x00ff) != 0x006c) {
2123 static const u32 set[] = {
2124 0x0065, 0x0066, 0x0067, 0x0068,
2125 0x0069, 0x006a, 0x006b, 0x006c
2129 mdio_write(ioaddr, 0x1f, 0x0002);
2132 for (i = 0; i < ARRAY_SIZE(set); i++)
2133 mdio_write(ioaddr, 0x0d, val | set[i]);
2136 static const struct phy_reg phy_reg_init[] = {
2144 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2147 mdio_write(ioaddr, 0x1f, 0x0002);
2148 mdio_patch(ioaddr, 0x0d, 0x0300);
2149 mdio_patch(ioaddr, 0x0f, 0x0010);
2151 mdio_write(ioaddr, 0x1f, 0x0002);
2152 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2153 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2155 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2158 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2160 static const struct phy_reg phy_reg_init_0[] = {
2185 static const struct phy_reg phy_reg_init_1[] = {
2498 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2500 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2501 static const struct phy_reg phy_reg_init[] = {
2512 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514 val = mdio_read(ioaddr, 0x0d);
2515 if ((val & 0x00ff) != 0x006c) {
2517 0x0065, 0x0066, 0x0067, 0x0068,
2518 0x0069, 0x006a, 0x006b, 0x006c
2522 mdio_write(ioaddr, 0x1f, 0x0002);
2525 for (i = 0; i < ARRAY_SIZE(set); i++)
2526 mdio_write(ioaddr, 0x0d, val | set[i]);
2529 static const struct phy_reg phy_reg_init[] = {
2537 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2540 mdio_write(ioaddr, 0x1f, 0x0002);
2541 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2542 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2544 mdio_write(ioaddr, 0x1f, 0x0001);
2545 mdio_write(ioaddr, 0x17, 0x0cc0);
2547 mdio_write(ioaddr, 0x1f, 0x0002);
2548 mdio_patch(ioaddr, 0x0f, 0x0017);
2550 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2553 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2555 static const struct phy_reg phy_reg_init[] = {
2611 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2614 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2616 static const struct phy_reg phy_reg_init[] = {
2623 mdio_write(ioaddr, 0x1f, 0x0000);
2624 mdio_patch(ioaddr, 0x11, 1 << 12);
2625 mdio_patch(ioaddr, 0x19, 1 << 13);
2626 mdio_patch(ioaddr, 0x10, 1 << 15);
2628 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2631 static void rtl_hw_phy_config(struct net_device *dev)
2633 struct rtl8169_private *tp = netdev_priv(dev);
2634 void __iomem *ioaddr = tp->mmio_addr;
2636 rtl8169_print_mac_version(tp);
2638 switch (tp->mac_version) {
2639 case RTL_GIGA_MAC_VER_01:
2641 case RTL_GIGA_MAC_VER_02:
2642 case RTL_GIGA_MAC_VER_03:
2643 rtl8169s_hw_phy_config(ioaddr);
2645 case RTL_GIGA_MAC_VER_04:
2646 rtl8169sb_hw_phy_config(ioaddr);
2648 case RTL_GIGA_MAC_VER_05:
2649 rtl8169scd_hw_phy_config(tp, ioaddr);
2651 case RTL_GIGA_MAC_VER_06:
2652 rtl8169sce_hw_phy_config(ioaddr);
2654 case RTL_GIGA_MAC_VER_07:
2655 case RTL_GIGA_MAC_VER_08:
2656 case RTL_GIGA_MAC_VER_09:
2657 rtl8102e_hw_phy_config(ioaddr);
2659 case RTL_GIGA_MAC_VER_11:
2660 rtl8168bb_hw_phy_config(ioaddr);
2662 case RTL_GIGA_MAC_VER_12:
2663 rtl8168bef_hw_phy_config(ioaddr);
2665 case RTL_GIGA_MAC_VER_17:
2666 rtl8168bef_hw_phy_config(ioaddr);
2668 case RTL_GIGA_MAC_VER_18:
2669 rtl8168cp_1_hw_phy_config(ioaddr);
2671 case RTL_GIGA_MAC_VER_19:
2672 rtl8168c_1_hw_phy_config(ioaddr);
2674 case RTL_GIGA_MAC_VER_20:
2675 rtl8168c_2_hw_phy_config(ioaddr);
2677 case RTL_GIGA_MAC_VER_21:
2678 rtl8168c_3_hw_phy_config(ioaddr);
2680 case RTL_GIGA_MAC_VER_22:
2681 rtl8168c_4_hw_phy_config(ioaddr);
2683 case RTL_GIGA_MAC_VER_23:
2684 case RTL_GIGA_MAC_VER_24:
2685 rtl8168cp_2_hw_phy_config(ioaddr);
2687 case RTL_GIGA_MAC_VER_25:
2688 rtl8168d_1_hw_phy_config(ioaddr);
2690 case RTL_GIGA_MAC_VER_26:
2691 rtl8168d_2_hw_phy_config(ioaddr);
2693 case RTL_GIGA_MAC_VER_27:
2694 rtl8168d_3_hw_phy_config(ioaddr);
2702 static void rtl8169_phy_timer(unsigned long __opaque)
2704 struct net_device *dev = (struct net_device *)__opaque;
2705 struct rtl8169_private *tp = netdev_priv(dev);
2706 struct timer_list *timer = &tp->timer;
2707 void __iomem *ioaddr = tp->mmio_addr;
2708 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2710 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2712 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2715 spin_lock_irq(&tp->lock);
2717 if (tp->phy_reset_pending(ioaddr)) {
2719 * A busy loop could burn quite a few cycles on nowadays CPU.
2720 * Let's delay the execution of the timer for a few ticks.
2726 if (tp->link_ok(ioaddr))
2729 netif_warn(tp, link, dev, "PHY reset until link up\n");
2731 tp->phy_reset_enable(ioaddr);
2734 mod_timer(timer, jiffies + timeout);
2736 spin_unlock_irq(&tp->lock);
2739 static inline void rtl8169_delete_timer(struct net_device *dev)
2741 struct rtl8169_private *tp = netdev_priv(dev);
2742 struct timer_list *timer = &tp->timer;
2744 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2747 del_timer_sync(timer);
2750 static inline void rtl8169_request_timer(struct net_device *dev)
2752 struct rtl8169_private *tp = netdev_priv(dev);
2753 struct timer_list *timer = &tp->timer;
2755 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2758 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2761 #ifdef CONFIG_NET_POLL_CONTROLLER
2763 * Polling 'interrupt' - used by things like netconsole to send skbs
2764 * without having to re-enable interrupts. It's not called while
2765 * the interrupt routine is executing.
2767 static void rtl8169_netpoll(struct net_device *dev)
2769 struct rtl8169_private *tp = netdev_priv(dev);
2770 struct pci_dev *pdev = tp->pci_dev;
2772 disable_irq(pdev->irq);
2773 rtl8169_interrupt(pdev->irq, dev);
2774 enable_irq(pdev->irq);
2778 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2779 void __iomem *ioaddr)
2782 pci_release_regions(pdev);
2783 pci_clear_mwi(pdev);
2784 pci_disable_device(pdev);
2788 static void rtl8169_phy_reset(struct net_device *dev,
2789 struct rtl8169_private *tp)
2791 void __iomem *ioaddr = tp->mmio_addr;
2794 tp->phy_reset_enable(ioaddr);
2795 for (i = 0; i < 100; i++) {
2796 if (!tp->phy_reset_pending(ioaddr))
2800 netif_err(tp, link, dev, "PHY reset failed\n");
2803 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2805 void __iomem *ioaddr = tp->mmio_addr;
2807 rtl_hw_phy_config(dev);
2809 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2810 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2814 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2816 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2817 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2819 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2820 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2822 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2823 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2826 rtl8169_phy_reset(dev, tp);
2829 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2830 * only 8101. Don't panic.
2832 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2834 if (RTL_R8(PHYstatus) & TBI_Enable)
2835 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2838 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2840 void __iomem *ioaddr = tp->mmio_addr;
2844 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2845 high = addr[4] | (addr[5] << 8);
2847 spin_lock_irq(&tp->lock);
2849 RTL_W8(Cfg9346, Cfg9346_Unlock);
2851 RTL_W32(MAC4, high);
2857 RTL_W8(Cfg9346, Cfg9346_Lock);
2859 spin_unlock_irq(&tp->lock);
2862 static int rtl_set_mac_address(struct net_device *dev, void *p)
2864 struct rtl8169_private *tp = netdev_priv(dev);
2865 struct sockaddr *addr = p;
2867 if (!is_valid_ether_addr(addr->sa_data))
2868 return -EADDRNOTAVAIL;
2870 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2872 rtl_rar_set(tp, dev->dev_addr);
2877 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2879 struct rtl8169_private *tp = netdev_priv(dev);
2880 struct mii_ioctl_data *data = if_mii(ifr);
2882 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2885 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2889 data->phy_id = 32; /* Internal PHY */
2893 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2897 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2903 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2908 static const struct rtl_cfg_info {
2909 void (*hw_start)(struct net_device *);
2910 unsigned int region;
2916 } rtl_cfg_infos [] = {
2918 .hw_start = rtl_hw_start_8169,
2921 .intr_event = SYSErr | LinkChg | RxOverflow |
2922 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2923 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2924 .features = RTL_FEATURE_GMII,
2925 .default_ver = RTL_GIGA_MAC_VER_01,
2928 .hw_start = rtl_hw_start_8168,
2931 .intr_event = SYSErr | LinkChg | RxOverflow |
2932 TxErr | TxOK | RxOK | RxErr,
2933 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2934 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2935 .default_ver = RTL_GIGA_MAC_VER_11,
2938 .hw_start = rtl_hw_start_8101,
2941 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2942 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2943 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2944 .features = RTL_FEATURE_MSI,
2945 .default_ver = RTL_GIGA_MAC_VER_13,
2949 /* Cfg9346_Unlock assumed. */
2950 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2951 const struct rtl_cfg_info *cfg)
2956 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2957 if (cfg->features & RTL_FEATURE_MSI) {
2958 if (pci_enable_msi(pdev)) {
2959 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2962 msi = RTL_FEATURE_MSI;
2965 RTL_W8(Config2, cfg2);
2969 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2971 if (tp->features & RTL_FEATURE_MSI) {
2972 pci_disable_msi(pdev);
2973 tp->features &= ~RTL_FEATURE_MSI;
2977 static const struct net_device_ops rtl8169_netdev_ops = {
2978 .ndo_open = rtl8169_open,
2979 .ndo_stop = rtl8169_close,
2980 .ndo_get_stats = rtl8169_get_stats,
2981 .ndo_start_xmit = rtl8169_start_xmit,
2982 .ndo_tx_timeout = rtl8169_tx_timeout,
2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_change_mtu = rtl8169_change_mtu,
2985 .ndo_set_mac_address = rtl_set_mac_address,
2986 .ndo_do_ioctl = rtl8169_ioctl,
2987 .ndo_set_multicast_list = rtl_set_rx_mode,
2988 #ifdef CONFIG_R8169_VLAN
2989 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2991 #ifdef CONFIG_NET_POLL_CONTROLLER
2992 .ndo_poll_controller = rtl8169_netpoll,
2997 static int __devinit
2998 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3000 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3001 const unsigned int region = cfg->region;
3002 struct rtl8169_private *tp;
3003 struct mii_if_info *mii;
3004 struct net_device *dev;
3005 void __iomem *ioaddr;
3009 if (netif_msg_drv(&debug)) {
3010 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3011 MODULENAME, RTL8169_VERSION);
3014 dev = alloc_etherdev(sizeof (*tp));
3016 if (netif_msg_drv(&debug))
3017 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3022 SET_NETDEV_DEV(dev, &pdev->dev);
3023 dev->netdev_ops = &rtl8169_netdev_ops;
3024 tp = netdev_priv(dev);
3027 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3031 mii->mdio_read = rtl_mdio_read;
3032 mii->mdio_write = rtl_mdio_write;
3033 mii->phy_id_mask = 0x1f;
3034 mii->reg_num_mask = 0x1f;
3035 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3037 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3038 rc = pci_enable_device(pdev);
3040 netif_err(tp, probe, dev, "enable failure\n");
3041 goto err_out_free_dev_1;
3044 if (pci_set_mwi(pdev) < 0)
3045 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3047 /* make sure PCI base addr 1 is MMIO */
3048 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3049 netif_err(tp, probe, dev,
3050 "region #%d not an MMIO resource, aborting\n",
3056 /* check for weird/broken PCI region reporting */
3057 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3058 netif_err(tp, probe, dev,
3059 "Invalid PCI region size(s), aborting\n");
3064 rc = pci_request_regions(pdev, MODULENAME);
3066 netif_err(tp, probe, dev, "could not request regions\n");
3070 tp->cp_cmd = PCIMulRW | RxChkSum;
3072 if ((sizeof(dma_addr_t) > 4) &&
3073 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3074 tp->cp_cmd |= PCIDAC;
3075 dev->features |= NETIF_F_HIGHDMA;
3077 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3079 netif_err(tp, probe, dev, "DMA configuration failed\n");
3080 goto err_out_free_res_3;
3084 /* ioremap MMIO region */
3085 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3087 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3089 goto err_out_free_res_3;
3092 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3094 netif_info(tp, probe, dev, "no PCI Express capability\n");
3096 RTL_W16(IntrMask, 0x0000);
3098 /* Soft reset the chip. */
3099 RTL_W8(ChipCmd, CmdReset);
3101 /* Check that the chip has finished the reset. */
3102 for (i = 0; i < 100; i++) {
3103 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3105 msleep_interruptible(1);
3108 RTL_W16(IntrStatus, 0xffff);
3110 pci_set_master(pdev);
3112 /* Identify chip attached to board */
3113 rtl8169_get_mac_version(tp, ioaddr);
3115 /* Use appropriate default if unknown */
3116 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3117 netif_notice(tp, probe, dev,
3118 "unknown MAC, using family default\n");
3119 tp->mac_version = cfg->default_ver;
3122 rtl8169_print_mac_version(tp);
3124 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3125 if (tp->mac_version == rtl_chip_info[i].mac_version)
3128 if (i == ARRAY_SIZE(rtl_chip_info)) {
3130 "driver bug, MAC version not found in rtl_chip_info\n");
3135 RTL_W8(Cfg9346, Cfg9346_Unlock);
3136 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3137 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3138 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3139 tp->features |= RTL_FEATURE_WOL;
3140 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3141 tp->features |= RTL_FEATURE_WOL;
3142 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3143 RTL_W8(Cfg9346, Cfg9346_Lock);
3145 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3146 (RTL_R8(PHYstatus) & TBI_Enable)) {
3147 tp->set_speed = rtl8169_set_speed_tbi;
3148 tp->get_settings = rtl8169_gset_tbi;
3149 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3150 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3151 tp->link_ok = rtl8169_tbi_link_ok;
3152 tp->do_ioctl = rtl_tbi_ioctl;
3154 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3156 tp->set_speed = rtl8169_set_speed_xmii;
3157 tp->get_settings = rtl8169_gset_xmii;
3158 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3159 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3160 tp->link_ok = rtl8169_xmii_link_ok;
3161 tp->do_ioctl = rtl_xmii_ioctl;
3164 spin_lock_init(&tp->lock);
3166 tp->mmio_addr = ioaddr;
3168 /* Get MAC address */
3169 for (i = 0; i < MAC_ADDR_LEN; i++)
3170 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3171 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3173 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3174 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3175 dev->irq = pdev->irq;
3176 dev->base_addr = (unsigned long) ioaddr;
3178 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3180 #ifdef CONFIG_R8169_VLAN
3181 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3184 tp->intr_mask = 0xffff;
3185 tp->align = cfg->align;
3186 tp->hw_start = cfg->hw_start;
3187 tp->intr_event = cfg->intr_event;
3188 tp->napi_event = cfg->napi_event;
3190 init_timer(&tp->timer);
3191 tp->timer.data = (unsigned long) dev;
3192 tp->timer.function = rtl8169_phy_timer;
3194 rc = register_netdev(dev);
3198 pci_set_drvdata(pdev, dev);
3200 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3201 rtl_chip_info[tp->chipset].name,
3202 dev->base_addr, dev->dev_addr,
3203 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3205 rtl8169_init_phy(dev, tp);
3208 * Pretend we are using VLANs; This bypasses a nasty bug where
3209 * Interrupts stop flowing on high load on 8110SCd controllers.
3211 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3212 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3214 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3216 if (pci_dev_run_wake(pdev)) {
3217 pm_runtime_set_active(&pdev->dev);
3218 pm_runtime_enable(&pdev->dev);
3220 pm_runtime_idle(&pdev->dev);
3226 rtl_disable_msi(pdev, tp);
3229 pci_release_regions(pdev);
3231 pci_clear_mwi(pdev);
3232 pci_disable_device(pdev);
3238 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3240 struct net_device *dev = pci_get_drvdata(pdev);
3241 struct rtl8169_private *tp = netdev_priv(dev);
3243 pm_runtime_get_sync(&pdev->dev);
3245 flush_scheduled_work();
3247 unregister_netdev(dev);
3249 if (pci_dev_run_wake(pdev)) {
3250 pm_runtime_disable(&pdev->dev);
3251 pm_runtime_set_suspended(&pdev->dev);
3253 pm_runtime_put_noidle(&pdev->dev);
3255 /* restore original MAC address */
3256 rtl_rar_set(tp, dev->perm_addr);
3258 rtl_disable_msi(pdev, tp);
3259 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3260 pci_set_drvdata(pdev, NULL);
3263 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3266 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3268 if (max_frame != 16383)
3269 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3270 "NIC may lead to frame reception errors!\n");
3272 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3275 static int rtl8169_open(struct net_device *dev)
3277 struct rtl8169_private *tp = netdev_priv(dev);
3278 struct pci_dev *pdev = tp->pci_dev;
3279 int retval = -ENOMEM;
3281 pm_runtime_get_sync(&pdev->dev);
3284 * Note that we use a magic value here, its wierd I know
3285 * its done because, some subset of rtl8169 hardware suffers from
3286 * a problem in which frames received that are longer than
3287 * the size set in RxMaxSize register return garbage sizes
3288 * when received. To avoid this we need to turn off filtering,
3289 * which is done by setting a value of 16383 in the RxMaxSize register
3290 * and allocating 16k frames to handle the largest possible rx value
3291 * thats what the magic math below does.
3293 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3296 * Rx and Tx desscriptors needs 256 bytes alignment.
3297 * pci_alloc_consistent provides more.
3299 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3301 if (!tp->TxDescArray)
3302 goto err_pm_runtime_put;
3304 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3306 if (!tp->RxDescArray)
3309 retval = rtl8169_init_ring(dev);
3313 INIT_DELAYED_WORK(&tp->task, NULL);
3317 retval = request_irq(dev->irq, rtl8169_interrupt,
3318 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3321 goto err_release_ring_2;
3323 napi_enable(&tp->napi);
3327 rtl8169_request_timer(dev);
3329 tp->saved_wolopts = 0;
3330 pm_runtime_put_noidle(&pdev->dev);
3332 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3337 rtl8169_rx_clear(tp);
3339 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3341 tp->RxDescArray = NULL;
3343 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3345 tp->TxDescArray = NULL;
3347 pm_runtime_put_noidle(&pdev->dev);
3351 static void rtl8169_hw_reset(void __iomem *ioaddr)
3353 /* Disable interrupts */
3354 rtl8169_irq_mask_and_ack(ioaddr);
3356 /* Reset the chipset */
3357 RTL_W8(ChipCmd, CmdReset);
3363 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3365 void __iomem *ioaddr = tp->mmio_addr;
3366 u32 cfg = rtl8169_rx_config;
3368 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3369 RTL_W32(RxConfig, cfg);
3371 /* Set DMA burst size and Interframe Gap Time */
3372 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3373 (InterFrameGap << TxInterFrameGapShift));
3376 static void rtl_hw_start(struct net_device *dev)
3378 struct rtl8169_private *tp = netdev_priv(dev);
3379 void __iomem *ioaddr = tp->mmio_addr;
3382 /* Soft reset the chip. */
3383 RTL_W8(ChipCmd, CmdReset);
3385 /* Check that the chip has finished the reset. */
3386 for (i = 0; i < 100; i++) {
3387 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3389 msleep_interruptible(1);
3394 netif_start_queue(dev);
3398 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3399 void __iomem *ioaddr)
3402 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3403 * register to be written before TxDescAddrLow to work.
3404 * Switching from MMIO to I/O access fixes the issue as well.
3406 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3407 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3408 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3409 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3412 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3416 cmd = RTL_R16(CPlusCmd);
3417 RTL_W16(CPlusCmd, cmd);
3421 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3423 /* Low hurts. Let's disable the filtering. */
3424 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3427 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3429 static const struct {
3434 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3435 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3436 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3437 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3442 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3443 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3444 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3445 RTL_W32(0x7c, p->val);
3451 static void rtl_hw_start_8169(struct net_device *dev)
3453 struct rtl8169_private *tp = netdev_priv(dev);
3454 void __iomem *ioaddr = tp->mmio_addr;
3455 struct pci_dev *pdev = tp->pci_dev;
3457 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3458 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3459 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3462 RTL_W8(Cfg9346, Cfg9346_Unlock);
3463 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3464 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3465 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3466 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3467 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3469 RTL_W8(EarlyTxThres, EarlyTxThld);
3471 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3473 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3474 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3475 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3476 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3477 rtl_set_rx_tx_config_registers(tp);
3479 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3481 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3482 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3483 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3484 "Bit-3 and bit-14 MUST be 1\n");
3485 tp->cp_cmd |= (1 << 14);
3488 RTL_W16(CPlusCmd, tp->cp_cmd);
3490 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3493 * Undocumented corner. Supposedly:
3494 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3496 RTL_W16(IntrMitigate, 0x0000);
3498 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3500 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3501 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3502 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3503 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3504 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3505 rtl_set_rx_tx_config_registers(tp);
3508 RTL_W8(Cfg9346, Cfg9346_Lock);
3510 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3513 RTL_W32(RxMissed, 0);
3515 rtl_set_rx_mode(dev);
3517 /* no early-rx interrupts */
3518 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3520 /* Enable all known interrupts by setting the interrupt mask. */
3521 RTL_W16(IntrMask, tp->intr_event);
3524 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3526 struct net_device *dev = pci_get_drvdata(pdev);
3527 struct rtl8169_private *tp = netdev_priv(dev);
3528 int cap = tp->pcie_cap;
3533 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3534 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3535 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3539 static void rtl_csi_access_enable(void __iomem *ioaddr)
3543 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3544 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3548 unsigned int offset;
3553 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3558 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3559 rtl_ephy_write(ioaddr, e->offset, w);
3564 static void rtl_disable_clock_request(struct pci_dev *pdev)
3566 struct net_device *dev = pci_get_drvdata(pdev);
3567 struct rtl8169_private *tp = netdev_priv(dev);
3568 int cap = tp->pcie_cap;
3573 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3574 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3575 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3579 #define R8168_CPCMD_QUIRK_MASK (\
3590 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3596 rtl_tx_performance_tweak(pdev,
3597 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3600 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3602 rtl_hw_start_8168bb(ioaddr, pdev);
3604 RTL_W8(EarlyTxThres, EarlyTxThld);
3606 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3609 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3611 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3613 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3615 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3617 rtl_disable_clock_request(pdev);
3619 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3622 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3624 static const struct ephy_info e_info_8168cp[] = {
3625 { 0x01, 0, 0x0001 },
3626 { 0x02, 0x0800, 0x1000 },
3627 { 0x03, 0, 0x0042 },
3628 { 0x06, 0x0080, 0x0000 },
3632 rtl_csi_access_enable(ioaddr);
3634 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3636 __rtl_hw_start_8168cp(ioaddr, pdev);
3639 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3641 rtl_csi_access_enable(ioaddr);
3643 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3645 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3647 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3650 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3652 rtl_csi_access_enable(ioaddr);
3654 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3657 RTL_W8(DBG_REG, 0x20);
3659 RTL_W8(EarlyTxThres, EarlyTxThld);
3661 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3663 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3666 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3668 static const struct ephy_info e_info_8168c_1[] = {
3669 { 0x02, 0x0800, 0x1000 },
3670 { 0x03, 0, 0x0002 },
3671 { 0x06, 0x0080, 0x0000 }
3674 rtl_csi_access_enable(ioaddr);
3676 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3678 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3680 __rtl_hw_start_8168cp(ioaddr, pdev);
3683 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3685 static const struct ephy_info e_info_8168c_2[] = {
3686 { 0x01, 0, 0x0001 },
3687 { 0x03, 0x0400, 0x0220 }
3690 rtl_csi_access_enable(ioaddr);
3692 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3694 __rtl_hw_start_8168cp(ioaddr, pdev);
3697 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3699 rtl_hw_start_8168c_2(ioaddr, pdev);
3702 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3704 rtl_csi_access_enable(ioaddr);
3706 __rtl_hw_start_8168cp(ioaddr, pdev);
3709 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3711 rtl_csi_access_enable(ioaddr);
3713 rtl_disable_clock_request(pdev);
3715 RTL_W8(EarlyTxThres, EarlyTxThld);
3717 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3719 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3722 static void rtl_hw_start_8168(struct net_device *dev)
3724 struct rtl8169_private *tp = netdev_priv(dev);
3725 void __iomem *ioaddr = tp->mmio_addr;
3726 struct pci_dev *pdev = tp->pci_dev;
3728 RTL_W8(Cfg9346, Cfg9346_Unlock);
3730 RTL_W8(EarlyTxThres, EarlyTxThld);
3732 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3734 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3736 RTL_W16(CPlusCmd, tp->cp_cmd);
3738 RTL_W16(IntrMitigate, 0x5151);
3740 /* Work around for RxFIFO overflow. */
3741 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3742 tp->intr_event |= RxFIFOOver | PCSTimeout;
3743 tp->intr_event &= ~RxOverflow;
3746 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3748 rtl_set_rx_mode(dev);
3750 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3751 (InterFrameGap << TxInterFrameGapShift));
3755 switch (tp->mac_version) {
3756 case RTL_GIGA_MAC_VER_11:
3757 rtl_hw_start_8168bb(ioaddr, pdev);
3760 case RTL_GIGA_MAC_VER_12:
3761 case RTL_GIGA_MAC_VER_17:
3762 rtl_hw_start_8168bef(ioaddr, pdev);
3765 case RTL_GIGA_MAC_VER_18:
3766 rtl_hw_start_8168cp_1(ioaddr, pdev);
3769 case RTL_GIGA_MAC_VER_19:
3770 rtl_hw_start_8168c_1(ioaddr, pdev);
3773 case RTL_GIGA_MAC_VER_20:
3774 rtl_hw_start_8168c_2(ioaddr, pdev);
3777 case RTL_GIGA_MAC_VER_21:
3778 rtl_hw_start_8168c_3(ioaddr, pdev);
3781 case RTL_GIGA_MAC_VER_22:
3782 rtl_hw_start_8168c_4(ioaddr, pdev);
3785 case RTL_GIGA_MAC_VER_23:
3786 rtl_hw_start_8168cp_2(ioaddr, pdev);
3789 case RTL_GIGA_MAC_VER_24:
3790 rtl_hw_start_8168cp_3(ioaddr, pdev);
3793 case RTL_GIGA_MAC_VER_25:
3794 case RTL_GIGA_MAC_VER_26:
3795 case RTL_GIGA_MAC_VER_27:
3796 rtl_hw_start_8168d(ioaddr, pdev);
3800 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3801 dev->name, tp->mac_version);
3805 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3807 RTL_W8(Cfg9346, Cfg9346_Lock);
3809 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3811 RTL_W16(IntrMask, tp->intr_event);
3814 #define R810X_CPCMD_QUIRK_MASK (\
3826 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3828 static const struct ephy_info e_info_8102e_1[] = {
3829 { 0x01, 0, 0x6e65 },
3830 { 0x02, 0, 0x091f },
3831 { 0x03, 0, 0xc2f9 },
3832 { 0x06, 0, 0xafb5 },
3833 { 0x07, 0, 0x0e00 },
3834 { 0x19, 0, 0xec80 },
3835 { 0x01, 0, 0x2e65 },
3840 rtl_csi_access_enable(ioaddr);
3842 RTL_W8(DBG_REG, FIX_NAK_1);
3844 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3847 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3848 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3850 cfg1 = RTL_R8(Config1);
3851 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3852 RTL_W8(Config1, cfg1 & ~LEDS0);
3854 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3856 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3859 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3861 rtl_csi_access_enable(ioaddr);
3863 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3865 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3866 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3868 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3871 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3873 rtl_hw_start_8102e_2(ioaddr, pdev);
3875 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3878 static void rtl_hw_start_8101(struct net_device *dev)
3880 struct rtl8169_private *tp = netdev_priv(dev);
3881 void __iomem *ioaddr = tp->mmio_addr;
3882 struct pci_dev *pdev = tp->pci_dev;
3884 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3885 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3886 int cap = tp->pcie_cap;
3889 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3890 PCI_EXP_DEVCTL_NOSNOOP_EN);
3894 switch (tp->mac_version) {
3895 case RTL_GIGA_MAC_VER_07:
3896 rtl_hw_start_8102e_1(ioaddr, pdev);
3899 case RTL_GIGA_MAC_VER_08:
3900 rtl_hw_start_8102e_3(ioaddr, pdev);
3903 case RTL_GIGA_MAC_VER_09:
3904 rtl_hw_start_8102e_2(ioaddr, pdev);
3908 RTL_W8(Cfg9346, Cfg9346_Unlock);
3910 RTL_W8(EarlyTxThres, EarlyTxThld);
3912 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3914 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3916 RTL_W16(CPlusCmd, tp->cp_cmd);
3918 RTL_W16(IntrMitigate, 0x0000);
3920 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3922 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3923 rtl_set_rx_tx_config_registers(tp);
3925 RTL_W8(Cfg9346, Cfg9346_Lock);
3929 rtl_set_rx_mode(dev);
3931 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3933 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3935 RTL_W16(IntrMask, tp->intr_event);
3938 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3940 struct rtl8169_private *tp = netdev_priv(dev);
3943 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3948 if (!netif_running(dev))
3953 rtl8169_set_rxbufsize(tp, dev->mtu);
3955 ret = rtl8169_init_ring(dev);
3959 napi_enable(&tp->napi);
3963 rtl8169_request_timer(dev);
3969 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3971 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3972 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3975 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3976 struct sk_buff **sk_buff, struct RxDesc *desc)
3978 struct pci_dev *pdev = tp->pci_dev;
3980 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3981 PCI_DMA_FROMDEVICE);
3982 dev_kfree_skb(*sk_buff);
3984 rtl8169_make_unusable_by_asic(desc);
3987 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3989 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3991 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3994 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3997 desc->addr = cpu_to_le64(mapping);
3999 rtl8169_mark_to_asic(desc, rx_buf_sz);
4002 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
4003 struct net_device *dev,
4004 struct RxDesc *desc, int rx_buf_sz,
4007 struct sk_buff *skb;
4011 pad = align ? align : NET_IP_ALIGN;
4013 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
4017 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
4019 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
4020 PCI_DMA_FROMDEVICE);
4022 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4027 rtl8169_make_unusable_by_asic(desc);
4031 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4035 for (i = 0; i < NUM_RX_DESC; i++) {
4036 if (tp->Rx_skbuff[i]) {
4037 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4038 tp->RxDescArray + i);
4043 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4048 for (cur = start; end - cur != 0; cur++) {
4049 struct sk_buff *skb;
4050 unsigned int i = cur % NUM_RX_DESC;
4052 WARN_ON((s32)(end - cur) < 0);
4054 if (tp->Rx_skbuff[i])
4057 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4058 tp->RxDescArray + i,
4059 tp->rx_buf_sz, tp->align);
4063 tp->Rx_skbuff[i] = skb;
4068 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4070 desc->opts1 |= cpu_to_le32(RingEnd);
4073 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4075 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4078 static int rtl8169_init_ring(struct net_device *dev)
4080 struct rtl8169_private *tp = netdev_priv(dev);
4082 rtl8169_init_ring_indexes(tp);
4084 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4085 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4087 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4090 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4095 rtl8169_rx_clear(tp);
4099 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4100 struct TxDesc *desc)
4102 unsigned int len = tx_skb->len;
4104 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4111 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4115 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4116 unsigned int entry = i % NUM_TX_DESC;
4117 struct ring_info *tx_skb = tp->tx_skb + entry;
4118 unsigned int len = tx_skb->len;
4121 struct sk_buff *skb = tx_skb->skb;
4123 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4124 tp->TxDescArray + entry);
4129 tp->dev->stats.tx_dropped++;
4132 tp->cur_tx = tp->dirty_tx = 0;
4135 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4137 struct rtl8169_private *tp = netdev_priv(dev);
4139 PREPARE_DELAYED_WORK(&tp->task, task);
4140 schedule_delayed_work(&tp->task, 4);
4143 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4145 struct rtl8169_private *tp = netdev_priv(dev);
4146 void __iomem *ioaddr = tp->mmio_addr;
4148 synchronize_irq(dev->irq);
4150 /* Wait for any pending NAPI task to complete */
4151 napi_disable(&tp->napi);
4153 rtl8169_irq_mask_and_ack(ioaddr);
4155 tp->intr_mask = 0xffff;
4156 RTL_W16(IntrMask, tp->intr_event);
4157 napi_enable(&tp->napi);
4160 static void rtl8169_reinit_task(struct work_struct *work)
4162 struct rtl8169_private *tp =
4163 container_of(work, struct rtl8169_private, task.work);
4164 struct net_device *dev = tp->dev;
4169 if (!netif_running(dev))
4172 rtl8169_wait_for_quiescence(dev);
4175 ret = rtl8169_open(dev);
4176 if (unlikely(ret < 0)) {
4177 if (net_ratelimit())
4178 netif_err(tp, drv, dev,
4179 "reinit failure (status = %d). Rescheduling\n",
4181 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4188 static void rtl8169_reset_task(struct work_struct *work)
4190 struct rtl8169_private *tp =
4191 container_of(work, struct rtl8169_private, task.work);
4192 struct net_device *dev = tp->dev;
4196 if (!netif_running(dev))
4199 rtl8169_wait_for_quiescence(dev);
4201 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4202 rtl8169_tx_clear(tp);
4204 if (tp->dirty_rx == tp->cur_rx) {
4205 rtl8169_init_ring_indexes(tp);
4207 netif_wake_queue(dev);
4208 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4210 if (net_ratelimit())
4211 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4212 rtl8169_schedule_work(dev, rtl8169_reset_task);
4219 static void rtl8169_tx_timeout(struct net_device *dev)
4221 struct rtl8169_private *tp = netdev_priv(dev);
4223 rtl8169_hw_reset(tp->mmio_addr);
4225 /* Let's wait a bit while any (async) irq lands on */
4226 rtl8169_schedule_work(dev, rtl8169_reset_task);
4229 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4232 struct skb_shared_info *info = skb_shinfo(skb);
4233 unsigned int cur_frag, entry;
4234 struct TxDesc * uninitialized_var(txd);
4237 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4238 skb_frag_t *frag = info->frags + cur_frag;
4243 entry = (entry + 1) % NUM_TX_DESC;
4245 txd = tp->TxDescArray + entry;
4247 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4248 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4250 /* anti gcc 2.95.3 bugware (sic) */
4251 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4253 txd->opts1 = cpu_to_le32(status);
4254 txd->addr = cpu_to_le64(mapping);
4256 tp->tx_skb[entry].len = len;
4260 tp->tx_skb[entry].skb = skb;
4261 txd->opts1 |= cpu_to_le32(LastFrag);
4267 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4269 if (dev->features & NETIF_F_TSO) {
4270 u32 mss = skb_shinfo(skb)->gso_size;
4273 return LargeSend | ((mss & MSSMask) << MSSShift);
4275 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4276 const struct iphdr *ip = ip_hdr(skb);
4278 if (ip->protocol == IPPROTO_TCP)
4279 return IPCS | TCPCS;
4280 else if (ip->protocol == IPPROTO_UDP)
4281 return IPCS | UDPCS;
4282 WARN_ON(1); /* we need a WARN() */
4287 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4288 struct net_device *dev)
4290 struct rtl8169_private *tp = netdev_priv(dev);
4291 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4292 struct TxDesc *txd = tp->TxDescArray + entry;
4293 void __iomem *ioaddr = tp->mmio_addr;
4298 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4299 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4303 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4306 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4308 frags = rtl8169_xmit_frags(tp, skb, opts1);
4310 len = skb_headlen(skb);
4314 opts1 |= FirstFrag | LastFrag;
4315 tp->tx_skb[entry].skb = skb;
4318 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4320 tp->tx_skb[entry].len = len;
4321 txd->addr = cpu_to_le64(mapping);
4322 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4326 /* anti gcc 2.95.3 bugware (sic) */
4327 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4328 txd->opts1 = cpu_to_le32(status);
4330 tp->cur_tx += frags + 1;
4334 RTL_W8(TxPoll, NPQ); /* set polling bit */
4336 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4337 netif_stop_queue(dev);
4339 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4340 netif_wake_queue(dev);
4343 return NETDEV_TX_OK;
4346 netif_stop_queue(dev);
4347 dev->stats.tx_dropped++;
4348 return NETDEV_TX_BUSY;
4351 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4353 struct rtl8169_private *tp = netdev_priv(dev);
4354 struct pci_dev *pdev = tp->pci_dev;
4355 void __iomem *ioaddr = tp->mmio_addr;
4356 u16 pci_status, pci_cmd;
4358 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4359 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4361 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4362 pci_cmd, pci_status);
4365 * The recovery sequence below admits a very elaborated explanation:
4366 * - it seems to work;
4367 * - I did not see what else could be done;
4368 * - it makes iop3xx happy.
4370 * Feel free to adjust to your needs.
4372 if (pdev->broken_parity_status)
4373 pci_cmd &= ~PCI_COMMAND_PARITY;
4375 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4377 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4379 pci_write_config_word(pdev, PCI_STATUS,
4380 pci_status & (PCI_STATUS_DETECTED_PARITY |
4381 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4382 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4384 /* The infamous DAC f*ckup only happens at boot time */
4385 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4386 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4387 tp->cp_cmd &= ~PCIDAC;
4388 RTL_W16(CPlusCmd, tp->cp_cmd);
4389 dev->features &= ~NETIF_F_HIGHDMA;
4392 rtl8169_hw_reset(ioaddr);
4394 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4397 static void rtl8169_tx_interrupt(struct net_device *dev,
4398 struct rtl8169_private *tp,
4399 void __iomem *ioaddr)
4401 unsigned int dirty_tx, tx_left;
4403 dirty_tx = tp->dirty_tx;
4405 tx_left = tp->cur_tx - dirty_tx;
4407 while (tx_left > 0) {
4408 unsigned int entry = dirty_tx % NUM_TX_DESC;
4409 struct ring_info *tx_skb = tp->tx_skb + entry;
4410 u32 len = tx_skb->len;
4414 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4415 if (status & DescOwn)
4418 dev->stats.tx_bytes += len;
4419 dev->stats.tx_packets++;
4421 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4423 if (status & LastFrag) {
4424 dev_kfree_skb(tx_skb->skb);
4431 if (tp->dirty_tx != dirty_tx) {
4432 tp->dirty_tx = dirty_tx;
4434 if (netif_queue_stopped(dev) &&
4435 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4436 netif_wake_queue(dev);
4439 * 8168 hack: TxPoll requests are lost when the Tx packets are
4440 * too close. Let's kick an extra TxPoll request when a burst
4441 * of start_xmit activity is detected (if it is not detected,
4442 * it is slow enough). -- FR
4445 if (tp->cur_tx != dirty_tx)
4446 RTL_W8(TxPoll, NPQ);
4450 static inline int rtl8169_fragmented_frame(u32 status)
4452 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4455 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4457 u32 opts1 = le32_to_cpu(desc->opts1);
4458 u32 status = opts1 & RxProtoMask;
4460 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4461 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4462 ((status == RxProtoIP) && !(opts1 & IPFail)))
4463 skb->ip_summed = CHECKSUM_UNNECESSARY;
4465 skb->ip_summed = CHECKSUM_NONE;
4468 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4469 struct rtl8169_private *tp, int pkt_size,
4472 struct sk_buff *skb;
4475 if (pkt_size >= rx_copybreak)
4478 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4482 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4483 PCI_DMA_FROMDEVICE);
4484 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4492 * Warning : rtl8169_rx_interrupt() might be called :
4493 * 1) from NAPI (softirq) context
4494 * (polling = 1 : we should call netif_receive_skb())
4495 * 2) from process context (rtl8169_reset_task())
4496 * (polling = 0 : we must call netif_rx() instead)
4498 static int rtl8169_rx_interrupt(struct net_device *dev,
4499 struct rtl8169_private *tp,
4500 void __iomem *ioaddr, u32 budget)
4502 unsigned int cur_rx, rx_left;
4503 unsigned int delta, count;
4504 int polling = (budget != ~(u32)0) ? 1 : 0;
4506 cur_rx = tp->cur_rx;
4507 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4508 rx_left = min(rx_left, budget);
4510 for (; rx_left > 0; rx_left--, cur_rx++) {
4511 unsigned int entry = cur_rx % NUM_RX_DESC;
4512 struct RxDesc *desc = tp->RxDescArray + entry;
4516 status = le32_to_cpu(desc->opts1);
4518 if (status & DescOwn)
4520 if (unlikely(status & RxRES)) {
4521 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4523 dev->stats.rx_errors++;
4524 if (status & (RxRWT | RxRUNT))
4525 dev->stats.rx_length_errors++;
4527 dev->stats.rx_crc_errors++;
4528 if (status & RxFOVF) {
4529 rtl8169_schedule_work(dev, rtl8169_reset_task);
4530 dev->stats.rx_fifo_errors++;
4532 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4534 struct sk_buff *skb = tp->Rx_skbuff[entry];
4535 dma_addr_t addr = le64_to_cpu(desc->addr);
4536 int pkt_size = (status & 0x00001FFF) - 4;
4537 struct pci_dev *pdev = tp->pci_dev;
4540 * The driver does not support incoming fragmented
4541 * frames. They are seen as a symptom of over-mtu
4544 if (unlikely(rtl8169_fragmented_frame(status))) {
4545 dev->stats.rx_dropped++;
4546 dev->stats.rx_length_errors++;
4547 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4551 rtl8169_rx_csum(skb, desc);
4553 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4554 pci_dma_sync_single_for_device(pdev, addr,
4555 pkt_size, PCI_DMA_FROMDEVICE);
4556 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4558 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4559 PCI_DMA_FROMDEVICE);
4560 tp->Rx_skbuff[entry] = NULL;
4563 skb_put(skb, pkt_size);
4564 skb->protocol = eth_type_trans(skb, dev);
4566 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4567 if (likely(polling))
4568 netif_receive_skb(skb);
4573 dev->stats.rx_bytes += pkt_size;
4574 dev->stats.rx_packets++;
4577 /* Work around for AMD plateform. */
4578 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4579 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4585 count = cur_rx - tp->cur_rx;
4586 tp->cur_rx = cur_rx;
4588 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4589 if (!delta && count)
4590 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4591 tp->dirty_rx += delta;
4594 * FIXME: until there is periodic timer to try and refill the ring,
4595 * a temporary shortage may definitely kill the Rx process.
4596 * - disable the asic to try and avoid an overflow and kick it again
4598 * - how do others driver handle this condition (Uh oh...).
4600 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4601 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4606 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4608 struct net_device *dev = dev_instance;
4609 struct rtl8169_private *tp = netdev_priv(dev);
4610 void __iomem *ioaddr = tp->mmio_addr;
4614 /* loop handling interrupts until we have no new ones or
4615 * we hit a invalid/hotplug case.
4617 status = RTL_R16(IntrStatus);
4618 while (status && status != 0xffff) {
4621 /* Handle all of the error cases first. These will reset
4622 * the chip, so just exit the loop.
4624 if (unlikely(!netif_running(dev))) {
4625 rtl8169_asic_down(ioaddr);
4629 /* Work around for rx fifo overflow */
4630 if (unlikely(status & RxFIFOOver) &&
4631 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4632 netif_stop_queue(dev);
4633 rtl8169_tx_timeout(dev);
4637 if (unlikely(status & SYSErr)) {
4638 rtl8169_pcierr_interrupt(dev);
4642 if (status & LinkChg)
4643 rtl8169_check_link_status(dev, tp, ioaddr);
4645 /* We need to see the lastest version of tp->intr_mask to
4646 * avoid ignoring an MSI interrupt and having to wait for
4647 * another event which may never come.
4650 if (status & tp->intr_mask & tp->napi_event) {
4651 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4652 tp->intr_mask = ~tp->napi_event;
4654 if (likely(napi_schedule_prep(&tp->napi)))
4655 __napi_schedule(&tp->napi);
4657 netif_info(tp, intr, dev,
4658 "interrupt %04x in poll\n", status);
4661 /* We only get a new MSI interrupt when all active irq
4662 * sources on the chip have been acknowledged. So, ack
4663 * everything we've seen and check if new sources have become
4664 * active to avoid blocking all interrupts from the chip.
4667 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4668 status = RTL_R16(IntrStatus);
4671 return IRQ_RETVAL(handled);
4674 static int rtl8169_poll(struct napi_struct *napi, int budget)
4676 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4677 struct net_device *dev = tp->dev;
4678 void __iomem *ioaddr = tp->mmio_addr;
4681 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4682 rtl8169_tx_interrupt(dev, tp, ioaddr);
4684 if (work_done < budget) {
4685 napi_complete(napi);
4687 /* We need for force the visibility of tp->intr_mask
4688 * for other CPUs, as we can loose an MSI interrupt
4689 * and potentially wait for a retransmit timeout if we don't.
4690 * The posted write to IntrMask is safe, as it will
4691 * eventually make it to the chip and we won't loose anything
4694 tp->intr_mask = 0xffff;
4696 RTL_W16(IntrMask, tp->intr_event);
4702 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4704 struct rtl8169_private *tp = netdev_priv(dev);
4706 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4709 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4710 RTL_W32(RxMissed, 0);
4713 static void rtl8169_down(struct net_device *dev)
4715 struct rtl8169_private *tp = netdev_priv(dev);
4716 void __iomem *ioaddr = tp->mmio_addr;
4717 unsigned int intrmask;
4719 rtl8169_delete_timer(dev);
4721 netif_stop_queue(dev);
4723 napi_disable(&tp->napi);
4726 spin_lock_irq(&tp->lock);
4728 rtl8169_asic_down(ioaddr);
4730 rtl8169_rx_missed(dev, ioaddr);
4732 spin_unlock_irq(&tp->lock);
4734 synchronize_irq(dev->irq);
4736 /* Give a racing hard_start_xmit a few cycles to complete. */
4737 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4740 * And now for the 50k$ question: are IRQ disabled or not ?
4742 * Two paths lead here:
4744 * -> netif_running() is available to sync the current code and the
4745 * IRQ handler. See rtl8169_interrupt for details.
4746 * 2) dev->change_mtu
4747 * -> rtl8169_poll can not be issued again and re-enable the
4748 * interruptions. Let's simply issue the IRQ down sequence again.
4750 * No loop if hotpluged or major error (0xffff).
4752 intrmask = RTL_R16(IntrMask);
4753 if (intrmask && (intrmask != 0xffff))
4756 rtl8169_tx_clear(tp);
4758 rtl8169_rx_clear(tp);
4761 static int rtl8169_close(struct net_device *dev)
4763 struct rtl8169_private *tp = netdev_priv(dev);
4764 struct pci_dev *pdev = tp->pci_dev;
4766 pm_runtime_get_sync(&pdev->dev);
4768 /* update counters before going down */
4769 rtl8169_update_counters(dev);
4773 free_irq(dev->irq, dev);
4775 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4777 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4779 tp->TxDescArray = NULL;
4780 tp->RxDescArray = NULL;
4782 pm_runtime_put_sync(&pdev->dev);
4787 static void rtl_set_rx_mode(struct net_device *dev)
4789 struct rtl8169_private *tp = netdev_priv(dev);
4790 void __iomem *ioaddr = tp->mmio_addr;
4791 unsigned long flags;
4792 u32 mc_filter[2]; /* Multicast hash filter */
4796 if (dev->flags & IFF_PROMISC) {
4797 /* Unconditionally log net taps. */
4798 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4800 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4802 mc_filter[1] = mc_filter[0] = 0xffffffff;
4803 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4804 (dev->flags & IFF_ALLMULTI)) {
4805 /* Too many to filter perfectly -- accept all multicasts. */
4806 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4807 mc_filter[1] = mc_filter[0] = 0xffffffff;
4809 struct netdev_hw_addr *ha;
4811 rx_mode = AcceptBroadcast | AcceptMyPhys;
4812 mc_filter[1] = mc_filter[0] = 0;
4813 netdev_for_each_mc_addr(ha, dev) {
4814 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4815 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4816 rx_mode |= AcceptMulticast;
4820 spin_lock_irqsave(&tp->lock, flags);
4822 tmp = rtl8169_rx_config | rx_mode |
4823 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4825 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4826 u32 data = mc_filter[0];
4828 mc_filter[0] = swab32(mc_filter[1]);
4829 mc_filter[1] = swab32(data);
4832 RTL_W32(MAR0 + 4, mc_filter[1]);
4833 RTL_W32(MAR0 + 0, mc_filter[0]);
4835 RTL_W32(RxConfig, tmp);
4837 spin_unlock_irqrestore(&tp->lock, flags);
4841 * rtl8169_get_stats - Get rtl8169 read/write statistics
4842 * @dev: The Ethernet Device to get statistics for
4844 * Get TX/RX statistics for rtl8169
4846 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4848 struct rtl8169_private *tp = netdev_priv(dev);
4849 void __iomem *ioaddr = tp->mmio_addr;
4850 unsigned long flags;
4852 if (netif_running(dev)) {
4853 spin_lock_irqsave(&tp->lock, flags);
4854 rtl8169_rx_missed(dev, ioaddr);
4855 spin_unlock_irqrestore(&tp->lock, flags);
4861 static void rtl8169_net_suspend(struct net_device *dev)
4863 if (!netif_running(dev))
4866 netif_device_detach(dev);
4867 netif_stop_queue(dev);
4872 static int rtl8169_suspend(struct device *device)
4874 struct pci_dev *pdev = to_pci_dev(device);
4875 struct net_device *dev = pci_get_drvdata(pdev);
4877 rtl8169_net_suspend(dev);
4882 static void __rtl8169_resume(struct net_device *dev)
4884 netif_device_attach(dev);
4885 rtl8169_schedule_work(dev, rtl8169_reset_task);
4888 static int rtl8169_resume(struct device *device)
4890 struct pci_dev *pdev = to_pci_dev(device);
4891 struct net_device *dev = pci_get_drvdata(pdev);
4893 if (netif_running(dev))
4894 __rtl8169_resume(dev);
4899 static int rtl8169_runtime_suspend(struct device *device)
4901 struct pci_dev *pdev = to_pci_dev(device);
4902 struct net_device *dev = pci_get_drvdata(pdev);
4903 struct rtl8169_private *tp = netdev_priv(dev);
4905 if (!tp->TxDescArray)
4908 spin_lock_irq(&tp->lock);
4909 tp->saved_wolopts = __rtl8169_get_wol(tp);
4910 __rtl8169_set_wol(tp, WAKE_ANY);
4911 spin_unlock_irq(&tp->lock);
4913 rtl8169_net_suspend(dev);
4918 static int rtl8169_runtime_resume(struct device *device)
4920 struct pci_dev *pdev = to_pci_dev(device);
4921 struct net_device *dev = pci_get_drvdata(pdev);
4922 struct rtl8169_private *tp = netdev_priv(dev);
4924 if (!tp->TxDescArray)
4927 spin_lock_irq(&tp->lock);
4928 __rtl8169_set_wol(tp, tp->saved_wolopts);
4929 tp->saved_wolopts = 0;
4930 spin_unlock_irq(&tp->lock);
4932 __rtl8169_resume(dev);
4937 static int rtl8169_runtime_idle(struct device *device)
4939 struct pci_dev *pdev = to_pci_dev(device);
4940 struct net_device *dev = pci_get_drvdata(pdev);
4941 struct rtl8169_private *tp = netdev_priv(dev);
4943 if (!tp->TxDescArray)
4946 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4950 static const struct dev_pm_ops rtl8169_pm_ops = {
4951 .suspend = rtl8169_suspend,
4952 .resume = rtl8169_resume,
4953 .freeze = rtl8169_suspend,
4954 .thaw = rtl8169_resume,
4955 .poweroff = rtl8169_suspend,
4956 .restore = rtl8169_resume,
4957 .runtime_suspend = rtl8169_runtime_suspend,
4958 .runtime_resume = rtl8169_runtime_resume,
4959 .runtime_idle = rtl8169_runtime_idle,
4962 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4964 #else /* !CONFIG_PM */
4966 #define RTL8169_PM_OPS NULL
4968 #endif /* !CONFIG_PM */
4970 static void rtl_shutdown(struct pci_dev *pdev)
4972 struct net_device *dev = pci_get_drvdata(pdev);
4973 struct rtl8169_private *tp = netdev_priv(dev);
4974 void __iomem *ioaddr = tp->mmio_addr;
4976 rtl8169_net_suspend(dev);
4978 /* restore original MAC address */
4979 rtl_rar_set(tp, dev->perm_addr);
4981 spin_lock_irq(&tp->lock);
4983 rtl8169_asic_down(ioaddr);
4985 spin_unlock_irq(&tp->lock);
4987 if (system_state == SYSTEM_POWER_OFF) {
4988 /* WoL fails with some 8168 when the receiver is disabled. */
4989 if (tp->features & RTL_FEATURE_WOL) {
4990 pci_clear_master(pdev);
4992 RTL_W8(ChipCmd, CmdRxEnb);
4997 pci_wake_from_d3(pdev, true);
4998 pci_set_power_state(pdev, PCI_D3hot);
5002 static struct pci_driver rtl8169_pci_driver = {
5004 .id_table = rtl8169_pci_tbl,
5005 .probe = rtl8169_init_one,
5006 .remove = __devexit_p(rtl8169_remove_one),
5007 .shutdown = rtl_shutdown,
5008 .driver.pm = RTL8169_PM_OPS,
5011 static int __init rtl8169_init_module(void)
5013 return pci_register_driver(&rtl8169_pci_driver);
5016 static void __exit rtl8169_cleanup_module(void)
5018 pci_unregister_driver(&rtl8169_pci_driver);
5021 module_init(rtl8169_init_module);
5022 module_exit(rtl8169_cleanup_module);