2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit = 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE = 0x00,
94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126 static const struct {
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130 } rtl_chip_info[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
167 static void rtl_hw_start_8169(struct net_device *);
168 static void rtl_hw_start_8168(struct net_device *);
169 static void rtl_hw_start_8101(struct net_device *);
171 static struct pci_device_id rtl8169_pci_tbl[] = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189 static int rx_copybreak = 200;
196 MAC0 = 0, /* Ethernet hardware address. */
198 MAR0 = 8, /* Multicast filter. */
199 CounterAddrLow = 0x10,
200 CounterAddrHigh = 0x14,
201 TxDescStartAddrLow = 0x20,
202 TxDescStartAddrHigh = 0x24,
203 TxHDescStartAddrLow = 0x28,
204 TxHDescStartAddrHigh = 0x2c,
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
231 FuncEventMask = 0xf4,
232 FuncPresetState = 0xf8,
233 FuncForceEvent = 0xfc,
236 enum rtl8110_registers {
242 enum rtl8168_8101_registers {
245 #define CSIAR_FLAG 0x80000000
246 #define CSIAR_WRITE_CMD 0x80000000
247 #define CSIAR_BYTE_ENABLE 0x0f
248 #define CSIAR_BYTE_ENABLE_SHIFT 12
249 #define CSIAR_ADDR_MASK 0x0fff
252 #define EPHYAR_FLAG 0x80000000
253 #define EPHYAR_WRITE_CMD 0x80000000
254 #define EPHYAR_REG_MASK 0x1f
255 #define EPHYAR_REG_SHIFT 16
256 #define EPHYAR_DATA_MASK 0xffff
258 #define FIX_NAK_1 (1 << 4)
259 #define FIX_NAK_2 (1 << 3)
261 #define EFUSEAR_FLAG 0x80000000
262 #define EFUSEAR_WRITE_CMD 0x80000000
263 #define EFUSEAR_READ_CMD 0x00000000
264 #define EFUSEAR_REG_MASK 0x03ff
265 #define EFUSEAR_REG_SHIFT 8
266 #define EFUSEAR_DATA_MASK 0xff
269 enum rtl_register_content {
270 /* InterruptStatusBits */
274 TxDescUnavail = 0x0080,
296 /* TXPoll register p.5 */
297 HPQ = 0x80, /* Poll cmd on the high prio queue */
298 NPQ = 0x40, /* Poll cmd on the low prio queue */
299 FSWInt = 0x01, /* Forced software interrupt */
303 Cfg9346_Unlock = 0xc0,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
311 AcceptAllPhys = 0x01,
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321 /* Config1 register p.24 */
324 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
325 Speed_down = (1 << 4),
329 PMEnable = (1 << 0), /* Power Management Enable */
331 /* Config2 register p. 25 */
332 PCI_Clock_66MHz = 0x01,
333 PCI_Clock_33MHz = 0x00,
335 /* Config3 register p.25 */
336 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
337 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
338 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
340 /* Config5 register p.27 */
341 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
342 MWF = (1 << 5), /* Accept Multicast wakeup frame */
343 UWF = (1 << 4), /* Accept Unicast wakeup frame */
344 LanWake = (1 << 1), /* LanWake enable/disable */
345 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
348 TBIReset = 0x80000000,
349 TBILoopback = 0x40000000,
350 TBINwEnable = 0x20000000,
351 TBINwRestart = 0x10000000,
352 TBILinkOk = 0x02000000,
353 TBINwComplete = 0x01000000,
356 EnableBist = (1 << 15), // 8168 8101
357 Mac_dbgo_oe = (1 << 14), // 8168 8101
358 Normal_mode = (1 << 13), // unused
359 Force_half_dup = (1 << 12), // 8168 8101
360 Force_rxflow_en = (1 << 11), // 8168 8101
361 Force_txflow_en = (1 << 10), // 8168 8101
362 Cxpl_dbg_sel = (1 << 9), // 8168 8101
363 ASF = (1 << 8), // 8168 8101
364 PktCntrDisable = (1 << 7), // 8168 8101
365 Mac_dbgo_sel = 0x001c, // 8168
370 INTT_0 = 0x0000, // 8168
371 INTT_1 = 0x0001, // 8168
372 INTT_2 = 0x0002, // 8168
373 INTT_3 = 0x0003, // 8168
375 /* rtl8169_PHYstatus */
386 TBILinkOK = 0x02000000,
388 /* DumpCounterCommand */
392 enum desc_status_bit {
393 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
394 RingEnd = (1 << 30), /* End of descriptor ring */
395 FirstFrag = (1 << 29), /* First segment of a packet */
396 LastFrag = (1 << 28), /* Final segment of a packet */
399 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
400 MSSShift = 16, /* MSS value position */
401 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
402 IPCS = (1 << 18), /* Calculate IP checksum */
403 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
404 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
405 TxVlanTag = (1 << 17), /* Add VLAN tag */
408 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
409 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
411 #define RxProtoUDP (PID1)
412 #define RxProtoTCP (PID0)
413 #define RxProtoIP (PID1 | PID0)
414 #define RxProtoMask RxProtoIP
416 IPFail = (1 << 16), /* IP checksum failed */
417 UDPFail = (1 << 15), /* UDP/IP checksum failed */
418 TCPFail = (1 << 14), /* TCP/IP checksum failed */
419 RxVlanTag = (1 << 16), /* VLAN tag available */
422 #define RsvdMask 0x3fffc000
439 u8 __pad[sizeof(void *) - sizeof(u32)];
443 RTL_FEATURE_WOL = (1 << 0),
444 RTL_FEATURE_MSI = (1 << 1),
445 RTL_FEATURE_GMII = (1 << 2),
448 struct rtl8169_counters {
455 __le32 tx_one_collision;
456 __le32 tx_multi_collision;
464 struct rtl8169_private {
465 void __iomem *mmio_addr; /* memory map physical address */
466 struct pci_dev *pci_dev; /* Index of PCI device */
467 struct net_device *dev;
468 struct napi_struct napi;
469 spinlock_t lock; /* spin lock flag */
473 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
477 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
478 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
479 dma_addr_t TxPhyAddr;
480 dma_addr_t RxPhyAddr;
481 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
485 struct timer_list timer;
490 int phy_1000_ctrl_reg;
491 #ifdef CONFIG_R8169_VLAN
492 struct vlan_group *vlgrp;
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
495 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
496 void (*phy_reset_enable)(void __iomem *);
497 void (*hw_start)(struct net_device *);
498 unsigned int (*phy_reset_pending)(void __iomem *);
499 unsigned int (*link_ok)(void __iomem *);
500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
502 struct delayed_work task;
505 struct mii_if_info mii;
506 struct rtl8169_counters counters;
509 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
510 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
511 module_param(rx_copybreak, int, 0);
512 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
513 module_param(use_dac, int, 0);
514 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
515 module_param_named(debug, debug.msg_enable, int, 0);
516 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
517 MODULE_LICENSE("GPL");
518 MODULE_VERSION(RTL8169_VERSION);
520 static int rtl8169_open(struct net_device *dev);
521 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
522 struct net_device *dev);
523 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
524 static int rtl8169_init_ring(struct net_device *dev);
525 static void rtl_hw_start(struct net_device *dev);
526 static int rtl8169_close(struct net_device *dev);
527 static void rtl_set_rx_mode(struct net_device *dev);
528 static void rtl8169_tx_timeout(struct net_device *dev);
529 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
530 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
531 void __iomem *, u32 budget);
532 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
533 static void rtl8169_down(struct net_device *dev);
534 static void rtl8169_rx_clear(struct rtl8169_private *tp);
535 static int rtl8169_poll(struct napi_struct *napi, int budget);
537 static const unsigned int rtl8169_rx_config =
538 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
540 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
544 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
546 for (i = 20; i > 0; i--) {
548 * Check if the RTL8169 has completed writing to the specified
551 if (!(RTL_R32(PHYAR) & 0x80000000))
557 static int mdio_read(void __iomem *ioaddr, int reg_addr)
561 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
563 for (i = 20; i > 0; i--) {
565 * Check if the RTL8169 has completed retrieving data from
566 * the specified MII register.
568 if (RTL_R32(PHYAR) & 0x80000000) {
569 value = RTL_R32(PHYAR) & 0xffff;
577 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
579 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
582 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
586 val = mdio_read(ioaddr, reg_addr);
587 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
590 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
593 struct rtl8169_private *tp = netdev_priv(dev);
594 void __iomem *ioaddr = tp->mmio_addr;
596 mdio_write(ioaddr, location, val);
599 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
601 struct rtl8169_private *tp = netdev_priv(dev);
602 void __iomem *ioaddr = tp->mmio_addr;
604 return mdio_read(ioaddr, location);
607 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
611 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
612 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
614 for (i = 0; i < 100; i++) {
615 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
621 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
626 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
628 for (i = 0; i < 100; i++) {
629 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
630 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
639 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
643 RTL_W32(CSIDR, value);
644 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
645 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
647 for (i = 0; i < 100; i++) {
648 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
654 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
659 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
660 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
662 for (i = 0; i < 100; i++) {
663 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
664 value = RTL_R32(CSIDR);
673 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
678 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
680 for (i = 0; i < 300; i++) {
681 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
682 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
691 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
693 RTL_W16(IntrMask, 0x0000);
695 RTL_W16(IntrStatus, 0xffff);
698 static void rtl8169_asic_down(void __iomem *ioaddr)
700 RTL_W8(ChipCmd, 0x00);
701 rtl8169_irq_mask_and_ack(ioaddr);
705 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
707 return RTL_R32(TBICSR) & TBIReset;
710 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
712 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
715 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
717 return RTL_R32(TBICSR) & TBILinkOk;
720 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
722 return RTL_R8(PHYstatus) & LinkStatus;
725 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
727 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
730 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
734 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
735 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
738 static void rtl8169_check_link_status(struct net_device *dev,
739 struct rtl8169_private *tp,
740 void __iomem *ioaddr)
744 spin_lock_irqsave(&tp->lock, flags);
745 if (tp->link_ok(ioaddr)) {
746 netif_carrier_on(dev);
747 if (netif_msg_ifup(tp))
748 printk(KERN_INFO PFX "%s: link up\n", dev->name);
750 if (netif_msg_ifdown(tp))
751 printk(KERN_INFO PFX "%s: link down\n", dev->name);
752 netif_carrier_off(dev);
754 spin_unlock_irqrestore(&tp->lock, flags);
757 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
765 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
766 wol->supported = WAKE_ANY;
768 spin_lock_irq(&tp->lock);
770 options = RTL_R8(Config1);
771 if (!(options & PMEnable))
774 options = RTL_R8(Config3);
775 if (options & LinkUp)
776 wol->wolopts |= WAKE_PHY;
777 if (options & MagicPacket)
778 wol->wolopts |= WAKE_MAGIC;
780 options = RTL_R8(Config5);
782 wol->wolopts |= WAKE_UCAST;
784 wol->wolopts |= WAKE_BCAST;
786 wol->wolopts |= WAKE_MCAST;
789 spin_unlock_irq(&tp->lock);
792 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
794 struct rtl8169_private *tp = netdev_priv(dev);
795 void __iomem *ioaddr = tp->mmio_addr;
802 { WAKE_ANY, Config1, PMEnable },
803 { WAKE_PHY, Config3, LinkUp },
804 { WAKE_MAGIC, Config3, MagicPacket },
805 { WAKE_UCAST, Config5, UWF },
806 { WAKE_BCAST, Config5, BWF },
807 { WAKE_MCAST, Config5, MWF },
808 { WAKE_ANY, Config5, LanWake }
811 spin_lock_irq(&tp->lock);
813 RTL_W8(Cfg9346, Cfg9346_Unlock);
815 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
816 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
817 if (wol->wolopts & cfg[i].opt)
818 options |= cfg[i].mask;
819 RTL_W8(cfg[i].reg, options);
822 RTL_W8(Cfg9346, Cfg9346_Lock);
825 tp->features |= RTL_FEATURE_WOL;
827 tp->features &= ~RTL_FEATURE_WOL;
828 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
830 spin_unlock_irq(&tp->lock);
835 static void rtl8169_get_drvinfo(struct net_device *dev,
836 struct ethtool_drvinfo *info)
838 struct rtl8169_private *tp = netdev_priv(dev);
840 strcpy(info->driver, MODULENAME);
841 strcpy(info->version, RTL8169_VERSION);
842 strcpy(info->bus_info, pci_name(tp->pci_dev));
845 static int rtl8169_get_regs_len(struct net_device *dev)
847 return R8169_REGS_SIZE;
850 static int rtl8169_set_speed_tbi(struct net_device *dev,
851 u8 autoneg, u16 speed, u8 duplex)
853 struct rtl8169_private *tp = netdev_priv(dev);
854 void __iomem *ioaddr = tp->mmio_addr;
858 reg = RTL_R32(TBICSR);
859 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
860 (duplex == DUPLEX_FULL)) {
861 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
862 } else if (autoneg == AUTONEG_ENABLE)
863 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
865 if (netif_msg_link(tp)) {
866 printk(KERN_WARNING "%s: "
867 "incorrect speed setting refused in TBI mode\n",
876 static int rtl8169_set_speed_xmii(struct net_device *dev,
877 u8 autoneg, u16 speed, u8 duplex)
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
883 if (autoneg == AUTONEG_ENABLE) {
886 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
887 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888 ADVERTISE_100HALF | ADVERTISE_100FULL);
889 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
891 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
894 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
904 } else if (netif_msg_link(tp)) {
905 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
909 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
916 * Vendor specific (0x1f) and reserved (0x0e) MII
919 mdio_write(ioaddr, 0x1f, 0x0000);
920 mdio_write(ioaddr, 0x0e, 0x0000);
923 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
928 if (speed == SPEED_10)
930 else if (speed == SPEED_100)
931 bmcr = BMCR_SPEED100;
935 if (duplex == DUPLEX_FULL)
936 bmcr |= BMCR_FULLDPLX;
938 mdio_write(ioaddr, 0x1f, 0x0000);
941 tp->phy_1000_ctrl_reg = giga_ctrl;
943 mdio_write(ioaddr, MII_BMCR, bmcr);
945 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948 mdio_write(ioaddr, 0x17, 0x2138);
949 mdio_write(ioaddr, 0x0e, 0x0260);
951 mdio_write(ioaddr, 0x17, 0x2108);
952 mdio_write(ioaddr, 0x0e, 0x0000);
959 static int rtl8169_set_speed(struct net_device *dev,
960 u8 autoneg, u16 speed, u8 duplex)
962 struct rtl8169_private *tp = netdev_priv(dev);
965 ret = tp->set_speed(dev, autoneg, speed, duplex);
967 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
968 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
973 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
975 struct rtl8169_private *tp = netdev_priv(dev);
979 spin_lock_irqsave(&tp->lock, flags);
980 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981 spin_unlock_irqrestore(&tp->lock, flags);
986 static u32 rtl8169_get_rx_csum(struct net_device *dev)
988 struct rtl8169_private *tp = netdev_priv(dev);
990 return tp->cp_cmd & RxChkSum;
993 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
999 spin_lock_irqsave(&tp->lock, flags);
1002 tp->cp_cmd |= RxChkSum;
1004 tp->cp_cmd &= ~RxChkSum;
1006 RTL_W16(CPlusCmd, tp->cp_cmd);
1009 spin_unlock_irqrestore(&tp->lock, flags);
1014 #ifdef CONFIG_R8169_VLAN
1016 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017 struct sk_buff *skb)
1019 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1023 static void rtl8169_vlan_rx_register(struct net_device *dev,
1024 struct vlan_group *grp)
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027 void __iomem *ioaddr = tp->mmio_addr;
1028 unsigned long flags;
1030 spin_lock_irqsave(&tp->lock, flags);
1033 tp->cp_cmd |= RxVlan;
1035 tp->cp_cmd &= ~RxVlan;
1036 RTL_W16(CPlusCmd, tp->cp_cmd);
1038 spin_unlock_irqrestore(&tp->lock, flags);
1041 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1042 struct sk_buff *skb)
1044 u32 opts2 = le32_to_cpu(desc->opts2);
1045 struct vlan_group *vlgrp = tp->vlgrp;
1048 if (vlgrp && (opts2 & RxVlanTag)) {
1049 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1057 #else /* !CONFIG_R8169_VLAN */
1059 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1060 struct sk_buff *skb)
1065 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1066 struct sk_buff *skb)
1073 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1075 struct rtl8169_private *tp = netdev_priv(dev);
1076 void __iomem *ioaddr = tp->mmio_addr;
1080 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1081 cmd->port = PORT_FIBRE;
1082 cmd->transceiver = XCVR_INTERNAL;
1084 status = RTL_R32(TBICSR);
1085 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1086 cmd->autoneg = !!(status & TBINwEnable);
1088 cmd->speed = SPEED_1000;
1089 cmd->duplex = DUPLEX_FULL; /* Always set */
1094 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1096 struct rtl8169_private *tp = netdev_priv(dev);
1098 return mii_ethtool_gset(&tp->mii, cmd);
1101 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1103 struct rtl8169_private *tp = netdev_priv(dev);
1104 unsigned long flags;
1107 spin_lock_irqsave(&tp->lock, flags);
1109 rc = tp->get_settings(dev, cmd);
1111 spin_unlock_irqrestore(&tp->lock, flags);
1115 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1118 struct rtl8169_private *tp = netdev_priv(dev);
1119 unsigned long flags;
1121 if (regs->len > R8169_REGS_SIZE)
1122 regs->len = R8169_REGS_SIZE;
1124 spin_lock_irqsave(&tp->lock, flags);
1125 memcpy_fromio(p, tp->mmio_addr, regs->len);
1126 spin_unlock_irqrestore(&tp->lock, flags);
1129 static u32 rtl8169_get_msglevel(struct net_device *dev)
1131 struct rtl8169_private *tp = netdev_priv(dev);
1133 return tp->msg_enable;
1136 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1138 struct rtl8169_private *tp = netdev_priv(dev);
1140 tp->msg_enable = value;
1143 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1150 "tx_single_collisions",
1151 "tx_multi_collisions",
1159 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1163 return ARRAY_SIZE(rtl8169_gstrings);
1169 static void rtl8169_update_counters(struct net_device *dev)
1171 struct rtl8169_private *tp = netdev_priv(dev);
1172 void __iomem *ioaddr = tp->mmio_addr;
1173 struct rtl8169_counters *counters;
1179 * Some chips are unable to dump tally counters when the receiver
1182 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1185 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1189 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1190 cmd = (u64)paddr & DMA_BIT_MASK(32);
1191 RTL_W32(CounterAddrLow, cmd);
1192 RTL_W32(CounterAddrLow, cmd | CounterDump);
1195 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1196 /* copy updated counters */
1197 memcpy(&tp->counters, counters, sizeof(*counters));
1203 RTL_W32(CounterAddrLow, 0);
1204 RTL_W32(CounterAddrHigh, 0);
1206 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1209 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1210 struct ethtool_stats *stats, u64 *data)
1212 struct rtl8169_private *tp = netdev_priv(dev);
1216 rtl8169_update_counters(dev);
1218 data[0] = le64_to_cpu(tp->counters.tx_packets);
1219 data[1] = le64_to_cpu(tp->counters.rx_packets);
1220 data[2] = le64_to_cpu(tp->counters.tx_errors);
1221 data[3] = le32_to_cpu(tp->counters.rx_errors);
1222 data[4] = le16_to_cpu(tp->counters.rx_missed);
1223 data[5] = le16_to_cpu(tp->counters.align_errors);
1224 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1225 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1226 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1227 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1228 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1229 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1230 data[12] = le16_to_cpu(tp->counters.tx_underun);
1233 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1237 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1242 static const struct ethtool_ops rtl8169_ethtool_ops = {
1243 .get_drvinfo = rtl8169_get_drvinfo,
1244 .get_regs_len = rtl8169_get_regs_len,
1245 .get_link = ethtool_op_get_link,
1246 .get_settings = rtl8169_get_settings,
1247 .set_settings = rtl8169_set_settings,
1248 .get_msglevel = rtl8169_get_msglevel,
1249 .set_msglevel = rtl8169_set_msglevel,
1250 .get_rx_csum = rtl8169_get_rx_csum,
1251 .set_rx_csum = rtl8169_set_rx_csum,
1252 .set_tx_csum = ethtool_op_set_tx_csum,
1253 .set_sg = ethtool_op_set_sg,
1254 .set_tso = ethtool_op_set_tso,
1255 .get_regs = rtl8169_get_regs,
1256 .get_wol = rtl8169_get_wol,
1257 .set_wol = rtl8169_set_wol,
1258 .get_strings = rtl8169_get_strings,
1259 .get_sset_count = rtl8169_get_sset_count,
1260 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1263 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1264 void __iomem *ioaddr)
1267 * The driver currently handles the 8168Bf and the 8168Be identically
1268 * but they can be identified more specifically through the test below
1271 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1273 * Same thing for the 8101Eb and the 8101Ec:
1275 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1283 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1284 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1285 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1286 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1289 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1290 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1291 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1292 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1293 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1294 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1295 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1296 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1297 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1300 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1301 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1302 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1303 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1306 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1307 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1308 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1309 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1310 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1311 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1312 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1313 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1314 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1315 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1316 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1317 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1318 /* FIXME: where did these entries come from ? -- FR */
1319 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1320 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1323 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1324 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1325 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1326 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1327 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1328 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1331 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1335 reg = RTL_R32(TxConfig);
1336 while ((reg & p->mask) != p->val)
1338 tp->mac_version = p->mac_version;
1341 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1343 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1351 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1354 mdio_write(ioaddr, regs->reg, regs->val);
1359 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1361 struct phy_reg phy_reg_init[] = {
1423 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1426 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1428 struct phy_reg phy_reg_init[] = {
1434 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1437 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1438 void __iomem *ioaddr)
1440 struct pci_dev *pdev = tp->pci_dev;
1441 u16 vendor_id, device_id;
1443 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1444 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1446 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1449 mdio_write(ioaddr, 0x1f, 0x0001);
1450 mdio_write(ioaddr, 0x10, 0xf01b);
1451 mdio_write(ioaddr, 0x1f, 0x0000);
1454 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1455 void __iomem *ioaddr)
1457 struct phy_reg phy_reg_init[] = {
1497 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1499 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1502 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1504 struct phy_reg phy_reg_init[] = {
1552 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1555 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1557 struct phy_reg phy_reg_init[] = {
1562 mdio_write(ioaddr, 0x1f, 0x0001);
1563 mdio_patch(ioaddr, 0x16, 1 << 0);
1565 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1568 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1570 struct phy_reg phy_reg_init[] = {
1576 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1579 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1581 struct phy_reg phy_reg_init[] = {
1589 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1592 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1594 struct phy_reg phy_reg_init[] = {
1600 mdio_write(ioaddr, 0x1f, 0x0000);
1601 mdio_patch(ioaddr, 0x14, 1 << 5);
1602 mdio_patch(ioaddr, 0x0d, 1 << 5);
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1607 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1609 struct phy_reg phy_reg_init[] = {
1629 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1631 mdio_patch(ioaddr, 0x14, 1 << 5);
1632 mdio_patch(ioaddr, 0x0d, 1 << 5);
1633 mdio_write(ioaddr, 0x1f, 0x0000);
1636 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1638 struct phy_reg phy_reg_init[] = {
1656 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1658 mdio_patch(ioaddr, 0x16, 1 << 0);
1659 mdio_patch(ioaddr, 0x14, 1 << 5);
1660 mdio_patch(ioaddr, 0x0d, 1 << 5);
1661 mdio_write(ioaddr, 0x1f, 0x0000);
1664 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1666 struct phy_reg phy_reg_init[] = {
1678 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1680 mdio_patch(ioaddr, 0x16, 1 << 0);
1681 mdio_patch(ioaddr, 0x14, 1 << 5);
1682 mdio_patch(ioaddr, 0x0d, 1 << 5);
1683 mdio_write(ioaddr, 0x1f, 0x0000);
1686 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1688 rtl8168c_3_hw_phy_config(ioaddr);
1691 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1693 static struct phy_reg phy_reg_init_0[] = {
1712 static struct phy_reg phy_reg_init_1[] = {
1719 static struct phy_reg phy_reg_init_2[] = {
2075 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2077 mdio_write(ioaddr, 0x1f, 0x0002);
2078 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2079 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2081 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2083 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2084 struct phy_reg phy_reg_init[] = {
2094 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2096 val = mdio_read(ioaddr, 0x0d);
2098 if ((val & 0x00ff) != 0x006c) {
2100 0x0065, 0x0066, 0x0067, 0x0068,
2101 0x0069, 0x006a, 0x006b, 0x006c
2105 mdio_write(ioaddr, 0x1f, 0x0002);
2108 for (i = 0; i < ARRAY_SIZE(set); i++)
2109 mdio_write(ioaddr, 0x0d, val | set[i]);
2112 struct phy_reg phy_reg_init[] = {
2120 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2123 mdio_write(ioaddr, 0x1f, 0x0002);
2124 mdio_patch(ioaddr, 0x0d, 0x0300);
2125 mdio_patch(ioaddr, 0x0f, 0x0010);
2127 mdio_write(ioaddr, 0x1f, 0x0002);
2128 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2129 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2131 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2134 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2136 static struct phy_reg phy_reg_init_0[] = {
2161 static struct phy_reg phy_reg_init_1[] = {
2474 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2476 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2477 struct phy_reg phy_reg_init[] = {
2488 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2490 val = mdio_read(ioaddr, 0x0d);
2491 if ((val & 0x00ff) != 0x006c) {
2493 0x0065, 0x0066, 0x0067, 0x0068,
2494 0x0069, 0x006a, 0x006b, 0x006c
2498 mdio_write(ioaddr, 0x1f, 0x0002);
2501 for (i = 0; i < ARRAY_SIZE(set); i++)
2502 mdio_write(ioaddr, 0x0d, val | set[i]);
2505 struct phy_reg phy_reg_init[] = {
2513 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2516 mdio_write(ioaddr, 0x1f, 0x0002);
2517 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2518 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2520 mdio_write(ioaddr, 0x1f, 0x0001);
2521 mdio_write(ioaddr, 0x17, 0x0cc0);
2523 mdio_write(ioaddr, 0x1f, 0x0002);
2524 mdio_patch(ioaddr, 0x0f, 0x0017);
2526 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2529 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2531 struct phy_reg phy_reg_init[] = {
2587 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2590 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2592 struct phy_reg phy_reg_init[] = {
2599 mdio_write(ioaddr, 0x1f, 0x0000);
2600 mdio_patch(ioaddr, 0x11, 1 << 12);
2601 mdio_patch(ioaddr, 0x19, 1 << 13);
2602 mdio_patch(ioaddr, 0x10, 1 << 15);
2604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2607 static void rtl_hw_phy_config(struct net_device *dev)
2609 struct rtl8169_private *tp = netdev_priv(dev);
2610 void __iomem *ioaddr = tp->mmio_addr;
2612 rtl8169_print_mac_version(tp);
2614 switch (tp->mac_version) {
2615 case RTL_GIGA_MAC_VER_01:
2617 case RTL_GIGA_MAC_VER_02:
2618 case RTL_GIGA_MAC_VER_03:
2619 rtl8169s_hw_phy_config(ioaddr);
2621 case RTL_GIGA_MAC_VER_04:
2622 rtl8169sb_hw_phy_config(ioaddr);
2624 case RTL_GIGA_MAC_VER_05:
2625 rtl8169scd_hw_phy_config(tp, ioaddr);
2627 case RTL_GIGA_MAC_VER_06:
2628 rtl8169sce_hw_phy_config(ioaddr);
2630 case RTL_GIGA_MAC_VER_07:
2631 case RTL_GIGA_MAC_VER_08:
2632 case RTL_GIGA_MAC_VER_09:
2633 rtl8102e_hw_phy_config(ioaddr);
2635 case RTL_GIGA_MAC_VER_11:
2636 rtl8168bb_hw_phy_config(ioaddr);
2638 case RTL_GIGA_MAC_VER_12:
2639 rtl8168bef_hw_phy_config(ioaddr);
2641 case RTL_GIGA_MAC_VER_17:
2642 rtl8168bef_hw_phy_config(ioaddr);
2644 case RTL_GIGA_MAC_VER_18:
2645 rtl8168cp_1_hw_phy_config(ioaddr);
2647 case RTL_GIGA_MAC_VER_19:
2648 rtl8168c_1_hw_phy_config(ioaddr);
2650 case RTL_GIGA_MAC_VER_20:
2651 rtl8168c_2_hw_phy_config(ioaddr);
2653 case RTL_GIGA_MAC_VER_21:
2654 rtl8168c_3_hw_phy_config(ioaddr);
2656 case RTL_GIGA_MAC_VER_22:
2657 rtl8168c_4_hw_phy_config(ioaddr);
2659 case RTL_GIGA_MAC_VER_23:
2660 case RTL_GIGA_MAC_VER_24:
2661 rtl8168cp_2_hw_phy_config(ioaddr);
2663 case RTL_GIGA_MAC_VER_25:
2664 rtl8168d_1_hw_phy_config(ioaddr);
2666 case RTL_GIGA_MAC_VER_26:
2667 rtl8168d_2_hw_phy_config(ioaddr);
2669 case RTL_GIGA_MAC_VER_27:
2670 rtl8168d_3_hw_phy_config(ioaddr);
2678 static void rtl8169_phy_timer(unsigned long __opaque)
2680 struct net_device *dev = (struct net_device *)__opaque;
2681 struct rtl8169_private *tp = netdev_priv(dev);
2682 struct timer_list *timer = &tp->timer;
2683 void __iomem *ioaddr = tp->mmio_addr;
2684 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2686 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2688 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2691 spin_lock_irq(&tp->lock);
2693 if (tp->phy_reset_pending(ioaddr)) {
2695 * A busy loop could burn quite a few cycles on nowadays CPU.
2696 * Let's delay the execution of the timer for a few ticks.
2702 if (tp->link_ok(ioaddr))
2705 if (netif_msg_link(tp))
2706 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
2708 tp->phy_reset_enable(ioaddr);
2711 mod_timer(timer, jiffies + timeout);
2713 spin_unlock_irq(&tp->lock);
2716 static inline void rtl8169_delete_timer(struct net_device *dev)
2718 struct rtl8169_private *tp = netdev_priv(dev);
2719 struct timer_list *timer = &tp->timer;
2721 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2724 del_timer_sync(timer);
2727 static inline void rtl8169_request_timer(struct net_device *dev)
2729 struct rtl8169_private *tp = netdev_priv(dev);
2730 struct timer_list *timer = &tp->timer;
2732 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2735 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2738 #ifdef CONFIG_NET_POLL_CONTROLLER
2740 * Polling 'interrupt' - used by things like netconsole to send skbs
2741 * without having to re-enable interrupts. It's not called while
2742 * the interrupt routine is executing.
2744 static void rtl8169_netpoll(struct net_device *dev)
2746 struct rtl8169_private *tp = netdev_priv(dev);
2747 struct pci_dev *pdev = tp->pci_dev;
2749 disable_irq(pdev->irq);
2750 rtl8169_interrupt(pdev->irq, dev);
2751 enable_irq(pdev->irq);
2755 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2756 void __iomem *ioaddr)
2759 pci_release_regions(pdev);
2760 pci_disable_device(pdev);
2764 static void rtl8169_phy_reset(struct net_device *dev,
2765 struct rtl8169_private *tp)
2767 void __iomem *ioaddr = tp->mmio_addr;
2770 tp->phy_reset_enable(ioaddr);
2771 for (i = 0; i < 100; i++) {
2772 if (!tp->phy_reset_pending(ioaddr))
2776 if (netif_msg_link(tp))
2777 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
2780 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2782 void __iomem *ioaddr = tp->mmio_addr;
2784 rtl_hw_phy_config(dev);
2786 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2787 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2791 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2793 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2794 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2796 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2797 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2799 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2800 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2803 rtl8169_phy_reset(dev, tp);
2806 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2807 * only 8101. Don't panic.
2809 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2811 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
2812 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
2815 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2817 void __iomem *ioaddr = tp->mmio_addr;
2821 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2822 high = addr[4] | (addr[5] << 8);
2824 spin_lock_irq(&tp->lock);
2826 RTL_W8(Cfg9346, Cfg9346_Unlock);
2828 RTL_W32(MAC4, high);
2829 RTL_W8(Cfg9346, Cfg9346_Lock);
2831 spin_unlock_irq(&tp->lock);
2834 static int rtl_set_mac_address(struct net_device *dev, void *p)
2836 struct rtl8169_private *tp = netdev_priv(dev);
2837 struct sockaddr *addr = p;
2839 if (!is_valid_ether_addr(addr->sa_data))
2840 return -EADDRNOTAVAIL;
2842 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2844 rtl_rar_set(tp, dev->dev_addr);
2849 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2851 struct rtl8169_private *tp = netdev_priv(dev);
2852 struct mii_ioctl_data *data = if_mii(ifr);
2854 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2857 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2861 data->phy_id = 32; /* Internal PHY */
2865 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2869 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2875 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2880 static const struct rtl_cfg_info {
2881 void (*hw_start)(struct net_device *);
2882 unsigned int region;
2888 } rtl_cfg_infos [] = {
2890 .hw_start = rtl_hw_start_8169,
2893 .intr_event = SYSErr | LinkChg | RxOverflow |
2894 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2895 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2896 .features = RTL_FEATURE_GMII,
2897 .default_ver = RTL_GIGA_MAC_VER_01,
2900 .hw_start = rtl_hw_start_8168,
2903 .intr_event = SYSErr | LinkChg | RxOverflow |
2904 TxErr | TxOK | RxOK | RxErr,
2905 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2906 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2907 .default_ver = RTL_GIGA_MAC_VER_11,
2910 .hw_start = rtl_hw_start_8101,
2913 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2914 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2915 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2916 .features = RTL_FEATURE_MSI,
2917 .default_ver = RTL_GIGA_MAC_VER_13,
2921 /* Cfg9346_Unlock assumed. */
2922 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2923 const struct rtl_cfg_info *cfg)
2928 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2929 if (cfg->features & RTL_FEATURE_MSI) {
2930 if (pci_enable_msi(pdev)) {
2931 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2934 msi = RTL_FEATURE_MSI;
2937 RTL_W8(Config2, cfg2);
2941 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2943 if (tp->features & RTL_FEATURE_MSI) {
2944 pci_disable_msi(pdev);
2945 tp->features &= ~RTL_FEATURE_MSI;
2949 static const struct net_device_ops rtl8169_netdev_ops = {
2950 .ndo_open = rtl8169_open,
2951 .ndo_stop = rtl8169_close,
2952 .ndo_get_stats = rtl8169_get_stats,
2953 .ndo_start_xmit = rtl8169_start_xmit,
2954 .ndo_tx_timeout = rtl8169_tx_timeout,
2955 .ndo_validate_addr = eth_validate_addr,
2956 .ndo_change_mtu = rtl8169_change_mtu,
2957 .ndo_set_mac_address = rtl_set_mac_address,
2958 .ndo_do_ioctl = rtl8169_ioctl,
2959 .ndo_set_multicast_list = rtl_set_rx_mode,
2960 #ifdef CONFIG_R8169_VLAN
2961 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2963 #ifdef CONFIG_NET_POLL_CONTROLLER
2964 .ndo_poll_controller = rtl8169_netpoll,
2969 static int __devinit
2970 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2972 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2973 const unsigned int region = cfg->region;
2974 struct rtl8169_private *tp;
2975 struct mii_if_info *mii;
2976 struct net_device *dev;
2977 void __iomem *ioaddr;
2981 if (netif_msg_drv(&debug)) {
2982 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2983 MODULENAME, RTL8169_VERSION);
2986 dev = alloc_etherdev(sizeof (*tp));
2988 if (netif_msg_drv(&debug))
2989 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2994 SET_NETDEV_DEV(dev, &pdev->dev);
2995 dev->netdev_ops = &rtl8169_netdev_ops;
2996 tp = netdev_priv(dev);
2999 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3003 mii->mdio_read = rtl_mdio_read;
3004 mii->mdio_write = rtl_mdio_write;
3005 mii->phy_id_mask = 0x1f;
3006 mii->reg_num_mask = 0x1f;
3007 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3009 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3010 rc = pci_enable_device(pdev);
3012 if (netif_msg_probe(tp))
3013 dev_err(&pdev->dev, "enable failure\n");
3014 goto err_out_free_dev_1;
3017 rc = pci_set_mwi(pdev);
3019 goto err_out_disable_2;
3021 /* make sure PCI base addr 1 is MMIO */
3022 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3023 if (netif_msg_probe(tp)) {
3025 "region #%d not an MMIO resource, aborting\n",
3032 /* check for weird/broken PCI region reporting */
3033 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3034 if (netif_msg_probe(tp)) {
3036 "Invalid PCI region size(s), aborting\n");
3042 rc = pci_request_regions(pdev, MODULENAME);
3044 if (netif_msg_probe(tp))
3045 dev_err(&pdev->dev, "could not request regions.\n");
3049 tp->cp_cmd = PCIMulRW | RxChkSum;
3051 if ((sizeof(dma_addr_t) > 4) &&
3052 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3053 tp->cp_cmd |= PCIDAC;
3054 dev->features |= NETIF_F_HIGHDMA;
3056 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3058 if (netif_msg_probe(tp)) {
3060 "DMA configuration failed.\n");
3062 goto err_out_free_res_4;
3066 /* ioremap MMIO region */
3067 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3069 if (netif_msg_probe(tp))
3070 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
3072 goto err_out_free_res_4;
3075 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3076 if (!tp->pcie_cap && netif_msg_probe(tp))
3077 dev_info(&pdev->dev, "no PCI Express capability\n");
3079 RTL_W16(IntrMask, 0x0000);
3081 /* Soft reset the chip. */
3082 RTL_W8(ChipCmd, CmdReset);
3084 /* Check that the chip has finished the reset. */
3085 for (i = 0; i < 100; i++) {
3086 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3088 msleep_interruptible(1);
3091 RTL_W16(IntrStatus, 0xffff);
3093 pci_set_master(pdev);
3095 /* Identify chip attached to board */
3096 rtl8169_get_mac_version(tp, ioaddr);
3098 /* Use appropriate default if unknown */
3099 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3100 if (netif_msg_probe(tp)) {
3101 dev_notice(&pdev->dev,
3102 "unknown MAC, using family default\n");
3104 tp->mac_version = cfg->default_ver;
3107 rtl8169_print_mac_version(tp);
3109 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3110 if (tp->mac_version == rtl_chip_info[i].mac_version)
3113 if (i == ARRAY_SIZE(rtl_chip_info)) {
3115 "driver bug, MAC version not found in rtl_chip_info\n");
3120 RTL_W8(Cfg9346, Cfg9346_Unlock);
3121 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3122 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3123 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3124 tp->features |= RTL_FEATURE_WOL;
3125 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3126 tp->features |= RTL_FEATURE_WOL;
3127 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3128 RTL_W8(Cfg9346, Cfg9346_Lock);
3130 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3131 (RTL_R8(PHYstatus) & TBI_Enable)) {
3132 tp->set_speed = rtl8169_set_speed_tbi;
3133 tp->get_settings = rtl8169_gset_tbi;
3134 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3135 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3136 tp->link_ok = rtl8169_tbi_link_ok;
3137 tp->do_ioctl = rtl_tbi_ioctl;
3139 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3141 tp->set_speed = rtl8169_set_speed_xmii;
3142 tp->get_settings = rtl8169_gset_xmii;
3143 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3144 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3145 tp->link_ok = rtl8169_xmii_link_ok;
3146 tp->do_ioctl = rtl_xmii_ioctl;
3149 spin_lock_init(&tp->lock);
3151 tp->mmio_addr = ioaddr;
3153 /* Get MAC address */
3154 for (i = 0; i < MAC_ADDR_LEN; i++)
3155 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3156 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3158 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3159 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3160 dev->irq = pdev->irq;
3161 dev->base_addr = (unsigned long) ioaddr;
3163 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3165 #ifdef CONFIG_R8169_VLAN
3166 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3169 tp->intr_mask = 0xffff;
3170 tp->align = cfg->align;
3171 tp->hw_start = cfg->hw_start;
3172 tp->intr_event = cfg->intr_event;
3173 tp->napi_event = cfg->napi_event;
3175 init_timer(&tp->timer);
3176 tp->timer.data = (unsigned long) dev;
3177 tp->timer.function = rtl8169_phy_timer;
3179 rc = register_netdev(dev);
3183 pci_set_drvdata(pdev, dev);
3185 if (netif_msg_probe(tp)) {
3186 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
3188 printk(KERN_INFO "%s: %s at 0x%lx, "
3189 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3190 "XID %08x IRQ %d\n",
3192 rtl_chip_info[tp->chipset].name,
3194 dev->dev_addr[0], dev->dev_addr[1],
3195 dev->dev_addr[2], dev->dev_addr[3],
3196 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
3199 rtl8169_init_phy(dev, tp);
3200 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3206 rtl_disable_msi(pdev, tp);
3209 pci_release_regions(pdev);
3211 pci_clear_mwi(pdev);
3213 pci_disable_device(pdev);
3219 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3221 struct net_device *dev = pci_get_drvdata(pdev);
3222 struct rtl8169_private *tp = netdev_priv(dev);
3224 flush_scheduled_work();
3226 unregister_netdev(dev);
3227 rtl_disable_msi(pdev, tp);
3228 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3229 pci_set_drvdata(pdev, NULL);
3232 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3233 struct net_device *dev)
3235 unsigned int mtu = dev->mtu;
3237 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
3240 static int rtl8169_open(struct net_device *dev)
3242 struct rtl8169_private *tp = netdev_priv(dev);
3243 struct pci_dev *pdev = tp->pci_dev;
3244 int retval = -ENOMEM;
3247 rtl8169_set_rxbufsize(tp, dev);
3250 * Rx and Tx desscriptors needs 256 bytes alignment.
3251 * pci_alloc_consistent provides more.
3253 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3255 if (!tp->TxDescArray)
3258 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3260 if (!tp->RxDescArray)
3263 retval = rtl8169_init_ring(dev);
3267 INIT_DELAYED_WORK(&tp->task, NULL);
3271 retval = request_irq(dev->irq, rtl8169_interrupt,
3272 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3275 goto err_release_ring_2;
3277 napi_enable(&tp->napi);
3281 rtl8169_request_timer(dev);
3283 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3288 rtl8169_rx_clear(tp);
3290 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3293 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3298 static void rtl8169_hw_reset(void __iomem *ioaddr)
3300 /* Disable interrupts */
3301 rtl8169_irq_mask_and_ack(ioaddr);
3303 /* Reset the chipset */
3304 RTL_W8(ChipCmd, CmdReset);
3310 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3312 void __iomem *ioaddr = tp->mmio_addr;
3313 u32 cfg = rtl8169_rx_config;
3315 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3316 RTL_W32(RxConfig, cfg);
3318 /* Set DMA burst size and Interframe Gap Time */
3319 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3320 (InterFrameGap << TxInterFrameGapShift));
3323 static void rtl_hw_start(struct net_device *dev)
3325 struct rtl8169_private *tp = netdev_priv(dev);
3326 void __iomem *ioaddr = tp->mmio_addr;
3329 /* Soft reset the chip. */
3330 RTL_W8(ChipCmd, CmdReset);
3332 /* Check that the chip has finished the reset. */
3333 for (i = 0; i < 100; i++) {
3334 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3336 msleep_interruptible(1);
3341 netif_start_queue(dev);
3345 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3346 void __iomem *ioaddr)
3349 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3350 * register to be written before TxDescAddrLow to work.
3351 * Switching from MMIO to I/O access fixes the issue as well.
3353 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3354 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3355 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3356 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3359 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3363 cmd = RTL_R16(CPlusCmd);
3364 RTL_W16(CPlusCmd, cmd);
3368 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3370 /* Low hurts. Let's disable the filtering. */
3371 RTL_W16(RxMaxSize, rx_buf_sz);
3374 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3381 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3382 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3383 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3384 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3389 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3390 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3391 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3392 RTL_W32(0x7c, p->val);
3398 static void rtl_hw_start_8169(struct net_device *dev)
3400 struct rtl8169_private *tp = netdev_priv(dev);
3401 void __iomem *ioaddr = tp->mmio_addr;
3402 struct pci_dev *pdev = tp->pci_dev;
3404 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3405 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3406 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3409 RTL_W8(Cfg9346, Cfg9346_Unlock);
3410 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3411 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3412 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3413 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3414 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3416 RTL_W8(EarlyTxThres, EarlyTxThld);
3418 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3420 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3421 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3422 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3424 rtl_set_rx_tx_config_registers(tp);
3426 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3428 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3429 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3430 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3431 "Bit-3 and bit-14 MUST be 1\n");
3432 tp->cp_cmd |= (1 << 14);
3435 RTL_W16(CPlusCmd, tp->cp_cmd);
3437 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3440 * Undocumented corner. Supposedly:
3441 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3443 RTL_W16(IntrMitigate, 0x0000);
3445 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3447 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3448 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3449 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3450 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3451 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3452 rtl_set_rx_tx_config_registers(tp);
3455 RTL_W8(Cfg9346, Cfg9346_Lock);
3457 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3460 RTL_W32(RxMissed, 0);
3462 rtl_set_rx_mode(dev);
3464 /* no early-rx interrupts */
3465 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3467 /* Enable all known interrupts by setting the interrupt mask. */
3468 RTL_W16(IntrMask, tp->intr_event);
3471 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3473 struct net_device *dev = pci_get_drvdata(pdev);
3474 struct rtl8169_private *tp = netdev_priv(dev);
3475 int cap = tp->pcie_cap;
3480 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3481 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3482 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3486 static void rtl_csi_access_enable(void __iomem *ioaddr)
3490 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3491 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3495 unsigned int offset;
3500 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
3505 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3506 rtl_ephy_write(ioaddr, e->offset, w);
3511 static void rtl_disable_clock_request(struct pci_dev *pdev)
3513 struct net_device *dev = pci_get_drvdata(pdev);
3514 struct rtl8169_private *tp = netdev_priv(dev);
3515 int cap = tp->pcie_cap;
3520 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3521 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3522 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3526 #define R8168_CPCMD_QUIRK_MASK (\
3537 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3539 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3541 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3543 rtl_tx_performance_tweak(pdev,
3544 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3547 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3549 rtl_hw_start_8168bb(ioaddr, pdev);
3551 RTL_W8(EarlyTxThres, EarlyTxThld);
3553 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3556 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3558 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3560 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3562 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3564 rtl_disable_clock_request(pdev);
3566 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3569 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3571 static struct ephy_info e_info_8168cp[] = {
3572 { 0x01, 0, 0x0001 },
3573 { 0x02, 0x0800, 0x1000 },
3574 { 0x03, 0, 0x0042 },
3575 { 0x06, 0x0080, 0x0000 },
3579 rtl_csi_access_enable(ioaddr);
3581 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3583 __rtl_hw_start_8168cp(ioaddr, pdev);
3586 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3588 rtl_csi_access_enable(ioaddr);
3590 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3592 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3597 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3599 rtl_csi_access_enable(ioaddr);
3601 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3604 RTL_W8(DBG_REG, 0x20);
3606 RTL_W8(EarlyTxThres, EarlyTxThld);
3608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3610 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3613 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3615 static struct ephy_info e_info_8168c_1[] = {
3616 { 0x02, 0x0800, 0x1000 },
3617 { 0x03, 0, 0x0002 },
3618 { 0x06, 0x0080, 0x0000 }
3621 rtl_csi_access_enable(ioaddr);
3623 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3625 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3627 __rtl_hw_start_8168cp(ioaddr, pdev);
3630 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3632 static struct ephy_info e_info_8168c_2[] = {
3633 { 0x01, 0, 0x0001 },
3634 { 0x03, 0x0400, 0x0220 }
3637 rtl_csi_access_enable(ioaddr);
3639 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3641 __rtl_hw_start_8168cp(ioaddr, pdev);
3644 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3646 rtl_hw_start_8168c_2(ioaddr, pdev);
3649 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3651 rtl_csi_access_enable(ioaddr);
3653 __rtl_hw_start_8168cp(ioaddr, pdev);
3656 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3658 rtl_csi_access_enable(ioaddr);
3660 rtl_disable_clock_request(pdev);
3662 RTL_W8(EarlyTxThres, EarlyTxThld);
3664 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3666 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3669 static void rtl_hw_start_8168(struct net_device *dev)
3671 struct rtl8169_private *tp = netdev_priv(dev);
3672 void __iomem *ioaddr = tp->mmio_addr;
3673 struct pci_dev *pdev = tp->pci_dev;
3675 RTL_W8(Cfg9346, Cfg9346_Unlock);
3677 RTL_W8(EarlyTxThres, EarlyTxThld);
3679 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3681 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3683 RTL_W16(CPlusCmd, tp->cp_cmd);
3685 RTL_W16(IntrMitigate, 0x5151);
3687 /* Work around for RxFIFO overflow. */
3688 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3689 tp->intr_event |= RxFIFOOver | PCSTimeout;
3690 tp->intr_event &= ~RxOverflow;
3693 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3695 rtl_set_rx_mode(dev);
3697 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3698 (InterFrameGap << TxInterFrameGapShift));
3702 switch (tp->mac_version) {
3703 case RTL_GIGA_MAC_VER_11:
3704 rtl_hw_start_8168bb(ioaddr, pdev);
3707 case RTL_GIGA_MAC_VER_12:
3708 case RTL_GIGA_MAC_VER_17:
3709 rtl_hw_start_8168bef(ioaddr, pdev);
3712 case RTL_GIGA_MAC_VER_18:
3713 rtl_hw_start_8168cp_1(ioaddr, pdev);
3716 case RTL_GIGA_MAC_VER_19:
3717 rtl_hw_start_8168c_1(ioaddr, pdev);
3720 case RTL_GIGA_MAC_VER_20:
3721 rtl_hw_start_8168c_2(ioaddr, pdev);
3724 case RTL_GIGA_MAC_VER_21:
3725 rtl_hw_start_8168c_3(ioaddr, pdev);
3728 case RTL_GIGA_MAC_VER_22:
3729 rtl_hw_start_8168c_4(ioaddr, pdev);
3732 case RTL_GIGA_MAC_VER_23:
3733 rtl_hw_start_8168cp_2(ioaddr, pdev);
3736 case RTL_GIGA_MAC_VER_24:
3737 rtl_hw_start_8168cp_3(ioaddr, pdev);
3740 case RTL_GIGA_MAC_VER_25:
3741 case RTL_GIGA_MAC_VER_26:
3742 case RTL_GIGA_MAC_VER_27:
3743 rtl_hw_start_8168d(ioaddr, pdev);
3747 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3748 dev->name, tp->mac_version);
3752 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3754 RTL_W8(Cfg9346, Cfg9346_Lock);
3756 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3758 RTL_W16(IntrMask, tp->intr_event);
3761 #define R810X_CPCMD_QUIRK_MASK (\
3773 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3775 static struct ephy_info e_info_8102e_1[] = {
3776 { 0x01, 0, 0x6e65 },
3777 { 0x02, 0, 0x091f },
3778 { 0x03, 0, 0xc2f9 },
3779 { 0x06, 0, 0xafb5 },
3780 { 0x07, 0, 0x0e00 },
3781 { 0x19, 0, 0xec80 },
3782 { 0x01, 0, 0x2e65 },
3787 rtl_csi_access_enable(ioaddr);
3789 RTL_W8(DBG_REG, FIX_NAK_1);
3791 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3794 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3795 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3797 cfg1 = RTL_R8(Config1);
3798 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3799 RTL_W8(Config1, cfg1 & ~LEDS0);
3801 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3803 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3806 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3808 rtl_csi_access_enable(ioaddr);
3810 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3812 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3813 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3815 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3818 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3820 rtl_hw_start_8102e_2(ioaddr, pdev);
3822 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3825 static void rtl_hw_start_8101(struct net_device *dev)
3827 struct rtl8169_private *tp = netdev_priv(dev);
3828 void __iomem *ioaddr = tp->mmio_addr;
3829 struct pci_dev *pdev = tp->pci_dev;
3831 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3832 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3833 int cap = tp->pcie_cap;
3836 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3837 PCI_EXP_DEVCTL_NOSNOOP_EN);
3841 switch (tp->mac_version) {
3842 case RTL_GIGA_MAC_VER_07:
3843 rtl_hw_start_8102e_1(ioaddr, pdev);
3846 case RTL_GIGA_MAC_VER_08:
3847 rtl_hw_start_8102e_3(ioaddr, pdev);
3850 case RTL_GIGA_MAC_VER_09:
3851 rtl_hw_start_8102e_2(ioaddr, pdev);
3855 RTL_W8(Cfg9346, Cfg9346_Unlock);
3857 RTL_W8(EarlyTxThres, EarlyTxThld);
3859 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3861 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3863 RTL_W16(CPlusCmd, tp->cp_cmd);
3865 RTL_W16(IntrMitigate, 0x0000);
3867 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3869 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3870 rtl_set_rx_tx_config_registers(tp);
3872 RTL_W8(Cfg9346, Cfg9346_Lock);
3876 rtl_set_rx_mode(dev);
3878 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3880 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3882 RTL_W16(IntrMask, tp->intr_event);
3885 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3887 struct rtl8169_private *tp = netdev_priv(dev);
3890 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3895 if (!netif_running(dev))
3900 rtl8169_set_rxbufsize(tp, dev);
3902 ret = rtl8169_init_ring(dev);
3906 napi_enable(&tp->napi);
3910 rtl8169_request_timer(dev);
3916 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3918 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3919 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3922 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3923 struct sk_buff **sk_buff, struct RxDesc *desc)
3925 struct pci_dev *pdev = tp->pci_dev;
3927 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3928 PCI_DMA_FROMDEVICE);
3929 dev_kfree_skb(*sk_buff);
3931 rtl8169_make_unusable_by_asic(desc);
3934 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3936 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3938 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3941 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3944 desc->addr = cpu_to_le64(mapping);
3946 rtl8169_mark_to_asic(desc, rx_buf_sz);
3949 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3950 struct net_device *dev,
3951 struct RxDesc *desc, int rx_buf_sz,
3954 struct sk_buff *skb;
3958 pad = align ? align : NET_IP_ALIGN;
3960 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3964 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3966 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3967 PCI_DMA_FROMDEVICE);
3969 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3974 rtl8169_make_unusable_by_asic(desc);
3978 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3982 for (i = 0; i < NUM_RX_DESC; i++) {
3983 if (tp->Rx_skbuff[i]) {
3984 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3985 tp->RxDescArray + i);
3990 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3995 for (cur = start; end - cur != 0; cur++) {
3996 struct sk_buff *skb;
3997 unsigned int i = cur % NUM_RX_DESC;
3999 WARN_ON((s32)(end - cur) < 0);
4001 if (tp->Rx_skbuff[i])
4004 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4005 tp->RxDescArray + i,
4006 tp->rx_buf_sz, tp->align);
4010 tp->Rx_skbuff[i] = skb;
4015 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4017 desc->opts1 |= cpu_to_le32(RingEnd);
4020 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4022 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4025 static int rtl8169_init_ring(struct net_device *dev)
4027 struct rtl8169_private *tp = netdev_priv(dev);
4029 rtl8169_init_ring_indexes(tp);
4031 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4032 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4034 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4037 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4042 rtl8169_rx_clear(tp);
4046 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4047 struct TxDesc *desc)
4049 unsigned int len = tx_skb->len;
4051 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4058 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4062 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4063 unsigned int entry = i % NUM_TX_DESC;
4064 struct ring_info *tx_skb = tp->tx_skb + entry;
4065 unsigned int len = tx_skb->len;
4068 struct sk_buff *skb = tx_skb->skb;
4070 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4071 tp->TxDescArray + entry);
4076 tp->dev->stats.tx_dropped++;
4079 tp->cur_tx = tp->dirty_tx = 0;
4082 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4084 struct rtl8169_private *tp = netdev_priv(dev);
4086 PREPARE_DELAYED_WORK(&tp->task, task);
4087 schedule_delayed_work(&tp->task, 4);
4090 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4092 struct rtl8169_private *tp = netdev_priv(dev);
4093 void __iomem *ioaddr = tp->mmio_addr;
4095 synchronize_irq(dev->irq);
4097 /* Wait for any pending NAPI task to complete */
4098 napi_disable(&tp->napi);
4100 rtl8169_irq_mask_and_ack(ioaddr);
4102 tp->intr_mask = 0xffff;
4103 RTL_W16(IntrMask, tp->intr_event);
4104 napi_enable(&tp->napi);
4107 static void rtl8169_reinit_task(struct work_struct *work)
4109 struct rtl8169_private *tp =
4110 container_of(work, struct rtl8169_private, task.work);
4111 struct net_device *dev = tp->dev;
4116 if (!netif_running(dev))
4119 rtl8169_wait_for_quiescence(dev);
4122 ret = rtl8169_open(dev);
4123 if (unlikely(ret < 0)) {
4124 if (net_ratelimit() && netif_msg_drv(tp)) {
4125 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
4126 " Rescheduling.\n", dev->name, ret);
4128 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4135 static void rtl8169_reset_task(struct work_struct *work)
4137 struct rtl8169_private *tp =
4138 container_of(work, struct rtl8169_private, task.work);
4139 struct net_device *dev = tp->dev;
4143 if (!netif_running(dev))
4146 rtl8169_wait_for_quiescence(dev);
4148 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4149 rtl8169_tx_clear(tp);
4151 if (tp->dirty_rx == tp->cur_rx) {
4152 rtl8169_init_ring_indexes(tp);
4154 netif_wake_queue(dev);
4155 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4157 if (net_ratelimit() && netif_msg_intr(tp)) {
4158 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
4161 rtl8169_schedule_work(dev, rtl8169_reset_task);
4168 static void rtl8169_tx_timeout(struct net_device *dev)
4170 struct rtl8169_private *tp = netdev_priv(dev);
4172 rtl8169_hw_reset(tp->mmio_addr);
4174 /* Let's wait a bit while any (async) irq lands on */
4175 rtl8169_schedule_work(dev, rtl8169_reset_task);
4178 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4181 struct skb_shared_info *info = skb_shinfo(skb);
4182 unsigned int cur_frag, entry;
4183 struct TxDesc * uninitialized_var(txd);
4186 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4187 skb_frag_t *frag = info->frags + cur_frag;
4192 entry = (entry + 1) % NUM_TX_DESC;
4194 txd = tp->TxDescArray + entry;
4196 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4197 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4199 /* anti gcc 2.95.3 bugware (sic) */
4200 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4202 txd->opts1 = cpu_to_le32(status);
4203 txd->addr = cpu_to_le64(mapping);
4205 tp->tx_skb[entry].len = len;
4209 tp->tx_skb[entry].skb = skb;
4210 txd->opts1 |= cpu_to_le32(LastFrag);
4216 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4218 if (dev->features & NETIF_F_TSO) {
4219 u32 mss = skb_shinfo(skb)->gso_size;
4222 return LargeSend | ((mss & MSSMask) << MSSShift);
4224 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4225 const struct iphdr *ip = ip_hdr(skb);
4227 if (ip->protocol == IPPROTO_TCP)
4228 return IPCS | TCPCS;
4229 else if (ip->protocol == IPPROTO_UDP)
4230 return IPCS | UDPCS;
4231 WARN_ON(1); /* we need a WARN() */
4236 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4237 struct net_device *dev)
4239 struct rtl8169_private *tp = netdev_priv(dev);
4240 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4241 struct TxDesc *txd = tp->TxDescArray + entry;
4242 void __iomem *ioaddr = tp->mmio_addr;
4247 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4248 if (netif_msg_drv(tp)) {
4250 "%s: BUG! Tx Ring full when queue awake!\n",
4256 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4259 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4261 frags = rtl8169_xmit_frags(tp, skb, opts1);
4263 len = skb_headlen(skb);
4267 opts1 |= FirstFrag | LastFrag;
4268 tp->tx_skb[entry].skb = skb;
4271 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4273 tp->tx_skb[entry].len = len;
4274 txd->addr = cpu_to_le64(mapping);
4275 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4279 /* anti gcc 2.95.3 bugware (sic) */
4280 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4281 txd->opts1 = cpu_to_le32(status);
4283 tp->cur_tx += frags + 1;
4287 RTL_W8(TxPoll, NPQ); /* set polling bit */
4289 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4290 netif_stop_queue(dev);
4292 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4293 netif_wake_queue(dev);
4296 return NETDEV_TX_OK;
4299 netif_stop_queue(dev);
4300 dev->stats.tx_dropped++;
4301 return NETDEV_TX_BUSY;
4304 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4306 struct rtl8169_private *tp = netdev_priv(dev);
4307 struct pci_dev *pdev = tp->pci_dev;
4308 void __iomem *ioaddr = tp->mmio_addr;
4309 u16 pci_status, pci_cmd;
4311 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4312 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4314 if (netif_msg_intr(tp)) {
4316 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4317 dev->name, pci_cmd, pci_status);
4321 * The recovery sequence below admits a very elaborated explanation:
4322 * - it seems to work;
4323 * - I did not see what else could be done;
4324 * - it makes iop3xx happy.
4326 * Feel free to adjust to your needs.
4328 if (pdev->broken_parity_status)
4329 pci_cmd &= ~PCI_COMMAND_PARITY;
4331 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4333 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4335 pci_write_config_word(pdev, PCI_STATUS,
4336 pci_status & (PCI_STATUS_DETECTED_PARITY |
4337 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4338 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4340 /* The infamous DAC f*ckup only happens at boot time */
4341 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4342 if (netif_msg_intr(tp))
4343 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
4344 tp->cp_cmd &= ~PCIDAC;
4345 RTL_W16(CPlusCmd, tp->cp_cmd);
4346 dev->features &= ~NETIF_F_HIGHDMA;
4349 rtl8169_hw_reset(ioaddr);
4351 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4354 static void rtl8169_tx_interrupt(struct net_device *dev,
4355 struct rtl8169_private *tp,
4356 void __iomem *ioaddr)
4358 unsigned int dirty_tx, tx_left;
4360 dirty_tx = tp->dirty_tx;
4362 tx_left = tp->cur_tx - dirty_tx;
4364 while (tx_left > 0) {
4365 unsigned int entry = dirty_tx % NUM_TX_DESC;
4366 struct ring_info *tx_skb = tp->tx_skb + entry;
4367 u32 len = tx_skb->len;
4371 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4372 if (status & DescOwn)
4375 dev->stats.tx_bytes += len;
4376 dev->stats.tx_packets++;
4378 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4380 if (status & LastFrag) {
4381 dev_kfree_skb(tx_skb->skb);
4388 if (tp->dirty_tx != dirty_tx) {
4389 tp->dirty_tx = dirty_tx;
4391 if (netif_queue_stopped(dev) &&
4392 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4393 netif_wake_queue(dev);
4396 * 8168 hack: TxPoll requests are lost when the Tx packets are
4397 * too close. Let's kick an extra TxPoll request when a burst
4398 * of start_xmit activity is detected (if it is not detected,
4399 * it is slow enough). -- FR
4402 if (tp->cur_tx != dirty_tx)
4403 RTL_W8(TxPoll, NPQ);
4407 static inline int rtl8169_fragmented_frame(u32 status)
4409 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4412 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4414 u32 opts1 = le32_to_cpu(desc->opts1);
4415 u32 status = opts1 & RxProtoMask;
4417 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4418 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4419 ((status == RxProtoIP) && !(opts1 & IPFail)))
4420 skb->ip_summed = CHECKSUM_UNNECESSARY;
4422 skb->ip_summed = CHECKSUM_NONE;
4425 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4426 struct rtl8169_private *tp, int pkt_size,
4429 struct sk_buff *skb;
4432 if (pkt_size >= rx_copybreak)
4435 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
4439 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4440 PCI_DMA_FROMDEVICE);
4441 skb_reserve(skb, NET_IP_ALIGN);
4442 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4449 static int rtl8169_rx_interrupt(struct net_device *dev,
4450 struct rtl8169_private *tp,
4451 void __iomem *ioaddr, u32 budget)
4453 unsigned int cur_rx, rx_left;
4454 unsigned int delta, count;
4456 cur_rx = tp->cur_rx;
4457 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4458 rx_left = min(rx_left, budget);
4460 for (; rx_left > 0; rx_left--, cur_rx++) {
4461 unsigned int entry = cur_rx % NUM_RX_DESC;
4462 struct RxDesc *desc = tp->RxDescArray + entry;
4466 status = le32_to_cpu(desc->opts1);
4468 if (status & DescOwn)
4470 if (unlikely(status & RxRES)) {
4471 if (netif_msg_rx_err(tp)) {
4473 "%s: Rx ERROR. status = %08x\n",
4476 dev->stats.rx_errors++;
4477 if (status & (RxRWT | RxRUNT))
4478 dev->stats.rx_length_errors++;
4480 dev->stats.rx_crc_errors++;
4481 if (status & RxFOVF) {
4482 rtl8169_schedule_work(dev, rtl8169_reset_task);
4483 dev->stats.rx_fifo_errors++;
4485 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4487 struct sk_buff *skb = tp->Rx_skbuff[entry];
4488 dma_addr_t addr = le64_to_cpu(desc->addr);
4489 int pkt_size = (status & 0x00001FFF) - 4;
4490 struct pci_dev *pdev = tp->pci_dev;
4493 * The driver does not support incoming fragmented
4494 * frames. They are seen as a symptom of over-mtu
4497 if (unlikely(rtl8169_fragmented_frame(status))) {
4498 dev->stats.rx_dropped++;
4499 dev->stats.rx_length_errors++;
4500 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4504 rtl8169_rx_csum(skb, desc);
4506 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4507 pci_dma_sync_single_for_device(pdev, addr,
4508 pkt_size, PCI_DMA_FROMDEVICE);
4509 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4511 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4512 PCI_DMA_FROMDEVICE);
4513 tp->Rx_skbuff[entry] = NULL;
4516 skb_put(skb, pkt_size);
4517 skb->protocol = eth_type_trans(skb, dev);
4519 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4520 netif_receive_skb(skb);
4522 dev->stats.rx_bytes += pkt_size;
4523 dev->stats.rx_packets++;
4526 /* Work around for AMD plateform. */
4527 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4528 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4534 count = cur_rx - tp->cur_rx;
4535 tp->cur_rx = cur_rx;
4537 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4538 if (!delta && count && netif_msg_intr(tp))
4539 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
4540 tp->dirty_rx += delta;
4543 * FIXME: until there is periodic timer to try and refill the ring,
4544 * a temporary shortage may definitely kill the Rx process.
4545 * - disable the asic to try and avoid an overflow and kick it again
4547 * - how do others driver handle this condition (Uh oh...).
4549 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
4550 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
4555 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4557 struct net_device *dev = dev_instance;
4558 struct rtl8169_private *tp = netdev_priv(dev);
4559 void __iomem *ioaddr = tp->mmio_addr;
4563 /* loop handling interrupts until we have no new ones or
4564 * we hit a invalid/hotplug case.
4566 status = RTL_R16(IntrStatus);
4567 while (status && status != 0xffff) {
4570 /* Handle all of the error cases first. These will reset
4571 * the chip, so just exit the loop.
4573 if (unlikely(!netif_running(dev))) {
4574 rtl8169_asic_down(ioaddr);
4578 /* Work around for rx fifo overflow */
4579 if (unlikely(status & RxFIFOOver) &&
4580 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4581 netif_stop_queue(dev);
4582 rtl8169_tx_timeout(dev);
4586 if (unlikely(status & SYSErr)) {
4587 rtl8169_pcierr_interrupt(dev);
4591 if (status & LinkChg)
4592 rtl8169_check_link_status(dev, tp, ioaddr);
4594 /* We need to see the lastest version of tp->intr_mask to
4595 * avoid ignoring an MSI interrupt and having to wait for
4596 * another event which may never come.
4599 if (status & tp->intr_mask & tp->napi_event) {
4600 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4601 tp->intr_mask = ~tp->napi_event;
4603 if (likely(napi_schedule_prep(&tp->napi)))
4604 __napi_schedule(&tp->napi);
4605 else if (netif_msg_intr(tp)) {
4606 printk(KERN_INFO "%s: interrupt %04x in poll\n",
4611 /* We only get a new MSI interrupt when all active irq
4612 * sources on the chip have been acknowledged. So, ack
4613 * everything we've seen and check if new sources have become
4614 * active to avoid blocking all interrupts from the chip.
4617 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4618 status = RTL_R16(IntrStatus);
4621 return IRQ_RETVAL(handled);
4624 static int rtl8169_poll(struct napi_struct *napi, int budget)
4626 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4627 struct net_device *dev = tp->dev;
4628 void __iomem *ioaddr = tp->mmio_addr;
4631 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4632 rtl8169_tx_interrupt(dev, tp, ioaddr);
4634 if (work_done < budget) {
4635 napi_complete(napi);
4637 /* We need for force the visibility of tp->intr_mask
4638 * for other CPUs, as we can loose an MSI interrupt
4639 * and potentially wait for a retransmit timeout if we don't.
4640 * The posted write to IntrMask is safe, as it will
4641 * eventually make it to the chip and we won't loose anything
4644 tp->intr_mask = 0xffff;
4646 RTL_W16(IntrMask, tp->intr_event);
4652 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4654 struct rtl8169_private *tp = netdev_priv(dev);
4656 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4659 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4660 RTL_W32(RxMissed, 0);
4663 static void rtl8169_down(struct net_device *dev)
4665 struct rtl8169_private *tp = netdev_priv(dev);
4666 void __iomem *ioaddr = tp->mmio_addr;
4667 unsigned int intrmask;
4669 rtl8169_delete_timer(dev);
4671 netif_stop_queue(dev);
4673 napi_disable(&tp->napi);
4676 spin_lock_irq(&tp->lock);
4678 rtl8169_asic_down(ioaddr);
4680 rtl8169_rx_missed(dev, ioaddr);
4682 spin_unlock_irq(&tp->lock);
4684 synchronize_irq(dev->irq);
4686 /* Give a racing hard_start_xmit a few cycles to complete. */
4687 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4690 * And now for the 50k$ question: are IRQ disabled or not ?
4692 * Two paths lead here:
4694 * -> netif_running() is available to sync the current code and the
4695 * IRQ handler. See rtl8169_interrupt for details.
4696 * 2) dev->change_mtu
4697 * -> rtl8169_poll can not be issued again and re-enable the
4698 * interruptions. Let's simply issue the IRQ down sequence again.
4700 * No loop if hotpluged or major error (0xffff).
4702 intrmask = RTL_R16(IntrMask);
4703 if (intrmask && (intrmask != 0xffff))
4706 rtl8169_tx_clear(tp);
4708 rtl8169_rx_clear(tp);
4711 static int rtl8169_close(struct net_device *dev)
4713 struct rtl8169_private *tp = netdev_priv(dev);
4714 struct pci_dev *pdev = tp->pci_dev;
4716 /* update counters before going down */
4717 rtl8169_update_counters(dev);
4721 free_irq(dev->irq, dev);
4723 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4725 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4727 tp->TxDescArray = NULL;
4728 tp->RxDescArray = NULL;
4733 static void rtl_set_rx_mode(struct net_device *dev)
4735 struct rtl8169_private *tp = netdev_priv(dev);
4736 void __iomem *ioaddr = tp->mmio_addr;
4737 unsigned long flags;
4738 u32 mc_filter[2]; /* Multicast hash filter */
4742 if (dev->flags & IFF_PROMISC) {
4743 /* Unconditionally log net taps. */
4744 if (netif_msg_link(tp)) {
4745 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
4749 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4751 mc_filter[1] = mc_filter[0] = 0xffffffff;
4752 } else if ((dev->mc_count > multicast_filter_limit)
4753 || (dev->flags & IFF_ALLMULTI)) {
4754 /* Too many to filter perfectly -- accept all multicasts. */
4755 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4756 mc_filter[1] = mc_filter[0] = 0xffffffff;
4758 struct dev_mc_list *mclist;
4761 rx_mode = AcceptBroadcast | AcceptMyPhys;
4762 mc_filter[1] = mc_filter[0] = 0;
4763 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
4764 i++, mclist = mclist->next) {
4765 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4766 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4767 rx_mode |= AcceptMulticast;
4771 spin_lock_irqsave(&tp->lock, flags);
4773 tmp = rtl8169_rx_config | rx_mode |
4774 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4776 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4777 u32 data = mc_filter[0];
4779 mc_filter[0] = swab32(mc_filter[1]);
4780 mc_filter[1] = swab32(data);
4783 RTL_W32(MAR0 + 0, mc_filter[0]);
4784 RTL_W32(MAR0 + 4, mc_filter[1]);
4786 RTL_W32(RxConfig, tmp);
4788 spin_unlock_irqrestore(&tp->lock, flags);
4792 * rtl8169_get_stats - Get rtl8169 read/write statistics
4793 * @dev: The Ethernet Device to get statistics for
4795 * Get TX/RX statistics for rtl8169
4797 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4799 struct rtl8169_private *tp = netdev_priv(dev);
4800 void __iomem *ioaddr = tp->mmio_addr;
4801 unsigned long flags;
4803 if (netif_running(dev)) {
4804 spin_lock_irqsave(&tp->lock, flags);
4805 rtl8169_rx_missed(dev, ioaddr);
4806 spin_unlock_irqrestore(&tp->lock, flags);
4812 static void rtl8169_net_suspend(struct net_device *dev)
4814 if (!netif_running(dev))
4817 netif_device_detach(dev);
4818 netif_stop_queue(dev);
4823 static int rtl8169_suspend(struct device *device)
4825 struct pci_dev *pdev = to_pci_dev(device);
4826 struct net_device *dev = pci_get_drvdata(pdev);
4828 rtl8169_net_suspend(dev);
4833 static int rtl8169_resume(struct device *device)
4835 struct pci_dev *pdev = to_pci_dev(device);
4836 struct net_device *dev = pci_get_drvdata(pdev);
4838 if (!netif_running(dev))
4841 netif_device_attach(dev);
4843 rtl8169_schedule_work(dev, rtl8169_reset_task);
4848 static struct dev_pm_ops rtl8169_pm_ops = {
4849 .suspend = rtl8169_suspend,
4850 .resume = rtl8169_resume,
4851 .freeze = rtl8169_suspend,
4852 .thaw = rtl8169_resume,
4853 .poweroff = rtl8169_suspend,
4854 .restore = rtl8169_resume,
4857 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4859 #else /* !CONFIG_PM */
4861 #define RTL8169_PM_OPS NULL
4863 #endif /* !CONFIG_PM */
4865 static void rtl_shutdown(struct pci_dev *pdev)
4867 struct net_device *dev = pci_get_drvdata(pdev);
4868 struct rtl8169_private *tp = netdev_priv(dev);
4869 void __iomem *ioaddr = tp->mmio_addr;
4871 rtl8169_net_suspend(dev);
4873 spin_lock_irq(&tp->lock);
4875 rtl8169_asic_down(ioaddr);
4877 spin_unlock_irq(&tp->lock);
4879 if (system_state == SYSTEM_POWER_OFF) {
4880 /* WoL fails with some 8168 when the receiver is disabled. */
4881 if (tp->features & RTL_FEATURE_WOL) {
4882 pci_clear_master(pdev);
4884 RTL_W8(ChipCmd, CmdRxEnb);
4889 pci_wake_from_d3(pdev, true);
4890 pci_set_power_state(pdev, PCI_D3hot);
4894 static struct pci_driver rtl8169_pci_driver = {
4896 .id_table = rtl8169_pci_tbl,
4897 .probe = rtl8169_init_one,
4898 .remove = __devexit_p(rtl8169_remove_one),
4899 .shutdown = rtl_shutdown,
4900 .driver.pm = RTL8169_PM_OPS,
4903 static int __init rtl8169_init_module(void)
4905 return pci_register_driver(&rtl8169_pci_driver);
4908 static void __exit rtl8169_cleanup_module(void)
4910 pci_unregister_driver(&rtl8169_pci_driver);
4913 module_init(rtl8169_init_module);
4914 module_exit(rtl8169_cleanup_module);