2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit = 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) readl (ioaddr + (reg))
94 RTL_GIGA_MAC_NONE = 0x00,
95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device *);
169 static void rtl_hw_start_8168(struct net_device *);
170 static void rtl_hw_start_8101(struct net_device *);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
188 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
195 static int rx_copybreak = 16383;
202 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
237 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8,
239 FuncForceEvent = 0xfc,
242 enum rtl8110_registers {
248 enum rtl8168_8101_registers {
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0f
254 #define CSIAR_BYTE_ENABLE_SHIFT 12
255 #define CSIAR_ADDR_MASK 0x0fff
258 #define EPHYAR_FLAG 0x80000000
259 #define EPHYAR_WRITE_CMD 0x80000000
260 #define EPHYAR_REG_MASK 0x1f
261 #define EPHYAR_REG_SHIFT 16
262 #define EPHYAR_DATA_MASK 0xffff
264 #define FIX_NAK_1 (1 << 4)
265 #define FIX_NAK_2 (1 << 3)
267 #define EFUSEAR_FLAG 0x80000000
268 #define EFUSEAR_WRITE_CMD 0x80000000
269 #define EFUSEAR_READ_CMD 0x00000000
270 #define EFUSEAR_REG_MASK 0x03ff
271 #define EFUSEAR_REG_SHIFT 8
272 #define EFUSEAR_DATA_MASK 0xff
275 enum rtl_register_content {
276 /* InterruptStatusBits */
280 TxDescUnavail = 0x0080,
302 /* TXPoll register p.5 */
303 HPQ = 0x80, /* Poll cmd on the high prio queue */
304 NPQ = 0x40, /* Poll cmd on the low prio queue */
305 FSWInt = 0x01, /* Forced software interrupt */
309 Cfg9346_Unlock = 0xc0,
314 AcceptBroadcast = 0x08,
315 AcceptMulticast = 0x04,
317 AcceptAllPhys = 0x01,
324 TxInterFrameGapShift = 24,
325 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
327 /* Config1 register p.24 */
330 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
331 Speed_down = (1 << 4),
335 PMEnable = (1 << 0), /* Power Management Enable */
337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz = 0x01,
339 PCI_Clock_33MHz = 0x00,
341 /* Config3 register p.25 */
342 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
344 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
346 /* Config5 register p.27 */
347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake = (1 << 1), /* LanWake enable/disable */
351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
354 TBIReset = 0x80000000,
355 TBILoopback = 0x40000000,
356 TBINwEnable = 0x20000000,
357 TBINwRestart = 0x10000000,
358 TBILinkOk = 0x02000000,
359 TBINwComplete = 0x01000000,
362 EnableBist = (1 << 15), // 8168 8101
363 Mac_dbgo_oe = (1 << 14), // 8168 8101
364 Normal_mode = (1 << 13), // unused
365 Force_half_dup = (1 << 12), // 8168 8101
366 Force_rxflow_en = (1 << 11), // 8168 8101
367 Force_txflow_en = (1 << 10), // 8168 8101
368 Cxpl_dbg_sel = (1 << 9), // 8168 8101
369 ASF = (1 << 8), // 8168 8101
370 PktCntrDisable = (1 << 7), // 8168 8101
371 Mac_dbgo_sel = 0x001c, // 8168
376 INTT_0 = 0x0000, // 8168
377 INTT_1 = 0x0001, // 8168
378 INTT_2 = 0x0002, // 8168
379 INTT_3 = 0x0003, // 8168
381 /* rtl8169_PHYstatus */
392 TBILinkOK = 0x02000000,
394 /* DumpCounterCommand */
398 enum desc_status_bit {
399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
417 #define RxProtoUDP (PID1)
418 #define RxProtoTCP (PID0)
419 #define RxProtoIP (PID1 | PID0)
420 #define RxProtoMask RxProtoIP
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
428 #define RsvdMask 0x3fffc000
445 u8 __pad[sizeof(void *) - sizeof(u32)];
449 RTL_FEATURE_WOL = (1 << 0),
450 RTL_FEATURE_MSI = (1 << 1),
451 RTL_FEATURE_GMII = (1 << 2),
454 struct rtl8169_counters {
461 __le32 tx_one_collision;
462 __le32 tx_multi_collision;
470 struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */
473 struct net_device *dev;
474 struct napi_struct napi;
475 spinlock_t lock; /* spin lock flag */
479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
483 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
491 struct timer_list timer;
496 int phy_1000_ctrl_reg;
497 #ifdef CONFIG_R8169_VLAN
498 struct vlan_group *vlgrp;
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
501 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
502 void (*phy_reset_enable)(void __iomem *);
503 void (*hw_start)(struct net_device *);
504 unsigned int (*phy_reset_pending)(void __iomem *);
505 unsigned int (*link_ok)(void __iomem *);
506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
508 struct delayed_work task;
511 struct mii_if_info mii;
512 struct rtl8169_counters counters;
516 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
517 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
518 module_param(rx_copybreak, int, 0);
519 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
520 module_param(use_dac, int, 0);
521 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
522 module_param_named(debug, debug.msg_enable, int, 0);
523 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
524 MODULE_LICENSE("GPL");
525 MODULE_VERSION(RTL8169_VERSION);
527 static int rtl8169_open(struct net_device *dev);
528 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
529 struct net_device *dev);
530 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
531 static int rtl8169_init_ring(struct net_device *dev);
532 static void rtl_hw_start(struct net_device *dev);
533 static int rtl8169_close(struct net_device *dev);
534 static void rtl_set_rx_mode(struct net_device *dev);
535 static void rtl8169_tx_timeout(struct net_device *dev);
536 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
537 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
538 void __iomem *, u32 budget);
539 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
540 static void rtl8169_down(struct net_device *dev);
541 static void rtl8169_rx_clear(struct rtl8169_private *tp);
542 static int rtl8169_poll(struct napi_struct *napi, int budget);
544 static const unsigned int rtl8169_rx_config =
545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
547 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
553 for (i = 20; i > 0; i--) {
555 * Check if the RTL8169 has completed writing to the specified
558 if (!(RTL_R32(PHYAR) & 0x80000000))
563 * According to hardware specs a 20us delay is required after write
564 * complete indication, but before sending next command.
569 static int mdio_read(void __iomem *ioaddr, int reg_addr)
573 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
575 for (i = 20; i > 0; i--) {
577 * Check if the RTL8169 has completed retrieving data from
578 * the specified MII register.
580 if (RTL_R32(PHYAR) & 0x80000000) {
581 value = RTL_R32(PHYAR) & 0xffff;
587 * According to hardware specs a 20us delay is required after read
588 * complete indication, but before sending next command.
595 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
597 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
600 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
604 val = mdio_read(ioaddr, reg_addr);
605 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
608 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
611 struct rtl8169_private *tp = netdev_priv(dev);
612 void __iomem *ioaddr = tp->mmio_addr;
614 mdio_write(ioaddr, location, val);
617 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
619 struct rtl8169_private *tp = netdev_priv(dev);
620 void __iomem *ioaddr = tp->mmio_addr;
622 return mdio_read(ioaddr, location);
625 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
629 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
630 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
632 for (i = 0; i < 100; i++) {
633 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
639 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
644 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
646 for (i = 0; i < 100; i++) {
647 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
648 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
657 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
661 RTL_W32(CSIDR, value);
662 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
663 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
665 for (i = 0; i < 100; i++) {
666 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
672 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
677 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
678 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
680 for (i = 0; i < 100; i++) {
681 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
682 value = RTL_R32(CSIDR);
691 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
696 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
698 for (i = 0; i < 300; i++) {
699 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
700 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
709 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
711 RTL_W16(IntrMask, 0x0000);
713 RTL_W16(IntrStatus, 0xffff);
716 static void rtl8169_asic_down(void __iomem *ioaddr)
718 RTL_W8(ChipCmd, 0x00);
719 rtl8169_irq_mask_and_ack(ioaddr);
723 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
725 return RTL_R32(TBICSR) & TBIReset;
728 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
730 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
733 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
735 return RTL_R32(TBICSR) & TBILinkOk;
738 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
740 return RTL_R8(PHYstatus) & LinkStatus;
743 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
745 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
748 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
752 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
753 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
756 static void rtl8169_check_link_status(struct net_device *dev,
757 struct rtl8169_private *tp,
758 void __iomem *ioaddr)
762 spin_lock_irqsave(&tp->lock, flags);
763 if (tp->link_ok(ioaddr)) {
764 /* This is to cancel a scheduled suspend if there's one. */
765 pm_request_resume(&tp->pci_dev->dev);
766 netif_carrier_on(dev);
767 netif_info(tp, ifup, dev, "link up\n");
769 netif_carrier_off(dev);
770 netif_info(tp, ifdown, dev, "link down\n");
771 pm_schedule_suspend(&tp->pci_dev->dev, 100);
773 spin_unlock_irqrestore(&tp->lock, flags);
776 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
778 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
780 void __iomem *ioaddr = tp->mmio_addr;
784 options = RTL_R8(Config1);
785 if (!(options & PMEnable))
788 options = RTL_R8(Config3);
789 if (options & LinkUp)
791 if (options & MagicPacket)
792 wolopts |= WAKE_MAGIC;
794 options = RTL_R8(Config5);
796 wolopts |= WAKE_UCAST;
798 wolopts |= WAKE_BCAST;
800 wolopts |= WAKE_MCAST;
805 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
807 struct rtl8169_private *tp = netdev_priv(dev);
809 spin_lock_irq(&tp->lock);
811 wol->supported = WAKE_ANY;
812 wol->wolopts = __rtl8169_get_wol(tp);
814 spin_unlock_irq(&tp->lock);
817 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
819 void __iomem *ioaddr = tp->mmio_addr;
821 static const struct {
826 { WAKE_ANY, Config1, PMEnable },
827 { WAKE_PHY, Config3, LinkUp },
828 { WAKE_MAGIC, Config3, MagicPacket },
829 { WAKE_UCAST, Config5, UWF },
830 { WAKE_BCAST, Config5, BWF },
831 { WAKE_MCAST, Config5, MWF },
832 { WAKE_ANY, Config5, LanWake }
835 RTL_W8(Cfg9346, Cfg9346_Unlock);
837 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
838 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
839 if (wolopts & cfg[i].opt)
840 options |= cfg[i].mask;
841 RTL_W8(cfg[i].reg, options);
844 RTL_W8(Cfg9346, Cfg9346_Lock);
847 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
849 struct rtl8169_private *tp = netdev_priv(dev);
851 spin_lock_irq(&tp->lock);
854 tp->features |= RTL_FEATURE_WOL;
856 tp->features &= ~RTL_FEATURE_WOL;
857 __rtl8169_set_wol(tp, wol->wolopts);
858 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
860 spin_unlock_irq(&tp->lock);
865 static void rtl8169_get_drvinfo(struct net_device *dev,
866 struct ethtool_drvinfo *info)
868 struct rtl8169_private *tp = netdev_priv(dev);
870 strcpy(info->driver, MODULENAME);
871 strcpy(info->version, RTL8169_VERSION);
872 strcpy(info->bus_info, pci_name(tp->pci_dev));
875 static int rtl8169_get_regs_len(struct net_device *dev)
877 return R8169_REGS_SIZE;
880 static int rtl8169_set_speed_tbi(struct net_device *dev,
881 u8 autoneg, u16 speed, u8 duplex)
883 struct rtl8169_private *tp = netdev_priv(dev);
884 void __iomem *ioaddr = tp->mmio_addr;
888 reg = RTL_R32(TBICSR);
889 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
890 (duplex == DUPLEX_FULL)) {
891 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
892 } else if (autoneg == AUTONEG_ENABLE)
893 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
895 netif_warn(tp, link, dev,
896 "incorrect speed setting refused in TBI mode\n");
903 static int rtl8169_set_speed_xmii(struct net_device *dev,
904 u8 autoneg, u16 speed, u8 duplex)
906 struct rtl8169_private *tp = netdev_priv(dev);
907 void __iomem *ioaddr = tp->mmio_addr;
910 if (autoneg == AUTONEG_ENABLE) {
913 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
914 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
915 ADVERTISE_100HALF | ADVERTISE_100FULL);
916 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
918 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
919 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
921 /* The 8100e/8101e/8102e do Fast Ethernet only. */
922 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
923 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
924 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
925 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
926 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
927 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
928 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
929 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
930 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
932 netif_info(tp, link, dev,
933 "PHY does not support 1000Mbps\n");
936 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
938 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
939 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
940 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
943 * Vendor specific (0x1f) and reserved (0x0e) MII
946 mdio_write(ioaddr, 0x1f, 0x0000);
947 mdio_write(ioaddr, 0x0e, 0x0000);
950 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
951 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
955 if (speed == SPEED_10)
957 else if (speed == SPEED_100)
958 bmcr = BMCR_SPEED100;
962 if (duplex == DUPLEX_FULL)
963 bmcr |= BMCR_FULLDPLX;
965 mdio_write(ioaddr, 0x1f, 0x0000);
968 tp->phy_1000_ctrl_reg = giga_ctrl;
970 mdio_write(ioaddr, MII_BMCR, bmcr);
972 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
973 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
974 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
975 mdio_write(ioaddr, 0x17, 0x2138);
976 mdio_write(ioaddr, 0x0e, 0x0260);
978 mdio_write(ioaddr, 0x17, 0x2108);
979 mdio_write(ioaddr, 0x0e, 0x0000);
986 static int rtl8169_set_speed(struct net_device *dev,
987 u8 autoneg, u16 speed, u8 duplex)
989 struct rtl8169_private *tp = netdev_priv(dev);
992 ret = tp->set_speed(dev, autoneg, speed, duplex);
994 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
995 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1000 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1002 struct rtl8169_private *tp = netdev_priv(dev);
1003 unsigned long flags;
1006 spin_lock_irqsave(&tp->lock, flags);
1007 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1008 spin_unlock_irqrestore(&tp->lock, flags);
1013 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1015 struct rtl8169_private *tp = netdev_priv(dev);
1017 return tp->cp_cmd & RxChkSum;
1020 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1022 struct rtl8169_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->mmio_addr;
1024 unsigned long flags;
1026 spin_lock_irqsave(&tp->lock, flags);
1029 tp->cp_cmd |= RxChkSum;
1031 tp->cp_cmd &= ~RxChkSum;
1033 RTL_W16(CPlusCmd, tp->cp_cmd);
1036 spin_unlock_irqrestore(&tp->lock, flags);
1041 #ifdef CONFIG_R8169_VLAN
1043 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1044 struct sk_buff *skb)
1046 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1047 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1050 static void rtl8169_vlan_rx_register(struct net_device *dev,
1051 struct vlan_group *grp)
1053 struct rtl8169_private *tp = netdev_priv(dev);
1054 void __iomem *ioaddr = tp->mmio_addr;
1055 unsigned long flags;
1057 spin_lock_irqsave(&tp->lock, flags);
1060 * Do not disable RxVlan on 8110SCd.
1062 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1063 tp->cp_cmd |= RxVlan;
1065 tp->cp_cmd &= ~RxVlan;
1066 RTL_W16(CPlusCmd, tp->cp_cmd);
1068 spin_unlock_irqrestore(&tp->lock, flags);
1071 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1072 struct sk_buff *skb, int polling)
1074 u32 opts2 = le32_to_cpu(desc->opts2);
1075 struct vlan_group *vlgrp = tp->vlgrp;
1078 if (vlgrp && (opts2 & RxVlanTag)) {
1079 u16 vtag = swab16(opts2 & 0xffff);
1081 if (likely(polling))
1082 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1084 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1092 #else /* !CONFIG_R8169_VLAN */
1094 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1095 struct sk_buff *skb)
1100 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1101 struct sk_buff *skb, int polling)
1108 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1110 struct rtl8169_private *tp = netdev_priv(dev);
1111 void __iomem *ioaddr = tp->mmio_addr;
1115 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1116 cmd->port = PORT_FIBRE;
1117 cmd->transceiver = XCVR_INTERNAL;
1119 status = RTL_R32(TBICSR);
1120 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1121 cmd->autoneg = !!(status & TBINwEnable);
1123 cmd->speed = SPEED_1000;
1124 cmd->duplex = DUPLEX_FULL; /* Always set */
1129 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1131 struct rtl8169_private *tp = netdev_priv(dev);
1133 return mii_ethtool_gset(&tp->mii, cmd);
1136 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139 unsigned long flags;
1142 spin_lock_irqsave(&tp->lock, flags);
1144 rc = tp->get_settings(dev, cmd);
1146 spin_unlock_irqrestore(&tp->lock, flags);
1150 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1153 struct rtl8169_private *tp = netdev_priv(dev);
1154 unsigned long flags;
1156 if (regs->len > R8169_REGS_SIZE)
1157 regs->len = R8169_REGS_SIZE;
1159 spin_lock_irqsave(&tp->lock, flags);
1160 memcpy_fromio(p, tp->mmio_addr, regs->len);
1161 spin_unlock_irqrestore(&tp->lock, flags);
1164 static u32 rtl8169_get_msglevel(struct net_device *dev)
1166 struct rtl8169_private *tp = netdev_priv(dev);
1168 return tp->msg_enable;
1171 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1173 struct rtl8169_private *tp = netdev_priv(dev);
1175 tp->msg_enable = value;
1178 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1185 "tx_single_collisions",
1186 "tx_multi_collisions",
1194 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1198 return ARRAY_SIZE(rtl8169_gstrings);
1204 static void rtl8169_update_counters(struct net_device *dev)
1206 struct rtl8169_private *tp = netdev_priv(dev);
1207 void __iomem *ioaddr = tp->mmio_addr;
1208 struct rtl8169_counters *counters;
1214 * Some chips are unable to dump tally counters when the receiver
1217 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1220 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1224 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1225 cmd = (u64)paddr & DMA_BIT_MASK(32);
1226 RTL_W32(CounterAddrLow, cmd);
1227 RTL_W32(CounterAddrLow, cmd | CounterDump);
1230 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1231 /* copy updated counters */
1232 memcpy(&tp->counters, counters, sizeof(*counters));
1238 RTL_W32(CounterAddrLow, 0);
1239 RTL_W32(CounterAddrHigh, 0);
1241 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1244 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1245 struct ethtool_stats *stats, u64 *data)
1247 struct rtl8169_private *tp = netdev_priv(dev);
1251 rtl8169_update_counters(dev);
1253 data[0] = le64_to_cpu(tp->counters.tx_packets);
1254 data[1] = le64_to_cpu(tp->counters.rx_packets);
1255 data[2] = le64_to_cpu(tp->counters.tx_errors);
1256 data[3] = le32_to_cpu(tp->counters.rx_errors);
1257 data[4] = le16_to_cpu(tp->counters.rx_missed);
1258 data[5] = le16_to_cpu(tp->counters.align_errors);
1259 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1260 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1261 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1262 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1263 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1264 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1265 data[12] = le16_to_cpu(tp->counters.tx_underun);
1268 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1272 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1277 static const struct ethtool_ops rtl8169_ethtool_ops = {
1278 .get_drvinfo = rtl8169_get_drvinfo,
1279 .get_regs_len = rtl8169_get_regs_len,
1280 .get_link = ethtool_op_get_link,
1281 .get_settings = rtl8169_get_settings,
1282 .set_settings = rtl8169_set_settings,
1283 .get_msglevel = rtl8169_get_msglevel,
1284 .set_msglevel = rtl8169_set_msglevel,
1285 .get_rx_csum = rtl8169_get_rx_csum,
1286 .set_rx_csum = rtl8169_set_rx_csum,
1287 .set_tx_csum = ethtool_op_set_tx_csum,
1288 .set_sg = ethtool_op_set_sg,
1289 .set_tso = ethtool_op_set_tso,
1290 .get_regs = rtl8169_get_regs,
1291 .get_wol = rtl8169_get_wol,
1292 .set_wol = rtl8169_set_wol,
1293 .get_strings = rtl8169_get_strings,
1294 .get_sset_count = rtl8169_get_sset_count,
1295 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1298 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1299 void __iomem *ioaddr)
1302 * The driver currently handles the 8168Bf and the 8168Be identically
1303 * but they can be identified more specifically through the test below
1306 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1308 * Same thing for the 8101Eb and the 8101Ec:
1310 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1312 static const struct {
1318 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1319 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1320 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1321 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1324 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1325 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1326 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1327 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1328 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1329 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1330 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1331 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1332 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1335 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1336 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1337 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1338 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1341 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1342 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1343 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1344 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1345 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1346 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1347 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1348 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1349 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1350 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1351 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1352 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1353 /* FIXME: where did these entries come from ? -- FR */
1354 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1355 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1358 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1359 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1360 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1361 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1362 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1363 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1366 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1370 reg = RTL_R32(TxConfig);
1371 while ((reg & p->mask) != p->val)
1373 tp->mac_version = p->mac_version;
1376 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1378 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1386 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1389 mdio_write(ioaddr, regs->reg, regs->val);
1394 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1396 static const struct phy_reg phy_reg_init[] = {
1458 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1461 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1463 static const struct phy_reg phy_reg_init[] = {
1469 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1472 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1473 void __iomem *ioaddr)
1475 struct pci_dev *pdev = tp->pci_dev;
1476 u16 vendor_id, device_id;
1478 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1479 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1481 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1484 mdio_write(ioaddr, 0x1f, 0x0001);
1485 mdio_write(ioaddr, 0x10, 0xf01b);
1486 mdio_write(ioaddr, 0x1f, 0x0000);
1489 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1490 void __iomem *ioaddr)
1492 static const struct phy_reg phy_reg_init[] = {
1532 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1534 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1537 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1539 static const struct phy_reg phy_reg_init[] = {
1587 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1590 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1592 static const struct phy_reg phy_reg_init[] = {
1597 mdio_write(ioaddr, 0x1f, 0x0001);
1598 mdio_patch(ioaddr, 0x16, 1 << 0);
1600 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1603 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1605 static const struct phy_reg phy_reg_init[] = {
1611 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1614 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1616 static const struct phy_reg phy_reg_init[] = {
1624 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1627 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1629 static const struct phy_reg phy_reg_init[] = {
1635 mdio_write(ioaddr, 0x1f, 0x0000);
1636 mdio_patch(ioaddr, 0x14, 1 << 5);
1637 mdio_patch(ioaddr, 0x0d, 1 << 5);
1639 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1642 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1644 static const struct phy_reg phy_reg_init[] = {
1664 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1666 mdio_patch(ioaddr, 0x14, 1 << 5);
1667 mdio_patch(ioaddr, 0x0d, 1 << 5);
1668 mdio_write(ioaddr, 0x1f, 0x0000);
1671 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1673 static const struct phy_reg phy_reg_init[] = {
1691 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1693 mdio_patch(ioaddr, 0x16, 1 << 0);
1694 mdio_patch(ioaddr, 0x14, 1 << 5);
1695 mdio_patch(ioaddr, 0x0d, 1 << 5);
1696 mdio_write(ioaddr, 0x1f, 0x0000);
1699 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1701 static const struct phy_reg phy_reg_init[] = {
1713 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1715 mdio_patch(ioaddr, 0x16, 1 << 0);
1716 mdio_patch(ioaddr, 0x14, 1 << 5);
1717 mdio_patch(ioaddr, 0x0d, 1 << 5);
1718 mdio_write(ioaddr, 0x1f, 0x0000);
1721 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1723 rtl8168c_3_hw_phy_config(ioaddr);
1726 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1728 static const struct phy_reg phy_reg_init_0[] = {
1747 static const struct phy_reg phy_reg_init_1[] = {
1754 static const struct phy_reg phy_reg_init_2[] = {
2110 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2112 mdio_write(ioaddr, 0x1f, 0x0002);
2113 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2114 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2116 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2118 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2119 static const struct phy_reg phy_reg_init[] = {
2129 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2131 val = mdio_read(ioaddr, 0x0d);
2133 if ((val & 0x00ff) != 0x006c) {
2134 static const u32 set[] = {
2135 0x0065, 0x0066, 0x0067, 0x0068,
2136 0x0069, 0x006a, 0x006b, 0x006c
2140 mdio_write(ioaddr, 0x1f, 0x0002);
2143 for (i = 0; i < ARRAY_SIZE(set); i++)
2144 mdio_write(ioaddr, 0x0d, val | set[i]);
2147 static const struct phy_reg phy_reg_init[] = {
2155 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2158 mdio_write(ioaddr, 0x1f, 0x0002);
2159 mdio_patch(ioaddr, 0x0d, 0x0300);
2160 mdio_patch(ioaddr, 0x0f, 0x0010);
2162 mdio_write(ioaddr, 0x1f, 0x0002);
2163 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2164 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2166 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2169 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2171 static const struct phy_reg phy_reg_init_0[] = {
2196 static const struct phy_reg phy_reg_init_1[] = {
2509 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2511 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2512 static const struct phy_reg phy_reg_init[] = {
2523 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525 val = mdio_read(ioaddr, 0x0d);
2526 if ((val & 0x00ff) != 0x006c) {
2528 0x0065, 0x0066, 0x0067, 0x0068,
2529 0x0069, 0x006a, 0x006b, 0x006c
2533 mdio_write(ioaddr, 0x1f, 0x0002);
2536 for (i = 0; i < ARRAY_SIZE(set); i++)
2537 mdio_write(ioaddr, 0x0d, val | set[i]);
2540 static const struct phy_reg phy_reg_init[] = {
2548 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2551 mdio_write(ioaddr, 0x1f, 0x0002);
2552 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2553 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2555 mdio_write(ioaddr, 0x1f, 0x0001);
2556 mdio_write(ioaddr, 0x17, 0x0cc0);
2558 mdio_write(ioaddr, 0x1f, 0x0002);
2559 mdio_patch(ioaddr, 0x0f, 0x0017);
2561 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2564 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2566 static const struct phy_reg phy_reg_init[] = {
2622 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2625 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2627 static const struct phy_reg phy_reg_init[] = {
2634 mdio_write(ioaddr, 0x1f, 0x0000);
2635 mdio_patch(ioaddr, 0x11, 1 << 12);
2636 mdio_patch(ioaddr, 0x19, 1 << 13);
2637 mdio_patch(ioaddr, 0x10, 1 << 15);
2639 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642 static void rtl_hw_phy_config(struct net_device *dev)
2644 struct rtl8169_private *tp = netdev_priv(dev);
2645 void __iomem *ioaddr = tp->mmio_addr;
2647 rtl8169_print_mac_version(tp);
2649 switch (tp->mac_version) {
2650 case RTL_GIGA_MAC_VER_01:
2652 case RTL_GIGA_MAC_VER_02:
2653 case RTL_GIGA_MAC_VER_03:
2654 rtl8169s_hw_phy_config(ioaddr);
2656 case RTL_GIGA_MAC_VER_04:
2657 rtl8169sb_hw_phy_config(ioaddr);
2659 case RTL_GIGA_MAC_VER_05:
2660 rtl8169scd_hw_phy_config(tp, ioaddr);
2662 case RTL_GIGA_MAC_VER_06:
2663 rtl8169sce_hw_phy_config(ioaddr);
2665 case RTL_GIGA_MAC_VER_07:
2666 case RTL_GIGA_MAC_VER_08:
2667 case RTL_GIGA_MAC_VER_09:
2668 rtl8102e_hw_phy_config(ioaddr);
2670 case RTL_GIGA_MAC_VER_11:
2671 rtl8168bb_hw_phy_config(ioaddr);
2673 case RTL_GIGA_MAC_VER_12:
2674 rtl8168bef_hw_phy_config(ioaddr);
2676 case RTL_GIGA_MAC_VER_17:
2677 rtl8168bef_hw_phy_config(ioaddr);
2679 case RTL_GIGA_MAC_VER_18:
2680 rtl8168cp_1_hw_phy_config(ioaddr);
2682 case RTL_GIGA_MAC_VER_19:
2683 rtl8168c_1_hw_phy_config(ioaddr);
2685 case RTL_GIGA_MAC_VER_20:
2686 rtl8168c_2_hw_phy_config(ioaddr);
2688 case RTL_GIGA_MAC_VER_21:
2689 rtl8168c_3_hw_phy_config(ioaddr);
2691 case RTL_GIGA_MAC_VER_22:
2692 rtl8168c_4_hw_phy_config(ioaddr);
2694 case RTL_GIGA_MAC_VER_23:
2695 case RTL_GIGA_MAC_VER_24:
2696 rtl8168cp_2_hw_phy_config(ioaddr);
2698 case RTL_GIGA_MAC_VER_25:
2699 rtl8168d_1_hw_phy_config(ioaddr);
2701 case RTL_GIGA_MAC_VER_26:
2702 rtl8168d_2_hw_phy_config(ioaddr);
2704 case RTL_GIGA_MAC_VER_27:
2705 rtl8168d_3_hw_phy_config(ioaddr);
2713 static void rtl8169_phy_timer(unsigned long __opaque)
2715 struct net_device *dev = (struct net_device *)__opaque;
2716 struct rtl8169_private *tp = netdev_priv(dev);
2717 struct timer_list *timer = &tp->timer;
2718 void __iomem *ioaddr = tp->mmio_addr;
2719 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2721 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2723 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2726 spin_lock_irq(&tp->lock);
2728 if (tp->phy_reset_pending(ioaddr)) {
2730 * A busy loop could burn quite a few cycles on nowadays CPU.
2731 * Let's delay the execution of the timer for a few ticks.
2737 if (tp->link_ok(ioaddr))
2740 netif_warn(tp, link, dev, "PHY reset until link up\n");
2742 tp->phy_reset_enable(ioaddr);
2745 mod_timer(timer, jiffies + timeout);
2747 spin_unlock_irq(&tp->lock);
2750 static inline void rtl8169_delete_timer(struct net_device *dev)
2752 struct rtl8169_private *tp = netdev_priv(dev);
2753 struct timer_list *timer = &tp->timer;
2755 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2758 del_timer_sync(timer);
2761 static inline void rtl8169_request_timer(struct net_device *dev)
2763 struct rtl8169_private *tp = netdev_priv(dev);
2764 struct timer_list *timer = &tp->timer;
2766 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2769 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2772 #ifdef CONFIG_NET_POLL_CONTROLLER
2774 * Polling 'interrupt' - used by things like netconsole to send skbs
2775 * without having to re-enable interrupts. It's not called while
2776 * the interrupt routine is executing.
2778 static void rtl8169_netpoll(struct net_device *dev)
2780 struct rtl8169_private *tp = netdev_priv(dev);
2781 struct pci_dev *pdev = tp->pci_dev;
2783 disable_irq(pdev->irq);
2784 rtl8169_interrupt(pdev->irq, dev);
2785 enable_irq(pdev->irq);
2789 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2790 void __iomem *ioaddr)
2793 pci_release_regions(pdev);
2794 pci_clear_mwi(pdev);
2795 pci_disable_device(pdev);
2799 static void rtl8169_phy_reset(struct net_device *dev,
2800 struct rtl8169_private *tp)
2802 void __iomem *ioaddr = tp->mmio_addr;
2805 tp->phy_reset_enable(ioaddr);
2806 for (i = 0; i < 100; i++) {
2807 if (!tp->phy_reset_pending(ioaddr))
2811 netif_err(tp, link, dev, "PHY reset failed\n");
2814 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2816 void __iomem *ioaddr = tp->mmio_addr;
2818 rtl_hw_phy_config(dev);
2820 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2821 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2825 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2827 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2828 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2830 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2831 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2833 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2834 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2837 rtl8169_phy_reset(dev, tp);
2840 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2841 * only 8101. Don't panic.
2843 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2845 if (RTL_R8(PHYstatus) & TBI_Enable)
2846 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2849 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2851 void __iomem *ioaddr = tp->mmio_addr;
2855 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2856 high = addr[4] | (addr[5] << 8);
2858 spin_lock_irq(&tp->lock);
2860 RTL_W8(Cfg9346, Cfg9346_Unlock);
2862 RTL_W32(MAC4, high);
2868 RTL_W8(Cfg9346, Cfg9346_Lock);
2870 spin_unlock_irq(&tp->lock);
2873 static int rtl_set_mac_address(struct net_device *dev, void *p)
2875 struct rtl8169_private *tp = netdev_priv(dev);
2876 struct sockaddr *addr = p;
2878 if (!is_valid_ether_addr(addr->sa_data))
2879 return -EADDRNOTAVAIL;
2881 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2883 rtl_rar_set(tp, dev->dev_addr);
2888 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2890 struct rtl8169_private *tp = netdev_priv(dev);
2891 struct mii_ioctl_data *data = if_mii(ifr);
2893 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2896 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2900 data->phy_id = 32; /* Internal PHY */
2904 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2908 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2914 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2919 static const struct rtl_cfg_info {
2920 void (*hw_start)(struct net_device *);
2921 unsigned int region;
2927 } rtl_cfg_infos [] = {
2929 .hw_start = rtl_hw_start_8169,
2932 .intr_event = SYSErr | LinkChg | RxOverflow |
2933 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2934 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2935 .features = RTL_FEATURE_GMII,
2936 .default_ver = RTL_GIGA_MAC_VER_01,
2939 .hw_start = rtl_hw_start_8168,
2942 .intr_event = SYSErr | RxFIFOOver | LinkChg | RxOverflow |
2943 TxErr | TxOK | RxOK | RxErr,
2944 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2945 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2946 .default_ver = RTL_GIGA_MAC_VER_11,
2949 .hw_start = rtl_hw_start_8101,
2952 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2953 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2954 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2955 .features = RTL_FEATURE_MSI,
2956 .default_ver = RTL_GIGA_MAC_VER_13,
2960 /* Cfg9346_Unlock assumed. */
2961 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2962 const struct rtl_cfg_info *cfg)
2967 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2968 if (cfg->features & RTL_FEATURE_MSI) {
2969 if (pci_enable_msi(pdev)) {
2970 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2973 msi = RTL_FEATURE_MSI;
2976 RTL_W8(Config2, cfg2);
2980 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2982 if (tp->features & RTL_FEATURE_MSI) {
2983 pci_disable_msi(pdev);
2984 tp->features &= ~RTL_FEATURE_MSI;
2988 static const struct net_device_ops rtl8169_netdev_ops = {
2989 .ndo_open = rtl8169_open,
2990 .ndo_stop = rtl8169_close,
2991 .ndo_get_stats = rtl8169_get_stats,
2992 .ndo_start_xmit = rtl8169_start_xmit,
2993 .ndo_tx_timeout = rtl8169_tx_timeout,
2994 .ndo_validate_addr = eth_validate_addr,
2995 .ndo_change_mtu = rtl8169_change_mtu,
2996 .ndo_set_mac_address = rtl_set_mac_address,
2997 .ndo_do_ioctl = rtl8169_ioctl,
2998 .ndo_set_multicast_list = rtl_set_rx_mode,
2999 #ifdef CONFIG_R8169_VLAN
3000 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
3002 #ifdef CONFIG_NET_POLL_CONTROLLER
3003 .ndo_poll_controller = rtl8169_netpoll,
3008 static int __devinit
3009 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3011 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3012 const unsigned int region = cfg->region;
3013 struct rtl8169_private *tp;
3014 struct mii_if_info *mii;
3015 struct net_device *dev;
3016 void __iomem *ioaddr;
3020 if (netif_msg_drv(&debug)) {
3021 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3022 MODULENAME, RTL8169_VERSION);
3025 dev = alloc_etherdev(sizeof (*tp));
3027 if (netif_msg_drv(&debug))
3028 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3033 SET_NETDEV_DEV(dev, &pdev->dev);
3034 dev->netdev_ops = &rtl8169_netdev_ops;
3035 tp = netdev_priv(dev);
3038 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3042 mii->mdio_read = rtl_mdio_read;
3043 mii->mdio_write = rtl_mdio_write;
3044 mii->phy_id_mask = 0x1f;
3045 mii->reg_num_mask = 0x1f;
3046 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3048 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3049 rc = pci_enable_device(pdev);
3051 netif_err(tp, probe, dev, "enable failure\n");
3052 goto err_out_free_dev_1;
3055 if (pci_set_mwi(pdev) < 0)
3056 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3058 /* make sure PCI base addr 1 is MMIO */
3059 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3060 netif_err(tp, probe, dev,
3061 "region #%d not an MMIO resource, aborting\n",
3067 /* check for weird/broken PCI region reporting */
3068 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3069 netif_err(tp, probe, dev,
3070 "Invalid PCI region size(s), aborting\n");
3075 rc = pci_request_regions(pdev, MODULENAME);
3077 netif_err(tp, probe, dev, "could not request regions\n");
3081 tp->cp_cmd = PCIMulRW | RxChkSum;
3083 if ((sizeof(dma_addr_t) > 4) &&
3084 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3085 tp->cp_cmd |= PCIDAC;
3086 dev->features |= NETIF_F_HIGHDMA;
3088 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3090 netif_err(tp, probe, dev, "DMA configuration failed\n");
3091 goto err_out_free_res_3;
3095 /* ioremap MMIO region */
3096 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3098 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3100 goto err_out_free_res_3;
3103 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3105 netif_info(tp, probe, dev, "no PCI Express capability\n");
3107 RTL_W16(IntrMask, 0x0000);
3109 /* Soft reset the chip. */
3110 RTL_W8(ChipCmd, CmdReset);
3112 /* Check that the chip has finished the reset. */
3113 for (i = 0; i < 100; i++) {
3114 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3116 msleep_interruptible(1);
3119 RTL_W16(IntrStatus, 0xffff);
3121 pci_set_master(pdev);
3123 /* Identify chip attached to board */
3124 rtl8169_get_mac_version(tp, ioaddr);
3126 /* Use appropriate default if unknown */
3127 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3128 netif_notice(tp, probe, dev,
3129 "unknown MAC, using family default\n");
3130 tp->mac_version = cfg->default_ver;
3133 rtl8169_print_mac_version(tp);
3135 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3136 if (tp->mac_version == rtl_chip_info[i].mac_version)
3139 if (i == ARRAY_SIZE(rtl_chip_info)) {
3141 "driver bug, MAC version not found in rtl_chip_info\n");
3146 RTL_W8(Cfg9346, Cfg9346_Unlock);
3147 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3148 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3149 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3150 tp->features |= RTL_FEATURE_WOL;
3151 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3152 tp->features |= RTL_FEATURE_WOL;
3153 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3154 RTL_W8(Cfg9346, Cfg9346_Lock);
3156 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3157 (RTL_R8(PHYstatus) & TBI_Enable)) {
3158 tp->set_speed = rtl8169_set_speed_tbi;
3159 tp->get_settings = rtl8169_gset_tbi;
3160 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3161 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3162 tp->link_ok = rtl8169_tbi_link_ok;
3163 tp->do_ioctl = rtl_tbi_ioctl;
3165 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3167 tp->set_speed = rtl8169_set_speed_xmii;
3168 tp->get_settings = rtl8169_gset_xmii;
3169 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3170 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3171 tp->link_ok = rtl8169_xmii_link_ok;
3172 tp->do_ioctl = rtl_xmii_ioctl;
3175 spin_lock_init(&tp->lock);
3177 tp->mmio_addr = ioaddr;
3179 /* Get MAC address */
3180 for (i = 0; i < MAC_ADDR_LEN; i++)
3181 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3182 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3184 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3185 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3186 dev->irq = pdev->irq;
3187 dev->base_addr = (unsigned long) ioaddr;
3189 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3191 #ifdef CONFIG_R8169_VLAN
3192 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3194 dev->features |= NETIF_F_GRO;
3196 tp->intr_mask = 0xffff;
3197 tp->align = cfg->align;
3198 tp->hw_start = cfg->hw_start;
3199 tp->intr_event = cfg->intr_event;
3200 tp->napi_event = cfg->napi_event;
3202 init_timer(&tp->timer);
3203 tp->timer.data = (unsigned long) dev;
3204 tp->timer.function = rtl8169_phy_timer;
3206 rc = register_netdev(dev);
3210 pci_set_drvdata(pdev, dev);
3212 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3213 rtl_chip_info[tp->chipset].name,
3214 dev->base_addr, dev->dev_addr,
3215 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3217 rtl8169_init_phy(dev, tp);
3220 * Pretend we are using VLANs; This bypasses a nasty bug where
3221 * Interrupts stop flowing on high load on 8110SCd controllers.
3223 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3224 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3226 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3228 if (pci_dev_run_wake(pdev))
3229 pm_runtime_put_noidle(&pdev->dev);
3235 rtl_disable_msi(pdev, tp);
3238 pci_release_regions(pdev);
3240 pci_clear_mwi(pdev);
3241 pci_disable_device(pdev);
3247 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3249 struct net_device *dev = pci_get_drvdata(pdev);
3250 struct rtl8169_private *tp = netdev_priv(dev);
3252 flush_scheduled_work();
3254 unregister_netdev(dev);
3256 if (pci_dev_run_wake(pdev))
3257 pm_runtime_get_noresume(&pdev->dev);
3259 /* restore original MAC address */
3260 rtl_rar_set(tp, dev->perm_addr);
3262 rtl_disable_msi(pdev, tp);
3263 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3264 pci_set_drvdata(pdev, NULL);
3267 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3270 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3272 if (max_frame != 16383)
3273 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3274 "NIC may lead to frame reception errors!\n");
3276 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3279 static int rtl8169_open(struct net_device *dev)
3281 struct rtl8169_private *tp = netdev_priv(dev);
3282 struct pci_dev *pdev = tp->pci_dev;
3283 int retval = -ENOMEM;
3285 pm_runtime_get_sync(&pdev->dev);
3288 * Note that we use a magic value here, its wierd I know
3289 * its done because, some subset of rtl8169 hardware suffers from
3290 * a problem in which frames received that are longer than
3291 * the size set in RxMaxSize register return garbage sizes
3292 * when received. To avoid this we need to turn off filtering,
3293 * which is done by setting a value of 16383 in the RxMaxSize register
3294 * and allocating 16k frames to handle the largest possible rx value
3295 * thats what the magic math below does.
3297 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3300 * Rx and Tx desscriptors needs 256 bytes alignment.
3301 * pci_alloc_consistent provides more.
3303 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3305 if (!tp->TxDescArray)
3306 goto err_pm_runtime_put;
3308 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3310 if (!tp->RxDescArray)
3313 retval = rtl8169_init_ring(dev);
3317 INIT_DELAYED_WORK(&tp->task, NULL);
3321 retval = request_irq(dev->irq, rtl8169_interrupt,
3322 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3325 goto err_release_ring_2;
3327 napi_enable(&tp->napi);
3331 rtl8169_request_timer(dev);
3333 tp->saved_wolopts = 0;
3334 pm_runtime_put_noidle(&pdev->dev);
3336 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3341 rtl8169_rx_clear(tp);
3343 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3345 tp->RxDescArray = NULL;
3347 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3349 tp->TxDescArray = NULL;
3351 pm_runtime_put_noidle(&pdev->dev);
3355 static void rtl8169_hw_reset(void __iomem *ioaddr)
3357 /* Disable interrupts */
3358 rtl8169_irq_mask_and_ack(ioaddr);
3360 /* Reset the chipset */
3361 RTL_W8(ChipCmd, CmdReset);
3367 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3369 void __iomem *ioaddr = tp->mmio_addr;
3370 u32 cfg = rtl8169_rx_config;
3372 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3373 RTL_W32(RxConfig, cfg);
3375 /* Set DMA burst size and Interframe Gap Time */
3376 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3377 (InterFrameGap << TxInterFrameGapShift));
3380 static void rtl_hw_start(struct net_device *dev)
3382 struct rtl8169_private *tp = netdev_priv(dev);
3383 void __iomem *ioaddr = tp->mmio_addr;
3386 /* Soft reset the chip. */
3387 RTL_W8(ChipCmd, CmdReset);
3389 /* Check that the chip has finished the reset. */
3390 for (i = 0; i < 100; i++) {
3391 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3393 msleep_interruptible(1);
3398 netif_start_queue(dev);
3402 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3403 void __iomem *ioaddr)
3406 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3407 * register to be written before TxDescAddrLow to work.
3408 * Switching from MMIO to I/O access fixes the issue as well.
3410 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3411 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3412 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3413 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3416 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3420 cmd = RTL_R16(CPlusCmd);
3421 RTL_W16(CPlusCmd, cmd);
3425 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3427 /* Low hurts. Let's disable the filtering. */
3428 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3431 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3433 static const struct {
3438 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3439 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3440 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3441 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3446 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3447 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3448 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3449 RTL_W32(0x7c, p->val);
3455 static void rtl_hw_start_8169(struct net_device *dev)
3457 struct rtl8169_private *tp = netdev_priv(dev);
3458 void __iomem *ioaddr = tp->mmio_addr;
3459 struct pci_dev *pdev = tp->pci_dev;
3461 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3462 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3463 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3466 RTL_W8(Cfg9346, Cfg9346_Unlock);
3467 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3468 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3469 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3470 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3471 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3473 RTL_W8(EarlyTxThres, EarlyTxThld);
3475 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3477 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3478 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3479 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3480 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3481 rtl_set_rx_tx_config_registers(tp);
3483 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3485 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3486 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3487 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3488 "Bit-3 and bit-14 MUST be 1\n");
3489 tp->cp_cmd |= (1 << 14);
3492 RTL_W16(CPlusCmd, tp->cp_cmd);
3494 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3497 * Undocumented corner. Supposedly:
3498 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3500 RTL_W16(IntrMitigate, 0x0000);
3502 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3504 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3505 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3506 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3507 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3508 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3509 rtl_set_rx_tx_config_registers(tp);
3512 RTL_W8(Cfg9346, Cfg9346_Lock);
3514 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3517 RTL_W32(RxMissed, 0);
3519 rtl_set_rx_mode(dev);
3521 /* no early-rx interrupts */
3522 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3524 /* Enable all known interrupts by setting the interrupt mask. */
3525 RTL_W16(IntrMask, tp->intr_event);
3528 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3530 struct net_device *dev = pci_get_drvdata(pdev);
3531 struct rtl8169_private *tp = netdev_priv(dev);
3532 int cap = tp->pcie_cap;
3537 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3538 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3539 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3543 static void rtl_csi_access_enable(void __iomem *ioaddr)
3547 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3548 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3552 unsigned int offset;
3557 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3562 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3563 rtl_ephy_write(ioaddr, e->offset, w);
3568 static void rtl_disable_clock_request(struct pci_dev *pdev)
3570 struct net_device *dev = pci_get_drvdata(pdev);
3571 struct rtl8169_private *tp = netdev_priv(dev);
3572 int cap = tp->pcie_cap;
3577 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3578 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3579 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3583 #define R8168_CPCMD_QUIRK_MASK (\
3594 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3596 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3598 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3600 rtl_tx_performance_tweak(pdev,
3601 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3604 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3606 rtl_hw_start_8168bb(ioaddr, pdev);
3608 RTL_W8(EarlyTxThres, EarlyTxThld);
3610 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3613 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3615 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3617 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3619 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3621 rtl_disable_clock_request(pdev);
3623 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3626 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3628 static const struct ephy_info e_info_8168cp[] = {
3629 { 0x01, 0, 0x0001 },
3630 { 0x02, 0x0800, 0x1000 },
3631 { 0x03, 0, 0x0042 },
3632 { 0x06, 0x0080, 0x0000 },
3636 rtl_csi_access_enable(ioaddr);
3638 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3640 __rtl_hw_start_8168cp(ioaddr, pdev);
3643 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3645 rtl_csi_access_enable(ioaddr);
3647 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3649 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3651 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3654 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3656 rtl_csi_access_enable(ioaddr);
3658 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3661 RTL_W8(DBG_REG, 0x20);
3663 RTL_W8(EarlyTxThres, EarlyTxThld);
3665 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3667 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3670 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3672 static const struct ephy_info e_info_8168c_1[] = {
3673 { 0x02, 0x0800, 0x1000 },
3674 { 0x03, 0, 0x0002 },
3675 { 0x06, 0x0080, 0x0000 }
3678 rtl_csi_access_enable(ioaddr);
3680 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3682 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3684 __rtl_hw_start_8168cp(ioaddr, pdev);
3687 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3689 static const struct ephy_info e_info_8168c_2[] = {
3690 { 0x01, 0, 0x0001 },
3691 { 0x03, 0x0400, 0x0220 }
3694 rtl_csi_access_enable(ioaddr);
3696 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3698 __rtl_hw_start_8168cp(ioaddr, pdev);
3701 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3703 rtl_hw_start_8168c_2(ioaddr, pdev);
3706 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3708 rtl_csi_access_enable(ioaddr);
3710 __rtl_hw_start_8168cp(ioaddr, pdev);
3713 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3715 rtl_csi_access_enable(ioaddr);
3717 rtl_disable_clock_request(pdev);
3719 RTL_W8(EarlyTxThres, EarlyTxThld);
3721 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3723 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3726 static void rtl_hw_start_8168(struct net_device *dev)
3728 struct rtl8169_private *tp = netdev_priv(dev);
3729 void __iomem *ioaddr = tp->mmio_addr;
3730 struct pci_dev *pdev = tp->pci_dev;
3732 RTL_W8(Cfg9346, Cfg9346_Unlock);
3734 RTL_W8(EarlyTxThres, EarlyTxThld);
3736 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3738 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3740 RTL_W16(CPlusCmd, tp->cp_cmd);
3742 RTL_W16(IntrMitigate, 0x5151);
3744 /* Work around for RxFIFO overflow. */
3745 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3746 tp->intr_event |= RxFIFOOver | PCSTimeout;
3747 tp->intr_event &= ~RxOverflow;
3750 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3752 rtl_set_rx_mode(dev);
3754 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3755 (InterFrameGap << TxInterFrameGapShift));
3759 switch (tp->mac_version) {
3760 case RTL_GIGA_MAC_VER_11:
3761 rtl_hw_start_8168bb(ioaddr, pdev);
3764 case RTL_GIGA_MAC_VER_12:
3765 case RTL_GIGA_MAC_VER_17:
3766 rtl_hw_start_8168bef(ioaddr, pdev);
3769 case RTL_GIGA_MAC_VER_18:
3770 rtl_hw_start_8168cp_1(ioaddr, pdev);
3773 case RTL_GIGA_MAC_VER_19:
3774 rtl_hw_start_8168c_1(ioaddr, pdev);
3777 case RTL_GIGA_MAC_VER_20:
3778 rtl_hw_start_8168c_2(ioaddr, pdev);
3781 case RTL_GIGA_MAC_VER_21:
3782 rtl_hw_start_8168c_3(ioaddr, pdev);
3785 case RTL_GIGA_MAC_VER_22:
3786 rtl_hw_start_8168c_4(ioaddr, pdev);
3789 case RTL_GIGA_MAC_VER_23:
3790 rtl_hw_start_8168cp_2(ioaddr, pdev);
3793 case RTL_GIGA_MAC_VER_24:
3794 rtl_hw_start_8168cp_3(ioaddr, pdev);
3797 case RTL_GIGA_MAC_VER_25:
3798 case RTL_GIGA_MAC_VER_26:
3799 case RTL_GIGA_MAC_VER_27:
3800 rtl_hw_start_8168d(ioaddr, pdev);
3804 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3805 dev->name, tp->mac_version);
3809 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3811 RTL_W8(Cfg9346, Cfg9346_Lock);
3813 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3815 RTL_W16(IntrMask, tp->intr_event);
3818 #define R810X_CPCMD_QUIRK_MASK (\
3830 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3832 static const struct ephy_info e_info_8102e_1[] = {
3833 { 0x01, 0, 0x6e65 },
3834 { 0x02, 0, 0x091f },
3835 { 0x03, 0, 0xc2f9 },
3836 { 0x06, 0, 0xafb5 },
3837 { 0x07, 0, 0x0e00 },
3838 { 0x19, 0, 0xec80 },
3839 { 0x01, 0, 0x2e65 },
3844 rtl_csi_access_enable(ioaddr);
3846 RTL_W8(DBG_REG, FIX_NAK_1);
3848 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3851 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3852 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3854 cfg1 = RTL_R8(Config1);
3855 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3856 RTL_W8(Config1, cfg1 & ~LEDS0);
3858 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3860 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3863 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3865 rtl_csi_access_enable(ioaddr);
3867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3869 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3870 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3872 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3875 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3877 rtl_hw_start_8102e_2(ioaddr, pdev);
3879 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3882 static void rtl_hw_start_8101(struct net_device *dev)
3884 struct rtl8169_private *tp = netdev_priv(dev);
3885 void __iomem *ioaddr = tp->mmio_addr;
3886 struct pci_dev *pdev = tp->pci_dev;
3888 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3889 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3890 int cap = tp->pcie_cap;
3893 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3894 PCI_EXP_DEVCTL_NOSNOOP_EN);
3898 switch (tp->mac_version) {
3899 case RTL_GIGA_MAC_VER_07:
3900 rtl_hw_start_8102e_1(ioaddr, pdev);
3903 case RTL_GIGA_MAC_VER_08:
3904 rtl_hw_start_8102e_3(ioaddr, pdev);
3907 case RTL_GIGA_MAC_VER_09:
3908 rtl_hw_start_8102e_2(ioaddr, pdev);
3912 RTL_W8(Cfg9346, Cfg9346_Unlock);
3914 RTL_W8(EarlyTxThres, EarlyTxThld);
3916 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3918 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3920 RTL_W16(CPlusCmd, tp->cp_cmd);
3922 RTL_W16(IntrMitigate, 0x0000);
3924 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3926 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3927 rtl_set_rx_tx_config_registers(tp);
3929 RTL_W8(Cfg9346, Cfg9346_Lock);
3933 rtl_set_rx_mode(dev);
3935 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3937 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3939 RTL_W16(IntrMask, tp->intr_event);
3942 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3944 struct rtl8169_private *tp = netdev_priv(dev);
3947 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3952 if (!netif_running(dev))
3957 rtl8169_set_rxbufsize(tp, dev->mtu);
3959 ret = rtl8169_init_ring(dev);
3963 napi_enable(&tp->napi);
3967 rtl8169_request_timer(dev);
3973 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3975 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3976 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3979 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3980 struct sk_buff **sk_buff, struct RxDesc *desc)
3982 struct pci_dev *pdev = tp->pci_dev;
3984 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3985 PCI_DMA_FROMDEVICE);
3986 dev_kfree_skb(*sk_buff);
3988 rtl8169_make_unusable_by_asic(desc);
3991 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3993 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3995 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3998 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4001 desc->addr = cpu_to_le64(mapping);
4003 rtl8169_mark_to_asic(desc, rx_buf_sz);
4006 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
4007 struct net_device *dev,
4008 struct RxDesc *desc, int rx_buf_sz,
4011 struct sk_buff *skb;
4015 pad = align ? align : NET_IP_ALIGN;
4017 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
4021 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
4023 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
4024 PCI_DMA_FROMDEVICE);
4026 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4031 rtl8169_make_unusable_by_asic(desc);
4035 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4039 for (i = 0; i < NUM_RX_DESC; i++) {
4040 if (tp->Rx_skbuff[i]) {
4041 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4042 tp->RxDescArray + i);
4047 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4052 for (cur = start; end - cur != 0; cur++) {
4053 struct sk_buff *skb;
4054 unsigned int i = cur % NUM_RX_DESC;
4056 WARN_ON((s32)(end - cur) < 0);
4058 if (tp->Rx_skbuff[i])
4061 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4062 tp->RxDescArray + i,
4063 tp->rx_buf_sz, tp->align);
4067 tp->Rx_skbuff[i] = skb;
4072 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4074 desc->opts1 |= cpu_to_le32(RingEnd);
4077 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4079 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4082 static int rtl8169_init_ring(struct net_device *dev)
4084 struct rtl8169_private *tp = netdev_priv(dev);
4086 rtl8169_init_ring_indexes(tp);
4088 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4089 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4091 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4094 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4099 rtl8169_rx_clear(tp);
4103 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4104 struct TxDesc *desc)
4106 unsigned int len = tx_skb->len;
4108 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4115 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4119 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4120 unsigned int entry = i % NUM_TX_DESC;
4121 struct ring_info *tx_skb = tp->tx_skb + entry;
4122 unsigned int len = tx_skb->len;
4125 struct sk_buff *skb = tx_skb->skb;
4127 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4128 tp->TxDescArray + entry);
4133 tp->dev->stats.tx_dropped++;
4136 tp->cur_tx = tp->dirty_tx = 0;
4139 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4141 struct rtl8169_private *tp = netdev_priv(dev);
4143 PREPARE_DELAYED_WORK(&tp->task, task);
4144 schedule_delayed_work(&tp->task, 4);
4147 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4149 struct rtl8169_private *tp = netdev_priv(dev);
4150 void __iomem *ioaddr = tp->mmio_addr;
4152 synchronize_irq(dev->irq);
4154 /* Wait for any pending NAPI task to complete */
4155 napi_disable(&tp->napi);
4157 rtl8169_irq_mask_and_ack(ioaddr);
4159 tp->intr_mask = 0xffff;
4160 RTL_W16(IntrMask, tp->intr_event);
4161 napi_enable(&tp->napi);
4164 static void rtl8169_reinit_task(struct work_struct *work)
4166 struct rtl8169_private *tp =
4167 container_of(work, struct rtl8169_private, task.work);
4168 struct net_device *dev = tp->dev;
4173 if (!netif_running(dev))
4176 rtl8169_wait_for_quiescence(dev);
4179 ret = rtl8169_open(dev);
4180 if (unlikely(ret < 0)) {
4181 if (net_ratelimit())
4182 netif_err(tp, drv, dev,
4183 "reinit failure (status = %d). Rescheduling\n",
4185 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4192 static void rtl8169_reset_task(struct work_struct *work)
4194 struct rtl8169_private *tp =
4195 container_of(work, struct rtl8169_private, task.work);
4196 struct net_device *dev = tp->dev;
4200 if (!netif_running(dev))
4203 rtl8169_wait_for_quiescence(dev);
4205 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4206 rtl8169_tx_clear(tp);
4208 if (tp->dirty_rx == tp->cur_rx) {
4209 rtl8169_init_ring_indexes(tp);
4211 netif_wake_queue(dev);
4212 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4214 if (net_ratelimit())
4215 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4216 rtl8169_schedule_work(dev, rtl8169_reset_task);
4223 static void rtl8169_tx_timeout(struct net_device *dev)
4225 struct rtl8169_private *tp = netdev_priv(dev);
4227 rtl8169_hw_reset(tp->mmio_addr);
4229 /* Let's wait a bit while any (async) irq lands on */
4230 rtl8169_schedule_work(dev, rtl8169_reset_task);
4233 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4236 struct skb_shared_info *info = skb_shinfo(skb);
4237 unsigned int cur_frag, entry;
4238 struct TxDesc * uninitialized_var(txd);
4241 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4242 skb_frag_t *frag = info->frags + cur_frag;
4247 entry = (entry + 1) % NUM_TX_DESC;
4249 txd = tp->TxDescArray + entry;
4251 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4252 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4254 /* anti gcc 2.95.3 bugware (sic) */
4255 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4257 txd->opts1 = cpu_to_le32(status);
4258 txd->addr = cpu_to_le64(mapping);
4260 tp->tx_skb[entry].len = len;
4264 tp->tx_skb[entry].skb = skb;
4265 txd->opts1 |= cpu_to_le32(LastFrag);
4271 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4273 if (dev->features & NETIF_F_TSO) {
4274 u32 mss = skb_shinfo(skb)->gso_size;
4277 return LargeSend | ((mss & MSSMask) << MSSShift);
4279 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4280 const struct iphdr *ip = ip_hdr(skb);
4282 if (ip->protocol == IPPROTO_TCP)
4283 return IPCS | TCPCS;
4284 else if (ip->protocol == IPPROTO_UDP)
4285 return IPCS | UDPCS;
4286 WARN_ON(1); /* we need a WARN() */
4291 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4292 struct net_device *dev)
4294 struct rtl8169_private *tp = netdev_priv(dev);
4295 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4296 struct TxDesc *txd = tp->TxDescArray + entry;
4297 void __iomem *ioaddr = tp->mmio_addr;
4302 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4303 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4307 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4310 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4312 frags = rtl8169_xmit_frags(tp, skb, opts1);
4314 len = skb_headlen(skb);
4318 opts1 |= FirstFrag | LastFrag;
4319 tp->tx_skb[entry].skb = skb;
4322 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4324 tp->tx_skb[entry].len = len;
4325 txd->addr = cpu_to_le64(mapping);
4326 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4330 /* anti gcc 2.95.3 bugware (sic) */
4331 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4332 txd->opts1 = cpu_to_le32(status);
4334 tp->cur_tx += frags + 1;
4338 RTL_W8(TxPoll, NPQ); /* set polling bit */
4340 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4341 netif_stop_queue(dev);
4343 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4344 netif_wake_queue(dev);
4347 return NETDEV_TX_OK;
4350 netif_stop_queue(dev);
4351 dev->stats.tx_dropped++;
4352 return NETDEV_TX_BUSY;
4355 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4357 struct rtl8169_private *tp = netdev_priv(dev);
4358 struct pci_dev *pdev = tp->pci_dev;
4359 void __iomem *ioaddr = tp->mmio_addr;
4360 u16 pci_status, pci_cmd;
4362 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4363 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4365 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4366 pci_cmd, pci_status);
4369 * The recovery sequence below admits a very elaborated explanation:
4370 * - it seems to work;
4371 * - I did not see what else could be done;
4372 * - it makes iop3xx happy.
4374 * Feel free to adjust to your needs.
4376 if (pdev->broken_parity_status)
4377 pci_cmd &= ~PCI_COMMAND_PARITY;
4379 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4381 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4383 pci_write_config_word(pdev, PCI_STATUS,
4384 pci_status & (PCI_STATUS_DETECTED_PARITY |
4385 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4386 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4388 /* The infamous DAC f*ckup only happens at boot time */
4389 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4390 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4391 tp->cp_cmd &= ~PCIDAC;
4392 RTL_W16(CPlusCmd, tp->cp_cmd);
4393 dev->features &= ~NETIF_F_HIGHDMA;
4396 rtl8169_hw_reset(ioaddr);
4398 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4401 static void rtl8169_tx_interrupt(struct net_device *dev,
4402 struct rtl8169_private *tp,
4403 void __iomem *ioaddr)
4405 unsigned int dirty_tx, tx_left;
4407 dirty_tx = tp->dirty_tx;
4409 tx_left = tp->cur_tx - dirty_tx;
4411 while (tx_left > 0) {
4412 unsigned int entry = dirty_tx % NUM_TX_DESC;
4413 struct ring_info *tx_skb = tp->tx_skb + entry;
4414 u32 len = tx_skb->len;
4418 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4419 if (status & DescOwn)
4422 dev->stats.tx_bytes += len;
4423 dev->stats.tx_packets++;
4425 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4427 if (status & LastFrag) {
4428 dev_kfree_skb(tx_skb->skb);
4435 if (tp->dirty_tx != dirty_tx) {
4436 tp->dirty_tx = dirty_tx;
4438 if (netif_queue_stopped(dev) &&
4439 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4440 netif_wake_queue(dev);
4443 * 8168 hack: TxPoll requests are lost when the Tx packets are
4444 * too close. Let's kick an extra TxPoll request when a burst
4445 * of start_xmit activity is detected (if it is not detected,
4446 * it is slow enough). -- FR
4449 if (tp->cur_tx != dirty_tx)
4450 RTL_W8(TxPoll, NPQ);
4454 static inline int rtl8169_fragmented_frame(u32 status)
4456 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4459 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4461 u32 status = opts1 & RxProtoMask;
4463 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4464 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4465 ((status == RxProtoIP) && !(opts1 & IPFail)))
4466 skb->ip_summed = CHECKSUM_UNNECESSARY;
4468 skb_checksum_none_assert(skb);
4471 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4472 struct rtl8169_private *tp, int pkt_size,
4475 struct sk_buff *skb;
4478 if (pkt_size >= rx_copybreak)
4481 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4485 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4486 PCI_DMA_FROMDEVICE);
4487 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4495 * Warning : rtl8169_rx_interrupt() might be called :
4496 * 1) from NAPI (softirq) context
4497 * (polling = 1 : we should call netif_receive_skb())
4498 * 2) from process context (rtl8169_reset_task())
4499 * (polling = 0 : we must call netif_rx() instead)
4501 static int rtl8169_rx_interrupt(struct net_device *dev,
4502 struct rtl8169_private *tp,
4503 void __iomem *ioaddr, u32 budget)
4505 unsigned int cur_rx, rx_left;
4506 unsigned int delta, count;
4507 int polling = (budget != ~(u32)0) ? 1 : 0;
4509 cur_rx = tp->cur_rx;
4510 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4511 rx_left = min(rx_left, budget);
4513 for (; rx_left > 0; rx_left--, cur_rx++) {
4514 unsigned int entry = cur_rx % NUM_RX_DESC;
4515 struct RxDesc *desc = tp->RxDescArray + entry;
4519 status = le32_to_cpu(desc->opts1);
4521 if (status & DescOwn)
4523 if (unlikely(status & RxRES)) {
4524 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4526 dev->stats.rx_errors++;
4527 if (status & (RxRWT | RxRUNT))
4528 dev->stats.rx_length_errors++;
4530 dev->stats.rx_crc_errors++;
4531 if (status & RxFOVF) {
4532 rtl8169_schedule_work(dev, rtl8169_reset_task);
4533 dev->stats.rx_fifo_errors++;
4535 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4537 struct sk_buff *skb = tp->Rx_skbuff[entry];
4538 dma_addr_t addr = le64_to_cpu(desc->addr);
4539 int pkt_size = (status & 0x00001FFF) - 4;
4540 struct pci_dev *pdev = tp->pci_dev;
4543 * The driver does not support incoming fragmented
4544 * frames. They are seen as a symptom of over-mtu
4547 if (unlikely(rtl8169_fragmented_frame(status))) {
4548 dev->stats.rx_dropped++;
4549 dev->stats.rx_length_errors++;
4550 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4554 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4555 pci_dma_sync_single_for_device(pdev, addr,
4556 pkt_size, PCI_DMA_FROMDEVICE);
4557 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4559 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4560 PCI_DMA_FROMDEVICE);
4561 tp->Rx_skbuff[entry] = NULL;
4564 rtl8169_rx_csum(skb, status);
4565 skb_put(skb, pkt_size);
4566 skb->protocol = eth_type_trans(skb, dev);
4568 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4569 if (likely(polling))
4570 napi_gro_receive(&tp->napi, skb);
4575 dev->stats.rx_bytes += pkt_size;
4576 dev->stats.rx_packets++;
4579 /* Work around for AMD plateform. */
4580 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4581 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4587 count = cur_rx - tp->cur_rx;
4588 tp->cur_rx = cur_rx;
4590 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4591 if (!delta && count)
4592 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4593 tp->dirty_rx += delta;
4596 * FIXME: until there is periodic timer to try and refill the ring,
4597 * a temporary shortage may definitely kill the Rx process.
4598 * - disable the asic to try and avoid an overflow and kick it again
4600 * - how do others driver handle this condition (Uh oh...).
4602 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4603 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4608 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4610 struct net_device *dev = dev_instance;
4611 struct rtl8169_private *tp = netdev_priv(dev);
4612 void __iomem *ioaddr = tp->mmio_addr;
4616 /* loop handling interrupts until we have no new ones or
4617 * we hit a invalid/hotplug case.
4619 status = RTL_R16(IntrStatus);
4620 while (status && status != 0xffff) {
4623 /* Handle all of the error cases first. These will reset
4624 * the chip, so just exit the loop.
4626 if (unlikely(!netif_running(dev))) {
4627 rtl8169_asic_down(ioaddr);
4631 /* Work around for rx fifo overflow */
4632 if (unlikely(status & RxFIFOOver)) {
4633 netif_stop_queue(dev);
4634 rtl8169_tx_timeout(dev);
4638 if (unlikely(status & SYSErr)) {
4639 rtl8169_pcierr_interrupt(dev);
4643 if (status & LinkChg)
4644 rtl8169_check_link_status(dev, tp, ioaddr);
4646 /* We need to see the lastest version of tp->intr_mask to
4647 * avoid ignoring an MSI interrupt and having to wait for
4648 * another event which may never come.
4651 if (status & tp->intr_mask & tp->napi_event) {
4652 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4653 tp->intr_mask = ~tp->napi_event;
4655 if (likely(napi_schedule_prep(&tp->napi)))
4656 __napi_schedule(&tp->napi);
4658 netif_info(tp, intr, dev,
4659 "interrupt %04x in poll\n", status);
4662 /* We only get a new MSI interrupt when all active irq
4663 * sources on the chip have been acknowledged. So, ack
4664 * everything we've seen and check if new sources have become
4665 * active to avoid blocking all interrupts from the chip.
4668 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4669 status = RTL_R16(IntrStatus);
4672 return IRQ_RETVAL(handled);
4675 static int rtl8169_poll(struct napi_struct *napi, int budget)
4677 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4678 struct net_device *dev = tp->dev;
4679 void __iomem *ioaddr = tp->mmio_addr;
4682 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4683 rtl8169_tx_interrupt(dev, tp, ioaddr);
4685 if (work_done < budget) {
4686 napi_complete(napi);
4688 /* We need for force the visibility of tp->intr_mask
4689 * for other CPUs, as we can loose an MSI interrupt
4690 * and potentially wait for a retransmit timeout if we don't.
4691 * The posted write to IntrMask is safe, as it will
4692 * eventually make it to the chip and we won't loose anything
4695 tp->intr_mask = 0xffff;
4697 RTL_W16(IntrMask, tp->intr_event);
4703 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4705 struct rtl8169_private *tp = netdev_priv(dev);
4707 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4710 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4711 RTL_W32(RxMissed, 0);
4714 static void rtl8169_down(struct net_device *dev)
4716 struct rtl8169_private *tp = netdev_priv(dev);
4717 void __iomem *ioaddr = tp->mmio_addr;
4718 unsigned int intrmask;
4720 rtl8169_delete_timer(dev);
4722 netif_stop_queue(dev);
4724 napi_disable(&tp->napi);
4727 spin_lock_irq(&tp->lock);
4729 rtl8169_asic_down(ioaddr);
4731 rtl8169_rx_missed(dev, ioaddr);
4733 spin_unlock_irq(&tp->lock);
4735 synchronize_irq(dev->irq);
4737 /* Give a racing hard_start_xmit a few cycles to complete. */
4738 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4741 * And now for the 50k$ question: are IRQ disabled or not ?
4743 * Two paths lead here:
4745 * -> netif_running() is available to sync the current code and the
4746 * IRQ handler. See rtl8169_interrupt for details.
4747 * 2) dev->change_mtu
4748 * -> rtl8169_poll can not be issued again and re-enable the
4749 * interruptions. Let's simply issue the IRQ down sequence again.
4751 * No loop if hotpluged or major error (0xffff).
4753 intrmask = RTL_R16(IntrMask);
4754 if (intrmask && (intrmask != 0xffff))
4757 rtl8169_tx_clear(tp);
4759 rtl8169_rx_clear(tp);
4762 static int rtl8169_close(struct net_device *dev)
4764 struct rtl8169_private *tp = netdev_priv(dev);
4765 struct pci_dev *pdev = tp->pci_dev;
4767 pm_runtime_get_sync(&pdev->dev);
4769 /* update counters before going down */
4770 rtl8169_update_counters(dev);
4774 free_irq(dev->irq, dev);
4776 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4778 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4780 tp->TxDescArray = NULL;
4781 tp->RxDescArray = NULL;
4783 pm_runtime_put_sync(&pdev->dev);
4788 static void rtl_set_rx_mode(struct net_device *dev)
4790 struct rtl8169_private *tp = netdev_priv(dev);
4791 void __iomem *ioaddr = tp->mmio_addr;
4792 unsigned long flags;
4793 u32 mc_filter[2]; /* Multicast hash filter */
4797 if (dev->flags & IFF_PROMISC) {
4798 /* Unconditionally log net taps. */
4799 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4801 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4803 mc_filter[1] = mc_filter[0] = 0xffffffff;
4804 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4805 (dev->flags & IFF_ALLMULTI)) {
4806 /* Too many to filter perfectly -- accept all multicasts. */
4807 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4808 mc_filter[1] = mc_filter[0] = 0xffffffff;
4810 struct netdev_hw_addr *ha;
4812 rx_mode = AcceptBroadcast | AcceptMyPhys;
4813 mc_filter[1] = mc_filter[0] = 0;
4814 netdev_for_each_mc_addr(ha, dev) {
4815 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4816 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4817 rx_mode |= AcceptMulticast;
4821 spin_lock_irqsave(&tp->lock, flags);
4823 tmp = rtl8169_rx_config | rx_mode |
4824 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4826 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4827 u32 data = mc_filter[0];
4829 mc_filter[0] = swab32(mc_filter[1]);
4830 mc_filter[1] = swab32(data);
4833 RTL_W32(MAR0 + 4, mc_filter[1]);
4834 RTL_W32(MAR0 + 0, mc_filter[0]);
4836 RTL_W32(RxConfig, tmp);
4838 spin_unlock_irqrestore(&tp->lock, flags);
4842 * rtl8169_get_stats - Get rtl8169 read/write statistics
4843 * @dev: The Ethernet Device to get statistics for
4845 * Get TX/RX statistics for rtl8169
4847 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4849 struct rtl8169_private *tp = netdev_priv(dev);
4850 void __iomem *ioaddr = tp->mmio_addr;
4851 unsigned long flags;
4853 if (netif_running(dev)) {
4854 spin_lock_irqsave(&tp->lock, flags);
4855 rtl8169_rx_missed(dev, ioaddr);
4856 spin_unlock_irqrestore(&tp->lock, flags);
4862 static void rtl8169_net_suspend(struct net_device *dev)
4864 if (!netif_running(dev))
4867 netif_device_detach(dev);
4868 netif_stop_queue(dev);
4873 static int rtl8169_suspend(struct device *device)
4875 struct pci_dev *pdev = to_pci_dev(device);
4876 struct net_device *dev = pci_get_drvdata(pdev);
4878 rtl8169_net_suspend(dev);
4883 static void __rtl8169_resume(struct net_device *dev)
4885 netif_device_attach(dev);
4886 rtl8169_schedule_work(dev, rtl8169_reset_task);
4889 static int rtl8169_resume(struct device *device)
4891 struct pci_dev *pdev = to_pci_dev(device);
4892 struct net_device *dev = pci_get_drvdata(pdev);
4894 if (netif_running(dev))
4895 __rtl8169_resume(dev);
4900 static int rtl8169_runtime_suspend(struct device *device)
4902 struct pci_dev *pdev = to_pci_dev(device);
4903 struct net_device *dev = pci_get_drvdata(pdev);
4904 struct rtl8169_private *tp = netdev_priv(dev);
4906 if (!tp->TxDescArray)
4909 spin_lock_irq(&tp->lock);
4910 tp->saved_wolopts = __rtl8169_get_wol(tp);
4911 __rtl8169_set_wol(tp, WAKE_ANY);
4912 spin_unlock_irq(&tp->lock);
4914 rtl8169_net_suspend(dev);
4919 static int rtl8169_runtime_resume(struct device *device)
4921 struct pci_dev *pdev = to_pci_dev(device);
4922 struct net_device *dev = pci_get_drvdata(pdev);
4923 struct rtl8169_private *tp = netdev_priv(dev);
4925 if (!tp->TxDescArray)
4928 spin_lock_irq(&tp->lock);
4929 __rtl8169_set_wol(tp, tp->saved_wolopts);
4930 tp->saved_wolopts = 0;
4931 spin_unlock_irq(&tp->lock);
4933 __rtl8169_resume(dev);
4938 static int rtl8169_runtime_idle(struct device *device)
4940 struct pci_dev *pdev = to_pci_dev(device);
4941 struct net_device *dev = pci_get_drvdata(pdev);
4942 struct rtl8169_private *tp = netdev_priv(dev);
4944 if (!tp->TxDescArray)
4947 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4951 static const struct dev_pm_ops rtl8169_pm_ops = {
4952 .suspend = rtl8169_suspend,
4953 .resume = rtl8169_resume,
4954 .freeze = rtl8169_suspend,
4955 .thaw = rtl8169_resume,
4956 .poweroff = rtl8169_suspend,
4957 .restore = rtl8169_resume,
4958 .runtime_suspend = rtl8169_runtime_suspend,
4959 .runtime_resume = rtl8169_runtime_resume,
4960 .runtime_idle = rtl8169_runtime_idle,
4963 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4965 #else /* !CONFIG_PM */
4967 #define RTL8169_PM_OPS NULL
4969 #endif /* !CONFIG_PM */
4971 static void rtl_shutdown(struct pci_dev *pdev)
4973 struct net_device *dev = pci_get_drvdata(pdev);
4974 struct rtl8169_private *tp = netdev_priv(dev);
4975 void __iomem *ioaddr = tp->mmio_addr;
4977 rtl8169_net_suspend(dev);
4979 /* restore original MAC address */
4980 rtl_rar_set(tp, dev->perm_addr);
4982 spin_lock_irq(&tp->lock);
4984 rtl8169_asic_down(ioaddr);
4986 spin_unlock_irq(&tp->lock);
4988 if (system_state == SYSTEM_POWER_OFF) {
4989 /* WoL fails with some 8168 when the receiver is disabled. */
4990 if (tp->features & RTL_FEATURE_WOL) {
4991 pci_clear_master(pdev);
4993 RTL_W8(ChipCmd, CmdRxEnb);
4998 pci_wake_from_d3(pdev, true);
4999 pci_set_power_state(pdev, PCI_D3hot);
5003 static struct pci_driver rtl8169_pci_driver = {
5005 .id_table = rtl8169_pci_tbl,
5006 .probe = rtl8169_init_one,
5007 .remove = __devexit_p(rtl8169_remove_one),
5008 .shutdown = rtl_shutdown,
5009 .driver.pm = RTL8169_PM_OPS,
5012 static int __init rtl8169_init_module(void)
5014 return pci_register_driver(&rtl8169_pci_driver);
5017 static void __exit rtl8169_cleanup_module(void)
5019 pci_unregister_driver(&rtl8169_pci_driver);
5022 module_init(rtl8169_init_module);
5023 module_exit(rtl8169_cleanup_module);