2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
115 #define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
118 static const struct {
121 u32 RxConfigMask; /* Clears the bits supported by this chip */
122 } rtl_chip_info[] = {
123 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
129 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
130 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
132 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
133 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
136 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
137 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
140 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
141 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
152 static void rtl_hw_start_8169(struct net_device *);
153 static void rtl_hw_start_8168(struct net_device *);
154 static void rtl_hw_start_8101(struct net_device *);
156 static struct pci_device_id rtl8169_pci_tbl[] = {
157 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
158 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
162 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
165 { PCI_VENDOR_ID_LINKSYS, 0x1032,
166 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
168 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
174 static int rx_copybreak = 200;
181 MAC0 = 0, /* Ethernet hardware address. */
183 MAR0 = 8, /* Multicast filter. */
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
212 RxDescAddrLow = 0xe4,
213 RxDescAddrHigh = 0xe8,
216 FuncEventMask = 0xf4,
217 FuncPresetState = 0xf8,
218 FuncForceEvent = 0xfc,
221 enum rtl8110_registers {
227 enum rtl8168_8101_registers {
230 #define CSIAR_FLAG 0x80000000
231 #define CSIAR_WRITE_CMD 0x80000000
232 #define CSIAR_BYTE_ENABLE 0x0f
233 #define CSIAR_BYTE_ENABLE_SHIFT 12
234 #define CSIAR_ADDR_MASK 0x0fff
237 #define EPHYAR_FLAG 0x80000000
238 #define EPHYAR_WRITE_CMD 0x80000000
239 #define EPHYAR_REG_MASK 0x1f
240 #define EPHYAR_REG_SHIFT 16
241 #define EPHYAR_DATA_MASK 0xffff
243 #define FIX_NAK_1 (1 << 4)
244 #define FIX_NAK_2 (1 << 3)
247 enum rtl_register_content {
248 /* InterruptStatusBits */
252 TxDescUnavail = 0x0080,
274 /* TXPoll register p.5 */
275 HPQ = 0x80, /* Poll cmd on the high prio queue */
276 NPQ = 0x40, /* Poll cmd on the low prio queue */
277 FSWInt = 0x01, /* Forced software interrupt */
281 Cfg9346_Unlock = 0xc0,
286 AcceptBroadcast = 0x08,
287 AcceptMulticast = 0x04,
289 AcceptAllPhys = 0x01,
296 TxInterFrameGapShift = 24,
297 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
299 /* Config1 register p.24 */
302 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
303 Speed_down = (1 << 4),
307 PMEnable = (1 << 0), /* Power Management Enable */
309 /* Config2 register p. 25 */
310 PCI_Clock_66MHz = 0x01,
311 PCI_Clock_33MHz = 0x00,
313 /* Config3 register p.25 */
314 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
315 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
316 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
318 /* Config5 register p.27 */
319 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
320 MWF = (1 << 5), /* Accept Multicast wakeup frame */
321 UWF = (1 << 4), /* Accept Unicast wakeup frame */
322 LanWake = (1 << 1), /* LanWake enable/disable */
323 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
326 TBIReset = 0x80000000,
327 TBILoopback = 0x40000000,
328 TBINwEnable = 0x20000000,
329 TBINwRestart = 0x10000000,
330 TBILinkOk = 0x02000000,
331 TBINwComplete = 0x01000000,
334 EnableBist = (1 << 15), // 8168 8101
335 Mac_dbgo_oe = (1 << 14), // 8168 8101
336 Normal_mode = (1 << 13), // unused
337 Force_half_dup = (1 << 12), // 8168 8101
338 Force_rxflow_en = (1 << 11), // 8168 8101
339 Force_txflow_en = (1 << 10), // 8168 8101
340 Cxpl_dbg_sel = (1 << 9), // 8168 8101
341 ASF = (1 << 8), // 8168 8101
342 PktCntrDisable = (1 << 7), // 8168 8101
343 Mac_dbgo_sel = 0x001c, // 8168
348 INTT_0 = 0x0000, // 8168
349 INTT_1 = 0x0001, // 8168
350 INTT_2 = 0x0002, // 8168
351 INTT_3 = 0x0003, // 8168
353 /* rtl8169_PHYstatus */
364 TBILinkOK = 0x02000000,
366 /* DumpCounterCommand */
370 enum desc_status_bit {
371 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
372 RingEnd = (1 << 30), /* End of descriptor ring */
373 FirstFrag = (1 << 29), /* First segment of a packet */
374 LastFrag = (1 << 28), /* Final segment of a packet */
377 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
378 MSSShift = 16, /* MSS value position */
379 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
380 IPCS = (1 << 18), /* Calculate IP checksum */
381 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
382 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
383 TxVlanTag = (1 << 17), /* Add VLAN tag */
386 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
387 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
389 #define RxProtoUDP (PID1)
390 #define RxProtoTCP (PID0)
391 #define RxProtoIP (PID1 | PID0)
392 #define RxProtoMask RxProtoIP
394 IPFail = (1 << 16), /* IP checksum failed */
395 UDPFail = (1 << 15), /* UDP/IP checksum failed */
396 TCPFail = (1 << 14), /* TCP/IP checksum failed */
397 RxVlanTag = (1 << 16), /* VLAN tag available */
400 #define RsvdMask 0x3fffc000
417 u8 __pad[sizeof(void *) - sizeof(u32)];
421 RTL_FEATURE_WOL = (1 << 0),
422 RTL_FEATURE_MSI = (1 << 1),
423 RTL_FEATURE_GMII = (1 << 2),
426 struct rtl8169_private {
427 void __iomem *mmio_addr; /* memory map physical address */
428 struct pci_dev *pci_dev; /* Index of PCI device */
429 struct net_device *dev;
430 struct napi_struct napi;
431 spinlock_t lock; /* spin lock flag */
435 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
439 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
440 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr;
442 dma_addr_t RxPhyAddr;
443 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
447 struct timer_list timer;
452 int phy_auto_nego_reg;
453 int phy_1000_ctrl_reg;
454 #ifdef CONFIG_R8169_VLAN
455 struct vlan_group *vlgrp;
457 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
458 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
459 void (*phy_reset_enable)(void __iomem *);
460 void (*hw_start)(struct net_device *);
461 unsigned int (*phy_reset_pending)(void __iomem *);
462 unsigned int (*link_ok)(void __iomem *);
464 struct delayed_work task;
467 struct mii_if_info mii;
470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
472 module_param(rx_copybreak, int, 0);
473 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
474 module_param(use_dac, int, 0);
475 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
476 module_param_named(debug, debug.msg_enable, int, 0);
477 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
478 MODULE_LICENSE("GPL");
479 MODULE_VERSION(RTL8169_VERSION);
481 static int rtl8169_open(struct net_device *dev);
482 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
483 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
484 static int rtl8169_init_ring(struct net_device *dev);
485 static void rtl_hw_start(struct net_device *dev);
486 static int rtl8169_close(struct net_device *dev);
487 static void rtl_set_rx_mode(struct net_device *dev);
488 static void rtl8169_tx_timeout(struct net_device *dev);
489 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
490 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
491 void __iomem *, u32 budget);
492 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
493 static void rtl8169_down(struct net_device *dev);
494 static void rtl8169_rx_clear(struct rtl8169_private *tp);
495 static int rtl8169_poll(struct napi_struct *napi, int budget);
497 static const unsigned int rtl8169_rx_config =
498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
500 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
504 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
506 for (i = 20; i > 0; i--) {
508 * Check if the RTL8169 has completed writing to the specified
511 if (!(RTL_R32(PHYAR) & 0x80000000))
517 static int mdio_read(void __iomem *ioaddr, int reg_addr)
521 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
523 for (i = 20; i > 0; i--) {
525 * Check if the RTL8169 has completed retrieving data from
526 * the specified MII register.
528 if (RTL_R32(PHYAR) & 0x80000000) {
529 value = RTL_R32(PHYAR) & 0xffff;
537 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
539 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
542 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
545 struct rtl8169_private *tp = netdev_priv(dev);
546 void __iomem *ioaddr = tp->mmio_addr;
548 mdio_write(ioaddr, location, val);
551 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
556 return mdio_read(ioaddr, location);
559 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
563 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
564 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
566 for (i = 0; i < 100; i++) {
567 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
573 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
578 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
580 for (i = 0; i < 100; i++) {
581 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
582 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
591 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
595 RTL_W32(CSIDR, value);
596 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
597 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
599 for (i = 0; i < 100; i++) {
600 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
606 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
611 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
612 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
614 for (i = 0; i < 100; i++) {
615 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
616 value = RTL_R32(CSIDR);
625 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
627 RTL_W16(IntrMask, 0x0000);
629 RTL_W16(IntrStatus, 0xffff);
632 static void rtl8169_asic_down(void __iomem *ioaddr)
634 RTL_W8(ChipCmd, 0x00);
635 rtl8169_irq_mask_and_ack(ioaddr);
639 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
641 return RTL_R32(TBICSR) & TBIReset;
644 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
646 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
649 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
651 return RTL_R32(TBICSR) & TBILinkOk;
654 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
656 return RTL_R8(PHYstatus) & LinkStatus;
659 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
661 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
664 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
668 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
669 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
672 static void rtl8169_check_link_status(struct net_device *dev,
673 struct rtl8169_private *tp,
674 void __iomem *ioaddr)
678 spin_lock_irqsave(&tp->lock, flags);
679 if (tp->link_ok(ioaddr)) {
680 netif_carrier_on(dev);
681 if (netif_msg_ifup(tp))
682 printk(KERN_INFO PFX "%s: link up\n", dev->name);
684 if (netif_msg_ifdown(tp))
685 printk(KERN_INFO PFX "%s: link down\n", dev->name);
686 netif_carrier_off(dev);
688 spin_unlock_irqrestore(&tp->lock, flags);
691 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
693 struct rtl8169_private *tp = netdev_priv(dev);
694 void __iomem *ioaddr = tp->mmio_addr;
699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700 wol->supported = WAKE_ANY;
702 spin_lock_irq(&tp->lock);
704 options = RTL_R8(Config1);
705 if (!(options & PMEnable))
708 options = RTL_R8(Config3);
709 if (options & LinkUp)
710 wol->wolopts |= WAKE_PHY;
711 if (options & MagicPacket)
712 wol->wolopts |= WAKE_MAGIC;
714 options = RTL_R8(Config5);
716 wol->wolopts |= WAKE_UCAST;
718 wol->wolopts |= WAKE_BCAST;
720 wol->wolopts |= WAKE_MCAST;
723 spin_unlock_irq(&tp->lock);
726 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
728 struct rtl8169_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->mmio_addr;
736 { WAKE_ANY, Config1, PMEnable },
737 { WAKE_PHY, Config3, LinkUp },
738 { WAKE_MAGIC, Config3, MagicPacket },
739 { WAKE_UCAST, Config5, UWF },
740 { WAKE_BCAST, Config5, BWF },
741 { WAKE_MCAST, Config5, MWF },
742 { WAKE_ANY, Config5, LanWake }
745 spin_lock_irq(&tp->lock);
747 RTL_W8(Cfg9346, Cfg9346_Unlock);
749 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
750 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
751 if (wol->wolopts & cfg[i].opt)
752 options |= cfg[i].mask;
753 RTL_W8(cfg[i].reg, options);
756 RTL_W8(Cfg9346, Cfg9346_Lock);
759 tp->features |= RTL_FEATURE_WOL;
761 tp->features &= ~RTL_FEATURE_WOL;
762 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
764 spin_unlock_irq(&tp->lock);
769 static void rtl8169_get_drvinfo(struct net_device *dev,
770 struct ethtool_drvinfo *info)
772 struct rtl8169_private *tp = netdev_priv(dev);
774 strcpy(info->driver, MODULENAME);
775 strcpy(info->version, RTL8169_VERSION);
776 strcpy(info->bus_info, pci_name(tp->pci_dev));
779 static int rtl8169_get_regs_len(struct net_device *dev)
781 return R8169_REGS_SIZE;
784 static int rtl8169_set_speed_tbi(struct net_device *dev,
785 u8 autoneg, u16 speed, u8 duplex)
787 struct rtl8169_private *tp = netdev_priv(dev);
788 void __iomem *ioaddr = tp->mmio_addr;
792 reg = RTL_R32(TBICSR);
793 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
794 (duplex == DUPLEX_FULL)) {
795 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
796 } else if (autoneg == AUTONEG_ENABLE)
797 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
799 if (netif_msg_link(tp)) {
800 printk(KERN_WARNING "%s: "
801 "incorrect speed setting refused in TBI mode\n",
810 static int rtl8169_set_speed_xmii(struct net_device *dev,
811 u8 autoneg, u16 speed, u8 duplex)
813 struct rtl8169_private *tp = netdev_priv(dev);
814 void __iomem *ioaddr = tp->mmio_addr;
815 int auto_nego, giga_ctrl;
817 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
818 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
819 ADVERTISE_100HALF | ADVERTISE_100FULL);
820 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
821 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
823 if (autoneg == AUTONEG_ENABLE) {
824 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
825 ADVERTISE_100HALF | ADVERTISE_100FULL);
826 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
828 if (speed == SPEED_10)
829 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
830 else if (speed == SPEED_100)
831 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
832 else if (speed == SPEED_1000)
833 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
835 if (duplex == DUPLEX_HALF)
836 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
838 if (duplex == DUPLEX_FULL)
839 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
841 /* This tweak comes straight from Realtek's driver. */
842 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
843 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
844 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
845 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
851 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
852 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
853 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
854 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
855 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
856 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
858 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
859 netif_msg_link(tp)) {
860 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
863 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
866 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
868 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
869 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
870 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
871 mdio_write(ioaddr, 0x1f, 0x0000);
872 mdio_write(ioaddr, 0x0e, 0x0000);
875 tp->phy_auto_nego_reg = auto_nego;
876 tp->phy_1000_ctrl_reg = giga_ctrl;
878 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
879 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
880 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
884 static int rtl8169_set_speed(struct net_device *dev,
885 u8 autoneg, u16 speed, u8 duplex)
887 struct rtl8169_private *tp = netdev_priv(dev);
890 ret = tp->set_speed(dev, autoneg, speed, duplex);
892 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
893 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
898 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
900 struct rtl8169_private *tp = netdev_priv(dev);
904 spin_lock_irqsave(&tp->lock, flags);
905 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
906 spin_unlock_irqrestore(&tp->lock, flags);
911 static u32 rtl8169_get_rx_csum(struct net_device *dev)
913 struct rtl8169_private *tp = netdev_priv(dev);
915 return tp->cp_cmd & RxChkSum;
918 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
920 struct rtl8169_private *tp = netdev_priv(dev);
921 void __iomem *ioaddr = tp->mmio_addr;
924 spin_lock_irqsave(&tp->lock, flags);
927 tp->cp_cmd |= RxChkSum;
929 tp->cp_cmd &= ~RxChkSum;
931 RTL_W16(CPlusCmd, tp->cp_cmd);
934 spin_unlock_irqrestore(&tp->lock, flags);
939 #ifdef CONFIG_R8169_VLAN
941 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
944 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
945 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
948 static void rtl8169_vlan_rx_register(struct net_device *dev,
949 struct vlan_group *grp)
951 struct rtl8169_private *tp = netdev_priv(dev);
952 void __iomem *ioaddr = tp->mmio_addr;
955 spin_lock_irqsave(&tp->lock, flags);
958 tp->cp_cmd |= RxVlan;
960 tp->cp_cmd &= ~RxVlan;
961 RTL_W16(CPlusCmd, tp->cp_cmd);
963 spin_unlock_irqrestore(&tp->lock, flags);
966 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
969 u32 opts2 = le32_to_cpu(desc->opts2);
970 struct vlan_group *vlgrp = tp->vlgrp;
973 if (vlgrp && (opts2 & RxVlanTag)) {
974 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
982 #else /* !CONFIG_R8169_VLAN */
984 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
990 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
998 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001 void __iomem *ioaddr = tp->mmio_addr;
1005 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1006 cmd->port = PORT_FIBRE;
1007 cmd->transceiver = XCVR_INTERNAL;
1009 status = RTL_R32(TBICSR);
1010 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1011 cmd->autoneg = !!(status & TBINwEnable);
1013 cmd->speed = SPEED_1000;
1014 cmd->duplex = DUPLEX_FULL; /* Always set */
1019 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1021 struct rtl8169_private *tp = netdev_priv(dev);
1023 return mii_ethtool_gset(&tp->mii, cmd);
1026 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1028 struct rtl8169_private *tp = netdev_priv(dev);
1029 unsigned long flags;
1032 spin_lock_irqsave(&tp->lock, flags);
1034 rc = tp->get_settings(dev, cmd);
1036 spin_unlock_irqrestore(&tp->lock, flags);
1040 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1043 struct rtl8169_private *tp = netdev_priv(dev);
1044 unsigned long flags;
1046 if (regs->len > R8169_REGS_SIZE)
1047 regs->len = R8169_REGS_SIZE;
1049 spin_lock_irqsave(&tp->lock, flags);
1050 memcpy_fromio(p, tp->mmio_addr, regs->len);
1051 spin_unlock_irqrestore(&tp->lock, flags);
1054 static u32 rtl8169_get_msglevel(struct net_device *dev)
1056 struct rtl8169_private *tp = netdev_priv(dev);
1058 return tp->msg_enable;
1061 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1063 struct rtl8169_private *tp = netdev_priv(dev);
1065 tp->msg_enable = value;
1068 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1075 "tx_single_collisions",
1076 "tx_multi_collisions",
1084 struct rtl8169_counters {
1090 __le16 align_errors;
1091 __le32 tx_one_collision;
1092 __le32 tx_multi_collision;
1094 __le64 rx_broadcast;
1095 __le32 rx_multicast;
1100 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1104 return ARRAY_SIZE(rtl8169_gstrings);
1110 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1111 struct ethtool_stats *stats, u64 *data)
1113 struct rtl8169_private *tp = netdev_priv(dev);
1114 void __iomem *ioaddr = tp->mmio_addr;
1115 struct rtl8169_counters *counters;
1121 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1125 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1126 cmd = (u64)paddr & DMA_32BIT_MASK;
1127 RTL_W32(CounterAddrLow, cmd);
1128 RTL_W32(CounterAddrLow, cmd | CounterDump);
1130 while (RTL_R32(CounterAddrLow) & CounterDump) {
1131 if (msleep_interruptible(1))
1135 RTL_W32(CounterAddrLow, 0);
1136 RTL_W32(CounterAddrHigh, 0);
1138 data[0] = le64_to_cpu(counters->tx_packets);
1139 data[1] = le64_to_cpu(counters->rx_packets);
1140 data[2] = le64_to_cpu(counters->tx_errors);
1141 data[3] = le32_to_cpu(counters->rx_errors);
1142 data[4] = le16_to_cpu(counters->rx_missed);
1143 data[5] = le16_to_cpu(counters->align_errors);
1144 data[6] = le32_to_cpu(counters->tx_one_collision);
1145 data[7] = le32_to_cpu(counters->tx_multi_collision);
1146 data[8] = le64_to_cpu(counters->rx_unicast);
1147 data[9] = le64_to_cpu(counters->rx_broadcast);
1148 data[10] = le32_to_cpu(counters->rx_multicast);
1149 data[11] = le16_to_cpu(counters->tx_aborted);
1150 data[12] = le16_to_cpu(counters->tx_underun);
1152 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1155 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1159 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1164 static const struct ethtool_ops rtl8169_ethtool_ops = {
1165 .get_drvinfo = rtl8169_get_drvinfo,
1166 .get_regs_len = rtl8169_get_regs_len,
1167 .get_link = ethtool_op_get_link,
1168 .get_settings = rtl8169_get_settings,
1169 .set_settings = rtl8169_set_settings,
1170 .get_msglevel = rtl8169_get_msglevel,
1171 .set_msglevel = rtl8169_set_msglevel,
1172 .get_rx_csum = rtl8169_get_rx_csum,
1173 .set_rx_csum = rtl8169_set_rx_csum,
1174 .set_tx_csum = ethtool_op_set_tx_csum,
1175 .set_sg = ethtool_op_set_sg,
1176 .set_tso = ethtool_op_set_tso,
1177 .get_regs = rtl8169_get_regs,
1178 .get_wol = rtl8169_get_wol,
1179 .set_wol = rtl8169_set_wol,
1180 .get_strings = rtl8169_get_strings,
1181 .get_sset_count = rtl8169_get_sset_count,
1182 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1185 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1186 int bitnum, int bitval)
1190 val = mdio_read(ioaddr, reg);
1191 val = (bitval == 1) ?
1192 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1193 mdio_write(ioaddr, reg, val & 0xffff);
1196 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1197 void __iomem *ioaddr)
1200 * The driver currently handles the 8168Bf and the 8168Be identically
1201 * but they can be identified more specifically through the test below
1204 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1206 * Same thing for the 8101Eb and the 8101Ec:
1208 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1216 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1217 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1218 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1219 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1222 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1223 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1224 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1225 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1228 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1229 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1230 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1231 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1232 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1233 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1234 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1235 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1236 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1237 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1238 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1239 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1240 /* FIXME: where did these entries come from ? -- FR */
1241 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1242 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1245 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1246 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1247 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1248 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1249 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1250 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1252 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1256 reg = RTL_R32(TxConfig);
1257 while ((reg & p->mask) != p->val)
1259 tp->mac_version = p->mac_version;
1261 if (p->mask == 0x00000000) {
1262 struct pci_dev *pdev = tp->pci_dev;
1264 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1268 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1270 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1278 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1281 mdio_write(ioaddr, regs->reg, regs->val);
1286 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1289 u16 regs[5]; /* Beware of bit-sign propagation */
1290 } phy_magic[5] = { {
1291 { 0x0000, //w 4 15 12 0
1292 0x00a1, //w 3 15 0 00a1
1293 0x0008, //w 2 15 0 0008
1294 0x1020, //w 1 15 0 1020
1295 0x1000 } },{ //w 0 15 0 1000
1296 { 0x7000, //w 4 15 12 7
1297 0xff41, //w 3 15 0 ff41
1298 0xde60, //w 2 15 0 de60
1299 0x0140, //w 1 15 0 0140
1300 0x0077 } },{ //w 0 15 0 0077
1301 { 0xa000, //w 4 15 12 a
1302 0xdf01, //w 3 15 0 df01
1303 0xdf20, //w 2 15 0 df20
1304 0xff95, //w 1 15 0 ff95
1305 0xfa00 } },{ //w 0 15 0 fa00
1306 { 0xb000, //w 4 15 12 b
1307 0xff41, //w 3 15 0 ff41
1308 0xde20, //w 2 15 0 de20
1309 0x0140, //w 1 15 0 0140
1310 0x00bb } },{ //w 0 15 0 00bb
1311 { 0xf000, //w 4 15 12 f
1312 0xdf01, //w 3 15 0 df01
1313 0xdf20, //w 2 15 0 df20
1314 0xff95, //w 1 15 0 ff95
1315 0xbf00 } //w 0 15 0 bf00
1320 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1321 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1322 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1323 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1325 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1328 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1329 mdio_write(ioaddr, pos, val);
1331 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1332 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1333 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1335 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1338 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1340 struct phy_reg phy_reg_init[] = {
1346 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1349 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1351 struct phy_reg phy_reg_init[] = {
1359 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1362 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1364 struct phy_reg phy_reg_init[] = {
1381 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1384 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1386 struct phy_reg phy_reg_init[] = {
1397 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1400 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1402 struct phy_reg phy_reg_init[] = {
1409 mdio_write(ioaddr, 0x1f, 0x0000);
1410 mdio_patch(ioaddr, 0x11, 1 << 12);
1411 mdio_patch(ioaddr, 0x19, 1 << 13);
1413 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1416 static void rtl_hw_phy_config(struct net_device *dev)
1418 struct rtl8169_private *tp = netdev_priv(dev);
1419 void __iomem *ioaddr = tp->mmio_addr;
1421 rtl8169_print_mac_version(tp);
1423 switch (tp->mac_version) {
1424 case RTL_GIGA_MAC_VER_01:
1426 case RTL_GIGA_MAC_VER_02:
1427 case RTL_GIGA_MAC_VER_03:
1428 rtl8169s_hw_phy_config(ioaddr);
1430 case RTL_GIGA_MAC_VER_04:
1431 rtl8169sb_hw_phy_config(ioaddr);
1433 case RTL_GIGA_MAC_VER_07:
1434 case RTL_GIGA_MAC_VER_08:
1435 case RTL_GIGA_MAC_VER_09:
1436 rtl8102e_hw_phy_config(ioaddr);
1438 case RTL_GIGA_MAC_VER_18:
1439 rtl8168cp_hw_phy_config(ioaddr);
1441 case RTL_GIGA_MAC_VER_19:
1442 rtl8168c_hw_phy_config(ioaddr);
1444 case RTL_GIGA_MAC_VER_20:
1445 rtl8168cx_hw_phy_config(ioaddr);
1452 static void rtl8169_phy_timer(unsigned long __opaque)
1454 struct net_device *dev = (struct net_device *)__opaque;
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 struct timer_list *timer = &tp->timer;
1457 void __iomem *ioaddr = tp->mmio_addr;
1458 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1460 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1462 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1465 spin_lock_irq(&tp->lock);
1467 if (tp->phy_reset_pending(ioaddr)) {
1469 * A busy loop could burn quite a few cycles on nowadays CPU.
1470 * Let's delay the execution of the timer for a few ticks.
1476 if (tp->link_ok(ioaddr))
1479 if (netif_msg_link(tp))
1480 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1482 tp->phy_reset_enable(ioaddr);
1485 mod_timer(timer, jiffies + timeout);
1487 spin_unlock_irq(&tp->lock);
1490 static inline void rtl8169_delete_timer(struct net_device *dev)
1492 struct rtl8169_private *tp = netdev_priv(dev);
1493 struct timer_list *timer = &tp->timer;
1495 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1498 del_timer_sync(timer);
1501 static inline void rtl8169_request_timer(struct net_device *dev)
1503 struct rtl8169_private *tp = netdev_priv(dev);
1504 struct timer_list *timer = &tp->timer;
1506 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1509 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1512 #ifdef CONFIG_NET_POLL_CONTROLLER
1514 * Polling 'interrupt' - used by things like netconsole to send skbs
1515 * without having to re-enable interrupts. It's not called while
1516 * the interrupt routine is executing.
1518 static void rtl8169_netpoll(struct net_device *dev)
1520 struct rtl8169_private *tp = netdev_priv(dev);
1521 struct pci_dev *pdev = tp->pci_dev;
1523 disable_irq(pdev->irq);
1524 rtl8169_interrupt(pdev->irq, dev);
1525 enable_irq(pdev->irq);
1529 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1530 void __iomem *ioaddr)
1533 pci_release_regions(pdev);
1534 pci_disable_device(pdev);
1538 static void rtl8169_phy_reset(struct net_device *dev,
1539 struct rtl8169_private *tp)
1541 void __iomem *ioaddr = tp->mmio_addr;
1544 tp->phy_reset_enable(ioaddr);
1545 for (i = 0; i < 100; i++) {
1546 if (!tp->phy_reset_pending(ioaddr))
1550 if (netif_msg_link(tp))
1551 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1554 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1556 void __iomem *ioaddr = tp->mmio_addr;
1558 rtl_hw_phy_config(dev);
1560 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1561 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1565 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1567 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1568 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1570 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1571 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1573 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1574 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1577 rtl8169_phy_reset(dev, tp);
1580 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1581 * only 8101. Don't panic.
1583 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1585 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1586 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1589 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1591 void __iomem *ioaddr = tp->mmio_addr;
1595 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1596 high = addr[4] | (addr[5] << 8);
1598 spin_lock_irq(&tp->lock);
1600 RTL_W8(Cfg9346, Cfg9346_Unlock);
1602 RTL_W32(MAC4, high);
1603 RTL_W8(Cfg9346, Cfg9346_Lock);
1605 spin_unlock_irq(&tp->lock);
1608 static int rtl_set_mac_address(struct net_device *dev, void *p)
1610 struct rtl8169_private *tp = netdev_priv(dev);
1611 struct sockaddr *addr = p;
1613 if (!is_valid_ether_addr(addr->sa_data))
1614 return -EADDRNOTAVAIL;
1616 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1618 rtl_rar_set(tp, dev->dev_addr);
1623 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 struct mii_ioctl_data *data = if_mii(ifr);
1628 if (!netif_running(dev))
1633 data->phy_id = 32; /* Internal PHY */
1637 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1641 if (!capable(CAP_NET_ADMIN))
1643 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1649 static const struct rtl_cfg_info {
1650 void (*hw_start)(struct net_device *);
1651 unsigned int region;
1656 } rtl_cfg_infos [] = {
1658 .hw_start = rtl_hw_start_8169,
1661 .intr_event = SYSErr | LinkChg | RxOverflow |
1662 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1663 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1664 .features = RTL_FEATURE_GMII
1667 .hw_start = rtl_hw_start_8168,
1670 .intr_event = SYSErr | LinkChg | RxOverflow |
1671 TxErr | TxOK | RxOK | RxErr,
1672 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1673 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1676 .hw_start = rtl_hw_start_8101,
1679 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1680 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1681 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1682 .features = RTL_FEATURE_MSI
1686 /* Cfg9346_Unlock assumed. */
1687 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1688 const struct rtl_cfg_info *cfg)
1693 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1694 if (cfg->features & RTL_FEATURE_MSI) {
1695 if (pci_enable_msi(pdev)) {
1696 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1699 msi = RTL_FEATURE_MSI;
1702 RTL_W8(Config2, cfg2);
1706 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1708 if (tp->features & RTL_FEATURE_MSI) {
1709 pci_disable_msi(pdev);
1710 tp->features &= ~RTL_FEATURE_MSI;
1714 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1716 int ret, count = 100;
1720 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1726 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1729 } while (!(status & PCI_VPD_ADDR_F) && --count);
1731 if (!(status & PCI_VPD_ADDR_F))
1734 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1738 *val = cpu_to_le32(value);
1743 static void rtl_init_mac_address(struct rtl8169_private *tp,
1744 void __iomem *ioaddr)
1746 struct pci_dev *pdev = tp->pci_dev;
1750 DECLARE_MAC_BUF(buf);
1752 cfg1 = RTL_R8(Config1);
1753 if (!(cfg1 & VPD)) {
1754 dprintk("VPD access not enabled, enabling\n");
1755 RTL_W8(Cfg9346, Cfg9346_Unlock);
1756 RTL_W8(Config1, cfg1 | VPD);
1757 RTL_W8(Cfg9346, Cfg9346_Lock);
1760 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1764 /* MAC address is stored in EEPROM at offset 0x0e
1765 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1766 * address as defined in the PCI 2.2 Specifications, but the VPD data
1767 * is always consecutive 4-byte data starting from the VPD address
1770 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1771 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1772 dprintk("Reading MAC address from EEPROM failed\n");
1776 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1778 /* Write MAC address */
1779 rtl_rar_set(tp, mac);
1782 static int __devinit
1783 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1785 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1786 const unsigned int region = cfg->region;
1787 struct rtl8169_private *tp;
1788 struct mii_if_info *mii;
1789 struct net_device *dev;
1790 void __iomem *ioaddr;
1794 if (netif_msg_drv(&debug)) {
1795 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1796 MODULENAME, RTL8169_VERSION);
1799 dev = alloc_etherdev(sizeof (*tp));
1801 if (netif_msg_drv(&debug))
1802 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1807 SET_NETDEV_DEV(dev, &pdev->dev);
1808 tp = netdev_priv(dev);
1811 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1815 mii->mdio_read = rtl_mdio_read;
1816 mii->mdio_write = rtl_mdio_write;
1817 mii->phy_id_mask = 0x1f;
1818 mii->reg_num_mask = 0x1f;
1819 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1821 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1822 rc = pci_enable_device(pdev);
1824 if (netif_msg_probe(tp))
1825 dev_err(&pdev->dev, "enable failure\n");
1826 goto err_out_free_dev_1;
1829 rc = pci_set_mwi(pdev);
1831 goto err_out_disable_2;
1833 /* make sure PCI base addr 1 is MMIO */
1834 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1835 if (netif_msg_probe(tp)) {
1837 "region #%d not an MMIO resource, aborting\n",
1844 /* check for weird/broken PCI region reporting */
1845 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1846 if (netif_msg_probe(tp)) {
1848 "Invalid PCI region size(s), aborting\n");
1854 rc = pci_request_regions(pdev, MODULENAME);
1856 if (netif_msg_probe(tp))
1857 dev_err(&pdev->dev, "could not request regions.\n");
1861 tp->cp_cmd = PCIMulRW | RxChkSum;
1863 if ((sizeof(dma_addr_t) > 4) &&
1864 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1865 tp->cp_cmd |= PCIDAC;
1866 dev->features |= NETIF_F_HIGHDMA;
1868 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1870 if (netif_msg_probe(tp)) {
1872 "DMA configuration failed.\n");
1874 goto err_out_free_res_4;
1878 pci_set_master(pdev);
1880 /* ioremap MMIO region */
1881 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1883 if (netif_msg_probe(tp))
1884 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1886 goto err_out_free_res_4;
1889 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1890 if (!tp->pcie_cap && netif_msg_probe(tp))
1891 dev_info(&pdev->dev, "no PCI Express capability\n");
1893 /* Unneeded ? Don't mess with Mrs. Murphy. */
1894 rtl8169_irq_mask_and_ack(ioaddr);
1896 /* Soft reset the chip. */
1897 RTL_W8(ChipCmd, CmdReset);
1899 /* Check that the chip has finished the reset. */
1900 for (i = 0; i < 100; i++) {
1901 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1903 msleep_interruptible(1);
1906 /* Identify chip attached to board */
1907 rtl8169_get_mac_version(tp, ioaddr);
1909 rtl8169_print_mac_version(tp);
1911 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1912 if (tp->mac_version == rtl_chip_info[i].mac_version)
1915 if (i == ARRAY_SIZE(rtl_chip_info)) {
1916 /* Unknown chip: assume array element #0, original RTL-8169 */
1917 if (netif_msg_probe(tp)) {
1918 dev_printk(KERN_DEBUG, &pdev->dev,
1919 "unknown chip version, assuming %s\n",
1920 rtl_chip_info[0].name);
1926 RTL_W8(Cfg9346, Cfg9346_Unlock);
1927 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1928 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1929 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
1930 tp->features |= RTL_FEATURE_WOL;
1931 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
1932 tp->features |= RTL_FEATURE_WOL;
1933 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1934 RTL_W8(Cfg9346, Cfg9346_Lock);
1936 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1937 (RTL_R8(PHYstatus) & TBI_Enable)) {
1938 tp->set_speed = rtl8169_set_speed_tbi;
1939 tp->get_settings = rtl8169_gset_tbi;
1940 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1941 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1942 tp->link_ok = rtl8169_tbi_link_ok;
1944 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1946 tp->set_speed = rtl8169_set_speed_xmii;
1947 tp->get_settings = rtl8169_gset_xmii;
1948 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1949 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1950 tp->link_ok = rtl8169_xmii_link_ok;
1952 dev->do_ioctl = rtl8169_ioctl;
1955 /* Read MAC address from EEPROM */
1956 rtl_init_mac_address(tp, ioaddr);
1958 /* Get MAC address */
1959 for (i = 0; i < MAC_ADDR_LEN; i++)
1960 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1961 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1963 dev->open = rtl8169_open;
1964 dev->hard_start_xmit = rtl8169_start_xmit;
1965 dev->get_stats = rtl8169_get_stats;
1966 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1967 dev->stop = rtl8169_close;
1968 dev->tx_timeout = rtl8169_tx_timeout;
1969 dev->set_multicast_list = rtl_set_rx_mode;
1970 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1971 dev->irq = pdev->irq;
1972 dev->base_addr = (unsigned long) ioaddr;
1973 dev->change_mtu = rtl8169_change_mtu;
1974 dev->set_mac_address = rtl_set_mac_address;
1976 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1978 #ifdef CONFIG_R8169_VLAN
1979 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1980 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1983 #ifdef CONFIG_NET_POLL_CONTROLLER
1984 dev->poll_controller = rtl8169_netpoll;
1987 tp->intr_mask = 0xffff;
1988 tp->mmio_addr = ioaddr;
1989 tp->align = cfg->align;
1990 tp->hw_start = cfg->hw_start;
1991 tp->intr_event = cfg->intr_event;
1992 tp->napi_event = cfg->napi_event;
1994 init_timer(&tp->timer);
1995 tp->timer.data = (unsigned long) dev;
1996 tp->timer.function = rtl8169_phy_timer;
1998 spin_lock_init(&tp->lock);
2000 rc = register_netdev(dev);
2004 pci_set_drvdata(pdev, dev);
2006 if (netif_msg_probe(tp)) {
2007 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2009 printk(KERN_INFO "%s: %s at 0x%lx, "
2010 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2011 "XID %08x IRQ %d\n",
2013 rtl_chip_info[tp->chipset].name,
2015 dev->dev_addr[0], dev->dev_addr[1],
2016 dev->dev_addr[2], dev->dev_addr[3],
2017 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2020 rtl8169_init_phy(dev, tp);
2021 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2027 rtl_disable_msi(pdev, tp);
2030 pci_release_regions(pdev);
2032 pci_clear_mwi(pdev);
2034 pci_disable_device(pdev);
2040 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2042 struct net_device *dev = pci_get_drvdata(pdev);
2043 struct rtl8169_private *tp = netdev_priv(dev);
2045 flush_scheduled_work();
2047 unregister_netdev(dev);
2048 rtl_disable_msi(pdev, tp);
2049 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2050 pci_set_drvdata(pdev, NULL);
2053 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2054 struct net_device *dev)
2056 unsigned int mtu = dev->mtu;
2058 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2061 static int rtl8169_open(struct net_device *dev)
2063 struct rtl8169_private *tp = netdev_priv(dev);
2064 struct pci_dev *pdev = tp->pci_dev;
2065 int retval = -ENOMEM;
2068 rtl8169_set_rxbufsize(tp, dev);
2071 * Rx and Tx desscriptors needs 256 bytes alignment.
2072 * pci_alloc_consistent provides more.
2074 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2076 if (!tp->TxDescArray)
2079 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2081 if (!tp->RxDescArray)
2084 retval = rtl8169_init_ring(dev);
2088 INIT_DELAYED_WORK(&tp->task, NULL);
2092 retval = request_irq(dev->irq, rtl8169_interrupt,
2093 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2096 goto err_release_ring_2;
2098 napi_enable(&tp->napi);
2102 rtl8169_request_timer(dev);
2104 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2109 rtl8169_rx_clear(tp);
2111 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2114 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2119 static void rtl8169_hw_reset(void __iomem *ioaddr)
2121 /* Disable interrupts */
2122 rtl8169_irq_mask_and_ack(ioaddr);
2124 /* Reset the chipset */
2125 RTL_W8(ChipCmd, CmdReset);
2131 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2133 void __iomem *ioaddr = tp->mmio_addr;
2134 u32 cfg = rtl8169_rx_config;
2136 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2137 RTL_W32(RxConfig, cfg);
2139 /* Set DMA burst size and Interframe Gap Time */
2140 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2141 (InterFrameGap << TxInterFrameGapShift));
2144 static void rtl_hw_start(struct net_device *dev)
2146 struct rtl8169_private *tp = netdev_priv(dev);
2147 void __iomem *ioaddr = tp->mmio_addr;
2150 /* Soft reset the chip. */
2151 RTL_W8(ChipCmd, CmdReset);
2153 /* Check that the chip has finished the reset. */
2154 for (i = 0; i < 100; i++) {
2155 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2157 msleep_interruptible(1);
2162 netif_start_queue(dev);
2166 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2167 void __iomem *ioaddr)
2170 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2171 * register to be written before TxDescAddrLow to work.
2172 * Switching from MMIO to I/O access fixes the issue as well.
2174 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2175 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2176 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2177 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2180 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2184 cmd = RTL_R16(CPlusCmd);
2185 RTL_W16(CPlusCmd, cmd);
2189 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2191 /* Low hurts. Let's disable the filtering. */
2192 RTL_W16(RxMaxSize, 16383);
2195 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2202 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2203 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2204 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2205 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2210 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2211 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2212 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2213 RTL_W32(0x7c, p->val);
2219 static void rtl_hw_start_8169(struct net_device *dev)
2221 struct rtl8169_private *tp = netdev_priv(dev);
2222 void __iomem *ioaddr = tp->mmio_addr;
2223 struct pci_dev *pdev = tp->pci_dev;
2225 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2226 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2227 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2230 RTL_W8(Cfg9346, Cfg9346_Unlock);
2231 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2232 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2233 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2234 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2235 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2237 RTL_W8(EarlyTxThres, EarlyTxThld);
2239 rtl_set_rx_max_size(ioaddr);
2241 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2242 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2243 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2244 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2245 rtl_set_rx_tx_config_registers(tp);
2247 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2249 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2250 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2251 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2252 "Bit-3 and bit-14 MUST be 1\n");
2253 tp->cp_cmd |= (1 << 14);
2256 RTL_W16(CPlusCmd, tp->cp_cmd);
2258 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2261 * Undocumented corner. Supposedly:
2262 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2264 RTL_W16(IntrMitigate, 0x0000);
2266 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2268 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2269 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2270 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2271 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2272 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2273 rtl_set_rx_tx_config_registers(tp);
2276 RTL_W8(Cfg9346, Cfg9346_Lock);
2278 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2281 RTL_W32(RxMissed, 0);
2283 rtl_set_rx_mode(dev);
2285 /* no early-rx interrupts */
2286 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2288 /* Enable all known interrupts by setting the interrupt mask. */
2289 RTL_W16(IntrMask, tp->intr_event);
2292 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2294 struct net_device *dev = pci_get_drvdata(pdev);
2295 struct rtl8169_private *tp = netdev_priv(dev);
2296 int cap = tp->pcie_cap;
2301 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2302 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2303 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2307 static void rtl_csi_access_enable(void __iomem *ioaddr)
2311 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2312 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2316 unsigned int offset;
2321 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2326 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2327 rtl_ephy_write(ioaddr, e->offset, w);
2332 static void rtl_hw_start_8168(struct net_device *dev)
2334 struct rtl8169_private *tp = netdev_priv(dev);
2335 void __iomem *ioaddr = tp->mmio_addr;
2336 struct pci_dev *pdev = tp->pci_dev;
2338 RTL_W8(Cfg9346, Cfg9346_Unlock);
2340 RTL_W8(EarlyTxThres, EarlyTxThld);
2342 rtl_set_rx_max_size(ioaddr);
2344 rtl_set_rx_tx_config_registers(tp);
2346 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2348 RTL_W16(CPlusCmd, tp->cp_cmd);
2350 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2352 RTL_W16(IntrMitigate, 0x5151);
2354 /* Work around for RxFIFO overflow. */
2355 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2356 tp->intr_event |= RxFIFOOver | PCSTimeout;
2357 tp->intr_event &= ~RxOverflow;
2360 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2362 RTL_W8(Cfg9346, Cfg9346_Lock);
2366 rtl_set_rx_mode(dev);
2368 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2370 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2372 RTL_W16(IntrMask, tp->intr_event);
2375 #define R810X_CPCMD_QUIRK_MASK (\
2387 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2389 static struct ephy_info e_info_8102e_1[] = {
2390 { 0x01, 0, 0x6e65 },
2391 { 0x02, 0, 0x091f },
2392 { 0x03, 0, 0xc2f9 },
2393 { 0x06, 0, 0xafb5 },
2394 { 0x07, 0, 0x0e00 },
2395 { 0x19, 0, 0xec80 },
2396 { 0x01, 0, 0x2e65 },
2401 rtl_csi_access_enable(ioaddr);
2403 RTL_W8(DBG_REG, FIX_NAK_1);
2405 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2408 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2409 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2411 cfg1 = RTL_R8(Config1);
2412 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2413 RTL_W8(Config1, cfg1 & ~LEDS0);
2415 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2417 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2420 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2422 rtl_csi_access_enable(ioaddr);
2424 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2426 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2427 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2429 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2432 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2434 rtl_hw_start_8102e_2(ioaddr, pdev);
2436 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2439 static void rtl_hw_start_8101(struct net_device *dev)
2441 struct rtl8169_private *tp = netdev_priv(dev);
2442 void __iomem *ioaddr = tp->mmio_addr;
2443 struct pci_dev *pdev = tp->pci_dev;
2445 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2446 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2447 int cap = tp->pcie_cap;
2450 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2451 PCI_EXP_DEVCTL_NOSNOOP_EN);
2455 switch (tp->mac_version) {
2456 case RTL_GIGA_MAC_VER_07:
2457 rtl_hw_start_8102e_1(ioaddr, pdev);
2460 case RTL_GIGA_MAC_VER_08:
2461 rtl_hw_start_8102e_3(ioaddr, pdev);
2464 case RTL_GIGA_MAC_VER_09:
2465 rtl_hw_start_8102e_2(ioaddr, pdev);
2469 RTL_W8(Cfg9346, Cfg9346_Unlock);
2471 RTL_W8(EarlyTxThres, EarlyTxThld);
2473 rtl_set_rx_max_size(ioaddr);
2475 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2477 RTL_W16(CPlusCmd, tp->cp_cmd);
2479 RTL_W16(IntrMitigate, 0x0000);
2481 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2483 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2484 rtl_set_rx_tx_config_registers(tp);
2486 RTL_W8(Cfg9346, Cfg9346_Lock);
2490 rtl_set_rx_mode(dev);
2492 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2494 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2496 RTL_W16(IntrMask, tp->intr_event);
2499 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2501 struct rtl8169_private *tp = netdev_priv(dev);
2504 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2509 if (!netif_running(dev))
2514 rtl8169_set_rxbufsize(tp, dev);
2516 ret = rtl8169_init_ring(dev);
2520 napi_enable(&tp->napi);
2524 rtl8169_request_timer(dev);
2530 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2532 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2533 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2536 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2537 struct sk_buff **sk_buff, struct RxDesc *desc)
2539 struct pci_dev *pdev = tp->pci_dev;
2541 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2542 PCI_DMA_FROMDEVICE);
2543 dev_kfree_skb(*sk_buff);
2545 rtl8169_make_unusable_by_asic(desc);
2548 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2550 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2552 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2555 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2558 desc->addr = cpu_to_le64(mapping);
2560 rtl8169_mark_to_asic(desc, rx_buf_sz);
2563 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2564 struct net_device *dev,
2565 struct RxDesc *desc, int rx_buf_sz,
2568 struct sk_buff *skb;
2572 pad = align ? align : NET_IP_ALIGN;
2574 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2578 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2580 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2581 PCI_DMA_FROMDEVICE);
2583 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2588 rtl8169_make_unusable_by_asic(desc);
2592 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2596 for (i = 0; i < NUM_RX_DESC; i++) {
2597 if (tp->Rx_skbuff[i]) {
2598 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2599 tp->RxDescArray + i);
2604 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2609 for (cur = start; end - cur != 0; cur++) {
2610 struct sk_buff *skb;
2611 unsigned int i = cur % NUM_RX_DESC;
2613 WARN_ON((s32)(end - cur) < 0);
2615 if (tp->Rx_skbuff[i])
2618 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2619 tp->RxDescArray + i,
2620 tp->rx_buf_sz, tp->align);
2624 tp->Rx_skbuff[i] = skb;
2629 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2631 desc->opts1 |= cpu_to_le32(RingEnd);
2634 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2636 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2639 static int rtl8169_init_ring(struct net_device *dev)
2641 struct rtl8169_private *tp = netdev_priv(dev);
2643 rtl8169_init_ring_indexes(tp);
2645 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2646 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2648 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2651 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2656 rtl8169_rx_clear(tp);
2660 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2661 struct TxDesc *desc)
2663 unsigned int len = tx_skb->len;
2665 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2672 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2676 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2677 unsigned int entry = i % NUM_TX_DESC;
2678 struct ring_info *tx_skb = tp->tx_skb + entry;
2679 unsigned int len = tx_skb->len;
2682 struct sk_buff *skb = tx_skb->skb;
2684 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2685 tp->TxDescArray + entry);
2690 tp->dev->stats.tx_dropped++;
2693 tp->cur_tx = tp->dirty_tx = 0;
2696 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2698 struct rtl8169_private *tp = netdev_priv(dev);
2700 PREPARE_DELAYED_WORK(&tp->task, task);
2701 schedule_delayed_work(&tp->task, 4);
2704 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2706 struct rtl8169_private *tp = netdev_priv(dev);
2707 void __iomem *ioaddr = tp->mmio_addr;
2709 synchronize_irq(dev->irq);
2711 /* Wait for any pending NAPI task to complete */
2712 napi_disable(&tp->napi);
2714 rtl8169_irq_mask_and_ack(ioaddr);
2716 tp->intr_mask = 0xffff;
2717 RTL_W16(IntrMask, tp->intr_event);
2718 napi_enable(&tp->napi);
2721 static void rtl8169_reinit_task(struct work_struct *work)
2723 struct rtl8169_private *tp =
2724 container_of(work, struct rtl8169_private, task.work);
2725 struct net_device *dev = tp->dev;
2730 if (!netif_running(dev))
2733 rtl8169_wait_for_quiescence(dev);
2736 ret = rtl8169_open(dev);
2737 if (unlikely(ret < 0)) {
2738 if (net_ratelimit() && netif_msg_drv(tp)) {
2739 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2740 " Rescheduling.\n", dev->name, ret);
2742 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2749 static void rtl8169_reset_task(struct work_struct *work)
2751 struct rtl8169_private *tp =
2752 container_of(work, struct rtl8169_private, task.work);
2753 struct net_device *dev = tp->dev;
2757 if (!netif_running(dev))
2760 rtl8169_wait_for_quiescence(dev);
2762 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2763 rtl8169_tx_clear(tp);
2765 if (tp->dirty_rx == tp->cur_rx) {
2766 rtl8169_init_ring_indexes(tp);
2768 netif_wake_queue(dev);
2769 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2771 if (net_ratelimit() && netif_msg_intr(tp)) {
2772 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2775 rtl8169_schedule_work(dev, rtl8169_reset_task);
2782 static void rtl8169_tx_timeout(struct net_device *dev)
2784 struct rtl8169_private *tp = netdev_priv(dev);
2786 rtl8169_hw_reset(tp->mmio_addr);
2788 /* Let's wait a bit while any (async) irq lands on */
2789 rtl8169_schedule_work(dev, rtl8169_reset_task);
2792 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2795 struct skb_shared_info *info = skb_shinfo(skb);
2796 unsigned int cur_frag, entry;
2797 struct TxDesc * uninitialized_var(txd);
2800 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2801 skb_frag_t *frag = info->frags + cur_frag;
2806 entry = (entry + 1) % NUM_TX_DESC;
2808 txd = tp->TxDescArray + entry;
2810 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2811 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2813 /* anti gcc 2.95.3 bugware (sic) */
2814 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2816 txd->opts1 = cpu_to_le32(status);
2817 txd->addr = cpu_to_le64(mapping);
2819 tp->tx_skb[entry].len = len;
2823 tp->tx_skb[entry].skb = skb;
2824 txd->opts1 |= cpu_to_le32(LastFrag);
2830 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2832 if (dev->features & NETIF_F_TSO) {
2833 u32 mss = skb_shinfo(skb)->gso_size;
2836 return LargeSend | ((mss & MSSMask) << MSSShift);
2838 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2839 const struct iphdr *ip = ip_hdr(skb);
2841 if (ip->protocol == IPPROTO_TCP)
2842 return IPCS | TCPCS;
2843 else if (ip->protocol == IPPROTO_UDP)
2844 return IPCS | UDPCS;
2845 WARN_ON(1); /* we need a WARN() */
2850 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2852 struct rtl8169_private *tp = netdev_priv(dev);
2853 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2854 struct TxDesc *txd = tp->TxDescArray + entry;
2855 void __iomem *ioaddr = tp->mmio_addr;
2859 int ret = NETDEV_TX_OK;
2861 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2862 if (netif_msg_drv(tp)) {
2864 "%s: BUG! Tx Ring full when queue awake!\n",
2870 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2873 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2875 frags = rtl8169_xmit_frags(tp, skb, opts1);
2877 len = skb_headlen(skb);
2882 if (unlikely(len < ETH_ZLEN)) {
2883 if (skb_padto(skb, ETH_ZLEN))
2884 goto err_update_stats;
2888 opts1 |= FirstFrag | LastFrag;
2889 tp->tx_skb[entry].skb = skb;
2892 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2894 tp->tx_skb[entry].len = len;
2895 txd->addr = cpu_to_le64(mapping);
2896 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2900 /* anti gcc 2.95.3 bugware (sic) */
2901 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2902 txd->opts1 = cpu_to_le32(status);
2904 dev->trans_start = jiffies;
2906 tp->cur_tx += frags + 1;
2910 RTL_W8(TxPoll, NPQ); /* set polling bit */
2912 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2913 netif_stop_queue(dev);
2915 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2916 netif_wake_queue(dev);
2923 netif_stop_queue(dev);
2924 ret = NETDEV_TX_BUSY;
2926 dev->stats.tx_dropped++;
2930 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2932 struct rtl8169_private *tp = netdev_priv(dev);
2933 struct pci_dev *pdev = tp->pci_dev;
2934 void __iomem *ioaddr = tp->mmio_addr;
2935 u16 pci_status, pci_cmd;
2937 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2938 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2940 if (netif_msg_intr(tp)) {
2942 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2943 dev->name, pci_cmd, pci_status);
2947 * The recovery sequence below admits a very elaborated explanation:
2948 * - it seems to work;
2949 * - I did not see what else could be done;
2950 * - it makes iop3xx happy.
2952 * Feel free to adjust to your needs.
2954 if (pdev->broken_parity_status)
2955 pci_cmd &= ~PCI_COMMAND_PARITY;
2957 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2959 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2961 pci_write_config_word(pdev, PCI_STATUS,
2962 pci_status & (PCI_STATUS_DETECTED_PARITY |
2963 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2964 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2966 /* The infamous DAC f*ckup only happens at boot time */
2967 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2968 if (netif_msg_intr(tp))
2969 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2970 tp->cp_cmd &= ~PCIDAC;
2971 RTL_W16(CPlusCmd, tp->cp_cmd);
2972 dev->features &= ~NETIF_F_HIGHDMA;
2975 rtl8169_hw_reset(ioaddr);
2977 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2980 static void rtl8169_tx_interrupt(struct net_device *dev,
2981 struct rtl8169_private *tp,
2982 void __iomem *ioaddr)
2984 unsigned int dirty_tx, tx_left;
2986 dirty_tx = tp->dirty_tx;
2988 tx_left = tp->cur_tx - dirty_tx;
2990 while (tx_left > 0) {
2991 unsigned int entry = dirty_tx % NUM_TX_DESC;
2992 struct ring_info *tx_skb = tp->tx_skb + entry;
2993 u32 len = tx_skb->len;
2997 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2998 if (status & DescOwn)
3001 dev->stats.tx_bytes += len;
3002 dev->stats.tx_packets++;
3004 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3006 if (status & LastFrag) {
3007 dev_kfree_skb_irq(tx_skb->skb);
3014 if (tp->dirty_tx != dirty_tx) {
3015 tp->dirty_tx = dirty_tx;
3017 if (netif_queue_stopped(dev) &&
3018 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3019 netif_wake_queue(dev);
3022 * 8168 hack: TxPoll requests are lost when the Tx packets are
3023 * too close. Let's kick an extra TxPoll request when a burst
3024 * of start_xmit activity is detected (if it is not detected,
3025 * it is slow enough). -- FR
3028 if (tp->cur_tx != dirty_tx)
3029 RTL_W8(TxPoll, NPQ);
3033 static inline int rtl8169_fragmented_frame(u32 status)
3035 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3038 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3040 u32 opts1 = le32_to_cpu(desc->opts1);
3041 u32 status = opts1 & RxProtoMask;
3043 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3044 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3045 ((status == RxProtoIP) && !(opts1 & IPFail)))
3046 skb->ip_summed = CHECKSUM_UNNECESSARY;
3048 skb->ip_summed = CHECKSUM_NONE;
3051 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3052 struct rtl8169_private *tp, int pkt_size,
3055 struct sk_buff *skb;
3058 if (pkt_size >= rx_copybreak)
3061 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3065 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3066 PCI_DMA_FROMDEVICE);
3067 skb_reserve(skb, NET_IP_ALIGN);
3068 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3075 static int rtl8169_rx_interrupt(struct net_device *dev,
3076 struct rtl8169_private *tp,
3077 void __iomem *ioaddr, u32 budget)
3079 unsigned int cur_rx, rx_left;
3080 unsigned int delta, count;
3082 cur_rx = tp->cur_rx;
3083 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3084 rx_left = min(rx_left, budget);
3086 for (; rx_left > 0; rx_left--, cur_rx++) {
3087 unsigned int entry = cur_rx % NUM_RX_DESC;
3088 struct RxDesc *desc = tp->RxDescArray + entry;
3092 status = le32_to_cpu(desc->opts1);
3094 if (status & DescOwn)
3096 if (unlikely(status & RxRES)) {
3097 if (netif_msg_rx_err(tp)) {
3099 "%s: Rx ERROR. status = %08x\n",
3102 dev->stats.rx_errors++;
3103 if (status & (RxRWT | RxRUNT))
3104 dev->stats.rx_length_errors++;
3106 dev->stats.rx_crc_errors++;
3107 if (status & RxFOVF) {
3108 rtl8169_schedule_work(dev, rtl8169_reset_task);
3109 dev->stats.rx_fifo_errors++;
3111 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3113 struct sk_buff *skb = tp->Rx_skbuff[entry];
3114 dma_addr_t addr = le64_to_cpu(desc->addr);
3115 int pkt_size = (status & 0x00001FFF) - 4;
3116 struct pci_dev *pdev = tp->pci_dev;
3119 * The driver does not support incoming fragmented
3120 * frames. They are seen as a symptom of over-mtu
3123 if (unlikely(rtl8169_fragmented_frame(status))) {
3124 dev->stats.rx_dropped++;
3125 dev->stats.rx_length_errors++;
3126 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3130 rtl8169_rx_csum(skb, desc);
3132 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3133 pci_dma_sync_single_for_device(pdev, addr,
3134 pkt_size, PCI_DMA_FROMDEVICE);
3135 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3137 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3138 PCI_DMA_FROMDEVICE);
3139 tp->Rx_skbuff[entry] = NULL;
3142 skb_put(skb, pkt_size);
3143 skb->protocol = eth_type_trans(skb, dev);
3145 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3146 netif_receive_skb(skb);
3148 dev->last_rx = jiffies;
3149 dev->stats.rx_bytes += pkt_size;
3150 dev->stats.rx_packets++;
3153 /* Work around for AMD plateform. */
3154 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3155 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3161 count = cur_rx - tp->cur_rx;
3162 tp->cur_rx = cur_rx;
3164 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3165 if (!delta && count && netif_msg_intr(tp))
3166 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3167 tp->dirty_rx += delta;
3170 * FIXME: until there is periodic timer to try and refill the ring,
3171 * a temporary shortage may definitely kill the Rx process.
3172 * - disable the asic to try and avoid an overflow and kick it again
3174 * - how do others driver handle this condition (Uh oh...).
3176 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3177 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3182 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3184 struct net_device *dev = dev_instance;
3185 struct rtl8169_private *tp = netdev_priv(dev);
3186 void __iomem *ioaddr = tp->mmio_addr;
3190 status = RTL_R16(IntrStatus);
3192 /* hotplug/major error/no more work/shared irq */
3193 if ((status == 0xffff) || !status)
3198 if (unlikely(!netif_running(dev))) {
3199 rtl8169_asic_down(ioaddr);
3203 status &= tp->intr_mask;
3205 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3207 if (!(status & tp->intr_event))
3210 /* Work around for rx fifo overflow */
3211 if (unlikely(status & RxFIFOOver) &&
3212 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3213 netif_stop_queue(dev);
3214 rtl8169_tx_timeout(dev);
3218 if (unlikely(status & SYSErr)) {
3219 rtl8169_pcierr_interrupt(dev);
3223 if (status & LinkChg)
3224 rtl8169_check_link_status(dev, tp, ioaddr);
3226 if (status & tp->napi_event) {
3227 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3228 tp->intr_mask = ~tp->napi_event;
3230 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3231 __netif_rx_schedule(dev, &tp->napi);
3232 else if (netif_msg_intr(tp)) {
3233 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3238 return IRQ_RETVAL(handled);
3241 static int rtl8169_poll(struct napi_struct *napi, int budget)
3243 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3244 struct net_device *dev = tp->dev;
3245 void __iomem *ioaddr = tp->mmio_addr;
3248 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3249 rtl8169_tx_interrupt(dev, tp, ioaddr);
3251 if (work_done < budget) {
3252 netif_rx_complete(dev, napi);
3253 tp->intr_mask = 0xffff;
3255 * 20040426: the barrier is not strictly required but the
3256 * behavior of the irq handler could be less predictable
3257 * without it. Btw, the lack of flush for the posted pci
3258 * write is safe - FR
3261 RTL_W16(IntrMask, tp->intr_event);
3267 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3269 struct rtl8169_private *tp = netdev_priv(dev);
3271 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3274 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3275 RTL_W32(RxMissed, 0);
3278 static void rtl8169_down(struct net_device *dev)
3280 struct rtl8169_private *tp = netdev_priv(dev);
3281 void __iomem *ioaddr = tp->mmio_addr;
3282 unsigned int intrmask;
3284 rtl8169_delete_timer(dev);
3286 netif_stop_queue(dev);
3288 napi_disable(&tp->napi);
3291 spin_lock_irq(&tp->lock);
3293 rtl8169_asic_down(ioaddr);
3295 rtl8169_rx_missed(dev, ioaddr);
3297 spin_unlock_irq(&tp->lock);
3299 synchronize_irq(dev->irq);
3301 /* Give a racing hard_start_xmit a few cycles to complete. */
3302 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3305 * And now for the 50k$ question: are IRQ disabled or not ?
3307 * Two paths lead here:
3309 * -> netif_running() is available to sync the current code and the
3310 * IRQ handler. See rtl8169_interrupt for details.
3311 * 2) dev->change_mtu
3312 * -> rtl8169_poll can not be issued again and re-enable the
3313 * interruptions. Let's simply issue the IRQ down sequence again.
3315 * No loop if hotpluged or major error (0xffff).
3317 intrmask = RTL_R16(IntrMask);
3318 if (intrmask && (intrmask != 0xffff))
3321 rtl8169_tx_clear(tp);
3323 rtl8169_rx_clear(tp);
3326 static int rtl8169_close(struct net_device *dev)
3328 struct rtl8169_private *tp = netdev_priv(dev);
3329 struct pci_dev *pdev = tp->pci_dev;
3333 free_irq(dev->irq, dev);
3335 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3337 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3339 tp->TxDescArray = NULL;
3340 tp->RxDescArray = NULL;
3345 static void rtl_set_rx_mode(struct net_device *dev)
3347 struct rtl8169_private *tp = netdev_priv(dev);
3348 void __iomem *ioaddr = tp->mmio_addr;
3349 unsigned long flags;
3350 u32 mc_filter[2]; /* Multicast hash filter */
3354 if (dev->flags & IFF_PROMISC) {
3355 /* Unconditionally log net taps. */
3356 if (netif_msg_link(tp)) {
3357 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3361 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3363 mc_filter[1] = mc_filter[0] = 0xffffffff;
3364 } else if ((dev->mc_count > multicast_filter_limit)
3365 || (dev->flags & IFF_ALLMULTI)) {
3366 /* Too many to filter perfectly -- accept all multicasts. */
3367 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3368 mc_filter[1] = mc_filter[0] = 0xffffffff;
3370 struct dev_mc_list *mclist;
3373 rx_mode = AcceptBroadcast | AcceptMyPhys;
3374 mc_filter[1] = mc_filter[0] = 0;
3375 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3376 i++, mclist = mclist->next) {
3377 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3378 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3379 rx_mode |= AcceptMulticast;
3383 spin_lock_irqsave(&tp->lock, flags);
3385 tmp = rtl8169_rx_config | rx_mode |
3386 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3388 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3389 u32 data = mc_filter[0];
3391 mc_filter[0] = swab32(mc_filter[1]);
3392 mc_filter[1] = swab32(data);
3395 RTL_W32(MAR0 + 0, mc_filter[0]);
3396 RTL_W32(MAR0 + 4, mc_filter[1]);
3398 RTL_W32(RxConfig, tmp);
3400 spin_unlock_irqrestore(&tp->lock, flags);
3404 * rtl8169_get_stats - Get rtl8169 read/write statistics
3405 * @dev: The Ethernet Device to get statistics for
3407 * Get TX/RX statistics for rtl8169
3409 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3411 struct rtl8169_private *tp = netdev_priv(dev);
3412 void __iomem *ioaddr = tp->mmio_addr;
3413 unsigned long flags;
3415 if (netif_running(dev)) {
3416 spin_lock_irqsave(&tp->lock, flags);
3417 rtl8169_rx_missed(dev, ioaddr);
3418 spin_unlock_irqrestore(&tp->lock, flags);
3426 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3428 struct net_device *dev = pci_get_drvdata(pdev);
3429 struct rtl8169_private *tp = netdev_priv(dev);
3430 void __iomem *ioaddr = tp->mmio_addr;
3432 if (!netif_running(dev))
3433 goto out_pci_suspend;
3435 netif_device_detach(dev);
3436 netif_stop_queue(dev);
3438 spin_lock_irq(&tp->lock);
3440 rtl8169_asic_down(ioaddr);
3442 rtl8169_rx_missed(dev, ioaddr);
3444 spin_unlock_irq(&tp->lock);
3447 pci_save_state(pdev);
3448 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3449 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3450 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3455 static int rtl8169_resume(struct pci_dev *pdev)
3457 struct net_device *dev = pci_get_drvdata(pdev);
3459 pci_set_power_state(pdev, PCI_D0);
3460 pci_restore_state(pdev);
3461 pci_enable_wake(pdev, PCI_D0, 0);
3463 if (!netif_running(dev))
3466 netif_device_attach(dev);
3468 rtl8169_schedule_work(dev, rtl8169_reset_task);
3473 #endif /* CONFIG_PM */
3475 static struct pci_driver rtl8169_pci_driver = {
3477 .id_table = rtl8169_pci_tbl,
3478 .probe = rtl8169_init_one,
3479 .remove = __devexit_p(rtl8169_remove_one),
3481 .suspend = rtl8169_suspend,
3482 .resume = rtl8169_resume,
3486 static int __init rtl8169_init_module(void)
3488 return pci_register_driver(&rtl8169_pci_driver);
3491 static void __exit rtl8169_cleanup_module(void)
3493 pci_unregister_driver(&rtl8169_pci_driver);
3496 module_init(rtl8169_init_module);
3497 module_exit(rtl8169_cleanup_module);