2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit = 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE = 0x00,
94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126 static const struct {
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130 } rtl_chip_info[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
167 static void rtl_hw_start_8169(struct net_device *);
168 static void rtl_hw_start_8168(struct net_device *);
169 static void rtl_hw_start_8101(struct net_device *);
171 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
190 * we set our copybreak very high so that we don't have
191 * to allocate 16k frames all the time (see note in
194 static int rx_copybreak = 16383;
201 MAC0 = 0, /* Ethernet hardware address. */
203 MAR0 = 8, /* Multicast filter. */
204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
206 TxDescStartAddrLow = 0x20,
207 TxDescStartAddrHigh = 0x24,
208 TxHDescStartAddrLow = 0x28,
209 TxHDescStartAddrHigh = 0x2c,
232 RxDescAddrLow = 0xe4,
233 RxDescAddrHigh = 0xe8,
236 FuncEventMask = 0xf4,
237 FuncPresetState = 0xf8,
238 FuncForceEvent = 0xfc,
241 enum rtl8110_registers {
247 enum rtl8168_8101_registers {
250 #define CSIAR_FLAG 0x80000000
251 #define CSIAR_WRITE_CMD 0x80000000
252 #define CSIAR_BYTE_ENABLE 0x0f
253 #define CSIAR_BYTE_ENABLE_SHIFT 12
254 #define CSIAR_ADDR_MASK 0x0fff
257 #define EPHYAR_FLAG 0x80000000
258 #define EPHYAR_WRITE_CMD 0x80000000
259 #define EPHYAR_REG_MASK 0x1f
260 #define EPHYAR_REG_SHIFT 16
261 #define EPHYAR_DATA_MASK 0xffff
263 #define FIX_NAK_1 (1 << 4)
264 #define FIX_NAK_2 (1 << 3)
266 #define EFUSEAR_FLAG 0x80000000
267 #define EFUSEAR_WRITE_CMD 0x80000000
268 #define EFUSEAR_READ_CMD 0x00000000
269 #define EFUSEAR_REG_MASK 0x03ff
270 #define EFUSEAR_REG_SHIFT 8
271 #define EFUSEAR_DATA_MASK 0xff
274 enum rtl_register_content {
275 /* InterruptStatusBits */
279 TxDescUnavail = 0x0080,
301 /* TXPoll register p.5 */
302 HPQ = 0x80, /* Poll cmd on the high prio queue */
303 NPQ = 0x40, /* Poll cmd on the low prio queue */
304 FSWInt = 0x01, /* Forced software interrupt */
308 Cfg9346_Unlock = 0xc0,
313 AcceptBroadcast = 0x08,
314 AcceptMulticast = 0x04,
316 AcceptAllPhys = 0x01,
323 TxInterFrameGapShift = 24,
324 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
326 /* Config1 register p.24 */
329 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
330 Speed_down = (1 << 4),
334 PMEnable = (1 << 0), /* Power Management Enable */
336 /* Config2 register p. 25 */
337 PCI_Clock_66MHz = 0x01,
338 PCI_Clock_33MHz = 0x00,
340 /* Config3 register p.25 */
341 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
342 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
343 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
345 /* Config5 register p.27 */
346 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
347 MWF = (1 << 5), /* Accept Multicast wakeup frame */
348 UWF = (1 << 4), /* Accept Unicast wakeup frame */
349 LanWake = (1 << 1), /* LanWake enable/disable */
350 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
353 TBIReset = 0x80000000,
354 TBILoopback = 0x40000000,
355 TBINwEnable = 0x20000000,
356 TBINwRestart = 0x10000000,
357 TBILinkOk = 0x02000000,
358 TBINwComplete = 0x01000000,
361 EnableBist = (1 << 15), // 8168 8101
362 Mac_dbgo_oe = (1 << 14), // 8168 8101
363 Normal_mode = (1 << 13), // unused
364 Force_half_dup = (1 << 12), // 8168 8101
365 Force_rxflow_en = (1 << 11), // 8168 8101
366 Force_txflow_en = (1 << 10), // 8168 8101
367 Cxpl_dbg_sel = (1 << 9), // 8168 8101
368 ASF = (1 << 8), // 8168 8101
369 PktCntrDisable = (1 << 7), // 8168 8101
370 Mac_dbgo_sel = 0x001c, // 8168
375 INTT_0 = 0x0000, // 8168
376 INTT_1 = 0x0001, // 8168
377 INTT_2 = 0x0002, // 8168
378 INTT_3 = 0x0003, // 8168
380 /* rtl8169_PHYstatus */
391 TBILinkOK = 0x02000000,
393 /* DumpCounterCommand */
397 enum desc_status_bit {
398 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
399 RingEnd = (1 << 30), /* End of descriptor ring */
400 FirstFrag = (1 << 29), /* First segment of a packet */
401 LastFrag = (1 << 28), /* Final segment of a packet */
404 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
405 MSSShift = 16, /* MSS value position */
406 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
407 IPCS = (1 << 18), /* Calculate IP checksum */
408 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
409 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
410 TxVlanTag = (1 << 17), /* Add VLAN tag */
413 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
414 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
416 #define RxProtoUDP (PID1)
417 #define RxProtoTCP (PID0)
418 #define RxProtoIP (PID1 | PID0)
419 #define RxProtoMask RxProtoIP
421 IPFail = (1 << 16), /* IP checksum failed */
422 UDPFail = (1 << 15), /* UDP/IP checksum failed */
423 TCPFail = (1 << 14), /* TCP/IP checksum failed */
424 RxVlanTag = (1 << 16), /* VLAN tag available */
427 #define RsvdMask 0x3fffc000
444 u8 __pad[sizeof(void *) - sizeof(u32)];
448 RTL_FEATURE_WOL = (1 << 0),
449 RTL_FEATURE_MSI = (1 << 1),
450 RTL_FEATURE_GMII = (1 << 2),
453 struct rtl8169_counters {
460 __le32 tx_one_collision;
461 __le32 tx_multi_collision;
469 struct rtl8169_private {
470 void __iomem *mmio_addr; /* memory map physical address */
471 struct pci_dev *pci_dev; /* Index of PCI device */
472 struct net_device *dev;
473 struct napi_struct napi;
474 spinlock_t lock; /* spin lock flag */
478 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
479 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
482 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
483 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
484 dma_addr_t TxPhyAddr;
485 dma_addr_t RxPhyAddr;
486 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
487 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
490 struct timer_list timer;
495 int phy_1000_ctrl_reg;
496 #ifdef CONFIG_R8169_VLAN
497 struct vlan_group *vlgrp;
499 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
500 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
501 void (*phy_reset_enable)(void __iomem *);
502 void (*hw_start)(struct net_device *);
503 unsigned int (*phy_reset_pending)(void __iomem *);
504 unsigned int (*link_ok)(void __iomem *);
505 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
507 struct delayed_work task;
510 struct mii_if_info mii;
511 struct rtl8169_counters counters;
514 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
515 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
516 module_param(rx_copybreak, int, 0);
517 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
518 module_param(use_dac, int, 0);
519 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
520 module_param_named(debug, debug.msg_enable, int, 0);
521 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
522 MODULE_LICENSE("GPL");
523 MODULE_VERSION(RTL8169_VERSION);
525 static int rtl8169_open(struct net_device *dev);
526 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
527 struct net_device *dev);
528 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
529 static int rtl8169_init_ring(struct net_device *dev);
530 static void rtl_hw_start(struct net_device *dev);
531 static int rtl8169_close(struct net_device *dev);
532 static void rtl_set_rx_mode(struct net_device *dev);
533 static void rtl8169_tx_timeout(struct net_device *dev);
534 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
535 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
536 void __iomem *, u32 budget);
537 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
538 static void rtl8169_down(struct net_device *dev);
539 static void rtl8169_rx_clear(struct rtl8169_private *tp);
540 static int rtl8169_poll(struct napi_struct *napi, int budget);
542 static const unsigned int rtl8169_rx_config =
543 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
545 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
549 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
551 for (i = 20; i > 0; i--) {
553 * Check if the RTL8169 has completed writing to the specified
556 if (!(RTL_R32(PHYAR) & 0x80000000))
562 static int mdio_read(void __iomem *ioaddr, int reg_addr)
566 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
568 for (i = 20; i > 0; i--) {
570 * Check if the RTL8169 has completed retrieving data from
571 * the specified MII register.
573 if (RTL_R32(PHYAR) & 0x80000000) {
574 value = RTL_R32(PHYAR) & 0xffff;
582 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
584 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
587 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
591 val = mdio_read(ioaddr, reg_addr);
592 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
595 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
598 struct rtl8169_private *tp = netdev_priv(dev);
599 void __iomem *ioaddr = tp->mmio_addr;
601 mdio_write(ioaddr, location, val);
604 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
606 struct rtl8169_private *tp = netdev_priv(dev);
607 void __iomem *ioaddr = tp->mmio_addr;
609 return mdio_read(ioaddr, location);
612 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
616 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
617 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
619 for (i = 0; i < 100; i++) {
620 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
626 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
631 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
633 for (i = 0; i < 100; i++) {
634 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
635 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
644 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
648 RTL_W32(CSIDR, value);
649 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
650 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
652 for (i = 0; i < 100; i++) {
653 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
659 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
664 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
665 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
667 for (i = 0; i < 100; i++) {
668 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
669 value = RTL_R32(CSIDR);
678 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
683 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
685 for (i = 0; i < 300; i++) {
686 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
687 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
696 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
698 RTL_W16(IntrMask, 0x0000);
700 RTL_W16(IntrStatus, 0xffff);
703 static void rtl8169_asic_down(void __iomem *ioaddr)
705 RTL_W8(ChipCmd, 0x00);
706 rtl8169_irq_mask_and_ack(ioaddr);
710 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
712 return RTL_R32(TBICSR) & TBIReset;
715 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
717 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
720 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
722 return RTL_R32(TBICSR) & TBILinkOk;
725 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
727 return RTL_R8(PHYstatus) & LinkStatus;
730 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
732 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
735 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
739 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
740 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
743 static void rtl8169_check_link_status(struct net_device *dev,
744 struct rtl8169_private *tp,
745 void __iomem *ioaddr)
749 spin_lock_irqsave(&tp->lock, flags);
750 if (tp->link_ok(ioaddr)) {
751 netif_carrier_on(dev);
752 netif_info(tp, ifup, dev, "link up\n");
754 netif_carrier_off(dev);
755 netif_info(tp, ifdown, dev, "link down\n");
757 spin_unlock_irqrestore(&tp->lock, flags);
760 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
762 struct rtl8169_private *tp = netdev_priv(dev);
763 void __iomem *ioaddr = tp->mmio_addr;
768 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
769 wol->supported = WAKE_ANY;
771 spin_lock_irq(&tp->lock);
773 options = RTL_R8(Config1);
774 if (!(options & PMEnable))
777 options = RTL_R8(Config3);
778 if (options & LinkUp)
779 wol->wolopts |= WAKE_PHY;
780 if (options & MagicPacket)
781 wol->wolopts |= WAKE_MAGIC;
783 options = RTL_R8(Config5);
785 wol->wolopts |= WAKE_UCAST;
787 wol->wolopts |= WAKE_BCAST;
789 wol->wolopts |= WAKE_MCAST;
792 spin_unlock_irq(&tp->lock);
795 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
797 struct rtl8169_private *tp = netdev_priv(dev);
798 void __iomem *ioaddr = tp->mmio_addr;
800 static const struct {
805 { WAKE_ANY, Config1, PMEnable },
806 { WAKE_PHY, Config3, LinkUp },
807 { WAKE_MAGIC, Config3, MagicPacket },
808 { WAKE_UCAST, Config5, UWF },
809 { WAKE_BCAST, Config5, BWF },
810 { WAKE_MCAST, Config5, MWF },
811 { WAKE_ANY, Config5, LanWake }
814 spin_lock_irq(&tp->lock);
816 RTL_W8(Cfg9346, Cfg9346_Unlock);
818 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
819 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
820 if (wol->wolopts & cfg[i].opt)
821 options |= cfg[i].mask;
822 RTL_W8(cfg[i].reg, options);
825 RTL_W8(Cfg9346, Cfg9346_Lock);
828 tp->features |= RTL_FEATURE_WOL;
830 tp->features &= ~RTL_FEATURE_WOL;
831 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
833 spin_unlock_irq(&tp->lock);
838 static void rtl8169_get_drvinfo(struct net_device *dev,
839 struct ethtool_drvinfo *info)
841 struct rtl8169_private *tp = netdev_priv(dev);
843 strcpy(info->driver, MODULENAME);
844 strcpy(info->version, RTL8169_VERSION);
845 strcpy(info->bus_info, pci_name(tp->pci_dev));
848 static int rtl8169_get_regs_len(struct net_device *dev)
850 return R8169_REGS_SIZE;
853 static int rtl8169_set_speed_tbi(struct net_device *dev,
854 u8 autoneg, u16 speed, u8 duplex)
856 struct rtl8169_private *tp = netdev_priv(dev);
857 void __iomem *ioaddr = tp->mmio_addr;
861 reg = RTL_R32(TBICSR);
862 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
863 (duplex == DUPLEX_FULL)) {
864 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
865 } else if (autoneg == AUTONEG_ENABLE)
866 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
868 netif_warn(tp, link, dev,
869 "incorrect speed setting refused in TBI mode\n");
876 static int rtl8169_set_speed_xmii(struct net_device *dev,
877 u8 autoneg, u16 speed, u8 duplex)
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
883 if (autoneg == AUTONEG_ENABLE) {
886 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
887 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888 ADVERTISE_100HALF | ADVERTISE_100FULL);
889 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
891 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
894 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
905 netif_info(tp, link, dev,
906 "PHY does not support 1000Mbps\n");
909 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
916 * Vendor specific (0x1f) and reserved (0x0e) MII
919 mdio_write(ioaddr, 0x1f, 0x0000);
920 mdio_write(ioaddr, 0x0e, 0x0000);
923 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
928 if (speed == SPEED_10)
930 else if (speed == SPEED_100)
931 bmcr = BMCR_SPEED100;
935 if (duplex == DUPLEX_FULL)
936 bmcr |= BMCR_FULLDPLX;
938 mdio_write(ioaddr, 0x1f, 0x0000);
941 tp->phy_1000_ctrl_reg = giga_ctrl;
943 mdio_write(ioaddr, MII_BMCR, bmcr);
945 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948 mdio_write(ioaddr, 0x17, 0x2138);
949 mdio_write(ioaddr, 0x0e, 0x0260);
951 mdio_write(ioaddr, 0x17, 0x2108);
952 mdio_write(ioaddr, 0x0e, 0x0000);
959 static int rtl8169_set_speed(struct net_device *dev,
960 u8 autoneg, u16 speed, u8 duplex)
962 struct rtl8169_private *tp = netdev_priv(dev);
965 ret = tp->set_speed(dev, autoneg, speed, duplex);
967 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
968 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
973 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
975 struct rtl8169_private *tp = netdev_priv(dev);
979 spin_lock_irqsave(&tp->lock, flags);
980 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981 spin_unlock_irqrestore(&tp->lock, flags);
986 static u32 rtl8169_get_rx_csum(struct net_device *dev)
988 struct rtl8169_private *tp = netdev_priv(dev);
990 return tp->cp_cmd & RxChkSum;
993 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
999 spin_lock_irqsave(&tp->lock, flags);
1002 tp->cp_cmd |= RxChkSum;
1004 tp->cp_cmd &= ~RxChkSum;
1006 RTL_W16(CPlusCmd, tp->cp_cmd);
1009 spin_unlock_irqrestore(&tp->lock, flags);
1014 #ifdef CONFIG_R8169_VLAN
1016 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017 struct sk_buff *skb)
1019 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1023 static void rtl8169_vlan_rx_register(struct net_device *dev,
1024 struct vlan_group *grp)
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027 void __iomem *ioaddr = tp->mmio_addr;
1028 unsigned long flags;
1030 spin_lock_irqsave(&tp->lock, flags);
1033 * Do not disable RxVlan on 8110SCd.
1035 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1036 tp->cp_cmd |= RxVlan;
1038 tp->cp_cmd &= ~RxVlan;
1039 RTL_W16(CPlusCmd, tp->cp_cmd);
1041 spin_unlock_irqrestore(&tp->lock, flags);
1044 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1045 struct sk_buff *skb)
1047 u32 opts2 = le32_to_cpu(desc->opts2);
1048 struct vlan_group *vlgrp = tp->vlgrp;
1051 if (vlgrp && (opts2 & RxVlanTag)) {
1052 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1060 #else /* !CONFIG_R8169_VLAN */
1062 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1063 struct sk_buff *skb)
1068 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1069 struct sk_buff *skb)
1076 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1078 struct rtl8169_private *tp = netdev_priv(dev);
1079 void __iomem *ioaddr = tp->mmio_addr;
1083 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1084 cmd->port = PORT_FIBRE;
1085 cmd->transceiver = XCVR_INTERNAL;
1087 status = RTL_R32(TBICSR);
1088 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1089 cmd->autoneg = !!(status & TBINwEnable);
1091 cmd->speed = SPEED_1000;
1092 cmd->duplex = DUPLEX_FULL; /* Always set */
1097 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1099 struct rtl8169_private *tp = netdev_priv(dev);
1101 return mii_ethtool_gset(&tp->mii, cmd);
1104 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1106 struct rtl8169_private *tp = netdev_priv(dev);
1107 unsigned long flags;
1110 spin_lock_irqsave(&tp->lock, flags);
1112 rc = tp->get_settings(dev, cmd);
1114 spin_unlock_irqrestore(&tp->lock, flags);
1118 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 unsigned long flags;
1124 if (regs->len > R8169_REGS_SIZE)
1125 regs->len = R8169_REGS_SIZE;
1127 spin_lock_irqsave(&tp->lock, flags);
1128 memcpy_fromio(p, tp->mmio_addr, regs->len);
1129 spin_unlock_irqrestore(&tp->lock, flags);
1132 static u32 rtl8169_get_msglevel(struct net_device *dev)
1134 struct rtl8169_private *tp = netdev_priv(dev);
1136 return tp->msg_enable;
1139 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1141 struct rtl8169_private *tp = netdev_priv(dev);
1143 tp->msg_enable = value;
1146 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1153 "tx_single_collisions",
1154 "tx_multi_collisions",
1162 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1166 return ARRAY_SIZE(rtl8169_gstrings);
1172 static void rtl8169_update_counters(struct net_device *dev)
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175 void __iomem *ioaddr = tp->mmio_addr;
1176 struct rtl8169_counters *counters;
1182 * Some chips are unable to dump tally counters when the receiver
1185 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1188 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1192 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1193 cmd = (u64)paddr & DMA_BIT_MASK(32);
1194 RTL_W32(CounterAddrLow, cmd);
1195 RTL_W32(CounterAddrLow, cmd | CounterDump);
1198 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1199 /* copy updated counters */
1200 memcpy(&tp->counters, counters, sizeof(*counters));
1206 RTL_W32(CounterAddrLow, 0);
1207 RTL_W32(CounterAddrHigh, 0);
1209 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1212 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1213 struct ethtool_stats *stats, u64 *data)
1215 struct rtl8169_private *tp = netdev_priv(dev);
1219 rtl8169_update_counters(dev);
1221 data[0] = le64_to_cpu(tp->counters.tx_packets);
1222 data[1] = le64_to_cpu(tp->counters.rx_packets);
1223 data[2] = le64_to_cpu(tp->counters.tx_errors);
1224 data[3] = le32_to_cpu(tp->counters.rx_errors);
1225 data[4] = le16_to_cpu(tp->counters.rx_missed);
1226 data[5] = le16_to_cpu(tp->counters.align_errors);
1227 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1228 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1229 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1230 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1231 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1232 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1233 data[12] = le16_to_cpu(tp->counters.tx_underun);
1236 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1240 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1245 static const struct ethtool_ops rtl8169_ethtool_ops = {
1246 .get_drvinfo = rtl8169_get_drvinfo,
1247 .get_regs_len = rtl8169_get_regs_len,
1248 .get_link = ethtool_op_get_link,
1249 .get_settings = rtl8169_get_settings,
1250 .set_settings = rtl8169_set_settings,
1251 .get_msglevel = rtl8169_get_msglevel,
1252 .set_msglevel = rtl8169_set_msglevel,
1253 .get_rx_csum = rtl8169_get_rx_csum,
1254 .set_rx_csum = rtl8169_set_rx_csum,
1255 .set_tx_csum = ethtool_op_set_tx_csum,
1256 .set_sg = ethtool_op_set_sg,
1257 .set_tso = ethtool_op_set_tso,
1258 .get_regs = rtl8169_get_regs,
1259 .get_wol = rtl8169_get_wol,
1260 .set_wol = rtl8169_set_wol,
1261 .get_strings = rtl8169_get_strings,
1262 .get_sset_count = rtl8169_get_sset_count,
1263 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1266 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1267 void __iomem *ioaddr)
1270 * The driver currently handles the 8168Bf and the 8168Be identically
1271 * but they can be identified more specifically through the test below
1274 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1276 * Same thing for the 8101Eb and the 8101Ec:
1278 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1280 static const struct {
1286 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1287 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1288 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1289 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1292 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1293 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1294 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1295 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1296 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1297 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1298 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1299 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1300 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1303 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1304 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1305 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1306 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1309 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1310 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1311 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1312 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1313 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1314 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1315 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1316 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1317 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1318 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1319 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1320 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1321 /* FIXME: where did these entries come from ? -- FR */
1322 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1323 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1326 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1327 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1328 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1329 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1330 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1331 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1334 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1338 reg = RTL_R32(TxConfig);
1339 while ((reg & p->mask) != p->val)
1341 tp->mac_version = p->mac_version;
1344 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1346 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1354 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1357 mdio_write(ioaddr, regs->reg, regs->val);
1362 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1364 static const struct phy_reg phy_reg_init[] = {
1426 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1429 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1431 static const struct phy_reg phy_reg_init[] = {
1437 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1440 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1441 void __iomem *ioaddr)
1443 struct pci_dev *pdev = tp->pci_dev;
1444 u16 vendor_id, device_id;
1446 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1447 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1449 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1452 mdio_write(ioaddr, 0x1f, 0x0001);
1453 mdio_write(ioaddr, 0x10, 0xf01b);
1454 mdio_write(ioaddr, 0x1f, 0x0000);
1457 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1458 void __iomem *ioaddr)
1460 static const struct phy_reg phy_reg_init[] = {
1500 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1502 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1505 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1507 static const struct phy_reg phy_reg_init[] = {
1555 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1558 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1560 static const struct phy_reg phy_reg_init[] = {
1565 mdio_write(ioaddr, 0x1f, 0x0001);
1566 mdio_patch(ioaddr, 0x16, 1 << 0);
1568 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1571 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1573 static const struct phy_reg phy_reg_init[] = {
1579 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1582 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1584 static const struct phy_reg phy_reg_init[] = {
1592 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1595 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1597 static const struct phy_reg phy_reg_init[] = {
1603 mdio_write(ioaddr, 0x1f, 0x0000);
1604 mdio_patch(ioaddr, 0x14, 1 << 5);
1605 mdio_patch(ioaddr, 0x0d, 1 << 5);
1607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1610 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1612 static const struct phy_reg phy_reg_init[] = {
1632 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1634 mdio_patch(ioaddr, 0x14, 1 << 5);
1635 mdio_patch(ioaddr, 0x0d, 1 << 5);
1636 mdio_write(ioaddr, 0x1f, 0x0000);
1639 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1641 static const struct phy_reg phy_reg_init[] = {
1659 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1661 mdio_patch(ioaddr, 0x16, 1 << 0);
1662 mdio_patch(ioaddr, 0x14, 1 << 5);
1663 mdio_patch(ioaddr, 0x0d, 1 << 5);
1664 mdio_write(ioaddr, 0x1f, 0x0000);
1667 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1669 static const struct phy_reg phy_reg_init[] = {
1681 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1683 mdio_patch(ioaddr, 0x16, 1 << 0);
1684 mdio_patch(ioaddr, 0x14, 1 << 5);
1685 mdio_patch(ioaddr, 0x0d, 1 << 5);
1686 mdio_write(ioaddr, 0x1f, 0x0000);
1689 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1691 rtl8168c_3_hw_phy_config(ioaddr);
1694 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1696 static const struct phy_reg phy_reg_init_0[] = {
1715 static const struct phy_reg phy_reg_init_1[] = {
1722 static const struct phy_reg phy_reg_init_2[] = {
2078 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2080 mdio_write(ioaddr, 0x1f, 0x0002);
2081 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2082 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2084 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2086 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2087 static const struct phy_reg phy_reg_init[] = {
2097 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2099 val = mdio_read(ioaddr, 0x0d);
2101 if ((val & 0x00ff) != 0x006c) {
2102 static const u32 set[] = {
2103 0x0065, 0x0066, 0x0067, 0x0068,
2104 0x0069, 0x006a, 0x006b, 0x006c
2108 mdio_write(ioaddr, 0x1f, 0x0002);
2111 for (i = 0; i < ARRAY_SIZE(set); i++)
2112 mdio_write(ioaddr, 0x0d, val | set[i]);
2115 static const struct phy_reg phy_reg_init[] = {
2123 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2126 mdio_write(ioaddr, 0x1f, 0x0002);
2127 mdio_patch(ioaddr, 0x0d, 0x0300);
2128 mdio_patch(ioaddr, 0x0f, 0x0010);
2130 mdio_write(ioaddr, 0x1f, 0x0002);
2131 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2132 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2134 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2137 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2139 static const struct phy_reg phy_reg_init_0[] = {
2164 static const struct phy_reg phy_reg_init_1[] = {
2477 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2479 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2480 static const struct phy_reg phy_reg_init[] = {
2491 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2493 val = mdio_read(ioaddr, 0x0d);
2494 if ((val & 0x00ff) != 0x006c) {
2496 0x0065, 0x0066, 0x0067, 0x0068,
2497 0x0069, 0x006a, 0x006b, 0x006c
2501 mdio_write(ioaddr, 0x1f, 0x0002);
2504 for (i = 0; i < ARRAY_SIZE(set); i++)
2505 mdio_write(ioaddr, 0x0d, val | set[i]);
2508 static const struct phy_reg phy_reg_init[] = {
2516 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2519 mdio_write(ioaddr, 0x1f, 0x0002);
2520 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2521 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2523 mdio_write(ioaddr, 0x1f, 0x0001);
2524 mdio_write(ioaddr, 0x17, 0x0cc0);
2526 mdio_write(ioaddr, 0x1f, 0x0002);
2527 mdio_patch(ioaddr, 0x0f, 0x0017);
2529 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2532 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2534 static const struct phy_reg phy_reg_init[] = {
2590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2595 static const struct phy_reg phy_reg_init[] = {
2602 mdio_write(ioaddr, 0x1f, 0x0000);
2603 mdio_patch(ioaddr, 0x11, 1 << 12);
2604 mdio_patch(ioaddr, 0x19, 1 << 13);
2605 mdio_patch(ioaddr, 0x10, 1 << 15);
2607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2610 static void rtl_hw_phy_config(struct net_device *dev)
2612 struct rtl8169_private *tp = netdev_priv(dev);
2613 void __iomem *ioaddr = tp->mmio_addr;
2615 rtl8169_print_mac_version(tp);
2617 switch (tp->mac_version) {
2618 case RTL_GIGA_MAC_VER_01:
2620 case RTL_GIGA_MAC_VER_02:
2621 case RTL_GIGA_MAC_VER_03:
2622 rtl8169s_hw_phy_config(ioaddr);
2624 case RTL_GIGA_MAC_VER_04:
2625 rtl8169sb_hw_phy_config(ioaddr);
2627 case RTL_GIGA_MAC_VER_05:
2628 rtl8169scd_hw_phy_config(tp, ioaddr);
2630 case RTL_GIGA_MAC_VER_06:
2631 rtl8169sce_hw_phy_config(ioaddr);
2633 case RTL_GIGA_MAC_VER_07:
2634 case RTL_GIGA_MAC_VER_08:
2635 case RTL_GIGA_MAC_VER_09:
2636 rtl8102e_hw_phy_config(ioaddr);
2638 case RTL_GIGA_MAC_VER_11:
2639 rtl8168bb_hw_phy_config(ioaddr);
2641 case RTL_GIGA_MAC_VER_12:
2642 rtl8168bef_hw_phy_config(ioaddr);
2644 case RTL_GIGA_MAC_VER_17:
2645 rtl8168bef_hw_phy_config(ioaddr);
2647 case RTL_GIGA_MAC_VER_18:
2648 rtl8168cp_1_hw_phy_config(ioaddr);
2650 case RTL_GIGA_MAC_VER_19:
2651 rtl8168c_1_hw_phy_config(ioaddr);
2653 case RTL_GIGA_MAC_VER_20:
2654 rtl8168c_2_hw_phy_config(ioaddr);
2656 case RTL_GIGA_MAC_VER_21:
2657 rtl8168c_3_hw_phy_config(ioaddr);
2659 case RTL_GIGA_MAC_VER_22:
2660 rtl8168c_4_hw_phy_config(ioaddr);
2662 case RTL_GIGA_MAC_VER_23:
2663 case RTL_GIGA_MAC_VER_24:
2664 rtl8168cp_2_hw_phy_config(ioaddr);
2666 case RTL_GIGA_MAC_VER_25:
2667 rtl8168d_1_hw_phy_config(ioaddr);
2669 case RTL_GIGA_MAC_VER_26:
2670 rtl8168d_2_hw_phy_config(ioaddr);
2672 case RTL_GIGA_MAC_VER_27:
2673 rtl8168d_3_hw_phy_config(ioaddr);
2681 static void rtl8169_phy_timer(unsigned long __opaque)
2683 struct net_device *dev = (struct net_device *)__opaque;
2684 struct rtl8169_private *tp = netdev_priv(dev);
2685 struct timer_list *timer = &tp->timer;
2686 void __iomem *ioaddr = tp->mmio_addr;
2687 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2689 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2691 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2694 spin_lock_irq(&tp->lock);
2696 if (tp->phy_reset_pending(ioaddr)) {
2698 * A busy loop could burn quite a few cycles on nowadays CPU.
2699 * Let's delay the execution of the timer for a few ticks.
2705 if (tp->link_ok(ioaddr))
2708 netif_warn(tp, link, dev, "PHY reset until link up\n");
2710 tp->phy_reset_enable(ioaddr);
2713 mod_timer(timer, jiffies + timeout);
2715 spin_unlock_irq(&tp->lock);
2718 static inline void rtl8169_delete_timer(struct net_device *dev)
2720 struct rtl8169_private *tp = netdev_priv(dev);
2721 struct timer_list *timer = &tp->timer;
2723 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2726 del_timer_sync(timer);
2729 static inline void rtl8169_request_timer(struct net_device *dev)
2731 struct rtl8169_private *tp = netdev_priv(dev);
2732 struct timer_list *timer = &tp->timer;
2734 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2737 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2740 #ifdef CONFIG_NET_POLL_CONTROLLER
2742 * Polling 'interrupt' - used by things like netconsole to send skbs
2743 * without having to re-enable interrupts. It's not called while
2744 * the interrupt routine is executing.
2746 static void rtl8169_netpoll(struct net_device *dev)
2748 struct rtl8169_private *tp = netdev_priv(dev);
2749 struct pci_dev *pdev = tp->pci_dev;
2751 disable_irq(pdev->irq);
2752 rtl8169_interrupt(pdev->irq, dev);
2753 enable_irq(pdev->irq);
2757 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2758 void __iomem *ioaddr)
2761 pci_release_regions(pdev);
2762 pci_disable_device(pdev);
2766 static void rtl8169_phy_reset(struct net_device *dev,
2767 struct rtl8169_private *tp)
2769 void __iomem *ioaddr = tp->mmio_addr;
2772 tp->phy_reset_enable(ioaddr);
2773 for (i = 0; i < 100; i++) {
2774 if (!tp->phy_reset_pending(ioaddr))
2778 netif_err(tp, link, dev, "PHY reset failed\n");
2781 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2783 void __iomem *ioaddr = tp->mmio_addr;
2785 rtl_hw_phy_config(dev);
2787 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2788 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2792 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2794 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2795 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2797 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2798 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2800 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2801 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2804 rtl8169_phy_reset(dev, tp);
2807 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2808 * only 8101. Don't panic.
2810 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2812 if (RTL_R8(PHYstatus) & TBI_Enable)
2813 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2816 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2818 void __iomem *ioaddr = tp->mmio_addr;
2822 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2823 high = addr[4] | (addr[5] << 8);
2825 spin_lock_irq(&tp->lock);
2827 RTL_W8(Cfg9346, Cfg9346_Unlock);
2828 RTL_W32(MAC4, high);
2830 RTL_W8(Cfg9346, Cfg9346_Lock);
2832 spin_unlock_irq(&tp->lock);
2835 static int rtl_set_mac_address(struct net_device *dev, void *p)
2837 struct rtl8169_private *tp = netdev_priv(dev);
2838 struct sockaddr *addr = p;
2840 if (!is_valid_ether_addr(addr->sa_data))
2841 return -EADDRNOTAVAIL;
2843 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2845 rtl_rar_set(tp, dev->dev_addr);
2850 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2852 struct rtl8169_private *tp = netdev_priv(dev);
2853 struct mii_ioctl_data *data = if_mii(ifr);
2855 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2858 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2862 data->phy_id = 32; /* Internal PHY */
2866 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2870 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2876 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2881 static const struct rtl_cfg_info {
2882 void (*hw_start)(struct net_device *);
2883 unsigned int region;
2889 } rtl_cfg_infos [] = {
2891 .hw_start = rtl_hw_start_8169,
2894 .intr_event = SYSErr | LinkChg | RxOverflow |
2895 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2896 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2897 .features = RTL_FEATURE_GMII,
2898 .default_ver = RTL_GIGA_MAC_VER_01,
2901 .hw_start = rtl_hw_start_8168,
2904 .intr_event = SYSErr | LinkChg | RxOverflow |
2905 TxErr | TxOK | RxOK | RxErr,
2906 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2907 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2908 .default_ver = RTL_GIGA_MAC_VER_11,
2911 .hw_start = rtl_hw_start_8101,
2914 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2915 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2916 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2917 .features = RTL_FEATURE_MSI,
2918 .default_ver = RTL_GIGA_MAC_VER_13,
2922 /* Cfg9346_Unlock assumed. */
2923 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2924 const struct rtl_cfg_info *cfg)
2929 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2930 if (cfg->features & RTL_FEATURE_MSI) {
2931 if (pci_enable_msi(pdev)) {
2932 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2935 msi = RTL_FEATURE_MSI;
2938 RTL_W8(Config2, cfg2);
2942 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2944 if (tp->features & RTL_FEATURE_MSI) {
2945 pci_disable_msi(pdev);
2946 tp->features &= ~RTL_FEATURE_MSI;
2950 static const struct net_device_ops rtl8169_netdev_ops = {
2951 .ndo_open = rtl8169_open,
2952 .ndo_stop = rtl8169_close,
2953 .ndo_get_stats = rtl8169_get_stats,
2954 .ndo_start_xmit = rtl8169_start_xmit,
2955 .ndo_tx_timeout = rtl8169_tx_timeout,
2956 .ndo_validate_addr = eth_validate_addr,
2957 .ndo_change_mtu = rtl8169_change_mtu,
2958 .ndo_set_mac_address = rtl_set_mac_address,
2959 .ndo_do_ioctl = rtl8169_ioctl,
2960 .ndo_set_multicast_list = rtl_set_rx_mode,
2961 #ifdef CONFIG_R8169_VLAN
2962 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2964 #ifdef CONFIG_NET_POLL_CONTROLLER
2965 .ndo_poll_controller = rtl8169_netpoll,
2970 static int __devinit
2971 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2973 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2974 const unsigned int region = cfg->region;
2975 struct rtl8169_private *tp;
2976 struct mii_if_info *mii;
2977 struct net_device *dev;
2978 void __iomem *ioaddr;
2982 if (netif_msg_drv(&debug)) {
2983 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2984 MODULENAME, RTL8169_VERSION);
2987 dev = alloc_etherdev(sizeof (*tp));
2989 if (netif_msg_drv(&debug))
2990 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2995 SET_NETDEV_DEV(dev, &pdev->dev);
2996 dev->netdev_ops = &rtl8169_netdev_ops;
2997 tp = netdev_priv(dev);
3000 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3004 mii->mdio_read = rtl_mdio_read;
3005 mii->mdio_write = rtl_mdio_write;
3006 mii->phy_id_mask = 0x1f;
3007 mii->reg_num_mask = 0x1f;
3008 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3010 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3011 rc = pci_enable_device(pdev);
3013 netif_err(tp, probe, dev, "enable failure\n");
3014 goto err_out_free_dev_1;
3017 rc = pci_set_mwi(pdev);
3019 goto err_out_disable_2;
3021 /* make sure PCI base addr 1 is MMIO */
3022 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3023 netif_err(tp, probe, dev,
3024 "region #%d not an MMIO resource, aborting\n",
3030 /* check for weird/broken PCI region reporting */
3031 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3032 netif_err(tp, probe, dev,
3033 "Invalid PCI region size(s), aborting\n");
3038 rc = pci_request_regions(pdev, MODULENAME);
3040 netif_err(tp, probe, dev, "could not request regions\n");
3044 tp->cp_cmd = PCIMulRW | RxChkSum;
3046 if ((sizeof(dma_addr_t) > 4) &&
3047 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3048 tp->cp_cmd |= PCIDAC;
3049 dev->features |= NETIF_F_HIGHDMA;
3051 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3053 netif_err(tp, probe, dev, "DMA configuration failed\n");
3054 goto err_out_free_res_4;
3058 /* ioremap MMIO region */
3059 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3061 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3063 goto err_out_free_res_4;
3066 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3068 netif_info(tp, probe, dev, "no PCI Express capability\n");
3070 RTL_W16(IntrMask, 0x0000);
3072 /* Soft reset the chip. */
3073 RTL_W8(ChipCmd, CmdReset);
3075 /* Check that the chip has finished the reset. */
3076 for (i = 0; i < 100; i++) {
3077 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3079 msleep_interruptible(1);
3082 RTL_W16(IntrStatus, 0xffff);
3084 pci_set_master(pdev);
3086 /* Identify chip attached to board */
3087 rtl8169_get_mac_version(tp, ioaddr);
3089 /* Use appropriate default if unknown */
3090 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3091 netif_notice(tp, probe, dev,
3092 "unknown MAC, using family default\n");
3093 tp->mac_version = cfg->default_ver;
3096 rtl8169_print_mac_version(tp);
3098 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3099 if (tp->mac_version == rtl_chip_info[i].mac_version)
3102 if (i == ARRAY_SIZE(rtl_chip_info)) {
3104 "driver bug, MAC version not found in rtl_chip_info\n");
3109 RTL_W8(Cfg9346, Cfg9346_Unlock);
3110 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3111 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3112 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3113 tp->features |= RTL_FEATURE_WOL;
3114 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3115 tp->features |= RTL_FEATURE_WOL;
3116 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3117 RTL_W8(Cfg9346, Cfg9346_Lock);
3119 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3120 (RTL_R8(PHYstatus) & TBI_Enable)) {
3121 tp->set_speed = rtl8169_set_speed_tbi;
3122 tp->get_settings = rtl8169_gset_tbi;
3123 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3124 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3125 tp->link_ok = rtl8169_tbi_link_ok;
3126 tp->do_ioctl = rtl_tbi_ioctl;
3128 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3130 tp->set_speed = rtl8169_set_speed_xmii;
3131 tp->get_settings = rtl8169_gset_xmii;
3132 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3133 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3134 tp->link_ok = rtl8169_xmii_link_ok;
3135 tp->do_ioctl = rtl_xmii_ioctl;
3138 spin_lock_init(&tp->lock);
3140 tp->mmio_addr = ioaddr;
3142 /* Get MAC address */
3143 for (i = 0; i < MAC_ADDR_LEN; i++)
3144 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3145 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3147 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3148 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3149 dev->irq = pdev->irq;
3150 dev->base_addr = (unsigned long) ioaddr;
3152 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3154 #ifdef CONFIG_R8169_VLAN
3155 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3158 tp->intr_mask = 0xffff;
3159 tp->align = cfg->align;
3160 tp->hw_start = cfg->hw_start;
3161 tp->intr_event = cfg->intr_event;
3162 tp->napi_event = cfg->napi_event;
3164 init_timer(&tp->timer);
3165 tp->timer.data = (unsigned long) dev;
3166 tp->timer.function = rtl8169_phy_timer;
3168 rc = register_netdev(dev);
3172 pci_set_drvdata(pdev, dev);
3174 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3175 rtl_chip_info[tp->chipset].name,
3176 dev->base_addr, dev->dev_addr,
3177 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3179 rtl8169_init_phy(dev, tp);
3182 * Pretend we are using VLANs; This bypasses a nasty bug where
3183 * Interrupts stop flowing on high load on 8110SCd controllers.
3185 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3186 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3188 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3194 rtl_disable_msi(pdev, tp);
3197 pci_release_regions(pdev);
3199 pci_clear_mwi(pdev);
3201 pci_disable_device(pdev);
3207 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3209 struct net_device *dev = pci_get_drvdata(pdev);
3210 struct rtl8169_private *tp = netdev_priv(dev);
3212 flush_scheduled_work();
3214 unregister_netdev(dev);
3216 /* restore original MAC address */
3217 rtl_rar_set(tp, dev->perm_addr);
3219 rtl_disable_msi(pdev, tp);
3220 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3221 pci_set_drvdata(pdev, NULL);
3224 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3227 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3229 if (max_frame != 16383)
3230 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3231 "NIC may lead to frame reception errors!\n");
3233 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3236 static int rtl8169_open(struct net_device *dev)
3238 struct rtl8169_private *tp = netdev_priv(dev);
3239 struct pci_dev *pdev = tp->pci_dev;
3240 int retval = -ENOMEM;
3244 * Note that we use a magic value here, its wierd I know
3245 * its done because, some subset of rtl8169 hardware suffers from
3246 * a problem in which frames received that are longer than
3247 * the size set in RxMaxSize register return garbage sizes
3248 * when received. To avoid this we need to turn off filtering,
3249 * which is done by setting a value of 16383 in the RxMaxSize register
3250 * and allocating 16k frames to handle the largest possible rx value
3251 * thats what the magic math below does.
3253 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3256 * Rx and Tx desscriptors needs 256 bytes alignment.
3257 * pci_alloc_consistent provides more.
3259 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3261 if (!tp->TxDescArray)
3264 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3266 if (!tp->RxDescArray)
3269 retval = rtl8169_init_ring(dev);
3273 INIT_DELAYED_WORK(&tp->task, NULL);
3277 retval = request_irq(dev->irq, rtl8169_interrupt,
3278 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3281 goto err_release_ring_2;
3283 napi_enable(&tp->napi);
3287 rtl8169_request_timer(dev);
3289 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3294 rtl8169_rx_clear(tp);
3296 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3299 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3304 static void rtl8169_hw_reset(void __iomem *ioaddr)
3306 /* Disable interrupts */
3307 rtl8169_irq_mask_and_ack(ioaddr);
3309 /* Reset the chipset */
3310 RTL_W8(ChipCmd, CmdReset);
3316 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3318 void __iomem *ioaddr = tp->mmio_addr;
3319 u32 cfg = rtl8169_rx_config;
3321 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3322 RTL_W32(RxConfig, cfg);
3324 /* Set DMA burst size and Interframe Gap Time */
3325 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3326 (InterFrameGap << TxInterFrameGapShift));
3329 static void rtl_hw_start(struct net_device *dev)
3331 struct rtl8169_private *tp = netdev_priv(dev);
3332 void __iomem *ioaddr = tp->mmio_addr;
3335 /* Soft reset the chip. */
3336 RTL_W8(ChipCmd, CmdReset);
3338 /* Check that the chip has finished the reset. */
3339 for (i = 0; i < 100; i++) {
3340 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3342 msleep_interruptible(1);
3347 netif_start_queue(dev);
3351 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3352 void __iomem *ioaddr)
3355 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3356 * register to be written before TxDescAddrLow to work.
3357 * Switching from MMIO to I/O access fixes the issue as well.
3359 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3360 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3361 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3362 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3365 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3369 cmd = RTL_R16(CPlusCmd);
3370 RTL_W16(CPlusCmd, cmd);
3374 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3376 /* Low hurts. Let's disable the filtering. */
3377 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3380 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3382 static const struct {
3387 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3388 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3389 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3390 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3395 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3396 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3397 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3398 RTL_W32(0x7c, p->val);
3404 static void rtl_hw_start_8169(struct net_device *dev)
3406 struct rtl8169_private *tp = netdev_priv(dev);
3407 void __iomem *ioaddr = tp->mmio_addr;
3408 struct pci_dev *pdev = tp->pci_dev;
3410 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3411 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3412 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3415 RTL_W8(Cfg9346, Cfg9346_Unlock);
3416 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3417 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3418 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3419 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3420 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3422 RTL_W8(EarlyTxThres, EarlyTxThld);
3424 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3426 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3427 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3428 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3429 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3430 rtl_set_rx_tx_config_registers(tp);
3432 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3434 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3435 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3436 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3437 "Bit-3 and bit-14 MUST be 1\n");
3438 tp->cp_cmd |= (1 << 14);
3441 RTL_W16(CPlusCmd, tp->cp_cmd);
3443 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3446 * Undocumented corner. Supposedly:
3447 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3449 RTL_W16(IntrMitigate, 0x0000);
3451 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3453 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3454 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3455 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3456 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3457 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3458 rtl_set_rx_tx_config_registers(tp);
3461 RTL_W8(Cfg9346, Cfg9346_Lock);
3463 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3466 RTL_W32(RxMissed, 0);
3468 rtl_set_rx_mode(dev);
3470 /* no early-rx interrupts */
3471 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3473 /* Enable all known interrupts by setting the interrupt mask. */
3474 RTL_W16(IntrMask, tp->intr_event);
3477 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3479 struct net_device *dev = pci_get_drvdata(pdev);
3480 struct rtl8169_private *tp = netdev_priv(dev);
3481 int cap = tp->pcie_cap;
3486 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3487 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3488 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3492 static void rtl_csi_access_enable(void __iomem *ioaddr)
3496 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3497 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3501 unsigned int offset;
3506 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3511 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3512 rtl_ephy_write(ioaddr, e->offset, w);
3517 static void rtl_disable_clock_request(struct pci_dev *pdev)
3519 struct net_device *dev = pci_get_drvdata(pdev);
3520 struct rtl8169_private *tp = netdev_priv(dev);
3521 int cap = tp->pcie_cap;
3526 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3527 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3528 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3532 #define R8168_CPCMD_QUIRK_MASK (\
3543 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3545 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3547 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3549 rtl_tx_performance_tweak(pdev,
3550 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3553 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3555 rtl_hw_start_8168bb(ioaddr, pdev);
3557 RTL_W8(EarlyTxThres, EarlyTxThld);
3559 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3562 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3564 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3566 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3568 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3570 rtl_disable_clock_request(pdev);
3572 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3575 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3577 static const struct ephy_info e_info_8168cp[] = {
3578 { 0x01, 0, 0x0001 },
3579 { 0x02, 0x0800, 0x1000 },
3580 { 0x03, 0, 0x0042 },
3581 { 0x06, 0x0080, 0x0000 },
3585 rtl_csi_access_enable(ioaddr);
3587 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3589 __rtl_hw_start_8168cp(ioaddr, pdev);
3592 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3594 rtl_csi_access_enable(ioaddr);
3596 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3598 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3600 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3603 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3605 rtl_csi_access_enable(ioaddr);
3607 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3610 RTL_W8(DBG_REG, 0x20);
3612 RTL_W8(EarlyTxThres, EarlyTxThld);
3614 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3616 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3619 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3621 static const struct ephy_info e_info_8168c_1[] = {
3622 { 0x02, 0x0800, 0x1000 },
3623 { 0x03, 0, 0x0002 },
3624 { 0x06, 0x0080, 0x0000 }
3627 rtl_csi_access_enable(ioaddr);
3629 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3631 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3633 __rtl_hw_start_8168cp(ioaddr, pdev);
3636 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3638 static const struct ephy_info e_info_8168c_2[] = {
3639 { 0x01, 0, 0x0001 },
3640 { 0x03, 0x0400, 0x0220 }
3643 rtl_csi_access_enable(ioaddr);
3645 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3647 __rtl_hw_start_8168cp(ioaddr, pdev);
3650 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3652 rtl_hw_start_8168c_2(ioaddr, pdev);
3655 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3657 rtl_csi_access_enable(ioaddr);
3659 __rtl_hw_start_8168cp(ioaddr, pdev);
3662 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3664 rtl_csi_access_enable(ioaddr);
3666 rtl_disable_clock_request(pdev);
3668 RTL_W8(EarlyTxThres, EarlyTxThld);
3670 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3672 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3675 static void rtl_hw_start_8168(struct net_device *dev)
3677 struct rtl8169_private *tp = netdev_priv(dev);
3678 void __iomem *ioaddr = tp->mmio_addr;
3679 struct pci_dev *pdev = tp->pci_dev;
3681 RTL_W8(Cfg9346, Cfg9346_Unlock);
3683 RTL_W8(EarlyTxThres, EarlyTxThld);
3685 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3687 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3689 RTL_W16(CPlusCmd, tp->cp_cmd);
3691 RTL_W16(IntrMitigate, 0x5151);
3693 /* Work around for RxFIFO overflow. */
3694 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3695 tp->intr_event |= RxFIFOOver | PCSTimeout;
3696 tp->intr_event &= ~RxOverflow;
3699 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3701 rtl_set_rx_mode(dev);
3703 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3704 (InterFrameGap << TxInterFrameGapShift));
3708 switch (tp->mac_version) {
3709 case RTL_GIGA_MAC_VER_11:
3710 rtl_hw_start_8168bb(ioaddr, pdev);
3713 case RTL_GIGA_MAC_VER_12:
3714 case RTL_GIGA_MAC_VER_17:
3715 rtl_hw_start_8168bef(ioaddr, pdev);
3718 case RTL_GIGA_MAC_VER_18:
3719 rtl_hw_start_8168cp_1(ioaddr, pdev);
3722 case RTL_GIGA_MAC_VER_19:
3723 rtl_hw_start_8168c_1(ioaddr, pdev);
3726 case RTL_GIGA_MAC_VER_20:
3727 rtl_hw_start_8168c_2(ioaddr, pdev);
3730 case RTL_GIGA_MAC_VER_21:
3731 rtl_hw_start_8168c_3(ioaddr, pdev);
3734 case RTL_GIGA_MAC_VER_22:
3735 rtl_hw_start_8168c_4(ioaddr, pdev);
3738 case RTL_GIGA_MAC_VER_23:
3739 rtl_hw_start_8168cp_2(ioaddr, pdev);
3742 case RTL_GIGA_MAC_VER_24:
3743 rtl_hw_start_8168cp_3(ioaddr, pdev);
3746 case RTL_GIGA_MAC_VER_25:
3747 case RTL_GIGA_MAC_VER_26:
3748 case RTL_GIGA_MAC_VER_27:
3749 rtl_hw_start_8168d(ioaddr, pdev);
3753 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3754 dev->name, tp->mac_version);
3758 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3760 RTL_W8(Cfg9346, Cfg9346_Lock);
3762 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3764 RTL_W16(IntrMask, tp->intr_event);
3767 #define R810X_CPCMD_QUIRK_MASK (\
3779 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3781 static const struct ephy_info e_info_8102e_1[] = {
3782 { 0x01, 0, 0x6e65 },
3783 { 0x02, 0, 0x091f },
3784 { 0x03, 0, 0xc2f9 },
3785 { 0x06, 0, 0xafb5 },
3786 { 0x07, 0, 0x0e00 },
3787 { 0x19, 0, 0xec80 },
3788 { 0x01, 0, 0x2e65 },
3793 rtl_csi_access_enable(ioaddr);
3795 RTL_W8(DBG_REG, FIX_NAK_1);
3797 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3800 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3801 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3803 cfg1 = RTL_R8(Config1);
3804 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3805 RTL_W8(Config1, cfg1 & ~LEDS0);
3807 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3809 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3812 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3814 rtl_csi_access_enable(ioaddr);
3816 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3818 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3819 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3821 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3824 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3826 rtl_hw_start_8102e_2(ioaddr, pdev);
3828 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3831 static void rtl_hw_start_8101(struct net_device *dev)
3833 struct rtl8169_private *tp = netdev_priv(dev);
3834 void __iomem *ioaddr = tp->mmio_addr;
3835 struct pci_dev *pdev = tp->pci_dev;
3837 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3838 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3839 int cap = tp->pcie_cap;
3842 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3843 PCI_EXP_DEVCTL_NOSNOOP_EN);
3847 switch (tp->mac_version) {
3848 case RTL_GIGA_MAC_VER_07:
3849 rtl_hw_start_8102e_1(ioaddr, pdev);
3852 case RTL_GIGA_MAC_VER_08:
3853 rtl_hw_start_8102e_3(ioaddr, pdev);
3856 case RTL_GIGA_MAC_VER_09:
3857 rtl_hw_start_8102e_2(ioaddr, pdev);
3861 RTL_W8(Cfg9346, Cfg9346_Unlock);
3863 RTL_W8(EarlyTxThres, EarlyTxThld);
3865 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3867 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3869 RTL_W16(CPlusCmd, tp->cp_cmd);
3871 RTL_W16(IntrMitigate, 0x0000);
3873 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3875 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3876 rtl_set_rx_tx_config_registers(tp);
3878 RTL_W8(Cfg9346, Cfg9346_Lock);
3882 rtl_set_rx_mode(dev);
3884 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3886 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3888 RTL_W16(IntrMask, tp->intr_event);
3891 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3893 struct rtl8169_private *tp = netdev_priv(dev);
3896 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3901 if (!netif_running(dev))
3906 rtl8169_set_rxbufsize(tp, dev->mtu);
3908 ret = rtl8169_init_ring(dev);
3912 napi_enable(&tp->napi);
3916 rtl8169_request_timer(dev);
3922 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3924 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3925 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3928 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3929 struct sk_buff **sk_buff, struct RxDesc *desc)
3931 struct pci_dev *pdev = tp->pci_dev;
3933 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3934 PCI_DMA_FROMDEVICE);
3935 dev_kfree_skb(*sk_buff);
3937 rtl8169_make_unusable_by_asic(desc);
3940 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3942 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3944 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3947 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3950 desc->addr = cpu_to_le64(mapping);
3952 rtl8169_mark_to_asic(desc, rx_buf_sz);
3955 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3956 struct net_device *dev,
3957 struct RxDesc *desc, int rx_buf_sz,
3960 struct sk_buff *skb;
3964 pad = align ? align : NET_IP_ALIGN;
3966 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3970 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3972 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3973 PCI_DMA_FROMDEVICE);
3975 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3980 rtl8169_make_unusable_by_asic(desc);
3984 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3988 for (i = 0; i < NUM_RX_DESC; i++) {
3989 if (tp->Rx_skbuff[i]) {
3990 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3991 tp->RxDescArray + i);
3996 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4001 for (cur = start; end - cur != 0; cur++) {
4002 struct sk_buff *skb;
4003 unsigned int i = cur % NUM_RX_DESC;
4005 WARN_ON((s32)(end - cur) < 0);
4007 if (tp->Rx_skbuff[i])
4010 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4011 tp->RxDescArray + i,
4012 tp->rx_buf_sz, tp->align);
4016 tp->Rx_skbuff[i] = skb;
4021 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4023 desc->opts1 |= cpu_to_le32(RingEnd);
4026 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4028 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4031 static int rtl8169_init_ring(struct net_device *dev)
4033 struct rtl8169_private *tp = netdev_priv(dev);
4035 rtl8169_init_ring_indexes(tp);
4037 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4038 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4040 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4043 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4048 rtl8169_rx_clear(tp);
4052 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4053 struct TxDesc *desc)
4055 unsigned int len = tx_skb->len;
4057 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4064 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4068 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4069 unsigned int entry = i % NUM_TX_DESC;
4070 struct ring_info *tx_skb = tp->tx_skb + entry;
4071 unsigned int len = tx_skb->len;
4074 struct sk_buff *skb = tx_skb->skb;
4076 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4077 tp->TxDescArray + entry);
4082 tp->dev->stats.tx_dropped++;
4085 tp->cur_tx = tp->dirty_tx = 0;
4088 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4090 struct rtl8169_private *tp = netdev_priv(dev);
4092 PREPARE_DELAYED_WORK(&tp->task, task);
4093 schedule_delayed_work(&tp->task, 4);
4096 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4098 struct rtl8169_private *tp = netdev_priv(dev);
4099 void __iomem *ioaddr = tp->mmio_addr;
4101 synchronize_irq(dev->irq);
4103 /* Wait for any pending NAPI task to complete */
4104 napi_disable(&tp->napi);
4106 rtl8169_irq_mask_and_ack(ioaddr);
4108 tp->intr_mask = 0xffff;
4109 RTL_W16(IntrMask, tp->intr_event);
4110 napi_enable(&tp->napi);
4113 static void rtl8169_reinit_task(struct work_struct *work)
4115 struct rtl8169_private *tp =
4116 container_of(work, struct rtl8169_private, task.work);
4117 struct net_device *dev = tp->dev;
4122 if (!netif_running(dev))
4125 rtl8169_wait_for_quiescence(dev);
4128 ret = rtl8169_open(dev);
4129 if (unlikely(ret < 0)) {
4130 if (net_ratelimit())
4131 netif_err(tp, drv, dev,
4132 "reinit failure (status = %d). Rescheduling\n",
4134 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4141 static void rtl8169_reset_task(struct work_struct *work)
4143 struct rtl8169_private *tp =
4144 container_of(work, struct rtl8169_private, task.work);
4145 struct net_device *dev = tp->dev;
4149 if (!netif_running(dev))
4152 rtl8169_wait_for_quiescence(dev);
4154 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4155 rtl8169_tx_clear(tp);
4157 if (tp->dirty_rx == tp->cur_rx) {
4158 rtl8169_init_ring_indexes(tp);
4160 netif_wake_queue(dev);
4161 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4163 if (net_ratelimit())
4164 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4165 rtl8169_schedule_work(dev, rtl8169_reset_task);
4172 static void rtl8169_tx_timeout(struct net_device *dev)
4174 struct rtl8169_private *tp = netdev_priv(dev);
4176 rtl8169_hw_reset(tp->mmio_addr);
4178 /* Let's wait a bit while any (async) irq lands on */
4179 rtl8169_schedule_work(dev, rtl8169_reset_task);
4182 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4185 struct skb_shared_info *info = skb_shinfo(skb);
4186 unsigned int cur_frag, entry;
4187 struct TxDesc * uninitialized_var(txd);
4190 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4191 skb_frag_t *frag = info->frags + cur_frag;
4196 entry = (entry + 1) % NUM_TX_DESC;
4198 txd = tp->TxDescArray + entry;
4200 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4201 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4203 /* anti gcc 2.95.3 bugware (sic) */
4204 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4206 txd->opts1 = cpu_to_le32(status);
4207 txd->addr = cpu_to_le64(mapping);
4209 tp->tx_skb[entry].len = len;
4213 tp->tx_skb[entry].skb = skb;
4214 txd->opts1 |= cpu_to_le32(LastFrag);
4220 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4222 if (dev->features & NETIF_F_TSO) {
4223 u32 mss = skb_shinfo(skb)->gso_size;
4226 return LargeSend | ((mss & MSSMask) << MSSShift);
4228 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4229 const struct iphdr *ip = ip_hdr(skb);
4231 if (ip->protocol == IPPROTO_TCP)
4232 return IPCS | TCPCS;
4233 else if (ip->protocol == IPPROTO_UDP)
4234 return IPCS | UDPCS;
4235 WARN_ON(1); /* we need a WARN() */
4240 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4241 struct net_device *dev)
4243 struct rtl8169_private *tp = netdev_priv(dev);
4244 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4245 struct TxDesc *txd = tp->TxDescArray + entry;
4246 void __iomem *ioaddr = tp->mmio_addr;
4251 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4252 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4256 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4259 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4261 frags = rtl8169_xmit_frags(tp, skb, opts1);
4263 len = skb_headlen(skb);
4267 opts1 |= FirstFrag | LastFrag;
4268 tp->tx_skb[entry].skb = skb;
4271 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4273 tp->tx_skb[entry].len = len;
4274 txd->addr = cpu_to_le64(mapping);
4275 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4279 /* anti gcc 2.95.3 bugware (sic) */
4280 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4281 txd->opts1 = cpu_to_le32(status);
4283 tp->cur_tx += frags + 1;
4287 RTL_W8(TxPoll, NPQ); /* set polling bit */
4289 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4290 netif_stop_queue(dev);
4292 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4293 netif_wake_queue(dev);
4296 return NETDEV_TX_OK;
4299 netif_stop_queue(dev);
4300 dev->stats.tx_dropped++;
4301 return NETDEV_TX_BUSY;
4304 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4306 struct rtl8169_private *tp = netdev_priv(dev);
4307 struct pci_dev *pdev = tp->pci_dev;
4308 void __iomem *ioaddr = tp->mmio_addr;
4309 u16 pci_status, pci_cmd;
4311 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4312 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4314 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4315 pci_cmd, pci_status);
4318 * The recovery sequence below admits a very elaborated explanation:
4319 * - it seems to work;
4320 * - I did not see what else could be done;
4321 * - it makes iop3xx happy.
4323 * Feel free to adjust to your needs.
4325 if (pdev->broken_parity_status)
4326 pci_cmd &= ~PCI_COMMAND_PARITY;
4328 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4330 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4332 pci_write_config_word(pdev, PCI_STATUS,
4333 pci_status & (PCI_STATUS_DETECTED_PARITY |
4334 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4335 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4337 /* The infamous DAC f*ckup only happens at boot time */
4338 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4339 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4340 tp->cp_cmd &= ~PCIDAC;
4341 RTL_W16(CPlusCmd, tp->cp_cmd);
4342 dev->features &= ~NETIF_F_HIGHDMA;
4345 rtl8169_hw_reset(ioaddr);
4347 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4350 static void rtl8169_tx_interrupt(struct net_device *dev,
4351 struct rtl8169_private *tp,
4352 void __iomem *ioaddr)
4354 unsigned int dirty_tx, tx_left;
4356 dirty_tx = tp->dirty_tx;
4358 tx_left = tp->cur_tx - dirty_tx;
4360 while (tx_left > 0) {
4361 unsigned int entry = dirty_tx % NUM_TX_DESC;
4362 struct ring_info *tx_skb = tp->tx_skb + entry;
4363 u32 len = tx_skb->len;
4367 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4368 if (status & DescOwn)
4371 dev->stats.tx_bytes += len;
4372 dev->stats.tx_packets++;
4374 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4376 if (status & LastFrag) {
4377 dev_kfree_skb(tx_skb->skb);
4384 if (tp->dirty_tx != dirty_tx) {
4385 tp->dirty_tx = dirty_tx;
4387 if (netif_queue_stopped(dev) &&
4388 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4389 netif_wake_queue(dev);
4392 * 8168 hack: TxPoll requests are lost when the Tx packets are
4393 * too close. Let's kick an extra TxPoll request when a burst
4394 * of start_xmit activity is detected (if it is not detected,
4395 * it is slow enough). -- FR
4398 if (tp->cur_tx != dirty_tx)
4399 RTL_W8(TxPoll, NPQ);
4403 static inline int rtl8169_fragmented_frame(u32 status)
4405 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4408 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4410 u32 opts1 = le32_to_cpu(desc->opts1);
4411 u32 status = opts1 & RxProtoMask;
4413 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4414 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4415 ((status == RxProtoIP) && !(opts1 & IPFail)))
4416 skb->ip_summed = CHECKSUM_UNNECESSARY;
4418 skb->ip_summed = CHECKSUM_NONE;
4421 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4422 struct rtl8169_private *tp, int pkt_size,
4425 struct sk_buff *skb;
4428 if (pkt_size >= rx_copybreak)
4431 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4435 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4436 PCI_DMA_FROMDEVICE);
4437 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4444 static int rtl8169_rx_interrupt(struct net_device *dev,
4445 struct rtl8169_private *tp,
4446 void __iomem *ioaddr, u32 budget)
4448 unsigned int cur_rx, rx_left;
4449 unsigned int delta, count;
4451 cur_rx = tp->cur_rx;
4452 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4453 rx_left = min(rx_left, budget);
4455 for (; rx_left > 0; rx_left--, cur_rx++) {
4456 unsigned int entry = cur_rx % NUM_RX_DESC;
4457 struct RxDesc *desc = tp->RxDescArray + entry;
4461 status = le32_to_cpu(desc->opts1);
4463 if (status & DescOwn)
4465 if (unlikely(status & RxRES)) {
4466 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4468 dev->stats.rx_errors++;
4469 if (status & (RxRWT | RxRUNT))
4470 dev->stats.rx_length_errors++;
4472 dev->stats.rx_crc_errors++;
4473 if (status & RxFOVF) {
4474 rtl8169_schedule_work(dev, rtl8169_reset_task);
4475 dev->stats.rx_fifo_errors++;
4477 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4479 struct sk_buff *skb = tp->Rx_skbuff[entry];
4480 dma_addr_t addr = le64_to_cpu(desc->addr);
4481 int pkt_size = (status & 0x00001FFF) - 4;
4482 struct pci_dev *pdev = tp->pci_dev;
4485 * The driver does not support incoming fragmented
4486 * frames. They are seen as a symptom of over-mtu
4489 if (unlikely(rtl8169_fragmented_frame(status))) {
4490 dev->stats.rx_dropped++;
4491 dev->stats.rx_length_errors++;
4492 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4496 rtl8169_rx_csum(skb, desc);
4498 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4499 pci_dma_sync_single_for_device(pdev, addr,
4500 pkt_size, PCI_DMA_FROMDEVICE);
4501 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4503 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4504 PCI_DMA_FROMDEVICE);
4505 tp->Rx_skbuff[entry] = NULL;
4508 skb_put(skb, pkt_size);
4509 skb->protocol = eth_type_trans(skb, dev);
4511 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4512 netif_receive_skb(skb);
4514 dev->stats.rx_bytes += pkt_size;
4515 dev->stats.rx_packets++;
4518 /* Work around for AMD plateform. */
4519 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4520 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4526 count = cur_rx - tp->cur_rx;
4527 tp->cur_rx = cur_rx;
4529 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4530 if (!delta && count)
4531 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4532 tp->dirty_rx += delta;
4535 * FIXME: until there is periodic timer to try and refill the ring,
4536 * a temporary shortage may definitely kill the Rx process.
4537 * - disable the asic to try and avoid an overflow and kick it again
4539 * - how do others driver handle this condition (Uh oh...).
4541 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4542 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4547 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4549 struct net_device *dev = dev_instance;
4550 struct rtl8169_private *tp = netdev_priv(dev);
4551 void __iomem *ioaddr = tp->mmio_addr;
4555 /* loop handling interrupts until we have no new ones or
4556 * we hit a invalid/hotplug case.
4558 status = RTL_R16(IntrStatus);
4559 while (status && status != 0xffff) {
4562 /* Handle all of the error cases first. These will reset
4563 * the chip, so just exit the loop.
4565 if (unlikely(!netif_running(dev))) {
4566 rtl8169_asic_down(ioaddr);
4570 /* Work around for rx fifo overflow */
4571 if (unlikely(status & RxFIFOOver) &&
4572 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4573 netif_stop_queue(dev);
4574 rtl8169_tx_timeout(dev);
4578 if (unlikely(status & SYSErr)) {
4579 rtl8169_pcierr_interrupt(dev);
4583 if (status & LinkChg)
4584 rtl8169_check_link_status(dev, tp, ioaddr);
4586 /* We need to see the lastest version of tp->intr_mask to
4587 * avoid ignoring an MSI interrupt and having to wait for
4588 * another event which may never come.
4591 if (status & tp->intr_mask & tp->napi_event) {
4592 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4593 tp->intr_mask = ~tp->napi_event;
4595 if (likely(napi_schedule_prep(&tp->napi)))
4596 __napi_schedule(&tp->napi);
4598 netif_info(tp, intr, dev,
4599 "interrupt %04x in poll\n", status);
4602 /* We only get a new MSI interrupt when all active irq
4603 * sources on the chip have been acknowledged. So, ack
4604 * everything we've seen and check if new sources have become
4605 * active to avoid blocking all interrupts from the chip.
4608 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4609 status = RTL_R16(IntrStatus);
4612 return IRQ_RETVAL(handled);
4615 static int rtl8169_poll(struct napi_struct *napi, int budget)
4617 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4618 struct net_device *dev = tp->dev;
4619 void __iomem *ioaddr = tp->mmio_addr;
4622 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4623 rtl8169_tx_interrupt(dev, tp, ioaddr);
4625 if (work_done < budget) {
4626 napi_complete(napi);
4628 /* We need for force the visibility of tp->intr_mask
4629 * for other CPUs, as we can loose an MSI interrupt
4630 * and potentially wait for a retransmit timeout if we don't.
4631 * The posted write to IntrMask is safe, as it will
4632 * eventually make it to the chip and we won't loose anything
4635 tp->intr_mask = 0xffff;
4637 RTL_W16(IntrMask, tp->intr_event);
4643 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4645 struct rtl8169_private *tp = netdev_priv(dev);
4647 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4650 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4651 RTL_W32(RxMissed, 0);
4654 static void rtl8169_down(struct net_device *dev)
4656 struct rtl8169_private *tp = netdev_priv(dev);
4657 void __iomem *ioaddr = tp->mmio_addr;
4658 unsigned int intrmask;
4660 rtl8169_delete_timer(dev);
4662 netif_stop_queue(dev);
4664 napi_disable(&tp->napi);
4667 spin_lock_irq(&tp->lock);
4669 rtl8169_asic_down(ioaddr);
4671 rtl8169_rx_missed(dev, ioaddr);
4673 spin_unlock_irq(&tp->lock);
4675 synchronize_irq(dev->irq);
4677 /* Give a racing hard_start_xmit a few cycles to complete. */
4678 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4681 * And now for the 50k$ question: are IRQ disabled or not ?
4683 * Two paths lead here:
4685 * -> netif_running() is available to sync the current code and the
4686 * IRQ handler. See rtl8169_interrupt for details.
4687 * 2) dev->change_mtu
4688 * -> rtl8169_poll can not be issued again and re-enable the
4689 * interruptions. Let's simply issue the IRQ down sequence again.
4691 * No loop if hotpluged or major error (0xffff).
4693 intrmask = RTL_R16(IntrMask);
4694 if (intrmask && (intrmask != 0xffff))
4697 rtl8169_tx_clear(tp);
4699 rtl8169_rx_clear(tp);
4702 static int rtl8169_close(struct net_device *dev)
4704 struct rtl8169_private *tp = netdev_priv(dev);
4705 struct pci_dev *pdev = tp->pci_dev;
4707 /* update counters before going down */
4708 rtl8169_update_counters(dev);
4712 free_irq(dev->irq, dev);
4714 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4716 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4718 tp->TxDescArray = NULL;
4719 tp->RxDescArray = NULL;
4724 static void rtl_set_rx_mode(struct net_device *dev)
4726 struct rtl8169_private *tp = netdev_priv(dev);
4727 void __iomem *ioaddr = tp->mmio_addr;
4728 unsigned long flags;
4729 u32 mc_filter[2]; /* Multicast hash filter */
4733 if (dev->flags & IFF_PROMISC) {
4734 /* Unconditionally log net taps. */
4735 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4737 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4739 mc_filter[1] = mc_filter[0] = 0xffffffff;
4740 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4741 (dev->flags & IFF_ALLMULTI)) {
4742 /* Too many to filter perfectly -- accept all multicasts. */
4743 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4744 mc_filter[1] = mc_filter[0] = 0xffffffff;
4746 struct dev_mc_list *mclist;
4748 rx_mode = AcceptBroadcast | AcceptMyPhys;
4749 mc_filter[1] = mc_filter[0] = 0;
4750 netdev_for_each_mc_addr(mclist, dev) {
4751 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4752 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4753 rx_mode |= AcceptMulticast;
4757 spin_lock_irqsave(&tp->lock, flags);
4759 tmp = rtl8169_rx_config | rx_mode |
4760 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4762 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4763 u32 data = mc_filter[0];
4765 mc_filter[0] = swab32(mc_filter[1]);
4766 mc_filter[1] = swab32(data);
4769 RTL_W32(MAR0 + 4, mc_filter[1]);
4770 RTL_W32(MAR0 + 0, mc_filter[0]);
4772 RTL_W32(RxConfig, tmp);
4774 spin_unlock_irqrestore(&tp->lock, flags);
4778 * rtl8169_get_stats - Get rtl8169 read/write statistics
4779 * @dev: The Ethernet Device to get statistics for
4781 * Get TX/RX statistics for rtl8169
4783 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4785 struct rtl8169_private *tp = netdev_priv(dev);
4786 void __iomem *ioaddr = tp->mmio_addr;
4787 unsigned long flags;
4789 if (netif_running(dev)) {
4790 spin_lock_irqsave(&tp->lock, flags);
4791 rtl8169_rx_missed(dev, ioaddr);
4792 spin_unlock_irqrestore(&tp->lock, flags);
4798 static void rtl8169_net_suspend(struct net_device *dev)
4800 if (!netif_running(dev))
4803 netif_device_detach(dev);
4804 netif_stop_queue(dev);
4809 static int rtl8169_suspend(struct device *device)
4811 struct pci_dev *pdev = to_pci_dev(device);
4812 struct net_device *dev = pci_get_drvdata(pdev);
4814 rtl8169_net_suspend(dev);
4819 static int rtl8169_resume(struct device *device)
4821 struct pci_dev *pdev = to_pci_dev(device);
4822 struct net_device *dev = pci_get_drvdata(pdev);
4824 if (!netif_running(dev))
4827 netif_device_attach(dev);
4829 rtl8169_schedule_work(dev, rtl8169_reset_task);
4834 static const struct dev_pm_ops rtl8169_pm_ops = {
4835 .suspend = rtl8169_suspend,
4836 .resume = rtl8169_resume,
4837 .freeze = rtl8169_suspend,
4838 .thaw = rtl8169_resume,
4839 .poweroff = rtl8169_suspend,
4840 .restore = rtl8169_resume,
4843 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4845 #else /* !CONFIG_PM */
4847 #define RTL8169_PM_OPS NULL
4849 #endif /* !CONFIG_PM */
4851 static void rtl_shutdown(struct pci_dev *pdev)
4853 struct net_device *dev = pci_get_drvdata(pdev);
4854 struct rtl8169_private *tp = netdev_priv(dev);
4855 void __iomem *ioaddr = tp->mmio_addr;
4857 rtl8169_net_suspend(dev);
4859 /* restore original MAC address */
4860 rtl_rar_set(tp, dev->perm_addr);
4862 spin_lock_irq(&tp->lock);
4864 rtl8169_asic_down(ioaddr);
4866 spin_unlock_irq(&tp->lock);
4868 if (system_state == SYSTEM_POWER_OFF) {
4869 /* WoL fails with some 8168 when the receiver is disabled. */
4870 if (tp->features & RTL_FEATURE_WOL) {
4871 pci_clear_master(pdev);
4873 RTL_W8(ChipCmd, CmdRxEnb);
4878 pci_wake_from_d3(pdev, true);
4879 pci_set_power_state(pdev, PCI_D3hot);
4883 static struct pci_driver rtl8169_pci_driver = {
4885 .id_table = rtl8169_pci_tbl,
4886 .probe = rtl8169_init_one,
4887 .remove = __devexit_p(rtl8169_remove_one),
4888 .shutdown = rtl_shutdown,
4889 .driver.pm = RTL8169_PM_OPS,
4892 static int __init rtl8169_init_module(void)
4894 return pci_register_driver(&rtl8169_pci_driver);
4897 static void __exit rtl8169_cleanup_module(void)
4899 pci_unregister_driver(&rtl8169_pci_driver);
4902 module_init(rtl8169_init_module);
4903 module_exit(rtl8169_cleanup_module);