2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
29 #include <asm/system.h>
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define assert(expr) \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131 static const struct {
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135 } rtl_chip_info[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
173 static void rtl_hw_start_8169(struct net_device *);
174 static void rtl_hw_start_8168(struct net_device *);
175 static void rtl_hw_start_8101(struct net_device *);
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
195 static int rx_buf_sz = 16383;
202 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
241 #define TxPacketMax (8064 >> 7)
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
249 enum rtl8110_registers {
255 enum rtl8168_8101_registers {
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
282 enum rtl8168_registers {
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
309 enum rtl_register_content {
310 /* InterruptStatusBits */
314 TxDescUnavail = 0x0080,
336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
343 Cfg9346_Unlock = 0xc0,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
351 AcceptAllPhys = 0x01,
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
361 /* Config1 register p.24 */
364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down = (1 << 4),
369 PMEnable = (1 << 0), /* Power Management Enable */
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
380 /* Config5 register p.27 */
381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
415 /* rtl8169_PHYstatus */
426 TBILinkOK = 0x02000000,
428 /* DumpCounterCommand */
432 enum desc_status_bit {
433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
462 #define RsvdMask 0x3fffc000
479 u8 __pad[sizeof(void *) - sizeof(u32)];
483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
488 struct rtl8169_counters {
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
504 struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
507 struct net_device *dev;
508 struct napi_struct napi;
509 spinlock_t lock; /* spin lock flag */
513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
523 struct timer_list timer;
528 int phy_1000_ctrl_reg;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
545 void (*phy_reset_enable)(struct rtl8169_private *tp);
546 void (*hw_start)(struct net_device *);
547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
548 unsigned int (*link_ok)(void __iomem *);
549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
551 struct delayed_work task;
554 struct mii_if_info mii;
555 struct rtl8169_counters counters;
559 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
560 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
561 module_param(use_dac, int, 0);
562 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
563 module_param_named(debug, debug.msg_enable, int, 0);
564 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
565 MODULE_LICENSE("GPL");
566 MODULE_VERSION(RTL8169_VERSION);
567 MODULE_FIRMWARE(FIRMWARE_8168D_1);
568 MODULE_FIRMWARE(FIRMWARE_8168D_2);
570 static int rtl8169_open(struct net_device *dev);
571 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
572 struct net_device *dev);
573 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
574 static int rtl8169_init_ring(struct net_device *dev);
575 static void rtl_hw_start(struct net_device *dev);
576 static int rtl8169_close(struct net_device *dev);
577 static void rtl_set_rx_mode(struct net_device *dev);
578 static void rtl8169_tx_timeout(struct net_device *dev);
579 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
580 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
581 void __iomem *, u32 budget);
582 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
583 static void rtl8169_down(struct net_device *dev);
584 static void rtl8169_rx_clear(struct rtl8169_private *tp);
585 static int rtl8169_poll(struct napi_struct *napi, int budget);
587 static const unsigned int rtl8169_rx_config =
588 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
590 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
592 void __iomem *ioaddr = tp->mmio_addr;
595 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
596 for (i = 0; i < 20; i++) {
598 if (RTL_R32(OCPAR) & OCPAR_FLAG)
601 return RTL_R32(OCPDR);
604 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
606 void __iomem *ioaddr = tp->mmio_addr;
609 RTL_W32(OCPDR, data);
610 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
611 for (i = 0; i < 20; i++) {
613 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
618 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
623 RTL_W32(ERIAR, 0x800010e8);
625 for (i = 0; i < 5; i++) {
627 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
631 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
634 #define OOB_CMD_RESET 0x00
635 #define OOB_CMD_DRIVER_START 0x05
636 #define OOB_CMD_DRIVER_STOP 0x06
638 static void rtl8168_driver_start(struct rtl8169_private *tp)
642 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
644 for (i = 0; i < 10; i++) {
646 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
651 static void rtl8168_driver_stop(struct rtl8169_private *tp)
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
657 for (i = 0; i < 10; i++) {
659 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
665 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
669 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
671 for (i = 20; i > 0; i--) {
673 * Check if the RTL8169 has completed writing to the specified
676 if (!(RTL_R32(PHYAR) & 0x80000000))
681 * According to hardware specs a 20us delay is required after write
682 * complete indication, but before sending next command.
687 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
691 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
693 for (i = 20; i > 0; i--) {
695 * Check if the RTL8169 has completed retrieving data from
696 * the specified MII register.
698 if (RTL_R32(PHYAR) & 0x80000000) {
699 value = RTL_R32(PHYAR) & 0xffff;
705 * According to hardware specs a 20us delay is required after read
706 * complete indication, but before sending next command.
713 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
717 RTL_W32(OCPDR, data |
718 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
719 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
720 RTL_W32(EPHY_RXER_NUM, 0);
722 for (i = 0; i < 100; i++) {
724 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
729 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
731 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
732 (value & OCPDR_DATA_MASK));
735 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
739 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
742 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
743 RTL_W32(EPHY_RXER_NUM, 0);
745 for (i = 0; i < 100; i++) {
747 if (RTL_R32(OCPAR) & OCPAR_FLAG)
751 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
754 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
756 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
758 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
761 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
763 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
766 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
768 r8168dp_2_mdio_start(ioaddr);
770 r8169_mdio_write(ioaddr, reg_addr, value);
772 r8168dp_2_mdio_stop(ioaddr);
775 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
779 r8168dp_2_mdio_start(ioaddr);
781 value = r8169_mdio_read(ioaddr, reg_addr);
783 r8168dp_2_mdio_stop(ioaddr);
788 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
790 tp->mdio_ops.write(tp->mmio_addr, location, val);
793 static int rtl_readphy(struct rtl8169_private *tp, int location)
795 return tp->mdio_ops.read(tp->mmio_addr, location);
798 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
800 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
803 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
807 val = rtl_readphy(tp, reg_addr);
808 rtl_writephy(tp, reg_addr, (val | p) & ~m);
811 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
814 struct rtl8169_private *tp = netdev_priv(dev);
816 rtl_writephy(tp, location, val);
819 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
821 struct rtl8169_private *tp = netdev_priv(dev);
823 return rtl_readphy(tp, location);
826 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
830 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
831 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
833 for (i = 0; i < 100; i++) {
834 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
840 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
845 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
847 for (i = 0; i < 100; i++) {
848 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
849 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
858 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
862 RTL_W32(CSIDR, value);
863 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
864 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
866 for (i = 0; i < 100; i++) {
867 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
873 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
878 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
879 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
881 for (i = 0; i < 100; i++) {
882 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
883 value = RTL_R32(CSIDR);
892 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
897 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
899 for (i = 0; i < 300; i++) {
900 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
901 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
910 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
912 RTL_W16(IntrMask, 0x0000);
914 RTL_W16(IntrStatus, 0xffff);
917 static void rtl8169_asic_down(void __iomem *ioaddr)
919 RTL_W8(ChipCmd, 0x00);
920 rtl8169_irq_mask_and_ack(ioaddr);
924 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
926 void __iomem *ioaddr = tp->mmio_addr;
928 return RTL_R32(TBICSR) & TBIReset;
931 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
933 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
936 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
938 return RTL_R32(TBICSR) & TBILinkOk;
941 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
943 return RTL_R8(PHYstatus) & LinkStatus;
946 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
948 void __iomem *ioaddr = tp->mmio_addr;
950 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
953 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
957 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
958 rtl_writephy(tp, MII_BMCR, val & 0xffff);
961 static void __rtl8169_check_link_status(struct net_device *dev,
962 struct rtl8169_private *tp,
963 void __iomem *ioaddr,
968 spin_lock_irqsave(&tp->lock, flags);
969 if (tp->link_ok(ioaddr)) {
970 /* This is to cancel a scheduled suspend if there's one. */
972 pm_request_resume(&tp->pci_dev->dev);
973 netif_carrier_on(dev);
974 netif_info(tp, ifup, dev, "link up\n");
976 netif_carrier_off(dev);
977 netif_info(tp, ifdown, dev, "link down\n");
979 pm_schedule_suspend(&tp->pci_dev->dev, 100);
981 spin_unlock_irqrestore(&tp->lock, flags);
984 static void rtl8169_check_link_status(struct net_device *dev,
985 struct rtl8169_private *tp,
986 void __iomem *ioaddr)
988 __rtl8169_check_link_status(dev, tp, ioaddr, false);
991 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
993 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
995 void __iomem *ioaddr = tp->mmio_addr;
999 options = RTL_R8(Config1);
1000 if (!(options & PMEnable))
1003 options = RTL_R8(Config3);
1004 if (options & LinkUp)
1005 wolopts |= WAKE_PHY;
1006 if (options & MagicPacket)
1007 wolopts |= WAKE_MAGIC;
1009 options = RTL_R8(Config5);
1011 wolopts |= WAKE_UCAST;
1013 wolopts |= WAKE_BCAST;
1015 wolopts |= WAKE_MCAST;
1020 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1022 struct rtl8169_private *tp = netdev_priv(dev);
1024 spin_lock_irq(&tp->lock);
1026 wol->supported = WAKE_ANY;
1027 wol->wolopts = __rtl8169_get_wol(tp);
1029 spin_unlock_irq(&tp->lock);
1032 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1034 void __iomem *ioaddr = tp->mmio_addr;
1036 static const struct {
1041 { WAKE_ANY, Config1, PMEnable },
1042 { WAKE_PHY, Config3, LinkUp },
1043 { WAKE_MAGIC, Config3, MagicPacket },
1044 { WAKE_UCAST, Config5, UWF },
1045 { WAKE_BCAST, Config5, BWF },
1046 { WAKE_MCAST, Config5, MWF },
1047 { WAKE_ANY, Config5, LanWake }
1050 RTL_W8(Cfg9346, Cfg9346_Unlock);
1052 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1053 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1054 if (wolopts & cfg[i].opt)
1055 options |= cfg[i].mask;
1056 RTL_W8(cfg[i].reg, options);
1059 RTL_W8(Cfg9346, Cfg9346_Lock);
1062 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1064 struct rtl8169_private *tp = netdev_priv(dev);
1066 spin_lock_irq(&tp->lock);
1069 tp->features |= RTL_FEATURE_WOL;
1071 tp->features &= ~RTL_FEATURE_WOL;
1072 __rtl8169_set_wol(tp, wol->wolopts);
1073 spin_unlock_irq(&tp->lock);
1075 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1080 static void rtl8169_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1083 struct rtl8169_private *tp = netdev_priv(dev);
1085 strcpy(info->driver, MODULENAME);
1086 strcpy(info->version, RTL8169_VERSION);
1087 strcpy(info->bus_info, pci_name(tp->pci_dev));
1090 static int rtl8169_get_regs_len(struct net_device *dev)
1092 return R8169_REGS_SIZE;
1095 static int rtl8169_set_speed_tbi(struct net_device *dev,
1096 u8 autoneg, u16 speed, u8 duplex)
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099 void __iomem *ioaddr = tp->mmio_addr;
1103 reg = RTL_R32(TBICSR);
1104 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1105 (duplex == DUPLEX_FULL)) {
1106 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1107 } else if (autoneg == AUTONEG_ENABLE)
1108 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1110 netif_warn(tp, link, dev,
1111 "incorrect speed setting refused in TBI mode\n");
1118 static int rtl8169_set_speed_xmii(struct net_device *dev,
1119 u8 autoneg, u16 speed, u8 duplex)
1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 int giga_ctrl, bmcr;
1124 if (autoneg == AUTONEG_ENABLE) {
1127 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1128 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1129 ADVERTISE_100HALF | ADVERTISE_100FULL);
1130 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1132 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1133 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1135 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1136 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1137 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1138 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1139 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1144 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1146 netif_info(tp, link, dev,
1147 "PHY does not support 1000Mbps\n");
1150 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1152 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1153 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1154 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1157 * Vendor specific (0x1f) and reserved (0x0e) MII
1160 rtl_writephy(tp, 0x1f, 0x0000);
1161 rtl_writephy(tp, 0x0e, 0x0000);
1164 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1165 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1169 if (speed == SPEED_10)
1171 else if (speed == SPEED_100)
1172 bmcr = BMCR_SPEED100;
1176 if (duplex == DUPLEX_FULL)
1177 bmcr |= BMCR_FULLDPLX;
1179 rtl_writephy(tp, 0x1f, 0x0000);
1182 tp->phy_1000_ctrl_reg = giga_ctrl;
1184 rtl_writephy(tp, MII_BMCR, bmcr);
1186 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1187 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1188 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1189 rtl_writephy(tp, 0x17, 0x2138);
1190 rtl_writephy(tp, 0x0e, 0x0260);
1192 rtl_writephy(tp, 0x17, 0x2108);
1193 rtl_writephy(tp, 0x0e, 0x0000);
1200 static int rtl8169_set_speed(struct net_device *dev,
1201 u8 autoneg, u16 speed, u8 duplex)
1203 struct rtl8169_private *tp = netdev_priv(dev);
1206 ret = tp->set_speed(dev, autoneg, speed, duplex);
1208 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1209 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1214 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217 unsigned long flags;
1220 spin_lock_irqsave(&tp->lock, flags);
1221 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1222 spin_unlock_irqrestore(&tp->lock, flags);
1227 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1229 struct rtl8169_private *tp = netdev_priv(dev);
1231 return tp->cp_cmd & RxChkSum;
1234 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237 void __iomem *ioaddr = tp->mmio_addr;
1238 unsigned long flags;
1240 spin_lock_irqsave(&tp->lock, flags);
1243 tp->cp_cmd |= RxChkSum;
1245 tp->cp_cmd &= ~RxChkSum;
1247 RTL_W16(CPlusCmd, tp->cp_cmd);
1250 spin_unlock_irqrestore(&tp->lock, flags);
1255 #ifdef CONFIG_R8169_VLAN
1257 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1258 struct sk_buff *skb)
1260 return (vlan_tx_tag_present(skb)) ?
1261 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1264 static void rtl8169_vlan_rx_register(struct net_device *dev,
1265 struct vlan_group *grp)
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268 void __iomem *ioaddr = tp->mmio_addr;
1269 unsigned long flags;
1271 spin_lock_irqsave(&tp->lock, flags);
1274 * Do not disable RxVlan on 8110SCd.
1276 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1277 tp->cp_cmd |= RxVlan;
1279 tp->cp_cmd &= ~RxVlan;
1280 RTL_W16(CPlusCmd, tp->cp_cmd);
1282 spin_unlock_irqrestore(&tp->lock, flags);
1285 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1286 struct sk_buff *skb, int polling)
1288 u32 opts2 = le32_to_cpu(desc->opts2);
1289 struct vlan_group *vlgrp = tp->vlgrp;
1292 if (vlgrp && (opts2 & RxVlanTag)) {
1293 u16 vtag = swab16(opts2 & 0xffff);
1295 if (likely(polling))
1296 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1298 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1306 #else /* !CONFIG_R8169_VLAN */
1308 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1309 struct sk_buff *skb)
1314 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1315 struct sk_buff *skb, int polling)
1322 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1324 struct rtl8169_private *tp = netdev_priv(dev);
1325 void __iomem *ioaddr = tp->mmio_addr;
1329 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1330 cmd->port = PORT_FIBRE;
1331 cmd->transceiver = XCVR_INTERNAL;
1333 status = RTL_R32(TBICSR);
1334 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1335 cmd->autoneg = !!(status & TBINwEnable);
1337 cmd->speed = SPEED_1000;
1338 cmd->duplex = DUPLEX_FULL; /* Always set */
1343 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1345 struct rtl8169_private *tp = netdev_priv(dev);
1347 return mii_ethtool_gset(&tp->mii, cmd);
1350 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1352 struct rtl8169_private *tp = netdev_priv(dev);
1353 unsigned long flags;
1356 spin_lock_irqsave(&tp->lock, flags);
1358 rc = tp->get_settings(dev, cmd);
1360 spin_unlock_irqrestore(&tp->lock, flags);
1364 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 unsigned long flags;
1370 if (regs->len > R8169_REGS_SIZE)
1371 regs->len = R8169_REGS_SIZE;
1373 spin_lock_irqsave(&tp->lock, flags);
1374 memcpy_fromio(p, tp->mmio_addr, regs->len);
1375 spin_unlock_irqrestore(&tp->lock, flags);
1378 static u32 rtl8169_get_msglevel(struct net_device *dev)
1380 struct rtl8169_private *tp = netdev_priv(dev);
1382 return tp->msg_enable;
1385 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1387 struct rtl8169_private *tp = netdev_priv(dev);
1389 tp->msg_enable = value;
1392 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1399 "tx_single_collisions",
1400 "tx_multi_collisions",
1408 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1412 return ARRAY_SIZE(rtl8169_gstrings);
1418 static void rtl8169_update_counters(struct net_device *dev)
1420 struct rtl8169_private *tp = netdev_priv(dev);
1421 void __iomem *ioaddr = tp->mmio_addr;
1422 struct rtl8169_counters *counters;
1426 struct device *d = &tp->pci_dev->dev;
1429 * Some chips are unable to dump tally counters when the receiver
1432 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1435 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1439 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1440 cmd = (u64)paddr & DMA_BIT_MASK(32);
1441 RTL_W32(CounterAddrLow, cmd);
1442 RTL_W32(CounterAddrLow, cmd | CounterDump);
1445 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1446 /* copy updated counters */
1447 memcpy(&tp->counters, counters, sizeof(*counters));
1453 RTL_W32(CounterAddrLow, 0);
1454 RTL_W32(CounterAddrHigh, 0);
1456 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1459 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1460 struct ethtool_stats *stats, u64 *data)
1462 struct rtl8169_private *tp = netdev_priv(dev);
1466 rtl8169_update_counters(dev);
1468 data[0] = le64_to_cpu(tp->counters.tx_packets);
1469 data[1] = le64_to_cpu(tp->counters.rx_packets);
1470 data[2] = le64_to_cpu(tp->counters.tx_errors);
1471 data[3] = le32_to_cpu(tp->counters.rx_errors);
1472 data[4] = le16_to_cpu(tp->counters.rx_missed);
1473 data[5] = le16_to_cpu(tp->counters.align_errors);
1474 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1475 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1476 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1477 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1478 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1479 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1480 data[12] = le16_to_cpu(tp->counters.tx_underun);
1483 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1487 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1492 static const struct ethtool_ops rtl8169_ethtool_ops = {
1493 .get_drvinfo = rtl8169_get_drvinfo,
1494 .get_regs_len = rtl8169_get_regs_len,
1495 .get_link = ethtool_op_get_link,
1496 .get_settings = rtl8169_get_settings,
1497 .set_settings = rtl8169_set_settings,
1498 .get_msglevel = rtl8169_get_msglevel,
1499 .set_msglevel = rtl8169_set_msglevel,
1500 .get_rx_csum = rtl8169_get_rx_csum,
1501 .set_rx_csum = rtl8169_set_rx_csum,
1502 .set_tx_csum = ethtool_op_set_tx_csum,
1503 .set_sg = ethtool_op_set_sg,
1504 .set_tso = ethtool_op_set_tso,
1505 .get_regs = rtl8169_get_regs,
1506 .get_wol = rtl8169_get_wol,
1507 .set_wol = rtl8169_set_wol,
1508 .get_strings = rtl8169_get_strings,
1509 .get_sset_count = rtl8169_get_sset_count,
1510 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1513 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1514 void __iomem *ioaddr)
1517 * The driver currently handles the 8168Bf and the 8168Be identically
1518 * but they can be identified more specifically through the test below
1521 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1523 * Same thing for the 8101Eb and the 8101Ec:
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1527 static const struct {
1533 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1534 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1535 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1537 /* 8168DP family. */
1538 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1539 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1542 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1543 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1544 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1545 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1546 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1547 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1548 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1549 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1550 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1553 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1554 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1555 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1556 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1559 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1560 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1561 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1562 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1563 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1564 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1565 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1566 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1567 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1568 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1569 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1570 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1571 /* FIXME: where did these entries come from ? -- FR */
1572 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1573 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1576 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1577 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1578 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1579 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1580 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1581 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1584 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1588 reg = RTL_R32(TxConfig);
1589 while ((reg & p->mask) != p->val)
1591 tp->mac_version = p->mac_version;
1594 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1596 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1604 static void rtl_writephy_batch(struct rtl8169_private *tp,
1605 const struct phy_reg *regs, int len)
1608 rtl_writephy(tp, regs->reg, regs->val);
1613 #define PHY_READ 0x00000000
1614 #define PHY_DATA_OR 0x10000000
1615 #define PHY_DATA_AND 0x20000000
1616 #define PHY_BJMPN 0x30000000
1617 #define PHY_READ_EFUSE 0x40000000
1618 #define PHY_READ_MAC_BYTE 0x50000000
1619 #define PHY_WRITE_MAC_BYTE 0x60000000
1620 #define PHY_CLEAR_READCOUNT 0x70000000
1621 #define PHY_WRITE 0x80000000
1622 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1623 #define PHY_COMP_EQ_SKIPN 0xa0000000
1624 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1625 #define PHY_WRITE_PREVIOUS 0xc0000000
1626 #define PHY_SKIPN 0xd0000000
1627 #define PHY_DELAY_MS 0xe0000000
1628 #define PHY_WRITE_ERI_WORD 0xf0000000
1631 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1633 __le32 *phytable = (__le32 *)fw->data;
1634 struct net_device *dev = tp->dev;
1637 if (fw->size % sizeof(*phytable)) {
1638 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1642 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1643 u32 action = le32_to_cpu(phytable[i]);
1648 if ((action & 0xf0000000) != PHY_WRITE) {
1649 netif_err(tp, probe, dev,
1650 "unknown action 0x%08x\n", action);
1656 u32 action = le32_to_cpu(*phytable);
1657 u32 data = action & 0x0000ffff;
1658 u32 reg = (action & 0x0fff0000) >> 16;
1660 switch(action & 0xf0000000) {
1662 rtl_writephy(tp, reg, data);
1671 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1673 static const struct phy_reg phy_reg_init[] = {
1735 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1738 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1740 static const struct phy_reg phy_reg_init[] = {
1746 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1749 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1751 struct pci_dev *pdev = tp->pci_dev;
1752 u16 vendor_id, device_id;
1754 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1755 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1757 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1760 rtl_writephy(tp, 0x1f, 0x0001);
1761 rtl_writephy(tp, 0x10, 0xf01b);
1762 rtl_writephy(tp, 0x1f, 0x0000);
1765 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1767 static const struct phy_reg phy_reg_init[] = {
1807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1809 rtl8169scd_hw_phy_config_quirk(tp);
1812 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1814 static const struct phy_reg phy_reg_init[] = {
1862 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1865 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1867 static const struct phy_reg phy_reg_init[] = {
1872 rtl_writephy(tp, 0x1f, 0x0001);
1873 rtl_patchphy(tp, 0x16, 1 << 0);
1875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1878 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1880 static const struct phy_reg phy_reg_init[] = {
1886 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1889 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
1891 static const struct phy_reg phy_reg_init[] = {
1899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1902 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
1904 static const struct phy_reg phy_reg_init[] = {
1910 rtl_writephy(tp, 0x1f, 0x0000);
1911 rtl_patchphy(tp, 0x14, 1 << 5);
1912 rtl_patchphy(tp, 0x0d, 1 << 5);
1914 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1917 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
1919 static const struct phy_reg phy_reg_init[] = {
1939 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1941 rtl_patchphy(tp, 0x14, 1 << 5);
1942 rtl_patchphy(tp, 0x0d, 1 << 5);
1943 rtl_writephy(tp, 0x1f, 0x0000);
1946 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
1948 static const struct phy_reg phy_reg_init[] = {
1966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1968 rtl_patchphy(tp, 0x16, 1 << 0);
1969 rtl_patchphy(tp, 0x14, 1 << 5);
1970 rtl_patchphy(tp, 0x0d, 1 << 5);
1971 rtl_writephy(tp, 0x1f, 0x0000);
1974 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
1976 static const struct phy_reg phy_reg_init[] = {
1988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1990 rtl_patchphy(tp, 0x16, 1 << 0);
1991 rtl_patchphy(tp, 0x14, 1 << 5);
1992 rtl_patchphy(tp, 0x0d, 1 << 5);
1993 rtl_writephy(tp, 0x1f, 0x0000);
1996 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
1998 rtl8168c_3_hw_phy_config(tp);
2001 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2003 static const struct phy_reg phy_reg_init_0[] = {
2004 /* Channel Estimation */
2025 * enhance line driver power
2034 * Can not link to 1Gbps with bad cable
2035 * Decrease SNR threshold form 21.07dB to 19.04dB
2043 void __iomem *ioaddr = tp->mmio_addr;
2044 const struct firmware *fw;
2046 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2050 * Fine Tune Switching regulator parameter
2052 rtl_writephy(tp, 0x1f, 0x0002);
2053 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2054 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2056 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2057 static const struct phy_reg phy_reg_init[] = {
2067 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2069 val = rtl_readphy(tp, 0x0d);
2071 if ((val & 0x00ff) != 0x006c) {
2072 static const u32 set[] = {
2073 0x0065, 0x0066, 0x0067, 0x0068,
2074 0x0069, 0x006a, 0x006b, 0x006c
2078 rtl_writephy(tp, 0x1f, 0x0002);
2081 for (i = 0; i < ARRAY_SIZE(set); i++)
2082 rtl_writephy(tp, 0x0d, val | set[i]);
2085 static const struct phy_reg phy_reg_init[] = {
2093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2096 /* RSET couple improve */
2097 rtl_writephy(tp, 0x1f, 0x0002);
2098 rtl_patchphy(tp, 0x0d, 0x0300);
2099 rtl_patchphy(tp, 0x0f, 0x0010);
2101 /* Fine tune PLL performance */
2102 rtl_writephy(tp, 0x1f, 0x0002);
2103 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2104 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2106 rtl_writephy(tp, 0x1f, 0x0005);
2107 rtl_writephy(tp, 0x05, 0x001b);
2108 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
2109 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2110 rtl_phy_write_fw(tp, fw);
2111 release_firmware(fw);
2113 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2116 rtl_writephy(tp, 0x1f, 0x0000);
2119 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2121 static const struct phy_reg phy_reg_init_0[] = {
2122 /* Channel Estimation */
2143 * enhance line driver power
2152 * Can not link to 1Gbps with bad cable
2153 * Decrease SNR threshold form 21.07dB to 19.04dB
2161 void __iomem *ioaddr = tp->mmio_addr;
2162 const struct firmware *fw;
2164 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2166 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2167 static const struct phy_reg phy_reg_init[] = {
2178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2180 val = rtl_readphy(tp, 0x0d);
2181 if ((val & 0x00ff) != 0x006c) {
2182 static const u32 set[] = {
2183 0x0065, 0x0066, 0x0067, 0x0068,
2184 0x0069, 0x006a, 0x006b, 0x006c
2188 rtl_writephy(tp, 0x1f, 0x0002);
2191 for (i = 0; i < ARRAY_SIZE(set); i++)
2192 rtl_writephy(tp, 0x0d, val | set[i]);
2195 static const struct phy_reg phy_reg_init[] = {
2203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2206 /* Fine tune PLL performance */
2207 rtl_writephy(tp, 0x1f, 0x0002);
2208 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2209 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2211 /* Switching regulator Slew rate */
2212 rtl_writephy(tp, 0x1f, 0x0002);
2213 rtl_patchphy(tp, 0x0f, 0x0017);
2215 rtl_writephy(tp, 0x1f, 0x0005);
2216 rtl_writephy(tp, 0x05, 0x001b);
2217 if (rtl_readphy(tp, 0x06) == 0xb300 &&
2218 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2219 rtl_phy_write_fw(tp, fw);
2220 release_firmware(fw);
2222 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2225 rtl_writephy(tp, 0x1f, 0x0000);
2228 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2230 static const struct phy_reg phy_reg_init[] = {
2286 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2289 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2291 static const struct phy_reg phy_reg_init[] = {
2301 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2302 rtl_patchphy(tp, 0x0d, 1 << 5);
2305 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2307 static const struct phy_reg phy_reg_init[] = {
2314 rtl_writephy(tp, 0x1f, 0x0000);
2315 rtl_patchphy(tp, 0x11, 1 << 12);
2316 rtl_patchphy(tp, 0x19, 1 << 13);
2317 rtl_patchphy(tp, 0x10, 1 << 15);
2319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2322 static void rtl_hw_phy_config(struct net_device *dev)
2324 struct rtl8169_private *tp = netdev_priv(dev);
2326 rtl8169_print_mac_version(tp);
2328 switch (tp->mac_version) {
2329 case RTL_GIGA_MAC_VER_01:
2331 case RTL_GIGA_MAC_VER_02:
2332 case RTL_GIGA_MAC_VER_03:
2333 rtl8169s_hw_phy_config(tp);
2335 case RTL_GIGA_MAC_VER_04:
2336 rtl8169sb_hw_phy_config(tp);
2338 case RTL_GIGA_MAC_VER_05:
2339 rtl8169scd_hw_phy_config(tp);
2341 case RTL_GIGA_MAC_VER_06:
2342 rtl8169sce_hw_phy_config(tp);
2344 case RTL_GIGA_MAC_VER_07:
2345 case RTL_GIGA_MAC_VER_08:
2346 case RTL_GIGA_MAC_VER_09:
2347 rtl8102e_hw_phy_config(tp);
2349 case RTL_GIGA_MAC_VER_11:
2350 rtl8168bb_hw_phy_config(tp);
2352 case RTL_GIGA_MAC_VER_12:
2353 rtl8168bef_hw_phy_config(tp);
2355 case RTL_GIGA_MAC_VER_17:
2356 rtl8168bef_hw_phy_config(tp);
2358 case RTL_GIGA_MAC_VER_18:
2359 rtl8168cp_1_hw_phy_config(tp);
2361 case RTL_GIGA_MAC_VER_19:
2362 rtl8168c_1_hw_phy_config(tp);
2364 case RTL_GIGA_MAC_VER_20:
2365 rtl8168c_2_hw_phy_config(tp);
2367 case RTL_GIGA_MAC_VER_21:
2368 rtl8168c_3_hw_phy_config(tp);
2370 case RTL_GIGA_MAC_VER_22:
2371 rtl8168c_4_hw_phy_config(tp);
2373 case RTL_GIGA_MAC_VER_23:
2374 case RTL_GIGA_MAC_VER_24:
2375 rtl8168cp_2_hw_phy_config(tp);
2377 case RTL_GIGA_MAC_VER_25:
2378 rtl8168d_1_hw_phy_config(tp);
2380 case RTL_GIGA_MAC_VER_26:
2381 rtl8168d_2_hw_phy_config(tp);
2383 case RTL_GIGA_MAC_VER_27:
2384 rtl8168d_3_hw_phy_config(tp);
2386 case RTL_GIGA_MAC_VER_28:
2387 rtl8168d_4_hw_phy_config(tp);
2395 static void rtl8169_phy_timer(unsigned long __opaque)
2397 struct net_device *dev = (struct net_device *)__opaque;
2398 struct rtl8169_private *tp = netdev_priv(dev);
2399 struct timer_list *timer = &tp->timer;
2400 void __iomem *ioaddr = tp->mmio_addr;
2401 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2403 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2405 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2408 spin_lock_irq(&tp->lock);
2410 if (tp->phy_reset_pending(tp)) {
2412 * A busy loop could burn quite a few cycles on nowadays CPU.
2413 * Let's delay the execution of the timer for a few ticks.
2419 if (tp->link_ok(ioaddr))
2422 netif_warn(tp, link, dev, "PHY reset until link up\n");
2424 tp->phy_reset_enable(tp);
2427 mod_timer(timer, jiffies + timeout);
2429 spin_unlock_irq(&tp->lock);
2432 static inline void rtl8169_delete_timer(struct net_device *dev)
2434 struct rtl8169_private *tp = netdev_priv(dev);
2435 struct timer_list *timer = &tp->timer;
2437 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2440 del_timer_sync(timer);
2443 static inline void rtl8169_request_timer(struct net_device *dev)
2445 struct rtl8169_private *tp = netdev_priv(dev);
2446 struct timer_list *timer = &tp->timer;
2448 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2451 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2454 #ifdef CONFIG_NET_POLL_CONTROLLER
2456 * Polling 'interrupt' - used by things like netconsole to send skbs
2457 * without having to re-enable interrupts. It's not called while
2458 * the interrupt routine is executing.
2460 static void rtl8169_netpoll(struct net_device *dev)
2462 struct rtl8169_private *tp = netdev_priv(dev);
2463 struct pci_dev *pdev = tp->pci_dev;
2465 disable_irq(pdev->irq);
2466 rtl8169_interrupt(pdev->irq, dev);
2467 enable_irq(pdev->irq);
2471 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2472 void __iomem *ioaddr)
2475 pci_release_regions(pdev);
2476 pci_clear_mwi(pdev);
2477 pci_disable_device(pdev);
2481 static void rtl8169_phy_reset(struct net_device *dev,
2482 struct rtl8169_private *tp)
2486 tp->phy_reset_enable(tp);
2487 for (i = 0; i < 100; i++) {
2488 if (!tp->phy_reset_pending(tp))
2492 netif_err(tp, link, dev, "PHY reset failed\n");
2495 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2497 void __iomem *ioaddr = tp->mmio_addr;
2499 rtl_hw_phy_config(dev);
2501 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2502 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2506 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2508 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2509 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2511 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2512 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2514 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2515 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2518 rtl8169_phy_reset(dev, tp);
2521 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2522 * only 8101. Don't panic.
2524 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2526 if (RTL_R8(PHYstatus) & TBI_Enable)
2527 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2530 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2532 void __iomem *ioaddr = tp->mmio_addr;
2536 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2537 high = addr[4] | (addr[5] << 8);
2539 spin_lock_irq(&tp->lock);
2541 RTL_W8(Cfg9346, Cfg9346_Unlock);
2543 RTL_W32(MAC4, high);
2549 RTL_W8(Cfg9346, Cfg9346_Lock);
2551 spin_unlock_irq(&tp->lock);
2554 static int rtl_set_mac_address(struct net_device *dev, void *p)
2556 struct rtl8169_private *tp = netdev_priv(dev);
2557 struct sockaddr *addr = p;
2559 if (!is_valid_ether_addr(addr->sa_data))
2560 return -EADDRNOTAVAIL;
2562 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2564 rtl_rar_set(tp, dev->dev_addr);
2569 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2571 struct rtl8169_private *tp = netdev_priv(dev);
2572 struct mii_ioctl_data *data = if_mii(ifr);
2574 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2577 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2581 data->phy_id = 32; /* Internal PHY */
2585 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2589 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2595 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2600 static const struct rtl_cfg_info {
2601 void (*hw_start)(struct net_device *);
2602 unsigned int region;
2608 } rtl_cfg_infos [] = {
2610 .hw_start = rtl_hw_start_8169,
2613 .intr_event = SYSErr | LinkChg | RxOverflow |
2614 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2615 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2616 .features = RTL_FEATURE_GMII,
2617 .default_ver = RTL_GIGA_MAC_VER_01,
2620 .hw_start = rtl_hw_start_8168,
2623 .intr_event = SYSErr | LinkChg | RxOverflow |
2624 TxErr | TxOK | RxOK | RxErr,
2625 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2626 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2627 .default_ver = RTL_GIGA_MAC_VER_11,
2630 .hw_start = rtl_hw_start_8101,
2633 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2634 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2635 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2636 .features = RTL_FEATURE_MSI,
2637 .default_ver = RTL_GIGA_MAC_VER_13,
2641 /* Cfg9346_Unlock assumed. */
2642 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2643 const struct rtl_cfg_info *cfg)
2648 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2649 if (cfg->features & RTL_FEATURE_MSI) {
2650 if (pci_enable_msi(pdev)) {
2651 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2654 msi = RTL_FEATURE_MSI;
2657 RTL_W8(Config2, cfg2);
2661 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2663 if (tp->features & RTL_FEATURE_MSI) {
2664 pci_disable_msi(pdev);
2665 tp->features &= ~RTL_FEATURE_MSI;
2669 static const struct net_device_ops rtl8169_netdev_ops = {
2670 .ndo_open = rtl8169_open,
2671 .ndo_stop = rtl8169_close,
2672 .ndo_get_stats = rtl8169_get_stats,
2673 .ndo_start_xmit = rtl8169_start_xmit,
2674 .ndo_tx_timeout = rtl8169_tx_timeout,
2675 .ndo_validate_addr = eth_validate_addr,
2676 .ndo_change_mtu = rtl8169_change_mtu,
2677 .ndo_set_mac_address = rtl_set_mac_address,
2678 .ndo_do_ioctl = rtl8169_ioctl,
2679 .ndo_set_multicast_list = rtl_set_rx_mode,
2680 #ifdef CONFIG_R8169_VLAN
2681 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2683 #ifdef CONFIG_NET_POLL_CONTROLLER
2684 .ndo_poll_controller = rtl8169_netpoll,
2689 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2691 struct mdio_ops *ops = &tp->mdio_ops;
2693 switch (tp->mac_version) {
2694 case RTL_GIGA_MAC_VER_27:
2695 ops->write = r8168dp_1_mdio_write;
2696 ops->read = r8168dp_1_mdio_read;
2698 case RTL_GIGA_MAC_VER_28:
2699 ops->write = r8168dp_2_mdio_write;
2700 ops->read = r8168dp_2_mdio_read;
2703 ops->write = r8169_mdio_write;
2704 ops->read = r8169_mdio_read;
2709 static void r810x_phy_power_down(struct rtl8169_private *tp)
2711 rtl_writephy(tp, 0x1f, 0x0000);
2712 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2715 static void r810x_phy_power_up(struct rtl8169_private *tp)
2717 rtl_writephy(tp, 0x1f, 0x0000);
2718 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2721 static void r810x_pll_power_down(struct rtl8169_private *tp)
2723 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2724 rtl_writephy(tp, 0x1f, 0x0000);
2725 rtl_writephy(tp, MII_BMCR, 0x0000);
2729 r810x_phy_power_down(tp);
2732 static void r810x_pll_power_up(struct rtl8169_private *tp)
2734 r810x_phy_power_up(tp);
2737 static void r8168_phy_power_up(struct rtl8169_private *tp)
2739 rtl_writephy(tp, 0x1f, 0x0000);
2740 rtl_writephy(tp, 0x0e, 0x0000);
2741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2744 static void r8168_phy_power_down(struct rtl8169_private *tp)
2746 rtl_writephy(tp, 0x1f, 0x0000);
2747 rtl_writephy(tp, 0x0e, 0x0200);
2748 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2751 static void r8168_pll_power_down(struct rtl8169_private *tp)
2753 void __iomem *ioaddr = tp->mmio_addr;
2755 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2758 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2759 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2760 (RTL_R16(CPlusCmd) & ASF)) {
2764 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2765 rtl_writephy(tp, 0x1f, 0x0000);
2766 rtl_writephy(tp, MII_BMCR, 0x0000);
2768 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2769 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2773 r8168_phy_power_down(tp);
2775 switch (tp->mac_version) {
2776 case RTL_GIGA_MAC_VER_25:
2777 case RTL_GIGA_MAC_VER_26:
2778 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2783 static void r8168_pll_power_up(struct rtl8169_private *tp)
2785 void __iomem *ioaddr = tp->mmio_addr;
2787 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2790 switch (tp->mac_version) {
2791 case RTL_GIGA_MAC_VER_25:
2792 case RTL_GIGA_MAC_VER_26:
2793 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2797 r8168_phy_power_up(tp);
2800 static void rtl_pll_power_op(struct rtl8169_private *tp,
2801 void (*op)(struct rtl8169_private *))
2807 static void rtl_pll_power_down(struct rtl8169_private *tp)
2809 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2812 static void rtl_pll_power_up(struct rtl8169_private *tp)
2814 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2817 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2819 struct pll_power_ops *ops = &tp->pll_power_ops;
2821 switch (tp->mac_version) {
2822 case RTL_GIGA_MAC_VER_07:
2823 case RTL_GIGA_MAC_VER_08:
2824 case RTL_GIGA_MAC_VER_09:
2825 case RTL_GIGA_MAC_VER_10:
2826 case RTL_GIGA_MAC_VER_16:
2827 ops->down = r810x_pll_power_down;
2828 ops->up = r810x_pll_power_up;
2831 case RTL_GIGA_MAC_VER_11:
2832 case RTL_GIGA_MAC_VER_12:
2833 case RTL_GIGA_MAC_VER_17:
2834 case RTL_GIGA_MAC_VER_18:
2835 case RTL_GIGA_MAC_VER_19:
2836 case RTL_GIGA_MAC_VER_20:
2837 case RTL_GIGA_MAC_VER_21:
2838 case RTL_GIGA_MAC_VER_22:
2839 case RTL_GIGA_MAC_VER_23:
2840 case RTL_GIGA_MAC_VER_24:
2841 case RTL_GIGA_MAC_VER_25:
2842 case RTL_GIGA_MAC_VER_26:
2843 case RTL_GIGA_MAC_VER_27:
2844 case RTL_GIGA_MAC_VER_28:
2845 ops->down = r8168_pll_power_down;
2846 ops->up = r8168_pll_power_up;
2856 static int __devinit
2857 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2859 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2860 const unsigned int region = cfg->region;
2861 struct rtl8169_private *tp;
2862 struct mii_if_info *mii;
2863 struct net_device *dev;
2864 void __iomem *ioaddr;
2868 if (netif_msg_drv(&debug)) {
2869 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2870 MODULENAME, RTL8169_VERSION);
2873 dev = alloc_etherdev(sizeof (*tp));
2875 if (netif_msg_drv(&debug))
2876 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2881 SET_NETDEV_DEV(dev, &pdev->dev);
2882 dev->netdev_ops = &rtl8169_netdev_ops;
2883 tp = netdev_priv(dev);
2886 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2890 mii->mdio_read = rtl_mdio_read;
2891 mii->mdio_write = rtl_mdio_write;
2892 mii->phy_id_mask = 0x1f;
2893 mii->reg_num_mask = 0x1f;
2894 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2896 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2897 rc = pci_enable_device(pdev);
2899 netif_err(tp, probe, dev, "enable failure\n");
2900 goto err_out_free_dev_1;
2903 if (pci_set_mwi(pdev) < 0)
2904 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2906 /* make sure PCI base addr 1 is MMIO */
2907 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2908 netif_err(tp, probe, dev,
2909 "region #%d not an MMIO resource, aborting\n",
2915 /* check for weird/broken PCI region reporting */
2916 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2917 netif_err(tp, probe, dev,
2918 "Invalid PCI region size(s), aborting\n");
2923 rc = pci_request_regions(pdev, MODULENAME);
2925 netif_err(tp, probe, dev, "could not request regions\n");
2929 tp->cp_cmd = PCIMulRW | RxChkSum;
2931 if ((sizeof(dma_addr_t) > 4) &&
2932 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2933 tp->cp_cmd |= PCIDAC;
2934 dev->features |= NETIF_F_HIGHDMA;
2936 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2938 netif_err(tp, probe, dev, "DMA configuration failed\n");
2939 goto err_out_free_res_3;
2943 /* ioremap MMIO region */
2944 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2946 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2948 goto err_out_free_res_3;
2951 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2953 netif_info(tp, probe, dev, "no PCI Express capability\n");
2955 RTL_W16(IntrMask, 0x0000);
2957 /* Soft reset the chip. */
2958 RTL_W8(ChipCmd, CmdReset);
2960 /* Check that the chip has finished the reset. */
2961 for (i = 0; i < 100; i++) {
2962 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2964 msleep_interruptible(1);
2967 RTL_W16(IntrStatus, 0xffff);
2969 pci_set_master(pdev);
2971 /* Identify chip attached to board */
2972 rtl8169_get_mac_version(tp, ioaddr);
2974 rtl_init_mdio_ops(tp);
2975 rtl_init_pll_power_ops(tp);
2977 /* Use appropriate default if unknown */
2978 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2979 netif_notice(tp, probe, dev,
2980 "unknown MAC, using family default\n");
2981 tp->mac_version = cfg->default_ver;
2984 rtl8169_print_mac_version(tp);
2986 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2987 if (tp->mac_version == rtl_chip_info[i].mac_version)
2990 if (i == ARRAY_SIZE(rtl_chip_info)) {
2992 "driver bug, MAC version not found in rtl_chip_info\n");
2997 RTL_W8(Cfg9346, Cfg9346_Unlock);
2998 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2999 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3000 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3001 tp->features |= RTL_FEATURE_WOL;
3002 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3003 tp->features |= RTL_FEATURE_WOL;
3004 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3005 RTL_W8(Cfg9346, Cfg9346_Lock);
3007 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3008 (RTL_R8(PHYstatus) & TBI_Enable)) {
3009 tp->set_speed = rtl8169_set_speed_tbi;
3010 tp->get_settings = rtl8169_gset_tbi;
3011 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3012 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3013 tp->link_ok = rtl8169_tbi_link_ok;
3014 tp->do_ioctl = rtl_tbi_ioctl;
3016 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3018 tp->set_speed = rtl8169_set_speed_xmii;
3019 tp->get_settings = rtl8169_gset_xmii;
3020 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3021 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3022 tp->link_ok = rtl8169_xmii_link_ok;
3023 tp->do_ioctl = rtl_xmii_ioctl;
3026 spin_lock_init(&tp->lock);
3028 tp->mmio_addr = ioaddr;
3030 /* Get MAC address */
3031 for (i = 0; i < MAC_ADDR_LEN; i++)
3032 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3033 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3035 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3036 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3037 dev->irq = pdev->irq;
3038 dev->base_addr = (unsigned long) ioaddr;
3040 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3042 #ifdef CONFIG_R8169_VLAN
3043 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3045 dev->features |= NETIF_F_GRO;
3047 tp->intr_mask = 0xffff;
3048 tp->hw_start = cfg->hw_start;
3049 tp->intr_event = cfg->intr_event;
3050 tp->napi_event = cfg->napi_event;
3052 init_timer(&tp->timer);
3053 tp->timer.data = (unsigned long) dev;
3054 tp->timer.function = rtl8169_phy_timer;
3056 rc = register_netdev(dev);
3060 pci_set_drvdata(pdev, dev);
3062 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3063 rtl_chip_info[tp->chipset].name,
3064 dev->base_addr, dev->dev_addr,
3065 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3067 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3068 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3069 rtl8168_driver_start(tp);
3072 rtl8169_init_phy(dev, tp);
3075 * Pretend we are using VLANs; This bypasses a nasty bug where
3076 * Interrupts stop flowing on high load on 8110SCd controllers.
3078 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3079 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3081 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3083 if (pci_dev_run_wake(pdev))
3084 pm_runtime_put_noidle(&pdev->dev);
3090 rtl_disable_msi(pdev, tp);
3093 pci_release_regions(pdev);
3095 pci_clear_mwi(pdev);
3096 pci_disable_device(pdev);
3102 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3104 struct net_device *dev = pci_get_drvdata(pdev);
3105 struct rtl8169_private *tp = netdev_priv(dev);
3107 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3108 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3109 rtl8168_driver_stop(tp);
3112 cancel_delayed_work_sync(&tp->task);
3114 unregister_netdev(dev);
3116 if (pci_dev_run_wake(pdev))
3117 pm_runtime_get_noresume(&pdev->dev);
3119 /* restore original MAC address */
3120 rtl_rar_set(tp, dev->perm_addr);
3122 rtl_disable_msi(pdev, tp);
3123 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3124 pci_set_drvdata(pdev, NULL);
3127 static int rtl8169_open(struct net_device *dev)
3129 struct rtl8169_private *tp = netdev_priv(dev);
3130 struct pci_dev *pdev = tp->pci_dev;
3131 int retval = -ENOMEM;
3133 pm_runtime_get_sync(&pdev->dev);
3136 * Rx and Tx desscriptors needs 256 bytes alignment.
3137 * dma_alloc_coherent provides more.
3139 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3140 &tp->TxPhyAddr, GFP_KERNEL);
3141 if (!tp->TxDescArray)
3142 goto err_pm_runtime_put;
3144 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3145 &tp->RxPhyAddr, GFP_KERNEL);
3146 if (!tp->RxDescArray)
3149 retval = rtl8169_init_ring(dev);
3153 INIT_DELAYED_WORK(&tp->task, NULL);
3157 retval = request_irq(dev->irq, rtl8169_interrupt,
3158 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3161 goto err_release_ring_2;
3163 napi_enable(&tp->napi);
3165 rtl_pll_power_up(tp);
3169 rtl8169_request_timer(dev);
3171 tp->saved_wolopts = 0;
3172 pm_runtime_put_noidle(&pdev->dev);
3174 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3179 rtl8169_rx_clear(tp);
3181 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3183 tp->RxDescArray = NULL;
3185 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3187 tp->TxDescArray = NULL;
3189 pm_runtime_put_noidle(&pdev->dev);
3193 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3195 void __iomem *ioaddr = tp->mmio_addr;
3197 /* Disable interrupts */
3198 rtl8169_irq_mask_and_ack(ioaddr);
3200 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3201 while (RTL_R8(TxPoll) & NPQ)
3206 /* Reset the chipset */
3207 RTL_W8(ChipCmd, CmdReset);
3213 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3215 void __iomem *ioaddr = tp->mmio_addr;
3216 u32 cfg = rtl8169_rx_config;
3218 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3219 RTL_W32(RxConfig, cfg);
3221 /* Set DMA burst size and Interframe Gap Time */
3222 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3223 (InterFrameGap << TxInterFrameGapShift));
3226 static void rtl_hw_start(struct net_device *dev)
3228 struct rtl8169_private *tp = netdev_priv(dev);
3229 void __iomem *ioaddr = tp->mmio_addr;
3232 /* Soft reset the chip. */
3233 RTL_W8(ChipCmd, CmdReset);
3235 /* Check that the chip has finished the reset. */
3236 for (i = 0; i < 100; i++) {
3237 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3239 msleep_interruptible(1);
3244 netif_start_queue(dev);
3248 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3249 void __iomem *ioaddr)
3252 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3253 * register to be written before TxDescAddrLow to work.
3254 * Switching from MMIO to I/O access fixes the issue as well.
3256 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3257 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3258 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3259 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3262 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3266 cmd = RTL_R16(CPlusCmd);
3267 RTL_W16(CPlusCmd, cmd);
3271 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3273 /* Low hurts. Let's disable the filtering. */
3274 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3277 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3279 static const struct {
3284 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3285 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3286 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3287 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3292 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3293 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3294 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3295 RTL_W32(0x7c, p->val);
3301 static void rtl_hw_start_8169(struct net_device *dev)
3303 struct rtl8169_private *tp = netdev_priv(dev);
3304 void __iomem *ioaddr = tp->mmio_addr;
3305 struct pci_dev *pdev = tp->pci_dev;
3307 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3308 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3309 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3312 RTL_W8(Cfg9346, Cfg9346_Unlock);
3313 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3314 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3315 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3316 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3317 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3319 RTL_W8(EarlyTxThres, NoEarlyTx);
3321 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3323 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3324 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3325 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3326 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3327 rtl_set_rx_tx_config_registers(tp);
3329 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3331 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3332 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3333 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3334 "Bit-3 and bit-14 MUST be 1\n");
3335 tp->cp_cmd |= (1 << 14);
3338 RTL_W16(CPlusCmd, tp->cp_cmd);
3340 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3343 * Undocumented corner. Supposedly:
3344 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3346 RTL_W16(IntrMitigate, 0x0000);
3348 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3350 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3351 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3352 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3353 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3354 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3355 rtl_set_rx_tx_config_registers(tp);
3358 RTL_W8(Cfg9346, Cfg9346_Lock);
3360 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3363 RTL_W32(RxMissed, 0);
3365 rtl_set_rx_mode(dev);
3367 /* no early-rx interrupts */
3368 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3370 /* Enable all known interrupts by setting the interrupt mask. */
3371 RTL_W16(IntrMask, tp->intr_event);
3374 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3376 struct net_device *dev = pci_get_drvdata(pdev);
3377 struct rtl8169_private *tp = netdev_priv(dev);
3378 int cap = tp->pcie_cap;
3383 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3384 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3385 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3389 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3393 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3394 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3397 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3399 rtl_csi_access_enable(ioaddr, 0x17000000);
3402 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3404 rtl_csi_access_enable(ioaddr, 0x27000000);
3408 unsigned int offset;
3413 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3418 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3419 rtl_ephy_write(ioaddr, e->offset, w);
3424 static void rtl_disable_clock_request(struct pci_dev *pdev)
3426 struct net_device *dev = pci_get_drvdata(pdev);
3427 struct rtl8169_private *tp = netdev_priv(dev);
3428 int cap = tp->pcie_cap;
3433 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3434 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3435 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3439 static void rtl_enable_clock_request(struct pci_dev *pdev)
3441 struct net_device *dev = pci_get_drvdata(pdev);
3442 struct rtl8169_private *tp = netdev_priv(dev);
3443 int cap = tp->pcie_cap;
3448 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3449 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3450 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3454 #define R8168_CPCMD_QUIRK_MASK (\
3465 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3467 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3469 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3471 rtl_tx_performance_tweak(pdev,
3472 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3475 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3477 rtl_hw_start_8168bb(ioaddr, pdev);
3479 RTL_W8(MaxTxPacketSize, TxPacketMax);
3481 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3484 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3486 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3488 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3490 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3492 rtl_disable_clock_request(pdev);
3494 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3497 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3499 static const struct ephy_info e_info_8168cp[] = {
3500 { 0x01, 0, 0x0001 },
3501 { 0x02, 0x0800, 0x1000 },
3502 { 0x03, 0, 0x0042 },
3503 { 0x06, 0x0080, 0x0000 },
3507 rtl_csi_access_enable_2(ioaddr);
3509 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3511 __rtl_hw_start_8168cp(ioaddr, pdev);
3514 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3516 rtl_csi_access_enable_2(ioaddr);
3518 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3520 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3522 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3525 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3527 rtl_csi_access_enable_2(ioaddr);
3529 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3532 RTL_W8(DBG_REG, 0x20);
3534 RTL_W8(MaxTxPacketSize, TxPacketMax);
3536 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3538 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3541 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3543 static const struct ephy_info e_info_8168c_1[] = {
3544 { 0x02, 0x0800, 0x1000 },
3545 { 0x03, 0, 0x0002 },
3546 { 0x06, 0x0080, 0x0000 }
3549 rtl_csi_access_enable_2(ioaddr);
3551 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3553 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3555 __rtl_hw_start_8168cp(ioaddr, pdev);
3558 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3560 static const struct ephy_info e_info_8168c_2[] = {
3561 { 0x01, 0, 0x0001 },
3562 { 0x03, 0x0400, 0x0220 }
3565 rtl_csi_access_enable_2(ioaddr);
3567 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3569 __rtl_hw_start_8168cp(ioaddr, pdev);
3572 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3574 rtl_hw_start_8168c_2(ioaddr, pdev);
3577 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3579 rtl_csi_access_enable_2(ioaddr);
3581 __rtl_hw_start_8168cp(ioaddr, pdev);
3584 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3586 rtl_csi_access_enable_2(ioaddr);
3588 rtl_disable_clock_request(pdev);
3590 RTL_W8(MaxTxPacketSize, TxPacketMax);
3592 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3597 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3599 static const struct ephy_info e_info_8168d_4[] = {
3601 { 0x19, 0x20, 0x50 },
3606 rtl_csi_access_enable_1(ioaddr);
3608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3610 RTL_W8(MaxTxPacketSize, TxPacketMax);
3612 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3613 const struct ephy_info *e = e_info_8168d_4 + i;
3616 w = rtl_ephy_read(ioaddr, e->offset);
3617 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3620 rtl_enable_clock_request(pdev);
3623 static void rtl_hw_start_8168(struct net_device *dev)
3625 struct rtl8169_private *tp = netdev_priv(dev);
3626 void __iomem *ioaddr = tp->mmio_addr;
3627 struct pci_dev *pdev = tp->pci_dev;
3629 RTL_W8(Cfg9346, Cfg9346_Unlock);
3631 RTL_W8(MaxTxPacketSize, TxPacketMax);
3633 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3635 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3637 RTL_W16(CPlusCmd, tp->cp_cmd);
3639 RTL_W16(IntrMitigate, 0x5151);
3641 /* Work around for RxFIFO overflow. */
3642 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3643 tp->intr_event |= RxFIFOOver | PCSTimeout;
3644 tp->intr_event &= ~RxOverflow;
3647 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3649 rtl_set_rx_mode(dev);
3651 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3652 (InterFrameGap << TxInterFrameGapShift));
3656 switch (tp->mac_version) {
3657 case RTL_GIGA_MAC_VER_11:
3658 rtl_hw_start_8168bb(ioaddr, pdev);
3661 case RTL_GIGA_MAC_VER_12:
3662 case RTL_GIGA_MAC_VER_17:
3663 rtl_hw_start_8168bef(ioaddr, pdev);
3666 case RTL_GIGA_MAC_VER_18:
3667 rtl_hw_start_8168cp_1(ioaddr, pdev);
3670 case RTL_GIGA_MAC_VER_19:
3671 rtl_hw_start_8168c_1(ioaddr, pdev);
3674 case RTL_GIGA_MAC_VER_20:
3675 rtl_hw_start_8168c_2(ioaddr, pdev);
3678 case RTL_GIGA_MAC_VER_21:
3679 rtl_hw_start_8168c_3(ioaddr, pdev);
3682 case RTL_GIGA_MAC_VER_22:
3683 rtl_hw_start_8168c_4(ioaddr, pdev);
3686 case RTL_GIGA_MAC_VER_23:
3687 rtl_hw_start_8168cp_2(ioaddr, pdev);
3690 case RTL_GIGA_MAC_VER_24:
3691 rtl_hw_start_8168cp_3(ioaddr, pdev);
3694 case RTL_GIGA_MAC_VER_25:
3695 case RTL_GIGA_MAC_VER_26:
3696 case RTL_GIGA_MAC_VER_27:
3697 rtl_hw_start_8168d(ioaddr, pdev);
3700 case RTL_GIGA_MAC_VER_28:
3701 rtl_hw_start_8168d_4(ioaddr, pdev);
3705 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3706 dev->name, tp->mac_version);
3710 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3712 RTL_W8(Cfg9346, Cfg9346_Lock);
3714 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3716 RTL_W16(IntrMask, tp->intr_event);
3719 #define R810X_CPCMD_QUIRK_MASK (\
3731 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3733 static const struct ephy_info e_info_8102e_1[] = {
3734 { 0x01, 0, 0x6e65 },
3735 { 0x02, 0, 0x091f },
3736 { 0x03, 0, 0xc2f9 },
3737 { 0x06, 0, 0xafb5 },
3738 { 0x07, 0, 0x0e00 },
3739 { 0x19, 0, 0xec80 },
3740 { 0x01, 0, 0x2e65 },
3745 rtl_csi_access_enable_2(ioaddr);
3747 RTL_W8(DBG_REG, FIX_NAK_1);
3749 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3752 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3753 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3755 cfg1 = RTL_R8(Config1);
3756 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3757 RTL_W8(Config1, cfg1 & ~LEDS0);
3759 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3761 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3764 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3766 rtl_csi_access_enable_2(ioaddr);
3768 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3770 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3771 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3773 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3776 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3778 rtl_hw_start_8102e_2(ioaddr, pdev);
3780 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3783 static void rtl_hw_start_8101(struct net_device *dev)
3785 struct rtl8169_private *tp = netdev_priv(dev);
3786 void __iomem *ioaddr = tp->mmio_addr;
3787 struct pci_dev *pdev = tp->pci_dev;
3789 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3790 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3791 int cap = tp->pcie_cap;
3794 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3795 PCI_EXP_DEVCTL_NOSNOOP_EN);
3799 switch (tp->mac_version) {
3800 case RTL_GIGA_MAC_VER_07:
3801 rtl_hw_start_8102e_1(ioaddr, pdev);
3804 case RTL_GIGA_MAC_VER_08:
3805 rtl_hw_start_8102e_3(ioaddr, pdev);
3808 case RTL_GIGA_MAC_VER_09:
3809 rtl_hw_start_8102e_2(ioaddr, pdev);
3813 RTL_W8(Cfg9346, Cfg9346_Unlock);
3815 RTL_W8(MaxTxPacketSize, TxPacketMax);
3817 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3819 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3821 RTL_W16(CPlusCmd, tp->cp_cmd);
3823 RTL_W16(IntrMitigate, 0x0000);
3825 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3827 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3828 rtl_set_rx_tx_config_registers(tp);
3830 RTL_W8(Cfg9346, Cfg9346_Lock);
3834 rtl_set_rx_mode(dev);
3836 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3838 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3840 RTL_W16(IntrMask, tp->intr_event);
3843 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3845 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3852 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3854 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3855 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3858 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3859 void **data_buff, struct RxDesc *desc)
3861 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3866 rtl8169_make_unusable_by_asic(desc);
3869 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3871 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3873 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3876 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3879 desc->addr = cpu_to_le64(mapping);
3881 rtl8169_mark_to_asic(desc, rx_buf_sz);
3884 static inline void *rtl8169_align(void *data)
3886 return (void *)ALIGN((long)data, 16);
3889 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3890 struct RxDesc *desc)
3894 struct device *d = &tp->pci_dev->dev;
3895 struct net_device *dev = tp->dev;
3896 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3898 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3902 if (rtl8169_align(data) != data) {
3904 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3909 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3911 if (unlikely(dma_mapping_error(d, mapping))) {
3912 if (net_ratelimit())
3913 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3917 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3925 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3929 for (i = 0; i < NUM_RX_DESC; i++) {
3930 if (tp->Rx_databuff[i]) {
3931 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3932 tp->RxDescArray + i);
3937 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3939 desc->opts1 |= cpu_to_le32(RingEnd);
3942 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3946 for (i = 0; i < NUM_RX_DESC; i++) {
3949 if (tp->Rx_databuff[i])
3952 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3954 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3957 tp->Rx_databuff[i] = data;
3960 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3964 rtl8169_rx_clear(tp);
3968 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3970 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3973 static int rtl8169_init_ring(struct net_device *dev)
3975 struct rtl8169_private *tp = netdev_priv(dev);
3977 rtl8169_init_ring_indexes(tp);
3979 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3980 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3982 return rtl8169_rx_fill(tp);
3985 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3986 struct TxDesc *desc)
3988 unsigned int len = tx_skb->len;
3990 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3998 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4003 for (i = 0; i < n; i++) {
4004 unsigned int entry = (start + i) % NUM_TX_DESC;
4005 struct ring_info *tx_skb = tp->tx_skb + entry;
4006 unsigned int len = tx_skb->len;
4009 struct sk_buff *skb = tx_skb->skb;
4011 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4012 tp->TxDescArray + entry);
4014 tp->dev->stats.tx_dropped++;
4022 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4024 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4025 tp->cur_tx = tp->dirty_tx = 0;
4028 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4030 struct rtl8169_private *tp = netdev_priv(dev);
4032 PREPARE_DELAYED_WORK(&tp->task, task);
4033 schedule_delayed_work(&tp->task, 4);
4036 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4038 struct rtl8169_private *tp = netdev_priv(dev);
4039 void __iomem *ioaddr = tp->mmio_addr;
4041 synchronize_irq(dev->irq);
4043 /* Wait for any pending NAPI task to complete */
4044 napi_disable(&tp->napi);
4046 rtl8169_irq_mask_and_ack(ioaddr);
4048 tp->intr_mask = 0xffff;
4049 RTL_W16(IntrMask, tp->intr_event);
4050 napi_enable(&tp->napi);
4053 static void rtl8169_reinit_task(struct work_struct *work)
4055 struct rtl8169_private *tp =
4056 container_of(work, struct rtl8169_private, task.work);
4057 struct net_device *dev = tp->dev;
4062 if (!netif_running(dev))
4065 rtl8169_wait_for_quiescence(dev);
4068 ret = rtl8169_open(dev);
4069 if (unlikely(ret < 0)) {
4070 if (net_ratelimit())
4071 netif_err(tp, drv, dev,
4072 "reinit failure (status = %d). Rescheduling\n",
4074 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4081 static void rtl8169_reset_task(struct work_struct *work)
4083 struct rtl8169_private *tp =
4084 container_of(work, struct rtl8169_private, task.work);
4085 struct net_device *dev = tp->dev;
4089 if (!netif_running(dev))
4092 rtl8169_wait_for_quiescence(dev);
4094 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4095 rtl8169_tx_clear(tp);
4097 if (tp->dirty_rx == tp->cur_rx) {
4098 rtl8169_init_ring_indexes(tp);
4100 netif_wake_queue(dev);
4101 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4103 if (net_ratelimit())
4104 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4105 rtl8169_schedule_work(dev, rtl8169_reset_task);
4112 static void rtl8169_tx_timeout(struct net_device *dev)
4114 struct rtl8169_private *tp = netdev_priv(dev);
4116 rtl8169_hw_reset(tp);
4118 /* Let's wait a bit while any (async) irq lands on */
4119 rtl8169_schedule_work(dev, rtl8169_reset_task);
4122 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4125 struct skb_shared_info *info = skb_shinfo(skb);
4126 unsigned int cur_frag, entry;
4127 struct TxDesc * uninitialized_var(txd);
4128 struct device *d = &tp->pci_dev->dev;
4131 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4132 skb_frag_t *frag = info->frags + cur_frag;
4137 entry = (entry + 1) % NUM_TX_DESC;
4139 txd = tp->TxDescArray + entry;
4141 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4142 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4143 if (unlikely(dma_mapping_error(d, mapping))) {
4144 if (net_ratelimit())
4145 netif_err(tp, drv, tp->dev,
4146 "Failed to map TX fragments DMA!\n");
4150 /* anti gcc 2.95.3 bugware (sic) */
4151 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4153 txd->opts1 = cpu_to_le32(status);
4154 txd->addr = cpu_to_le64(mapping);
4156 tp->tx_skb[entry].len = len;
4160 tp->tx_skb[entry].skb = skb;
4161 txd->opts1 |= cpu_to_le32(LastFrag);
4167 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4171 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4173 if (dev->features & NETIF_F_TSO) {
4174 u32 mss = skb_shinfo(skb)->gso_size;
4177 return LargeSend | ((mss & MSSMask) << MSSShift);
4179 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4180 const struct iphdr *ip = ip_hdr(skb);
4182 if (ip->protocol == IPPROTO_TCP)
4183 return IPCS | TCPCS;
4184 else if (ip->protocol == IPPROTO_UDP)
4185 return IPCS | UDPCS;
4186 WARN_ON(1); /* we need a WARN() */
4191 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4192 struct net_device *dev)
4194 struct rtl8169_private *tp = netdev_priv(dev);
4195 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4196 struct TxDesc *txd = tp->TxDescArray + entry;
4197 void __iomem *ioaddr = tp->mmio_addr;
4198 struct device *d = &tp->pci_dev->dev;
4204 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4205 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4209 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4212 len = skb_headlen(skb);
4213 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4214 if (unlikely(dma_mapping_error(d, mapping))) {
4215 if (net_ratelimit())
4216 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4220 tp->tx_skb[entry].len = len;
4221 txd->addr = cpu_to_le64(mapping);
4222 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4224 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4226 frags = rtl8169_xmit_frags(tp, skb, opts1);
4232 opts1 |= FirstFrag | LastFrag;
4233 tp->tx_skb[entry].skb = skb;
4238 /* anti gcc 2.95.3 bugware (sic) */
4239 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4240 txd->opts1 = cpu_to_le32(status);
4242 tp->cur_tx += frags + 1;
4246 RTL_W8(TxPoll, NPQ); /* set polling bit */
4248 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4249 netif_stop_queue(dev);
4251 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4252 netif_wake_queue(dev);
4255 return NETDEV_TX_OK;
4258 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4261 dev->stats.tx_dropped++;
4262 return NETDEV_TX_OK;
4265 netif_stop_queue(dev);
4266 dev->stats.tx_dropped++;
4267 return NETDEV_TX_BUSY;
4270 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4272 struct rtl8169_private *tp = netdev_priv(dev);
4273 struct pci_dev *pdev = tp->pci_dev;
4274 u16 pci_status, pci_cmd;
4276 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4277 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4279 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4280 pci_cmd, pci_status);
4283 * The recovery sequence below admits a very elaborated explanation:
4284 * - it seems to work;
4285 * - I did not see what else could be done;
4286 * - it makes iop3xx happy.
4288 * Feel free to adjust to your needs.
4290 if (pdev->broken_parity_status)
4291 pci_cmd &= ~PCI_COMMAND_PARITY;
4293 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4295 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4297 pci_write_config_word(pdev, PCI_STATUS,
4298 pci_status & (PCI_STATUS_DETECTED_PARITY |
4299 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4300 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4302 /* The infamous DAC f*ckup only happens at boot time */
4303 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4304 void __iomem *ioaddr = tp->mmio_addr;
4306 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4307 tp->cp_cmd &= ~PCIDAC;
4308 RTL_W16(CPlusCmd, tp->cp_cmd);
4309 dev->features &= ~NETIF_F_HIGHDMA;
4312 rtl8169_hw_reset(tp);
4314 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4317 static void rtl8169_tx_interrupt(struct net_device *dev,
4318 struct rtl8169_private *tp,
4319 void __iomem *ioaddr)
4321 unsigned int dirty_tx, tx_left;
4323 dirty_tx = tp->dirty_tx;
4325 tx_left = tp->cur_tx - dirty_tx;
4327 while (tx_left > 0) {
4328 unsigned int entry = dirty_tx % NUM_TX_DESC;
4329 struct ring_info *tx_skb = tp->tx_skb + entry;
4333 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4334 if (status & DescOwn)
4337 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4338 tp->TxDescArray + entry);
4339 if (status & LastFrag) {
4340 dev->stats.tx_packets++;
4341 dev->stats.tx_bytes += tx_skb->skb->len;
4342 dev_kfree_skb(tx_skb->skb);
4349 if (tp->dirty_tx != dirty_tx) {
4350 tp->dirty_tx = dirty_tx;
4352 if (netif_queue_stopped(dev) &&
4353 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4354 netif_wake_queue(dev);
4357 * 8168 hack: TxPoll requests are lost when the Tx packets are
4358 * too close. Let's kick an extra TxPoll request when a burst
4359 * of start_xmit activity is detected (if it is not detected,
4360 * it is slow enough). -- FR
4363 if (tp->cur_tx != dirty_tx)
4364 RTL_W8(TxPoll, NPQ);
4368 static inline int rtl8169_fragmented_frame(u32 status)
4370 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4373 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4375 u32 status = opts1 & RxProtoMask;
4377 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4378 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4379 skb->ip_summed = CHECKSUM_UNNECESSARY;
4381 skb_checksum_none_assert(skb);
4384 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4385 struct rtl8169_private *tp,
4389 struct sk_buff *skb;
4390 struct device *d = &tp->pci_dev->dev;
4392 data = rtl8169_align(data);
4393 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4395 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4397 memcpy(skb->data, data, pkt_size);
4398 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4404 * Warning : rtl8169_rx_interrupt() might be called :
4405 * 1) from NAPI (softirq) context
4406 * (polling = 1 : we should call netif_receive_skb())
4407 * 2) from process context (rtl8169_reset_task())
4408 * (polling = 0 : we must call netif_rx() instead)
4410 static int rtl8169_rx_interrupt(struct net_device *dev,
4411 struct rtl8169_private *tp,
4412 void __iomem *ioaddr, u32 budget)
4414 unsigned int cur_rx, rx_left;
4416 int polling = (budget != ~(u32)0) ? 1 : 0;
4418 cur_rx = tp->cur_rx;
4419 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4420 rx_left = min(rx_left, budget);
4422 for (; rx_left > 0; rx_left--, cur_rx++) {
4423 unsigned int entry = cur_rx % NUM_RX_DESC;
4424 struct RxDesc *desc = tp->RxDescArray + entry;
4428 status = le32_to_cpu(desc->opts1);
4430 if (status & DescOwn)
4432 if (unlikely(status & RxRES)) {
4433 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4435 dev->stats.rx_errors++;
4436 if (status & (RxRWT | RxRUNT))
4437 dev->stats.rx_length_errors++;
4439 dev->stats.rx_crc_errors++;
4440 if (status & RxFOVF) {
4441 rtl8169_schedule_work(dev, rtl8169_reset_task);
4442 dev->stats.rx_fifo_errors++;
4444 rtl8169_mark_to_asic(desc, rx_buf_sz);
4446 struct sk_buff *skb;
4447 dma_addr_t addr = le64_to_cpu(desc->addr);
4448 int pkt_size = (status & 0x00001FFF) - 4;
4451 * The driver does not support incoming fragmented
4452 * frames. They are seen as a symptom of over-mtu
4455 if (unlikely(rtl8169_fragmented_frame(status))) {
4456 dev->stats.rx_dropped++;
4457 dev->stats.rx_length_errors++;
4458 rtl8169_mark_to_asic(desc, rx_buf_sz);
4462 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4463 tp, pkt_size, addr);
4464 rtl8169_mark_to_asic(desc, rx_buf_sz);
4466 dev->stats.rx_dropped++;
4470 rtl8169_rx_csum(skb, status);
4471 skb_put(skb, pkt_size);
4472 skb->protocol = eth_type_trans(skb, dev);
4474 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4475 if (likely(polling))
4476 napi_gro_receive(&tp->napi, skb);
4481 dev->stats.rx_bytes += pkt_size;
4482 dev->stats.rx_packets++;
4485 /* Work around for AMD plateform. */
4486 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4487 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4493 count = cur_rx - tp->cur_rx;
4494 tp->cur_rx = cur_rx;
4496 tp->dirty_rx += count;
4501 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4503 struct net_device *dev = dev_instance;
4504 struct rtl8169_private *tp = netdev_priv(dev);
4505 void __iomem *ioaddr = tp->mmio_addr;
4509 /* loop handling interrupts until we have no new ones or
4510 * we hit a invalid/hotplug case.
4512 status = RTL_R16(IntrStatus);
4513 while (status && status != 0xffff) {
4516 /* Handle all of the error cases first. These will reset
4517 * the chip, so just exit the loop.
4519 if (unlikely(!netif_running(dev))) {
4520 rtl8169_asic_down(ioaddr);
4524 /* Work around for rx fifo overflow */
4525 if (unlikely(status & RxFIFOOver) &&
4526 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4527 netif_stop_queue(dev);
4528 rtl8169_tx_timeout(dev);
4532 if (unlikely(status & SYSErr)) {
4533 rtl8169_pcierr_interrupt(dev);
4537 if (status & LinkChg)
4538 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4540 /* We need to see the lastest version of tp->intr_mask to
4541 * avoid ignoring an MSI interrupt and having to wait for
4542 * another event which may never come.
4545 if (status & tp->intr_mask & tp->napi_event) {
4546 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4547 tp->intr_mask = ~tp->napi_event;
4549 if (likely(napi_schedule_prep(&tp->napi)))
4550 __napi_schedule(&tp->napi);
4552 netif_info(tp, intr, dev,
4553 "interrupt %04x in poll\n", status);
4556 /* We only get a new MSI interrupt when all active irq
4557 * sources on the chip have been acknowledged. So, ack
4558 * everything we've seen and check if new sources have become
4559 * active to avoid blocking all interrupts from the chip.
4562 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4563 status = RTL_R16(IntrStatus);
4566 return IRQ_RETVAL(handled);
4569 static int rtl8169_poll(struct napi_struct *napi, int budget)
4571 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4572 struct net_device *dev = tp->dev;
4573 void __iomem *ioaddr = tp->mmio_addr;
4576 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4577 rtl8169_tx_interrupt(dev, tp, ioaddr);
4579 if (work_done < budget) {
4580 napi_complete(napi);
4582 /* We need for force the visibility of tp->intr_mask
4583 * for other CPUs, as we can loose an MSI interrupt
4584 * and potentially wait for a retransmit timeout if we don't.
4585 * The posted write to IntrMask is safe, as it will
4586 * eventually make it to the chip and we won't loose anything
4589 tp->intr_mask = 0xffff;
4591 RTL_W16(IntrMask, tp->intr_event);
4597 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4599 struct rtl8169_private *tp = netdev_priv(dev);
4601 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4604 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4605 RTL_W32(RxMissed, 0);
4608 static void rtl8169_down(struct net_device *dev)
4610 struct rtl8169_private *tp = netdev_priv(dev);
4611 void __iomem *ioaddr = tp->mmio_addr;
4613 rtl8169_delete_timer(dev);
4615 netif_stop_queue(dev);
4617 napi_disable(&tp->napi);
4619 spin_lock_irq(&tp->lock);
4621 rtl8169_asic_down(ioaddr);
4623 * At this point device interrupts can not be enabled in any function,
4624 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4625 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4627 rtl8169_rx_missed(dev, ioaddr);
4629 spin_unlock_irq(&tp->lock);
4631 synchronize_irq(dev->irq);
4633 /* Give a racing hard_start_xmit a few cycles to complete. */
4634 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4636 rtl8169_tx_clear(tp);
4638 rtl8169_rx_clear(tp);
4640 rtl_pll_power_down(tp);
4643 static int rtl8169_close(struct net_device *dev)
4645 struct rtl8169_private *tp = netdev_priv(dev);
4646 struct pci_dev *pdev = tp->pci_dev;
4648 pm_runtime_get_sync(&pdev->dev);
4650 /* update counters before going down */
4651 rtl8169_update_counters(dev);
4655 free_irq(dev->irq, dev);
4657 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4659 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4661 tp->TxDescArray = NULL;
4662 tp->RxDescArray = NULL;
4664 pm_runtime_put_sync(&pdev->dev);
4669 static void rtl_set_rx_mode(struct net_device *dev)
4671 struct rtl8169_private *tp = netdev_priv(dev);
4672 void __iomem *ioaddr = tp->mmio_addr;
4673 unsigned long flags;
4674 u32 mc_filter[2]; /* Multicast hash filter */
4678 if (dev->flags & IFF_PROMISC) {
4679 /* Unconditionally log net taps. */
4680 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4682 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4684 mc_filter[1] = mc_filter[0] = 0xffffffff;
4685 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4686 (dev->flags & IFF_ALLMULTI)) {
4687 /* Too many to filter perfectly -- accept all multicasts. */
4688 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4689 mc_filter[1] = mc_filter[0] = 0xffffffff;
4691 struct netdev_hw_addr *ha;
4693 rx_mode = AcceptBroadcast | AcceptMyPhys;
4694 mc_filter[1] = mc_filter[0] = 0;
4695 netdev_for_each_mc_addr(ha, dev) {
4696 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4697 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4698 rx_mode |= AcceptMulticast;
4702 spin_lock_irqsave(&tp->lock, flags);
4704 tmp = rtl8169_rx_config | rx_mode |
4705 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4707 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4708 u32 data = mc_filter[0];
4710 mc_filter[0] = swab32(mc_filter[1]);
4711 mc_filter[1] = swab32(data);
4714 RTL_W32(MAR0 + 4, mc_filter[1]);
4715 RTL_W32(MAR0 + 0, mc_filter[0]);
4717 RTL_W32(RxConfig, tmp);
4719 spin_unlock_irqrestore(&tp->lock, flags);
4723 * rtl8169_get_stats - Get rtl8169 read/write statistics
4724 * @dev: The Ethernet Device to get statistics for
4726 * Get TX/RX statistics for rtl8169
4728 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4730 struct rtl8169_private *tp = netdev_priv(dev);
4731 void __iomem *ioaddr = tp->mmio_addr;
4732 unsigned long flags;
4734 if (netif_running(dev)) {
4735 spin_lock_irqsave(&tp->lock, flags);
4736 rtl8169_rx_missed(dev, ioaddr);
4737 spin_unlock_irqrestore(&tp->lock, flags);
4743 static void rtl8169_net_suspend(struct net_device *dev)
4745 struct rtl8169_private *tp = netdev_priv(dev);
4747 if (!netif_running(dev))
4750 rtl_pll_power_down(tp);
4752 netif_device_detach(dev);
4753 netif_stop_queue(dev);
4758 static int rtl8169_suspend(struct device *device)
4760 struct pci_dev *pdev = to_pci_dev(device);
4761 struct net_device *dev = pci_get_drvdata(pdev);
4763 rtl8169_net_suspend(dev);
4768 static void __rtl8169_resume(struct net_device *dev)
4770 struct rtl8169_private *tp = netdev_priv(dev);
4772 netif_device_attach(dev);
4774 rtl_pll_power_up(tp);
4776 rtl8169_schedule_work(dev, rtl8169_reset_task);
4779 static int rtl8169_resume(struct device *device)
4781 struct pci_dev *pdev = to_pci_dev(device);
4782 struct net_device *dev = pci_get_drvdata(pdev);
4783 struct rtl8169_private *tp = netdev_priv(dev);
4785 rtl8169_init_phy(dev, tp);
4787 if (netif_running(dev))
4788 __rtl8169_resume(dev);
4793 static int rtl8169_runtime_suspend(struct device *device)
4795 struct pci_dev *pdev = to_pci_dev(device);
4796 struct net_device *dev = pci_get_drvdata(pdev);
4797 struct rtl8169_private *tp = netdev_priv(dev);
4799 if (!tp->TxDescArray)
4802 spin_lock_irq(&tp->lock);
4803 tp->saved_wolopts = __rtl8169_get_wol(tp);
4804 __rtl8169_set_wol(tp, WAKE_ANY);
4805 spin_unlock_irq(&tp->lock);
4807 rtl8169_net_suspend(dev);
4812 static int rtl8169_runtime_resume(struct device *device)
4814 struct pci_dev *pdev = to_pci_dev(device);
4815 struct net_device *dev = pci_get_drvdata(pdev);
4816 struct rtl8169_private *tp = netdev_priv(dev);
4818 if (!tp->TxDescArray)
4821 spin_lock_irq(&tp->lock);
4822 __rtl8169_set_wol(tp, tp->saved_wolopts);
4823 tp->saved_wolopts = 0;
4824 spin_unlock_irq(&tp->lock);
4826 rtl8169_init_phy(dev, tp);
4828 __rtl8169_resume(dev);
4833 static int rtl8169_runtime_idle(struct device *device)
4835 struct pci_dev *pdev = to_pci_dev(device);
4836 struct net_device *dev = pci_get_drvdata(pdev);
4837 struct rtl8169_private *tp = netdev_priv(dev);
4839 return tp->TxDescArray ? -EBUSY : 0;
4842 static const struct dev_pm_ops rtl8169_pm_ops = {
4843 .suspend = rtl8169_suspend,
4844 .resume = rtl8169_resume,
4845 .freeze = rtl8169_suspend,
4846 .thaw = rtl8169_resume,
4847 .poweroff = rtl8169_suspend,
4848 .restore = rtl8169_resume,
4849 .runtime_suspend = rtl8169_runtime_suspend,
4850 .runtime_resume = rtl8169_runtime_resume,
4851 .runtime_idle = rtl8169_runtime_idle,
4854 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4856 #else /* !CONFIG_PM */
4858 #define RTL8169_PM_OPS NULL
4860 #endif /* !CONFIG_PM */
4862 static void rtl_shutdown(struct pci_dev *pdev)
4864 struct net_device *dev = pci_get_drvdata(pdev);
4865 struct rtl8169_private *tp = netdev_priv(dev);
4866 void __iomem *ioaddr = tp->mmio_addr;
4868 rtl8169_net_suspend(dev);
4870 /* restore original MAC address */
4871 rtl_rar_set(tp, dev->perm_addr);
4873 spin_lock_irq(&tp->lock);
4875 rtl8169_asic_down(ioaddr);
4877 spin_unlock_irq(&tp->lock);
4879 if (system_state == SYSTEM_POWER_OFF) {
4880 /* WoL fails with some 8168 when the receiver is disabled. */
4881 if (tp->features & RTL_FEATURE_WOL) {
4882 pci_clear_master(pdev);
4884 RTL_W8(ChipCmd, CmdRxEnb);
4889 pci_wake_from_d3(pdev, true);
4890 pci_set_power_state(pdev, PCI_D3hot);
4894 static struct pci_driver rtl8169_pci_driver = {
4896 .id_table = rtl8169_pci_tbl,
4897 .probe = rtl8169_init_one,
4898 .remove = __devexit_p(rtl8169_remove_one),
4899 .shutdown = rtl_shutdown,
4900 .driver.pm = RTL8169_PM_OPS,
4903 static int __init rtl8169_init_module(void)
4905 return pci_register_driver(&rtl8169_pci_driver);
4908 static void __exit rtl8169_cleanup_module(void)
4910 pci_unregister_driver(&rtl8169_pci_driver);
4913 module_init(rtl8169_init_module);
4914 module_exit(rtl8169_cleanup_module);