1 /************************************************************************
2 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
18 typedef struct _XENA_dev_config {
19 /* Convention: mHAL_XXX is mask, vHAL_XXX is value */
21 /* General Control-Status Registers */
22 u64 general_int_status;
23 #define GEN_INTR_TXPIC BIT(0)
24 #define GEN_INTR_TXDMA BIT(1)
25 #define GEN_INTR_TXMAC BIT(2)
26 #define GEN_INTR_TXXGXS BIT(3)
27 #define GEN_INTR_TXTRAFFIC BIT(8)
28 #define GEN_INTR_RXPIC BIT(32)
29 #define GEN_INTR_RXDMA BIT(33)
30 #define GEN_INTR_RXMAC BIT(34)
31 #define GEN_INTR_MC BIT(35)
32 #define GEN_INTR_RXXGXS BIT(36)
33 #define GEN_INTR_RXTRAFFIC BIT(40)
34 #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
42 u8 unused0[0x100 - 0x10];
45 /* XGXS must be removed from reset only once. */
46 #define SW_RESET_XENA vBIT(0xA5,0,8)
47 #define SW_RESET_FLASH vBIT(0xA5,8,8)
48 #define SW_RESET_EOI vBIT(0xA5,16,8)
49 #define SW_RESET_ALL (SW_RESET_XENA | \
52 /* The SW_RESET register must read this value after a successful reset. */
53 #define SW_RESET_RAW_VAL 0xA5000000
57 #define ADAPTER_STATUS_TDMA_READY BIT(0)
58 #define ADAPTER_STATUS_RDMA_READY BIT(1)
59 #define ADAPTER_STATUS_PFC_READY BIT(2)
60 #define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
61 #define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
62 #define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
63 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
64 #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65 #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
66 #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
67 #define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
68 #define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
69 #define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
70 #define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
73 #define ADAPTER_CNTL_EN BIT(7)
74 #define ADAPTER_EOI_TX_ON BIT(15)
75 #define ADAPTER_LED_ON BIT(23)
76 #define ADAPTER_UDPI(val) vBIT(val,36,4)
77 #define ADAPTER_WAIT_INT BIT(48)
78 #define ADAPTER_ECC_EN BIT(55)
81 #define SERR_SOURCE_PIC BIT(0)
82 #define SERR_SOURCE_TXDMA BIT(1)
83 #define SERR_SOURCE_RXDMA BIT(2)
84 #define SERR_SOURCE_MAC BIT(3)
85 #define SERR_SOURCE_MC BIT(4)
86 #define SERR_SOURCE_XGXS BIT(5)
87 #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
95 #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
96 #define PCI_MODE_PCI_33 0
97 #define PCI_MODE_PCI_66 0x1
98 #define PCI_MODE_PCIX_M1_66 0x2
99 #define PCI_MODE_PCIX_M1_100 0x3
100 #define PCI_MODE_PCIX_M1_133 0x4
101 #define PCI_MODE_PCIX_M2_66 0x5
102 #define PCI_MODE_PCIX_M2_100 0x6
103 #define PCI_MODE_PCIX_M2_133 0x7
104 #define PCI_MODE_UNSUPPORTED BIT(0)
105 #define PCI_MODE_32_BITS BIT(8)
106 #define PCI_MODE_UNKNOWN_MODE BIT(9)
108 u8 unused_0[0x800 - 0x128];
110 /* PCI-X Controller registers */
113 #define PIC_INT_TX BIT(0)
114 #define PIC_INT_FLSH BIT(1)
115 #define PIC_INT_MDIO BIT(2)
116 #define PIC_INT_IIC BIT(3)
117 #define PIC_INT_GPIO BIT(4)
118 #define PIC_INT_RX BIT(32)
122 #define PCIX_INT_REG_ECC_SG_ERR BIT(0)
123 #define PCIX_INT_REG_ECC_DB_ERR BIT(1)
124 #define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
125 #define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
126 #define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
127 #define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
128 #define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
129 #define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
130 #define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
131 #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
132 #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
133 #define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
134 #define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
136 #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
137 #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
138 #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
147 #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
148 #define PIC_FLSH_INT_REG_ERR BIT(62)
153 #define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
154 #define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
155 #define MDIO_INT_REG_LASI BIT(39)
160 #define IIC_INT_REG_BUS_FSM_ERR BIT(4)
161 #define IIC_INT_REG_BIT_FSM_ERR BIT(5)
162 #define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
163 #define IIC_INT_REG_REQ_FSM_ERR BIT(7)
164 #define IIC_INT_REG_ACK_ERR BIT(8)
170 #define GPIO_INT_REG_LINK_DOWN BIT(1)
171 #define GPIO_INT_REG_LINK_UP BIT(2)
173 #define GPIO_INT_MASK_LINK_DOWN BIT(1)
174 #define GPIO_INT_MASK_LINK_UP BIT(2)
180 #define TX_TRAFFIC_INT_n(n) BIT(n)
184 #define RX_TRAFFIC_INT_n(n) BIT(n)
187 /* PIC Control registers */
189 #define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
190 #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
193 #define SWAPPER_CTRL_PIF_R_FE BIT(0)
194 #define SWAPPER_CTRL_PIF_R_SE BIT(1)
195 #define SWAPPER_CTRL_PIF_W_FE BIT(8)
196 #define SWAPPER_CTRL_PIF_W_SE BIT(9)
197 #define SWAPPER_CTRL_TXP_FE BIT(16)
198 #define SWAPPER_CTRL_TXP_SE BIT(17)
199 #define SWAPPER_CTRL_TXD_R_FE BIT(18)
200 #define SWAPPER_CTRL_TXD_R_SE BIT(19)
201 #define SWAPPER_CTRL_TXD_W_FE BIT(20)
202 #define SWAPPER_CTRL_TXD_W_SE BIT(21)
203 #define SWAPPER_CTRL_TXF_R_FE BIT(22)
204 #define SWAPPER_CTRL_TXF_R_SE BIT(23)
205 #define SWAPPER_CTRL_RXD_R_FE BIT(32)
206 #define SWAPPER_CTRL_RXD_R_SE BIT(33)
207 #define SWAPPER_CTRL_RXD_W_FE BIT(34)
208 #define SWAPPER_CTRL_RXD_W_SE BIT(35)
209 #define SWAPPER_CTRL_RXF_W_FE BIT(36)
210 #define SWAPPER_CTRL_RXF_W_SE BIT(37)
211 #define SWAPPER_CTRL_XMSI_FE BIT(40)
212 #define SWAPPER_CTRL_XMSI_SE BIT(41)
213 #define SWAPPER_CTRL_STATS_FE BIT(48)
214 #define SWAPPER_CTRL_STATS_SE BIT(49)
216 u64 pif_rd_swapper_fb;
217 #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
219 u64 scheduled_int_ctrl;
220 #define SCHED_INT_CTRL_TIMER_EN BIT(0)
221 #define SCHED_INT_CTRL_ONE_SHOT BIT(1)
222 #define SCHED_INT_CTRL_INT2MSI TBD
223 #define SCHED_INT_PERIOD TBD
226 #define TXREQTO_VAL(val) vBIT(val,0,32)
227 #define TXREQTO_EN BIT(63)
230 #define STATREQTO_VAL(n) TBD
231 #define STATREQTO_EN BIT(63)
233 u64 read_retry_delay;
234 u64 read_retry_acceleration;
235 u64 write_retry_delay;
236 u64 write_retry_acceleration;
244 #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
249 #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
253 #define STAT_BC(n) vBIT(n,4,12)
255 /* Automated statistics collection */
257 #define STAT_CFG_STAT_EN BIT(0)
258 #define STAT_CFG_ONE_SHOT_EN BIT(1)
259 #define STAT_CFG_STAT_NS_EN BIT(8)
260 #define STAT_CFG_STAT_RO BIT(9)
261 #define STAT_TRSF_PER(n) TBD
262 #define PER_SEC 0x208d5
263 #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
264 #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
268 /* General Configuration */
274 #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
275 #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
276 #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
277 #define I2C_CONTROL_READ BIT(24)
278 #define I2C_CONTROL_NACK BIT(25)
279 #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
280 #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
281 #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
282 #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
285 #define GPIO_CTRL_GPIO_0 BIT(8)
287 #define EXT_REQ_EN BIT(1)
288 #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
290 u8 unused7_1[0x230 - 0x208];
296 #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
298 u8 unused7_2[0x800 - 0x248];
300 /* TxDMA registers */
301 u64 txdma_int_status;
303 #define TXDMA_PFC_INT BIT(0)
304 #define TXDMA_TDA_INT BIT(1)
305 #define TXDMA_PCC_INT BIT(2)
306 #define TXDMA_TTI_INT BIT(3)
307 #define TXDMA_LSO_INT BIT(4)
308 #define TXDMA_TPA_INT BIT(5)
309 #define TXDMA_SM_INT BIT(6)
319 #define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
320 #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
341 u8 unused8[0x100 - 0xB8];
344 u64 tx_dma_wrap_stat;
346 /* Tx FIFO controller */
347 #define X_MAX_FIFOS 8
348 #define X_FIFO_MAX_LEN 0x1FFF /*8191 */
349 u64 tx_fifo_partition_0;
350 #define TX_FIFO_PARTITION_EN BIT(0)
351 #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
352 #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
353 #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
354 #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
356 u64 tx_fifo_partition_1;
357 #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
358 #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
359 #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
360 #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
362 u64 tx_fifo_partition_2;
363 #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
364 #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
365 #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
366 #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
368 u64 tx_fifo_partition_3;
369 #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
370 #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
371 #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
372 #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
374 #define TX_FIFO_PARTITION_PRI_0 0 /* highest */
375 #define TX_FIFO_PARTITION_PRI_1 1
376 #define TX_FIFO_PARTITION_PRI_2 2
377 #define TX_FIFO_PARTITION_PRI_3 3
378 #define TX_FIFO_PARTITION_PRI_4 4
379 #define TX_FIFO_PARTITION_PRI_5 5
380 #define TX_FIFO_PARTITION_PRI_6 6
381 #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
383 u64 tx_w_round_robin_0;
384 u64 tx_w_round_robin_1;
385 u64 tx_w_round_robin_2;
386 u64 tx_w_round_robin_3;
387 u64 tx_w_round_robin_4;
390 #define TTI_CMD_MEM_WE BIT(7)
391 #define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
392 #define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
393 #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
396 #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
397 #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
398 #define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
399 #define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
400 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
401 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
402 #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
405 #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
406 #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
407 #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
408 #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
410 /* Tx Protocol assist */
412 #define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
413 #define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
414 #define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
415 #define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
417 /* Recent add, used only debug purposes. */
420 u8 unused9[0x700 - 0x178];
422 u64 txdma_debug_ctrl;
424 u8 unused10[0x1800 - 0x1708];
426 /* RxDMA Registers */
427 u64 rxdma_int_status;
429 #define RXDMA_INT_RC_INT_M BIT(0)
430 #define RXDMA_INT_RPA_INT_M BIT(1)
431 #define RXDMA_INT_RDA_INT_M BIT(2)
432 #define RXDMA_INT_RTI_INT_M BIT(3)
442 u64 prc_pcix_err_reg;
443 u64 prc_pcix_err_mask;
444 u64 prc_pcix_err_alarm;
454 u8 unused11[0x100 - 0x88];
457 u64 rx_queue_priority;
458 #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
459 #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
460 #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
461 #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
462 #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
463 #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
464 #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
465 #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
467 #define RX_QUEUE_PRI_0 0 /* highest */
468 #define RX_QUEUE_PRI_1 1
469 #define RX_QUEUE_PRI_2 2
470 #define RX_QUEUE_PRI_3 3
471 #define RX_QUEUE_PRI_4 4
472 #define RX_QUEUE_PRI_5 5
473 #define RX_QUEUE_PRI_6 6
474 #define RX_QUEUE_PRI_7 7 /* lowest */
476 u64 rx_w_round_robin_0;
477 u64 rx_w_round_robin_1;
478 u64 rx_w_round_robin_2;
479 u64 rx_w_round_robin_3;
480 u64 rx_w_round_robin_4;
482 /* Per-ring controller regs */
483 #define RX_MAX_RINGS 8
485 #define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
486 #define RX_MIN_RINGS_SZ 0x3F /* 63 */
488 u64 prc_rxd0_n[RX_MAX_RINGS];
489 u64 prc_ctrl_n[RX_MAX_RINGS];
490 #define PRC_CTRL_RC_ENABLED BIT(7)
491 #define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
492 #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
493 #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
494 #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
495 #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
496 #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
497 #define PRC_CTRL_NO_SNOOP_DESC BIT(22)
498 #define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
499 #define PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
500 #define PRC_CTRL_GROUP_READS BIT(38)
501 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
503 u64 prc_alarm_action;
504 #define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
505 #define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
506 #define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
507 #define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
508 #define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
509 #define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
510 #define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
511 #define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
512 #define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
513 #define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
514 #define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
515 #define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
516 #define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
517 #define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
518 #define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
519 #define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
521 /* Receive traffic interrupts */
523 #define RTI_CMD_MEM_WE BIT(7)
524 #define RTI_CMD_MEM_STROBE BIT(15)
525 #define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
526 #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
527 #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
530 #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
531 #define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
532 #define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
533 #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
534 #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
535 #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
538 #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
539 #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
540 #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
541 #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
544 #define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
545 #define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
546 #define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
547 #define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
549 u8 unused12[0x700 - 0x1D8];
551 u64 rxdma_debug_ctrl;
553 u8 unused13[0x2000 - 0x1f08];
555 /* Media Access Controller Register */
558 #define MAC_INT_STATUS_TMAC_INT BIT(0)
559 #define MAC_INT_STATUS_RMAC_INT BIT(1)
561 u64 mac_tmac_err_reg;
562 #define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
563 #define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
564 #define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
565 u64 mac_tmac_err_mask;
566 u64 mac_tmac_err_alarm;
568 u64 mac_rmac_err_reg;
569 #define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
570 #define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
571 #define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
572 #define RMAC_LINK_STATE_CHANGE_INT BIT(31)
573 u64 mac_rmac_err_mask;
574 u64 mac_rmac_err_alarm;
576 u8 unused14[0x100 - 0x40];
579 #define MAC_CFG_TMAC_ENABLE BIT(0)
580 #define MAC_CFG_RMAC_ENABLE BIT(1)
581 #define MAC_CFG_LAN_NOT_WAN BIT(2)
582 #define MAC_CFG_TMAC_LOOPBACK BIT(3)
583 #define MAC_CFG_TMAC_APPEND_PAD BIT(4)
584 #define MAC_CFG_RMAC_STRIP_FCS BIT(5)
585 #define MAC_CFG_RMAC_STRIP_PAD BIT(6)
586 #define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
587 #define MAC_RMAC_DISCARD_PFRM BIT(8)
588 #define MAC_RMAC_BCAST_ENABLE BIT(9)
589 #define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
590 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
593 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
595 u64 rmac_max_pyld_len;
596 #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
597 #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
598 #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
601 #define RMAC_ERR_FCS BIT(0)
602 #define RMAC_ERR_FCS_ACCEPT BIT(1)
603 #define RMAC_ERR_TOO_LONG BIT(1)
604 #define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
605 #define RMAC_ERR_RUNT BIT(2)
606 #define RMAC_ERR_RUNT_ACCEPT BIT(2)
607 #define RMAC_ERR_LEN_MISMATCH BIT(3)
608 #define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
611 #define RMAC_CFG_KEY(val) vBIT(val,0,16)
613 #define MAX_MAC_ADDRESSES 16
614 #define MAX_MC_ADDRESSES 32 /* Multicast addresses */
615 #define MAC_MAC_ADDR_START_OFFSET 0
616 #define MAC_MC_ADDR_START_OFFSET 16
617 #define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
618 u64 rmac_addr_cmd_mem;
619 #define RMAC_ADDR_CMD_MEM_WE BIT(7)
620 #define RMAC_ADDR_CMD_MEM_RD 0
621 #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
622 #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
623 #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
625 u64 rmac_addr_data0_mem;
626 #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
627 #define RMAC_ADDR_DATA0_MEM_USER BIT(48)
629 u64 rmac_addr_data1_mem;
630 #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
636 #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
637 #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
638 #define RMAC_ADDR_BCAST_EN vBIT(0)_48
639 #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
644 #define RMAC_PAUSE_GEN BIT(0)
645 #define RMAC_PAUSE_GEN_ENABLE BIT(0)
646 #define RMAC_PAUSE_RX BIT(1)
647 #define RMAC_PAUSE_RX_ENABLE BIT(1)
648 #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
649 #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
653 u64 rmac_red_rate_q0q3;
654 u64 rmac_red_rate_q4q7;
657 #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
658 #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
659 #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
660 #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
661 #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
662 #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
664 #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
665 MAC_RX_LINK_UTIL_DISABLE
667 u64 rmac_invalid_ipg;
669 /* rx traffic steering */
670 #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
671 u64 rts_frm_len_n[8];
673 u64 rts_qos_steering;
675 #define MAX_DIX_MAP 4
676 u64 rts_dix_map_n[MAX_DIX_MAP];
677 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
678 #define RTS_DIX_MAP_SCW(val) BIT(val,21)
680 u64 rts_q_alternates;
684 #define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
685 #define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
688 #define RTS_PN_CAM_CTRL_WE BIT(7)
689 #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
690 #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
691 #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
693 #define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
694 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
695 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
698 #define RTS_DS_MEM_CTRL_WE BIT(7)
699 #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
700 #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
701 #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
703 #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
705 u8 unused16[0x700 - 0x220];
708 #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
710 u8 unused17[0x2800 - 0x2708];
712 /* memory controller registers */
714 #define MC_INT_STATUS_MC_INT BIT(0)
716 #define MC_INT_MASK_MC_INT BIT(0)
719 #define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
720 #define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
721 #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18)
722 #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20)
723 #define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
724 #define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
725 #define MC_ERR_REG_SM_ERR BIT(31)
726 #define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
727 BIT(6) | BIT(7) | BIT(17) | BIT(19))
728 #define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\
729 BIT(13) | BIT(14) | BIT(15) |\
734 u8 unused18[0x100 - 0x28];
736 /* MC configuration */
738 #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
739 #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
740 #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
741 #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
742 #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
743 #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
744 #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
745 #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
748 #define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
749 #define MC_RLDRAM_MRS_ENABLE BIT(47)
751 u64 mc_rldram_interleave;
753 u64 mc_pause_thresh_q0q3;
754 u64 mc_pause_thresh_q4q7;
756 u64 mc_red_thresh_q[8];
758 u8 unused19[0x200 - 0x168];
759 u64 mc_rldram_ref_per;
760 u8 unused20[0x220 - 0x208];
761 u64 mc_rldram_test_ctrl;
762 #define MC_RLDRAM_TEST_MODE BIT(47)
763 #define MC_RLDRAM_TEST_WRITE BIT(7)
764 #define MC_RLDRAM_TEST_GO BIT(15)
765 #define MC_RLDRAM_TEST_DONE BIT(23)
766 #define MC_RLDRAM_TEST_PASS BIT(31)
768 u8 unused21[0x240 - 0x228];
769 u64 mc_rldram_test_add;
770 u8 unused22[0x260 - 0x248];
771 u64 mc_rldram_test_d0;
772 u8 unused23[0x280 - 0x268];
773 u64 mc_rldram_test_d1;
774 u8 unused24[0x300 - 0x288];
775 u64 mc_rldram_test_d2;
777 u8 unused24_1[0x360 - 0x308];
779 #define MC_RLDRAM_ENABLE_ODT BIT(7)
781 u8 unused24_2[0x640 - 0x368];
782 u64 mc_rldram_ref_per_herc;
783 #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
785 u8 unused24_3[0x660 - 0x648];
786 u64 mc_rldram_mrs_herc;
788 u8 unused25[0x700 - 0x668];
791 u8 unused26[0x3000 - 0x2f08];
794 /* XGXS control registers */
797 #define XGXS_INT_STATUS_TXGXS BIT(0)
798 #define XGXS_INT_STATUS_RXGXS BIT(1)
800 #define XGXS_INT_MASK_TXGXS BIT(0)
801 #define XGXS_INT_MASK_RXGXS BIT(1)
803 u64 xgxs_txgxs_err_reg;
804 #define TXGXS_ECC_DB_ERR BIT(15)
805 u64 xgxs_txgxs_err_mask;
806 u64 xgxs_txgxs_err_alarm;
808 u64 xgxs_rxgxs_err_reg;
809 u64 xgxs_rxgxs_err_mask;
810 u64 xgxs_rxgxs_err_alarm;
812 u8 unused27[0x100 - 0x40];
818 u64 xgxs_efifo_cfg; /* CHANGED */
819 u64 rxgxs_ber_0; /* CHANGED */
820 u64 rxgxs_ber_1; /* CHANGED */
823 #define SPI_CONTROL_KEY(key) vBIT(key,0,4)
824 #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
825 #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
826 #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
827 #define SPI_CONTROL_SEL1 BIT(4)
828 #define SPI_CONTROL_REQ BIT(7)
829 #define SPI_CONTROL_NACK BIT(5)
830 #define SPI_CONTROL_DONE BIT(6)
832 #define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
835 #define XENA_REG_SPACE sizeof(XENA_dev_config_t)
836 #define XENA_EEPROM_SPACE (0x01 << 11)